diff options
Diffstat (limited to 'arch')
884 files changed, 21657 insertions, 9008 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index dfb18777b2..ea6d459dfe 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -4,6 +4,8 @@ config ARM select HAS_CACHE select HAVE_CONFIGURABLE_TEXT_BASE if !RELOCATABLE select HAVE_IMAGE_COMPRESSION + select HAVE_ARCH_KASAN + select ARM_OPTIMZED_STRING_FUNCTIONS if KASAN default y config ARM_LINUX @@ -477,4 +479,19 @@ config ARM_PSCI_DEBUG putc function. Only use for debugging. +config ARM_MODULE_PLTS + bool "Use PLTs to allow loading modules placed far from barebox image" + depends on MODULES + select QSORT + help + Allocate PLTs when loading modules so that jumps and calls whose + targets are too far away for their relative offsets to be encoded + in the instructions themselves can be bounced via veneers in the + module's PLT. The modules will use slightly more memory, but after + rounding up to page size, the actual memory footprint is usually + the same. + + Say y if your memory configuration puts the heap to far away from the + barebox image, causing relocation out of range errors + endmenu diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6c7373c206..96613cc5ba 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -10,14 +10,16 @@ endif ifeq ($(CONFIG_CPU_BIG_ENDIAN),y) KBUILD_CPPFLAGS += -mbig-endian -AS += -EB LD += -EB else KBUILD_CPPFLAGS += -mlittle-endian -AS += -EL LD += -EL endif +ifeq ($(CONFIG_ARM_MODULE_PLTS),y) +LDFLAGS_MODULE += -T $(srctree)/arch/arm/lib32/module.lds +endif + # Unaligned access is not supported when MMU is disabled, so given how # at least some of the code would be executed with MMU off, lets be # conservative and instruct the compiler not to generate any unaligned @@ -139,7 +141,7 @@ LDFLAGS_barebox += --gc-sections LDFLAGS_pbl += --gc-sections # early code often runs at addresses we are not linked at -KBUILD_CPPFLAGS += -fPIE +KBUILD_CFLAGS_KERNEL += -fPIE ifdef CONFIG_RELOCATABLE LDFLAGS_barebox += -pie diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index e9e9163d58..a02d80d2da 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -85,6 +85,7 @@ obj-$(CONFIG_MACH_NVIDIA_JETSON) += nvidia-jetson-tk1/ obj-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += nxp-imx6ull-evk/ obj-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += nxp-imx8mq-evk/ obj-$(CONFIG_MACH_NXP_IMX8MM_EVK) += nxp-imx8mm-evk/ +obj-$(CONFIG_MACH_NXP_IMX8MP_EVK) += nxp-imx8mp-evk/ obj-$(CONFIG_MACH_OMAP343xSDP) += omap343xdsp/ obj-$(CONFIG_MACH_OMAP3EVM) += omap3evm/ obj-$(CONFIG_MACH_PANDA) += panda/ @@ -104,6 +105,7 @@ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += plathome-openblocks-a6/ obj-$(CONFIG_MACH_PM9261) += pm9261/ obj-$(CONFIG_MACH_PM9263) += pm9263/ obj-$(CONFIG_MACH_PM9G45) += pm9g45/ +obj-$(CONFIG_MACH_PROTONIC_IMX6) += protonic-imx6/ obj-$(CONFIG_MACH_QIL_A9260) += qil-a926x/ obj-$(CONFIG_MACH_QIL_A9G20) += qil-a926x/ obj-$(CONFIG_MACH_RADXA_ROCK) += radxa-rock/ @@ -112,6 +114,7 @@ obj-$(CONFIG_MACH_REALQ7) += datamodul-edm-qmx6/ obj-$(CONFIG_MACH_RPI_COMMON) += raspberry-pi/ obj-$(CONFIG_MACH_SABRELITE) += freescale-mx6-sabrelite/ obj-$(CONFIG_MACH_SABRESD) += freescale-mx6-sabresd/ +obj-$(CONFIG_MACH_AC_SXB) += ac-sxb/ obj-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += freescale-mx6sx-sabresdb/ obj-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += sama5d27-giantboard/ obj-$(CONFIG_MACH_SAMA5D27_SOM1) += sama5d27-som1/ @@ -121,6 +124,7 @@ obj-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += microchip-ksz9477-evb/ obj-$(CONFIG_MACH_SAMA5D4_XPLAINED) += sama5d4_xplained/ obj-$(CONFIG_MACH_SAMA5D4EK) += sama5d4ek/ obj-$(CONFIG_MACH_SCB9328) += scb9328/ +obj-$(CONFIG_MACH_SEEED_ODYSSEY) += seeed-odyssey/ obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += altera-socdk/ obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/ obj-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += reflex-achilles/ @@ -128,7 +132,7 @@ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox/ obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += solidrun-microsom/ -obj-$(CONFIG_MACH_STM32MP157C_DK2) += stm32mp157c-dk2/ +obj-$(CONFIG_MACH_STM32MP15XX_DKX) += stm32mp15xx-dkx/ obj-$(CONFIG_MACH_LXA_MC1) += lxa-mc1/ obj-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += technexion-pico-hobbit/ obj-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += technexion-wandboard/ @@ -161,6 +165,7 @@ obj-$(CONFIG_MACH_VARISCITE_MX6) += variscite-mx6/ obj-$(CONFIG_MACH_VSCOM_BALTOS) += vscom-baltos/ obj-$(CONFIG_MACH_QEMU_VIRT64) += qemu-virt64/ obj-$(CONFIG_MACH_WARP7) += element14-warp7/ +obj-$(CONFIG_MACH_WEBASTO_CCBV2) += webasto-ccbv2/ obj-$(CONFIG_MACH_VF610_TWR) += freescale-vf610-twr/ obj-$(CONFIG_MACH_XILINX_ZCU104) += xilinx-zcu104/ obj-$(CONFIG_MACH_ZII_COMMON) += zii-common/ diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c index 44cf51b212..ef727f664d 100644 --- a/arch/arm/boards/a9m2410/a9m2410.c +++ b/arch/arm/boards/a9m2410/a9m2410.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix #include <common.h> #include <driver.h> diff --git a/arch/arm/boards/a9m2410/config.h b/arch/arm/boards/a9m2410/config.h index 1da99eacee..dbe4bb32cb 100644 --- a/arch/arm/boards/a9m2410/config.h +++ b/arch/arm/boards/a9m2410/config.h @@ -1,18 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /** * @file * @brief Global defintions for the ARM S3C2410 based a9m2410 CPU card */ -/* This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ #ifndef __CONFIG_H #define __CONFIG_H diff --git a/arch/arm/boards/a9m2440/a9m2410dev.c b/arch/arm/boards/a9m2440/a9m2410dev.c index b115c4a954..627a8c6158 100644 --- a/arch/arm/boards/a9m2440/a9m2410dev.c +++ b/arch/arm/boards/a9m2440/a9m2410dev.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009 Juergen Beisert - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Juergen Beisert /** * @file diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c index 587baf6cfd..de18ea0120 100644 --- a/arch/arm/boards/a9m2440/a9m2440.c +++ b/arch/arm/boards/a9m2440/a9m2440.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix #include <common.h> #include <driver.h> diff --git a/arch/arm/boards/a9m2440/baseboards.h b/arch/arm/boards/a9m2440/baseboards.h index f963edf1bc..be4ae65e82 100644 --- a/arch/arm/boards/a9m2440/baseboards.h +++ b/arch/arm/boards/a9m2440/baseboards.h @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009 Juergen Beisert - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Juergen Beisert #ifdef CONFIG_MACH_A9M2410DEV extern int a9m2410dev_devices_init(void); diff --git a/arch/arm/boards/a9m2440/config.h b/arch/arm/boards/a9m2440/config.h index 71d1225d18..c22ff53036 100644 --- a/arch/arm/boards/a9m2440/config.h +++ b/arch/arm/boards/a9m2440/config.h @@ -1,18 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /** * @file * @brief Global defintions for the ARM S3C2440 based a9m2440 CPU card */ -/* This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ #ifndef __CONFIG_H #define __CONFIG_H diff --git a/arch/arm/boards/ac-sxb/Makefile b/arch/arm/boards/ac-sxb/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/ac-sxb/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/ac-sxb/board.c b/arch/arm/boards/ac-sxb/board.c new file mode 100644 index 0000000000..3ea40dfb7d --- /dev/null +++ b/arch/arm/boards/ac-sxb/board.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright (C) 2017 Atlas Copco Industrial Technique + */ + +#include <common.h> +#include <init.h> +#include <mach/bbu.h> + +static int sxb_coredevices_init(void) +{ + if (!of_machine_is_compatible("ac,imx7d-sxb")) + return 0; + + imx7_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", 0); + + return 0; +} +coredevice_initcall(sxb_coredevices_init); diff --git a/arch/arm/boards/ac-sxb/flash-header-mx7d-lpddr2.imxcfg b/arch/arm/boards/ac-sxb/flash-header-mx7d-lpddr2.imxcfg new file mode 100644 index 0000000000..0b99f86d8b --- /dev/null +++ b/arch/arm/boards/ac-sxb/flash-header-mx7d-lpddr2.imxcfg @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright (C) 2017 Atlas Copco Industrial Technique + */ + +soc imx7 +loadaddr 0x00910000 +max_load_size 0x10000 +ivtofs 0x400 diff --git a/arch/arm/boards/ac-sxb/lowlevel.c b/arch/arm/boards/ac-sxb/lowlevel.c new file mode 100644 index 0000000000..a910555f9b --- /dev/null +++ b/arch/arm/boards/ac-sxb/lowlevel.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright (C) 2017 Atlas Copco Industrial Technique + */ + +#include <debug_ll.h> +#include <io.h> +#include <common.h> +#include <linux/sizes.h> +#include <mach/generic.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/imx7-ccm-regs.h> +#include <mach/iomux-mx7.h> +#include <mach/debug_ll.h> +#include <asm/cache.h> +#include <mach/esdctl.h> +#include <mach/xload.h> +#include <mach/imx7-ddr-regs.h> + +struct reginit { + u32 address; + u32 value; +}; + +static const struct reginit imx7d_ixb_dcd[] = { + {0x30340004, 0x4f400005}, + {0x30391000, 0x00000002}, + {MX7_DDRC_MSTR, 0x03020004}, + {MX7_DDRC_RFSHTMG, 0x00200038}, + {MX7_DDRC_MP_PCTRL_0, 0x00000001}, + {MX7_DDRC_INIT0, 0x00350001}, + {MX7_DDRC_INIT2, 0x00001105}, + {MX7_DDRC_INIT3, 0x00c20006}, + {MX7_DDRC_INIT4, 0x00020000}, + {MX7_DDRC_INIT5, 0x00110006}, + {MX7_DDRC_RANKCTL, 0x0000033f}, + {MX7_DDRC_DRAMTMG0, 0x080e110b}, + {MX7_DDRC_DRAMTMG1, 0x00020211}, + {MX7_DDRC_DRAMTMG2, 0x02040705}, + {MX7_DDRC_DRAMTMG3, 0x00504000}, + {MX7_DDRC_DRAMTMG4, 0x05010307}, + {MX7_DDRC_DRAMTMG5, 0x02020404}, + {MX7_DDRC_DRAMTMG6, 0x02020003}, + {MX7_DDRC_DRAMTMG7, 0x00000202}, + {MX7_DDRC_DRAMTMG8, 0x00000202}, + {MX7_DDRC_ZQCTL0, 0x20600018}, + {MX7_DDRC_ZQCTL1, 0x00e00100}, + {MX7_DDRC_DFITMG0, 0x02098203}, + {MX7_DDRC_DFITMG1, 0x00060303}, + {MX7_DDRC_DFIUPD0, 0x80400003}, + {MX7_DDRC_DFIUPD1, 0x00100020}, + {MX7_DDRC_DFIUPD2, 0x80100004}, + {MX7_DDRC_ADDRMAP0, 0x00000015}, + {MX7_DDRC_ADDRMAP1, 0x00080808}, + {MX7_DDRC_ADDRMAP4, 0x00000f0f}, + {MX7_DDRC_ADDRMAP5, 0x07070707}, + {MX7_DDRC_ADDRMAP6, 0x0f0f0707}, + {MX7_DDRC_ODTCFG, 0x06000600}, + {MX7_DDRC_ODTMAP, 0x00000000}, + {0x30391000, 0x00000000}, + {MX7_DDR_PHY_PHY_CON0, 0x17421640}, + {MX7_DDR_PHY_PHY_CON1, 0x10210100}, + {MX7_DDR_PHY_PHY_CON2, 0x00010000}, + {MX7_DDR_PHY_PHY_CON4, 0x00050408}, + {MX7_DDR_PHY_MDLL_CON0, 0x1010007e}, + {MX7_DDR_PHY_RODT_CON0, 0x01010000}, + {MX7_DDR_PHY_DRVDS_CON0, 0x00000d6e}, + {MX7_DDR_PHY_OFFSET_WR_CON0, 0x06060606}, + {MX7_DDR_PHY_OFFSET_RD_CON0, 0x0a0a0a0a}, + {MX7_DDR_PHY_CMD_SDLL_CON0, 0x01000008}, + {MX7_DDR_PHY_CMD_SDLL_CON0, 0x00000008}, + {MX7_DDR_PHY_LP_CON0, 0x0000000f}, + {MX7_DDR_PHY_ZQ_CON0, 0x0e487304}, + {MX7_DDR_PHY_ZQ_CON0, 0x0e4c7304}, + {MX7_DDR_PHY_ZQ_CON0, 0x0e4c7306}, + {MX7_DDR_PHY_ZQ_CON0, 0x0e487304}, + {0x30384130, 0x00000000}, + {0x30340020, 0x00000178}, + {0x30384130, 0x00000002}, +}; + +static inline void write_regs(const struct reginit *initvals, int count) +{ + int i; + + for (i = 0; i < count; i++) + writel(initvals[i].value, initvals[i].address); +} + +extern char __dtb_z_ac_sxb_start[]; + +static inline void setup_uart(void) +{ + imx7_early_setup_uart_clock(); + + imx7_setup_pad(MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX); + + imx7_uart_setup_ll(); + + putc_ll('>'); +} + +static noinline void imx7d_sxb_sram_setup(void) +{ + int ret; + + relocate_to_current_adr(); + setup_c(); + + pr_debug("configuring ddr...\n"); + write_regs(imx7d_ixb_dcd, ARRAY_SIZE(imx7d_ixb_dcd)); + + ret = imx7_esdhc_start_image(2); + + BUG_ON(ret); +} + +ENTRY_FUNCTION(start_ac_sxb, r0, r1, r2) +{ + imx7_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + if (get_pc() < 0x80000000) + imx7d_sxb_sram_setup(); + + imx7d_barebox_entry(__dtb_z_ac_sxb_start + get_runtime_offset()); +} diff --git a/arch/arm/boards/advantech-mx6/board.c b/arch/arm/boards/advantech-mx6/board.c index 4a30a845f1..67149d8994 100644 --- a/arch/arm/boards/advantech-mx6/board.c +++ b/arch/arm/boards/advantech-mx6/board.c @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2018 Christoph Fritz <chf.fritz@googlemail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2018 Christoph Fritz <chf.fritz@googlemail.com> #include <common.h> #include <init.h> diff --git a/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg index 996ecc708d..aefdf68e89 100644 --- a/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg +++ b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020e0774 0x000C0000 wm 32 0x020e0754 0x00000000 diff --git a/arch/arm/boards/advantech-mx6/lowlevel.c b/arch/arm/boards/advantech-mx6/lowlevel.c index de1d344dc1..d762f0e9a7 100644 --- a/arch/arm/boards/advantech-mx6/lowlevel.c +++ b/arch/arm/boards/advantech-mx6/lowlevel.c @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2018 Christoph Fritz <chf.fritz@googlemail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2018 Christoph Fritz <chf.fritz@googlemail.com> #include <debug_ll.h> #include <common.h> diff --git a/arch/arm/boards/afi-gf/board.c b/arch/arm/boards/afi-gf/board.c index 14e2603910..53d3b67008 100644 --- a/arch/arm/boards/afi-gf/board.c +++ b/arch/arm/boards/afi-gf/board.c @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jan Luebbe <j.luebbe@pengutronix.de> #include <common.h> #include <string.h> diff --git a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c index a199e4da1c..9777d15dfe 100644 --- a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c +++ b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c @@ -29,7 +29,7 @@ #include <mach/cyclone5-scan-manager.h> -static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] +static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, 0x00000000, @@ -57,7 +57,7 @@ static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCAN 0x00001000, }; -static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] +static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { 0x000C0300, 0x10040000, @@ -115,7 +115,7 @@ static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000080, }; -static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] +static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { 0x80040100, 0x00000000, @@ -149,7 +149,7 @@ static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000800, }; -static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] +static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { 0x0C420D80, 0x082000FF, diff --git a/arch/arm/boards/altera-socdk/lowlevel.c b/arch/arm/boards/altera-socdk/lowlevel.c index 36dbc55b96..822c3d8ee6 100644 --- a/arch/arm/boards/altera-socdk/lowlevel.c +++ b/arch/arm/boards/altera-socdk/lowlevel.c @@ -1,5 +1,3 @@ -#define SECT(name) __attribute__((section("socfpga_socdk_" #name))) name - #include "sdram_config.h" #include "pinmux_config.c" #include "pll_config.h" diff --git a/arch/arm/boards/altera-socdk/pinmux_config.c b/arch/arm/boards/altera-socdk/pinmux_config.c index 8bdaaedb80..ff784bbecf 100644 --- a/arch/arm/boards/altera-socdk/pinmux_config.c +++ b/arch/arm/boards/altera-socdk/pinmux_config.c @@ -30,7 +30,7 @@ #include <common.h> /* pin MUX configuration data */ -static unsigned long SECT(sys_mgr_init_table)[] = { +static unsigned long sys_mgr_init_table[] = { 0, /* EMACIO0 */ 2, /* EMACIO1 */ 2, /* EMACIO2 */ diff --git a/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c b/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c index c9011b2e21..6531383807 100644 --- a/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c +++ b/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c @@ -28,7 +28,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ static const uint32_t ac_rom_init_size = 36; -static const uint32_t SECT(ac_rom_init)[36] = { +static const uint32_t ac_rom_init[36] = { 0x20700000, 0x20780000, 0x10080431, diff --git a/arch/arm/boards/archosg9/archos_features.c b/arch/arm/boards/archosg9/archos_features.c index 0cffac7780..8642d344a5 100644 --- a/arch/arm/boards/archosg9/archos_features.c +++ b/arch/arm/boards/archosg9/archos_features.c @@ -1,14 +1,5 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later + #include <common.h> #include <asm/setup.h> #include "archos_features.h" diff --git a/arch/arm/boards/archosg9/board.c b/arch/arm/boards/archosg9/board.c index 52f7e86fbe..3289cfda3d 100644 --- a/arch/arm/boards/archosg9/board.c +++ b/arch/arm/boards/archosg9/board.c @@ -1,14 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <clock.h> diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c index b1045a44ed..f31ef1a7f2 100644 --- a/arch/arm/boards/archosg9/lowlevel.c +++ b/arch/arm/boards/archosg9/lowlevel.c @@ -1,14 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <io.h> diff --git a/arch/arm/boards/archosg9/mux.c b/arch/arm/boards/archosg9/mux.c index ce3cae38cb..dc85271208 100644 --- a/arch/arm/boards/archosg9/mux.c +++ b/arch/arm/boards/archosg9/mux.c @@ -1,14 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <init.h> diff --git a/arch/arm/boards/at91rm9200ek/init.c b/arch/arm/boards/at91rm9200ek/init.c index 2d9318575c..8c61a72e0b 100644 --- a/arch/arm/boards/at91rm9200ek/init.c +++ b/arch/arm/boards/at91rm9200ek/init.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> #include <common.h> #include <net.h> diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c index 037f46a78d..a1b283a25a 100644 --- a/arch/arm/boards/at91sam9260ek/init.c +++ b/arch/arm/boards/at91sam9260ek/init.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <init.h> diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c index a469dba92e..0ae5381af5 100644 --- a/arch/arm/boards/at91sam9261ek/init.c +++ b/arch/arm/boards/at91sam9261ek/init.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c index f7461ce041..bf2f1e8f9a 100644 --- a/arch/arm/boards/at91sam9263ek/init.c +++ b/arch/arm/boards/at91sam9263ek/init.c @@ -1,20 +1,6 @@ -/* - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> diff --git a/arch/arm/boards/at91sam9263ek/of_init.c b/arch/arm/boards/at91sam9263ek/of_init.c index 259287ccb5..3cb2fe22c9 100644 --- a/arch/arm/boards/at91sam9263ek/of_init.c +++ b/arch/arm/boards/at91sam9263ek/of_init.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2017 Sam Ravnborg <sam@ravnborg.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2017 Sam Ravnborg <sam@ravnborg.org> #include <common.h> #include <envfs.h> diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c index 2660104946..409e3cfeee 100644 --- a/arch/arm/boards/at91sam9m10g45ek/init.c +++ b/arch/arm/boards/at91sam9m10g45ek/init.c @@ -1,20 +1,6 @@ -/* - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> diff --git a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c index 0f3a035d1d..755e7ec029 100644 --- a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c +++ b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c @@ -11,7 +11,7 @@ #include <asm/barebox-arm.h> #include <mach/hardware.h> -#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_ddrsdrc.h> void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { diff --git a/arch/arm/boards/at91sam9m10ihd/hw_version.c b/arch/arm/boards/at91sam9m10ihd/hw_version.c index cab26b0ac4..1387c13718 100644 --- a/arch/arm/boards/at91sam9m10ihd/hw_version.c +++ b/arch/arm/boards/at91sam9m10ihd/hw_version.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <fs.h> diff --git a/arch/arm/boards/at91sam9m10ihd/hw_version.h b/arch/arm/boards/at91sam9m10ihd/hw_version.h index b9133440d3..a08bbc0529 100644 --- a/arch/arm/boards/at91sam9m10ihd/hw_version.h +++ b/arch/arm/boards/at91sam9m10ihd/hw_version.h @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #ifndef __HW_REVISION_H__ #define __HW_REVISION_H__ diff --git a/arch/arm/boards/at91sam9m10ihd/lowlevel.c b/arch/arm/boards/at91sam9m10ihd/lowlevel.c index e07ff892cd..817c7548c9 100644 --- a/arch/arm/boards/at91sam9m10ihd/lowlevel.c +++ b/arch/arm/boards/at91sam9m10ihd/lowlevel.c @@ -10,7 +10,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_ddrsdrc.h> #include <mach/at91sam9g45.h> #include <mach/hardware.h> diff --git a/arch/arm/boards/at91sam9n12ek/init.c b/arch/arm/boards/at91sam9n12ek/init.c index 72c6ff84ee..921f9fe5d8 100644 --- a/arch/arm/boards/at91sam9n12ek/init.c +++ b/arch/arm/boards/at91sam9n12ek/init.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <net.h> diff --git a/arch/arm/boards/at91sam9n12ek/lowlevel.c b/arch/arm/boards/at91sam9n12ek/lowlevel.c index 5bc18f8fca..4353555d0d 100644 --- a/arch/arm/boards/at91sam9n12ek/lowlevel.c +++ b/arch/arm/boards/at91sam9n12ek/lowlevel.c @@ -10,7 +10,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_ddrsdrc.h> #include <mach/hardware.h> void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) diff --git a/arch/arm/boards/at91sam9x5ek/hw_version.c b/arch/arm/boards/at91sam9x5ek/hw_version.c index f15cd3dc0c..4038f42ec2 100644 --- a/arch/arm/boards/at91sam9x5ek/hw_version.c +++ b/arch/arm/boards/at91sam9x5ek/hw_version.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <init.h> diff --git a/arch/arm/boards/at91sam9x5ek/hw_version.h b/arch/arm/boards/at91sam9x5ek/hw_version.h index 3f3c8003d9..322ad6bc37 100644 --- a/arch/arm/boards/at91sam9x5ek/hw_version.h +++ b/arch/arm/boards/at91sam9x5ek/hw_version.h @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #ifndef __HW_REVISION_H__ #define __HW_REVISION_H__ diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c index 65493ebbcd..a1c80bf441 100644 --- a/arch/arm/boards/at91sam9x5ek/init.c +++ b/arch/arm/boards/at91sam9x5ek/init.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <net.h> diff --git a/arch/arm/boards/at91sam9x5ek/lowlevel.c b/arch/arm/boards/at91sam9x5ek/lowlevel.c index c1433c8f7e..ebd417b19c 100644 --- a/arch/arm/boards/at91sam9x5ek/lowlevel.c +++ b/arch/arm/boards/at91sam9x5ek/lowlevel.c @@ -1,7 +1,6 @@ #include <common.h> #include <linux/sizes.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/hardware.h> +#include <mach/at91_ddrsdrc.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <io.h> diff --git a/arch/arm/boards/avnet-zedboard/board.c b/arch/arm/boards/avnet-zedboard/board.c index f53dde47c2..b8396d1996 100644 --- a/arch/arm/boards/avnet-zedboard/board.c +++ b/arch/arm/boards/avnet-zedboard/board.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> #include <asm/armlinux.h> #include <common.h> diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c index 6614e82a10..f7bdceb42a 100644 --- a/arch/arm/boards/avnet-zedboard/lowlevel.c +++ b/arch/arm/boards/avnet-zedboard/lowlevel.c @@ -1,18 +1,6 @@ -/* - * - * (c) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> + #include <common.h> #include <io.h> #include <asm/barebox-arm.h> diff --git a/arch/arm/boards/beagle/board.c b/arch/arm/boards/beagle/board.c index 460f42ac2d..7caac5727f 100644 --- a/arch/arm/boards/beagle/board.c +++ b/arch/arm/boards/beagle/board.c @@ -1,19 +1,5 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Raghavendra KH <r-khandenahally@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2008 Raghavendra KH <r-khandenahally@ti.com>, Texas Instruments (http://www.ti.com/) #include <common.h> #include <console.h> diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c index 819bdfae46..6d2144f95b 100644 --- a/arch/arm/boards/beaglebone/board.c +++ b/arch/arm/boards/beaglebone/board.c @@ -1,20 +1,6 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Raghavendra KH <r-khandenahally@ti.com> - * - * Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2008 Raghavendra KH <r-khandenahally@ti.com>, Texas Instruments (http://www.ti.com/) +// SPDX-FileCopyrightText: 2012 Jan Luebbe <j.luebbe@pengutronix.de> /** * @file diff --git a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x128mx16.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x128mx16.imxcfg index c5a286b4e0..65752f1790 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x128mx16.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x128mx16.imxcfg @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Boundary Devices - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices wm 32 MX6_MMDC_P0_MDPDC 0x00020036 wm 32 MX6_MMDC_P0_MDCFG0 0x555A7974 diff --git a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x256mx16.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x256mx16.imxcfg index 4d8a715150..7a72599b06 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x256mx16.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x256mx16.imxcfg @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Boundary Devices - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices wm 32 MX6_MMDC_P0_MDPDC 0x00020036 wm 32 MX6_MMDC_P0_MDCFG0 0x898E7974 diff --git a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x512mx16-qp.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x512mx16-qp.imxcfg index 6409b745d7..dffe480b8e 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x512mx16-qp.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x512mx16-qp.imxcfg @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2016 Boundary Devices - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2016 Boundary Devices /* NOC setup */ wm 32 0x00bb0008 0x00000004 diff --git a/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x128mx16.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x128mx16.imxcfg index 936a2f54bf..0be615baad 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x128mx16.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x128mx16.imxcfg @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Boundary Devices - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices wm 32 MX6_MMDC_P0_MDPDC 0x0002002D wm 32 MX6_MMDC_P0_MDCFG0 0x40435323 diff --git a/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x256mx16.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x256mx16.imxcfg index 09c855544d..6d7e17027f 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x256mx16.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x256mx16.imxcfg @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Boundary Devices - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices wm 32 MX6_MMDC_P0_MDPDC 0x0002002D wm 32 MX6_MMDC_P0_MDCFG0 0x696C5323 diff --git a/arch/arm/boards/boundarydevices-nitrogen6/board.c b/arch/arm/boards/boundarydevices-nitrogen6/board.c index d9514d9d48..dc2d5aa41c 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/board.c +++ b/arch/arm/boards/boundarydevices-nitrogen6/board.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2014 Lucas Stach, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Lucas Stach, Pengutronix #include <common.h> #include <init.h> diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg index 47b572db46..5da5fd9419 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg index cf3716dbaa..3ccf7591c5 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg index 8ed987daa8..7bdc0e736c 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg index e6d97d11c1..c6f5aa8484 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg index 50bbfc5bdd..797b9717e7 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/ccxmx51/flash-header.imxcfg b/arch/arm/boards/ccxmx51/flash-header.imxcfg index 251c4c1b9b..3b1df11133 100644 --- a/arch/arm/boards/ccxmx51/flash-header.imxcfg +++ b/arch/arm/boards/ccxmx51/flash-header.imxcfg @@ -1,6 +1,6 @@ soc imx51 loadaddr 0x90000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x73fa88a0 0x00000200 wm 32 0x73fa850c 0x000020c5 wm 32 0x73fa8510 0x000020c5 diff --git a/arch/arm/boards/ccxmx53/board.c b/arch/arm/boards/ccxmx53/board.c index 9d81cd80a3..b0faf8d280 100644 --- a/arch/arm/boards/ccxmx53/board.c +++ b/arch/arm/boards/ccxmx53/board.c @@ -1,19 +1,7 @@ -/* - * Copyright (C) 2015 Jason Cobham <cobham.jason@gmail.com> - * - * Board specific file for the Digi ConnectCore ccxmx53 SoM - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Jason Cobham <cobham.jason@gmail.com> + +/* Board specific file for the Digi ConnectCore ccxmx53 SoM */ #include <common.h> #include <init.h> diff --git a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg index 68d947c01d..390b75b4f2 100644 --- a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg +++ b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x70000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8554 0x00200000 wm 32 0x53fa8558 0x00200040 wm 32 0x53fa8560 0x00200000 diff --git a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg index b707dd64a6..c32ab9c162 100644 --- a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg +++ b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x70000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8554 0x00200000 wm 32 0x53fa8558 0x00200040 wm 32 0x53fa8560 0x00200000 diff --git a/arch/arm/boards/ccxmx53/lowlevel.c b/arch/arm/boards/ccxmx53/lowlevel.c index 1d2d8c6d90..5833ad4739 100644 --- a/arch/arm/boards/ccxmx53/lowlevel.c +++ b/arch/arm/boards/ccxmx53/lowlevel.c @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de> #include <debug_ll.h> #include <common.h> diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c b/arch/arm/boards/chumby_falconwing/falconwing.c index ea64fd6f47..82b9415e80 100644 --- a/arch/arm/boards/chumby_falconwing/falconwing.c +++ b/arch/arm/boards/chumby_falconwing/falconwing.c @@ -1,17 +1,6 @@ -/* - * (C) Copyright 2010 Juergen Beisert - Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Juergen Beisert, Pengutronix + #include <common.h> #include <init.h> #include <gpio.h> diff --git a/arch/arm/boards/clep7212/clep7212.c b/arch/arm/boards/clep7212/clep7212.c index 641fa15021..3b497a6bd2 100644 --- a/arch/arm/boards/clep7212/clep7212.c +++ b/arch/arm/boards/clep7212/clep7212.c @@ -1,11 +1,5 @@ -/* - * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Alexander Shiyan <shc_work@mail.ru> #include <common.h> #include <driver.h> diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c index 231329025b..41827dfa16 100644 --- a/arch/arm/boards/clep7212/lowlevel.c +++ b/arch/arm/boards/clep7212/lowlevel.c @@ -1,11 +1,5 @@ -/* - * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Alexander Shiyan <shc_work@mail.ru> #include <common.h> #include <init.h> diff --git a/arch/arm/boards/cm-fx6/board.c b/arch/arm/boards/cm-fx6/board.c index f4380629e3..5a1110860f 100644 --- a/arch/arm/boards/cm-fx6/board.c +++ b/arch/arm/boards/cm-fx6/board.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2015 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Sascha Hauer, Pengutronix #include <common.h> #include <init.h> diff --git a/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg b/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg index 9e8dce5877..4bb615ebb0 100644 --- a/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg +++ b/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg @@ -1,4 +1,4 @@ soc imx6 loadaddr 0x00907000 max_load_size 0x11000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c b/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c index 29b91e775f..5a951d1abf 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c +++ b/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c @@ -1,19 +1,8 @@ -/* - * Copyright (C) 2010 Juergen Beisert, Pengutronix <kernel@pengutronix.de> - * Copyright (C) 2011 Marc Kleine-Budde, Pengutronix <mkl@pengutronix.de> - * Copyright (C) 2011 Wolfram Sang, Pengutronix <w.sang@pengutronix.de> - * Copyright (C) 2012 Maxime Ripard, Free Electrons <maxime.ripard@free-electrons.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Juergen Beisert <kernel@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2011 Marc Kleine-Budde <mkl@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2011 Wolfram Sang <w.sang@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2012 Maxime Ripard <maxime.ripard@free-electrons.com>, Free Electrons #include <common.h> #include <environment.h> diff --git a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c index e4ccbdb2a3..fc39f0849a 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c +++ b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Free Electrons - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Free Electrons #include <common.h> @@ -112,4 +99,4 @@ void cfa10036_detect_hw(void) pr_info("Booting on a CFA10036 with %s\n", board_name); } -BAREBOX_MAGICVAR_NAMED(global_board_variant, global.board.variant, "The board variant"); +BAREBOX_MAGICVAR(global.board.variant, "The board variant"); diff --git a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.h b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.h index 2a5330ea17..63c4a5b037 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.h +++ b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.h @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Free Electrons - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Free Electrons #ifndef __HWDETECT_H__ #define __HWDETECT_H__ diff --git a/arch/arm/boards/datamodul-edm-qmx6/board.c b/arch/arm/boards/datamodul-edm-qmx6/board.c index d93c940e3d..5a24ca0806 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/board.c +++ b/arch/arm/boards/datamodul-edm-qmx6/board.c @@ -1,21 +1,5 @@ -/* - * Copyright (C) 2012 Steffen Trumtrar, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Steffen Trumtrar, Pengutronix #include <generated/mach-types.h> #include <environment.h> diff --git a/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg b/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg index 400a870154..14146bed22 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg +++ b/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg @@ -1,3 +1,3 @@ soc imx6 loadaddr 0x00907000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c index 23074326b5..8ac9317cb0 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c +++ b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c @@ -1,17 +1,6 @@ -/* - * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de> + #include <common.h> #include <linux/sizes.h> #include <io.h> diff --git a/arch/arm/boards/dfi-fs700-m60/board.c b/arch/arm/boards/dfi-fs700-m60/board.c index 2cb8e3106f..99e36da2ec 100644 --- a/arch/arm/boards/dfi-fs700-m60/board.c +++ b/arch/arm/boards/dfi-fs700-m60/board.c @@ -1,21 +1,6 @@ -/* - * Copyright (C) 2013 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer, Pengutronix + #define pr_fmt(fmt) "dfi-fs700-m60: " fmt #include <generated/mach-types.h> diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg index 2be0210dd6..fe8bd8cbd6 100644 --- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x27800000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg index fb34903e27..6919bd8c3f 100644 --- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x27800000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg index 42e98d65d3..709c11974b 100644 --- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x17800000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/dfi-fs700-m60/lowlevel.c b/arch/arm/boards/dfi-fs700-m60/lowlevel.c index 520ed4c46b..d898cb5c1e 100644 --- a/arch/arm/boards/dfi-fs700-m60/lowlevel.c +++ b/arch/arm/boards/dfi-fs700-m60/lowlevel.c @@ -1,17 +1,6 @@ -/* - * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de> + #include <common.h> #include <linux/sizes.h> #include <io.h> diff --git a/arch/arm/boards/digi-ccimx6ulsom/board.c b/arch/arm/boards/digi-ccimx6ulsom/board.c index 1fb451548f..b4fcc17e09 100644 --- a/arch/arm/boards/digi-ccimx6ulsom/board.c +++ b/arch/arm/boards/digi-ccimx6ulsom/board.c @@ -1,21 +1,5 @@ -/* - * Copyright (C) 2019 Rouven Czerwinski, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2019 Rouven Czerwinski, Pengutronix #include <common.h> #include <init.h> diff --git a/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg b/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg index 36edad7a3e..7b2a198672 100644 --- a/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg +++ b/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 /* Enable all clocks */ wm 32 0x020c4068 0xffffffff diff --git a/arch/arm/boards/dss11/init.c b/arch/arm/boards/dss11/init.c index 0d0b5e29bf..53168acb98 100644 --- a/arch/arm/boards/dss11/init.c +++ b/arch/arm/boards/dss11/init.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2011 Michael Grzeschik <mgr@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Michael Grzeschik <mgr@pengutronix.de> #include <common.h> #include <net.h> diff --git a/arch/arm/boards/duckbill/board.c b/arch/arm/boards/duckbill/board.c index 13d4ae43cf..dd22c81566 100644 --- a/arch/arm/boards/duckbill/board.c +++ b/arch/arm/boards/duckbill/board.c @@ -1,18 +1,7 @@ -/* - * Copyright (C) 2010 Juergen Beisert, Pengutronix <kernel@pengutronix.de> - * Copyright (C) 2011 Marc Kleine-Budde, Pengutronix <mkl@pengutronix.de> - * Copyright (C) 2011 Wolfram Sang, Pengutronix <w.sang@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Juergen Beisert <kernel@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2011 Marc Kleine-Budde <mkl@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2011 Wolfram Sang <w.sang@pengutronix.de>, Pengutronix #include <common.h> #include <environment.h> diff --git a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c index 6153de9005..9a814cba79 100644 --- a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c +++ b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c @@ -29,7 +29,7 @@ #include <mach/cyclone5-scan-manager.h> -static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, 0x00000000, 0x0FF00000, @@ -56,7 +56,7 @@ static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCAN 0x00001000, }; -static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { 0x000C0300, 0x300C0000, 0x300000C0, @@ -113,7 +113,7 @@ static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000080, }; -static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { 0x300C0300, 0x00000000, 0x0FF00000, @@ -146,7 +146,7 @@ static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000800, }; -static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { 0x0CC20D80, 0x0C3000FF, 0x0A804001, diff --git a/arch/arm/boards/ebv-socrates/lowlevel.c b/arch/arm/boards/ebv-socrates/lowlevel.c index ed2d4a72a5..3f12ae806f 100644 --- a/arch/arm/boards/ebv-socrates/lowlevel.c +++ b/arch/arm/boards/ebv-socrates/lowlevel.c @@ -1,5 +1,3 @@ -#define SECT(name) __attribute__((section("ebv_socrates_" #name))) name - #include "sdram_config.h" #include "pinmux_config.c" #include "pll_config.h" diff --git a/arch/arm/boards/ebv-socrates/pinmux_config.c b/arch/arm/boards/ebv-socrates/pinmux_config.c index 89e6b33c86..faa3122466 100644 --- a/arch/arm/boards/ebv-socrates/pinmux_config.c +++ b/arch/arm/boards/ebv-socrates/pinmux_config.c @@ -30,7 +30,7 @@ #include <common.h> /* pin MUX configuration data */ -static unsigned long SECT(sys_mgr_init_table)[] = { +static unsigned long sys_mgr_init_table[] = { 0, /* EMACIO0 */ 2, /* EMACIO1 */ 2, /* EMACIO2 */ @@ -238,4 +238,4 @@ static unsigned long SECT(sys_mgr_init_table)[] = { 0, /* SPIM1USEFPGA */ 0, /* USB0USEFPGA */ 0 /* SPIM0USEFPGA */ -}; +};
\ No newline at end of file diff --git a/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c b/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c index c52da56b79..5b5196ad77 100644 --- a/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c +++ b/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c @@ -1,5 +1,5 @@ static const uint32_t ac_rom_init_size = 36; -static const uint32_t SECT(ac_rom_init)[36] = +static const uint32_t ac_rom_init[36] = { 0x20700000, 0x20780000, diff --git a/arch/arm/boards/edb93xx/early_udelay.h b/arch/arm/boards/edb93xx/early_udelay.h index 371ab5088c..b902c3bfb7 100644 --- a/arch/arm/boards/edb93xx/early_udelay.h +++ b/arch/arm/boards/edb93xx/early_udelay.h @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> #include <common.h> diff --git a/arch/arm/boards/edb93xx/edb93xx.c b/arch/arm/boards/edb93xx/edb93xx.c index 62efa8fb96..4b5db60216 100644 --- a/arch/arm/boards/edb93xx/edb93xx.c +++ b/arch/arm/boards/edb93xx/edb93xx.c @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> #include <common.h> #include <driver.h> diff --git a/arch/arm/boards/edb93xx/edb93xx.h b/arch/arm/boards/edb93xx/edb93xx.h index 5293858f9d..efbe87684e 100644 --- a/arch/arm/boards/edb93xx/edb93xx.h +++ b/arch/arm/boards/edb93xx/edb93xx.h @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> #if defined(CONFIG_MACH_EDB9301) #define MACH_TYPE MACH_TYPE_EDB9301 diff --git a/arch/arm/boards/edb93xx/flash_cfg.c b/arch/arm/boards/edb93xx/flash_cfg.c index f3b8873bac..8400db69de 100644 --- a/arch/arm/boards/edb93xx/flash_cfg.c +++ b/arch/arm/boards/edb93xx/flash_cfg.c @@ -1,19 +1,7 @@ -/* - * Flash setup for Cirrus edb93xx boards - * - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> + +/* Flash setup for Cirrus edb93xx boards */ #include <common.h> #include <mach/ep93xx-regs.h> @@ -23,6 +11,9 @@ SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \ 1 << SMC_BCR_MW_SHIFT) +/* Called from assembly */ +void flash_cfg(void); + void flash_cfg(void) { struct smc_regs *smc = (struct smc_regs *)SMC_BASE; diff --git a/arch/arm/boards/edb93xx/pll_cfg.c b/arch/arm/boards/edb93xx/pll_cfg.c index 8be679e711..1a1c01aba2 100644 --- a/arch/arm/boards/edb93xx/pll_cfg.c +++ b/arch/arm/boards/edb93xx/pll_cfg.c @@ -1,27 +1,17 @@ -/* - * PLL setup for Cirrus edb93xx boards - * - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> +// SPDX-FileCopyrightText: 2006 Dominic Rath <Dominic.Rath@gmx.de> + +/* PLL setup for Cirrus edb93xx boards */ #include <common.h> #include <io.h> #include "pll_cfg.h" #include "early_udelay.h" +/* Called from assembly */ +void pll_cfg(void); + void pll_cfg(void) { struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; diff --git a/arch/arm/boards/edb93xx/pll_cfg.h b/arch/arm/boards/edb93xx/pll_cfg.h index ad3d896d93..b3258b5f7e 100644 --- a/arch/arm/boards/edb93xx/pll_cfg.h +++ b/arch/arm/boards/edb93xx/pll_cfg.h @@ -1,19 +1,7 @@ -/* - * PLL register values for Cirrus edb93xx boards - * - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> + +/* PLL register values for Cirrus edb93xx boards */ #include <config.h> #include <mach/ep93xx-regs.h> diff --git a/arch/arm/boards/edb93xx/sdram_cfg.c b/arch/arm/boards/edb93xx/sdram_cfg.c index 11e4fd7ca4..3cee834910 100644 --- a/arch/arm/boards/edb93xx/sdram_cfg.c +++ b/arch/arm/boards/edb93xx/sdram_cfg.c @@ -1,19 +1,6 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> +// SPDX-FileCopyrightText: 2006 Dominic Rath <Dominic.Rath@gmx.de> #include <common.h> #include <io.h> @@ -30,6 +17,9 @@ static void precharge_all_banks(void); static void setup_refresh_timer(void); static void program_mode_registers(void); +/* Called from assembly */ +void sdram_cfg(void); + void sdram_cfg(void) { struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; diff --git a/arch/arm/boards/edb93xx/sdram_cfg.h b/arch/arm/boards/edb93xx/sdram_cfg.h index a5720b8694..e1f78443e4 100644 --- a/arch/arm/boards/edb93xx/sdram_cfg.h +++ b/arch/arm/boards/edb93xx/sdram_cfg.h @@ -1,19 +1,6 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> +// SPDX-FileCopyrightText: 2006 Dominic Rath <Dominic.Rath@gmx.de> #include <config.h> #include <mach/ep93xx-regs.h> diff --git a/arch/arm/boards/efika-mx-smartbook/board.c b/arch/arm/boards/efika-mx-smartbook/board.c index ec41eb8c11..bf58eff718 100644 --- a/arch/arm/boards/efika-mx-smartbook/board.c +++ b/arch/arm/boards/efika-mx-smartbook/board.c @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <environment.h> #include <bootsource.h> diff --git a/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg b/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg index 53875ed319..60436e7e37 100644 --- a/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg +++ b/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg @@ -1,6 +1,6 @@ soc imx51 loadaddr 0x90000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x73fa88a0 0x00000000 wm 32 0x73fa850c 0x000020c5 wm 32 0x73fa8510 0x000020c5 diff --git a/arch/arm/boards/element14-warp7/board.c b/arch/arm/boards/element14-warp7/board.c index 84fc885da1..9427b467d0 100644 --- a/arch/arm/boards/element14-warp7/board.c +++ b/arch/arm/boards/element14-warp7/board.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2017 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2017 Sascha Hauer, Pengutronix #include <common.h> #include <init.h> diff --git a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg index 7aa5dd8d45..798f2cbcb0 100644 --- a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg +++ b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg @@ -11,7 +11,7 @@ soc imx7 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx7-ddr-regs.h> diff --git a/arch/arm/boards/eltec-hipercam/board.c b/arch/arm/boards/eltec-hipercam/board.c index 04ad253e6c..e192c4c2f5 100644 --- a/arch/arm/boards/eltec-hipercam/board.c +++ b/arch/arm/boards/eltec-hipercam/board.c @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2015 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Sascha Hauer <s.hauer@pengutronix.de> #include <common.h> #include <init.h> diff --git a/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg b/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg index f04adf86a4..5b422a7867 100644 --- a/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg +++ b/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/eltec-hipercam/lowlevel.c b/arch/arm/boards/eltec-hipercam/lowlevel.c index 2f2cd9aab7..7baed55706 100644 --- a/arch/arm/boards/eltec-hipercam/lowlevel.c +++ b/arch/arm/boards/eltec-hipercam/lowlevel.c @@ -1,17 +1,6 @@ -/* - * Copyright (C) 2015 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Sascha Hauer <s.hauer@pengutronix.de> + #include <common.h> #include <linux/sizes.h> #include <io.h> diff --git a/arch/arm/boards/embedsky-e9/board.c b/arch/arm/boards/embedsky-e9/board.c index e5f92636fb..0938a6d096 100644 --- a/arch/arm/boards/embedsky-e9/board.c +++ b/arch/arm/boards/embedsky-e9/board.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * Copyright (C) 2014 Andrey Panov <rockford@yandex.ru> * @@ -6,16 +8,6 @@ * * based on arch/arm/boards/freescale-mx6-sabrelite/board.c * Copyright (C) 2012 Steffen Trumtrar, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> diff --git a/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg b/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg index 1139312da6..d51dc17a12 100644 --- a/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg +++ b/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x27800000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg b/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg index bdaf60cb4a..afc95d9bd9 100644 --- a/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg +++ b/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020e05a8 0x00000030 wm 32 0x020e05b0 0x00000030 diff --git a/arch/arm/boards/embest-riotboard/board.c b/arch/arm/boards/embest-riotboard/board.c index eb956f1f50..2e0cc9f0ab 100644 --- a/arch/arm/boards/embest-riotboard/board.c +++ b/arch/arm/boards/embest-riotboard/board.c @@ -1,17 +1,6 @@ -/* - * Copyright (C) 2014 Eric Bénard <eric@eukrea.com> - * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Eric Bénard <eric@eukrea.com> +// SPDX-FileCopyrightText: 2013 Lucas Stach <l.stach@pengutronix.de> #include <asm/armlinux.h> #include <asm/io.h> diff --git a/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg b/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg index c9a8098f6d..bc30e4c387 100644 --- a/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg +++ b/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x20000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/eukrea_cpuimx25/Makefile b/arch/arm/boards/eukrea_cpuimx25/Makefile index 0e64b3ee73..1d2171fbdc 100644 --- a/arch/arm/boards/eukrea_cpuimx25/Makefile +++ b/arch/arm/boards/eukrea_cpuimx25/Makefile @@ -1,17 +1,5 @@ -# -# (C) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Eric Bénard <eric@eukrea.com>, Eukrea Electromatique obj-y += eukrea_cpuimx25.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c index e82f43d58e..494b89f53f 100644 --- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c +++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c @@ -1,19 +1,6 @@ -/* - * (C) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2010 Eric Bénard <eric@eukrea.com>, Eukrea Electromatique #include <common.h> #include <init.h> diff --git a/arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg b/arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg index b0c3b69b46..129498ca85 100644 --- a/arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg +++ b/arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg @@ -1,6 +1,6 @@ soc imx25 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0xb8001008 0x00000000 wm 32 0xb8001010 0x00000004 diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c index 9516c137a3..93cd64d90f 100644 --- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c @@ -1,19 +1,7 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2010 Eric Bénard <eric@eukrea.com>, Eukrea Electromatique + #include <common.h> #include <init.h> #include <mach/imx25-regs.h> diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c index 52971ed7ee..e8ac0cc8fa 100644 --- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c +++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c @@ -1,19 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * Copyright (C) 2009 Eric Benard, Eukrea Electromatique * Based on pcm038.c which is : * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * */ #include <common.h> diff --git a/arch/arm/boards/eukrea_cpuimx35/Makefile b/arch/arm/boards/eukrea_cpuimx35/Makefile index dd8f9eb0d4..f1a8e7a5d6 100644 --- a/arch/arm/boards/eukrea_cpuimx35/Makefile +++ b/arch/arm/boards/eukrea_cpuimx35/Makefile @@ -1,17 +1,5 @@ -# -# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Juergen Beisert <jbe@pengutronix.de> obj-y += eukrea_cpuimx35.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c index 220a484bde..9835452ddf 100644 --- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c +++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c @@ -1,25 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * Copyright (C) 2007 Sascha Hauer, Pengutronix * 2009 Marc Kleine-Budde, Pengutronix * (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * * Derived from: * * * mx35_3stack.c - board file for uboot-v1 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * */ #include <common.h> @@ -242,7 +232,7 @@ static int eukrea_cpuimx35_core_init(void) reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR0); reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; - reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT, + reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT; reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR2); reg |= 0x3 << MX35_CCM_CGR2_USB_SHIFT; diff --git a/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg b/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg index 85200bbb50..c1353e2904 100644 --- a/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg +++ b/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg @@ -1,6 +1,6 @@ soc imx35 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53F80004 0x00821000 wm 32 0x53F80004 0x00821000 diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index b641d68873..7970b82136 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -1,18 +1,6 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + #include <common.h> #include <init.h> #include <mach/imx35-regs.h> diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c index bb493d7c64..8d0d4a0e8a 100644 --- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c +++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c @@ -1,19 +1,6 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * (c) 2011 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix +// SPDX-FileCopyrightText: 2011 Eric Bénard <eric@eukrea.com>, Eukrea Electromatique #include <common.h> #include <net.h> diff --git a/arch/arm/boards/eukrea_cpuimx51/flash-header.imxcfg b/arch/arm/boards/eukrea_cpuimx51/flash-header.imxcfg index 5b51106284..85c128c8fd 100644 --- a/arch/arm/boards/eukrea_cpuimx51/flash-header.imxcfg +++ b/arch/arm/boards/eukrea_cpuimx51/flash-header.imxcfg @@ -1,5 +1,5 @@ soc imx51 -dcdofs 0x400 +ivtofs 0x400 loadaddr 0x90000000 wm 32 0x73fa88a0 0x00000200 wm 32 0x73fa850c 0x000020c5 diff --git a/arch/arm/boards/freescale-mx21-ads/imx21ads.c b/arch/arm/boards/freescale-mx21-ads/imx21ads.c index 2c54cd7030..92207b02d3 100644 --- a/arch/arm/boards/freescale-mx21-ads/imx21ads.c +++ b/arch/arm/boards/freescale-mx21-ads/imx21ads.c @@ -1,20 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * Copyright (C) 2009 Ivo Clarysse * * Based on imx27ads.c, * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * */ #include <common.h> diff --git a/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S b/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S index 16739b5577..9b6e4bd472 100644 --- a/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2010 Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com> #include <config.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c index 75a7d5a6b4..b12bb0dd79 100644 --- a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c +++ b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c @@ -1,18 +1,6 @@ -/* - * (C) Copyright 2010 Juergen Beisert - Pengutronix - * (C) Copyright 2011 Wolfram Sang - Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Juergen Beisert, Pengutronix +// SPDX-FileCopyrightText: 2011 Wolfram Sang, Pengutronix #include <common.h> #include <init.h> @@ -91,9 +79,7 @@ static int register_persistent_environment(void) /* use the full partition as our persistent environment storage */ cdev = devfs_add_partition("disk0.1", 0, cdev->size, DEVFS_PARTITION_FIXED, "env0"); - if (IS_ERR(cdev)) - return PTR_ERR(cdev); - return 0; + return PTR_ERR_OR_ZERO(cdev); } static int mx23_evk_devices_init(void) diff --git a/arch/arm/boards/freescale-mx25-3ds/3stack.c b/arch/arm/boards/freescale-mx25-3ds/3stack.c index 1b42a8a9ee..8707e02a64 100644 --- a/arch/arm/boards/freescale-mx25-3ds/3stack.c +++ b/arch/arm/boards/freescale-mx25-3ds/3stack.c @@ -1,18 +1,5 @@ -/* - * (C) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix #include <common.h> #include <init.h> diff --git a/arch/arm/boards/freescale-mx25-3ds/Makefile b/arch/arm/boards/freescale-mx25-3ds/Makefile index acc7c92ec2..dbb2e77ecb 100644 --- a/arch/arm/boards/freescale-mx25-3ds/Makefile +++ b/arch/arm/boards/freescale-mx25-3ds/Makefile @@ -1,17 +1,5 @@ -# -# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Juergen Beisert <jbe@pengutronix.de> lwl-y += lowlevel_init.o obj-y += 3stack.o diff --git a/arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg b/arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg index f195e8c002..8c1a257829 100644 --- a/arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg +++ b/arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg @@ -1,6 +1,6 @@ soc imx25 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0xb8002050 0x0000d843 wm 32 0xb8002054 0x22252521 wm 32 0xb8002058 0x22220a00 diff --git a/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S index 62dac94e4f..9be9c1a77b 100644 --- a/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S @@ -1,18 +1,5 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix #include <linux/sizes.h> #include <asm-generic/memory_layout.h> diff --git a/arch/arm/boards/freescale-mx27-ads/imx27ads.c b/arch/arm/boards/freescale-mx27-ads/imx27ads.c index c0f4e464c1..670ea2186f 100644 --- a/arch/arm/boards/freescale-mx27-ads/imx27ads.c +++ b/arch/arm/boards/freescale-mx27-ads/imx27ads.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> diff --git a/arch/arm/boards/freescale-mx35-3ds/3stack.c b/arch/arm/boards/freescale-mx35-3ds/3stack.c index 97a9968706..5b91c601f8 100644 --- a/arch/arm/boards/freescale-mx35-3ds/3stack.c +++ b/arch/arm/boards/freescale-mx35-3ds/3stack.c @@ -1,24 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * Copyright (C) 2007 Sascha Hauer, Pengutronix * 2009 Marc Kleine-Budde, Pengutronix * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * * Derived from: * * * mx35_3stack.c - board file for uboot-v1 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * */ #include <common.h> diff --git a/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h b/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h index 8222f87e51..9d0d492062 100644 --- a/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h +++ b/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h @@ -1,20 +1,6 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * (C) Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2008 Freescale Semiconductor, Inc. #ifndef __BOARD_MX35_3STACK_H #define __BOARD_MX35_3STACK_H diff --git a/arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg b/arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg index 6eb8bc242c..ea1803b7de 100644 --- a/arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg +++ b/arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg @@ -1,6 +1,6 @@ soc imx35 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0xb8002050 0x0000d843 wm 32 0xb8002054 0x22252521 diff --git a/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S index cb31b699e7..fbc08d8fae 100644 --- a/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S @@ -1,18 +1,5 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix #include <mach/imx35-regs.h> #include <mach/imx-pll.h> diff --git a/arch/arm/boards/freescale-mx51-babbage/board.c b/arch/arm/boards/freescale-mx51-babbage/board.c index 4839aa5683..330d8e4f52 100644 --- a/arch/arm/boards/freescale-mx51-babbage/board.c +++ b/arch/arm/boards/freescale-mx51-babbage/board.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #define pr_fmt(fmt) "babbage: " fmt diff --git a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg index bac6816fee..b4e11fc227 100644 --- a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg +++ b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x90000000 soc imx51 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x73fa88a0 0x00000200 wm 32 0x73fa850c 0x000020c5 wm 32 0x73fa8510 0x000020c5 diff --git a/arch/arm/boards/freescale-mx53-qsb/board.c b/arch/arm/boards/freescale-mx53-qsb/board.c index 0b1c927b81..f2cb5c56e7 100644 --- a/arch/arm/boards/freescale-mx53-qsb/board.c +++ b/arch/arm/boards/freescale-mx53-qsb/board.c @@ -1,18 +1,6 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix +// SPDX-FileCopyrightText: 2011 Marc Kleine-Budde <mkl@pengutronix.de> #include <environment.h> #include <partition.h> diff --git a/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg b/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg index f43b484ee6..2025f5da08 100644 --- a/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg +++ b/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x70000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8554 0x00300000 wm 32 0x53fa8558 0x00300040 wm 32 0x53fa8560 0x00300000 diff --git a/arch/arm/boards/freescale-mx53-smd/board.c b/arch/arm/boards/freescale-mx53-smd/board.c index 2b58f49205..98d3048dac 100644 --- a/arch/arm/boards/freescale-mx53-smd/board.c +++ b/arch/arm/boards/freescale-mx53-smd/board.c @@ -1,18 +1,6 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix +// SPDX-FileCopyrightText: 2011 Marc Kleine-Budde <mkl@pengutronix.de> #include <common.h> #include <environment.h> diff --git a/arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg b/arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg index 95bcd19805..fac4c29019 100644 --- a/arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg +++ b/arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x70000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8554 0x00300000 wm 32 0x53fa8558 0x00300040 wm 32 0x53fa8560 0x00300000 diff --git a/arch/arm/boards/freescale-mx53-vmx53/board.c b/arch/arm/boards/freescale-mx53-vmx53/board.c index 1859aaca26..aa93336ca2 100644 --- a/arch/arm/boards/freescale-mx53-vmx53/board.c +++ b/arch/arm/boards/freescale-mx53-vmx53/board.c @@ -1,19 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o. + /* - * Copyright (C) 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o. - * * Board specific file for Voipac X53-DMM-668 module equipped * with i.MX53 CPU - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> diff --git a/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg b/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg index 3bf73b65aa..e6f73df30e 100644 --- a/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg +++ b/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x70000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8554 0x00300000 wm 32 0x53fa8558 0x00300040 wm 32 0x53fa8560 0x00300000 diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c index 63fa58886c..1b39ef82c6 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/board.c +++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c @@ -1,17 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Steffen Trumtrar, Pengutronix + /* - * Copyright (C) 2012 Steffen Trumtrar, Pengutronix - * * based on arch/arm/boards/freescale-mx6-arm2/board.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> @@ -48,18 +39,6 @@ static iomux_v3_cfg_t sabrelite_enet_gpio_pads[] = { MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24, }; -static int sabrelite_mem_init(void) -{ - if (!of_machine_is_compatible("fsl,imx6q-sabrelite") && - !of_machine_is_compatible("fsl,imx6dl-sabrelite")) - return 0; - - arm_add_mem_device("ram0", 0x10000000, SZ_1G); - - return 0; -} -mem_initcall(sabrelite_mem_init); - static int ksz9021rn_phy_fixup(struct phy_device *dev) { phy_write(dev, 0x09, 0x0f00); @@ -79,37 +58,37 @@ static int ksz9021rn_phy_fixup(struct phy_device *dev) static struct gpio fec_gpios[] = { { - .gpio = 87, + .gpio = IMX_GPIO_NR(3, 23), .flags = GPIOF_OUT_INIT_LOW, .label = "phy-rst", }, { - .gpio = 190, + .gpio = IMX_GPIO_NR(6, 30), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-addr2", }, { - .gpio = 23, + .gpio = IMX_GPIO_NR(1, 23), .flags = GPIOF_OUT_INIT_LOW, .label = "phy-led-mode", }, { /* MODE strap-in pins: advertise all capabilities */ - .gpio = 185, + .gpio = IMX_GPIO_NR(6, 25), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-adv1", }, { - .gpio = 187, + .gpio = IMX_GPIO_NR(6, 27), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-adv1", }, { - .gpio = 188, + .gpio = IMX_GPIO_NR(6, 28), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-adv1", }, { - .gpio = 189, + .gpio = IMX_GPIO_NR(6, 29), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-adv1", }, { /* Enable 125 MHz clock output */ - .gpio = 184, + .gpio = IMX_GPIO_NR(6, 24), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-125MHz", }, @@ -148,9 +127,9 @@ fs_initcall(sabrelite_ksz9021rn_setup); static void sabrelite_ehci_init(void) { /* hub reset */ - gpio_direction_output(204, 0); + gpio_direction_output(IMX_GPIO_NR(7, 12), 0); udelay(2000); - gpio_set_value(204, 1); + gpio_set_value(IMX_GPIO_NR(7, 12), 1); } static int sabrelite_devices_init(void) diff --git a/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg b/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg index 3ce8562f51..d635c8b948 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg +++ b/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/freescale-mx6-sabresd/board.c b/arch/arm/boards/freescale-mx6-sabresd/board.c index a5059835df..b710c05a47 100644 --- a/arch/arm/boards/freescale-mx6-sabresd/board.c +++ b/arch/arm/boards/freescale-mx6-sabresd/board.c @@ -1,18 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * Copyright (C) 2013 Hubert Feurstein <h.feurstein@gmail.com> * * based on arch/arm/boards/freescale-mx6-sabrelite/board.c * Copyright (C) 2012 Steffen Trumtrar, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> diff --git a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg index 21f217cdf3..133f499ab9 100644 --- a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg +++ b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x20e05a8 0x00000030 wm 32 0x20e05b0 0x00000030 wm 32 0x20e0524 0x00000030 diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/board.c b/arch/arm/boards/freescale-mx6sx-sabresdb/board.c index 0fd9af80cb..3285e1f290 100644 --- a/arch/arm/boards/freescale-mx6sx-sabresdb/board.c +++ b/arch/arm/boards/freescale-mx6sx-sabresdb/board.c @@ -1,16 +1,6 @@ -/* - * Copyright (C) 2014 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sascha Hauer, Pengutronix + #define pr_fmt(fmt) "imx6sx-sdb: " fmt #include <environment.h> diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg b/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg index a96b3e7154..5536f342b4 100644 --- a/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg +++ b/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c b/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c index 6a6e27bf44..d3b58ac1be 100644 --- a/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c +++ b/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2014 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sascha Hauer, Pengutronix #include <debug_ll.h> #include <common.h> diff --git a/arch/arm/boards/freescale-mx7-sabresd/board.c b/arch/arm/boards/freescale-mx7-sabresd/board.c index 37941efdbe..e41d67017f 100644 --- a/arch/arm/boards/freescale-mx7-sabresd/board.c +++ b/arch/arm/boards/freescale-mx7-sabresd/board.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2017 Zodiac Inflight Innovation - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2017 Zodiac Inflight Innovation + +/* Author: Andrey Smirnov <andrew.smirnov@gmail.com> */ #include <common.h> #include <init.h> diff --git a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg index f4920bc133..41e0e9ca61 100644 --- a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg +++ b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg @@ -1,5 +1,5 @@ soc imx7 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/flash-header/imx7d-ddr-sabresd.imxcfg>
\ No newline at end of file diff --git a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg index 71150802bf..bcef9921fa 100644 --- a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg +++ b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg @@ -1,6 +1,6 @@ soc vf610 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/vf610-iomux-regs.h> #include <mach/vf610-ddrmc-regs.h> diff --git a/arch/arm/boards/friendlyarm-mini2440/config.h b/arch/arm/boards/friendlyarm-mini2440/config.h index 489697f6d5..86c78e54f6 100644 --- a/arch/arm/boards/friendlyarm-mini2440/config.h +++ b/arch/arm/boards/friendlyarm-mini2440/config.h @@ -1,18 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /** * @file * @brief Global defintions for the ARM S3C2440 based mini2440 CPU card */ -/* This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ #ifndef __CONFIG_H #define __CONFIG_H diff --git a/arch/arm/boards/friendlyarm-mini2440/mini2440.c b/arch/arm/boards/friendlyarm-mini2440/mini2440.c index 7f59cb99b2..413537d247 100644 --- a/arch/arm/boards/friendlyarm-mini2440/mini2440.c +++ b/arch/arm/boards/friendlyarm-mini2440/mini2440.c @@ -1,19 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * Copyright (C) 2010 Marek Belisko <marek.belisko@open-nandra.com> * * Based on a9m2440.c board init by Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * */ #include <common.h> diff --git a/arch/arm/boards/friendlyarm-mini6410/mini6410.c b/arch/arm/boards/friendlyarm-mini6410/mini6410.c index 90fb3f5c1e..3f5e8ca2a3 100644 --- a/arch/arm/boards/friendlyarm-mini6410/mini6410.c +++ b/arch/arm/boards/friendlyarm-mini6410/mini6410.c @@ -1,16 +1,6 @@ -/* - * Copyright (C) 2012 Juergen Beisert - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Juergen Beisert + #include <common.h> #include <driver.h> #include <init.h> diff --git a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c b/arch/arm/boards/friendlyarm-tiny210/lowlevel.c index 875c17677e..d79661b222 100644 --- a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c +++ b/arch/arm/boards/friendlyarm-tiny210/lowlevel.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2012 Alexey Galakhov - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2012 Alexey Galakhov #include <config.h> #include <common.h> diff --git a/arch/arm/boards/friendlyarm-tiny210/tiny210.c b/arch/arm/boards/friendlyarm-tiny210/tiny210.c index b40dc98c5b..c96aa83059 100644 --- a/arch/arm/boards/friendlyarm-tiny210/tiny210.c +++ b/arch/arm/boards/friendlyarm-tiny210/tiny210.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * Copyright (C) 2012 Alexey Galakhov * Based on Mini6410 code by Juergen Beisert @@ -12,16 +14,6 @@ * * (C) Copyright 2002 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> diff --git a/arch/arm/boards/friendlyarm-tiny6410/development-board.c b/arch/arm/boards/friendlyarm-tiny6410/development-board.c index 5dd05e4cc8..69c9768405 100644 --- a/arch/arm/boards/friendlyarm-tiny6410/development-board.c +++ b/arch/arm/boards/friendlyarm-tiny6410/development-board.c @@ -1,24 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Juergen Beisert + /* - * Copyright (C) 2012 Juergen Beisert - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * The FriendlyARM's Tiny6410 evaluation board comes with all connectors and * devices to make the Tiny6410 CPU card work. This includes: * * - the DM9000 network controller * - USB/MCI connectors * - display connector - * */ + #include <common.h> #include <driver.h> #include <init.h> diff --git a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c b/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c index 39179c83d8..a1126b7893 100644 --- a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c +++ b/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c @@ -1,16 +1,6 @@ -/* - * Copyright (C) 2012 Juergen Beisert - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Juergen Beisert + #include <common.h> #include <driver.h> #include <init.h> diff --git a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.h b/arch/arm/boards/friendlyarm-tiny6410/tiny6410.h index 98db422422..bbe8877ca0 100644 --- a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.h +++ b/arch/arm/boards/friendlyarm-tiny6410/tiny6410.h @@ -1,14 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later /* to be called by the base board */ void tiny6410_init(const char*); diff --git a/arch/arm/boards/gateworks-ventana/board.c b/arch/arm/boards/gateworks-ventana/board.c index 6f9e0343be..163f8338c6 100644 --- a/arch/arm/boards/gateworks-ventana/board.c +++ b/arch/arm/boards/gateworks-ventana/board.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2014 Lucas Stach, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Lucas Stach, Pengutronix #include <common.h> #include <environment.h> diff --git a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg index b9a6fc12ff..98c7ae6095 100644 --- a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg +++ b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/gateworks-ventana/gsc.c b/arch/arm/boards/gateworks-ventana/gsc.c index 92244d12da..ae639bca86 100644 --- a/arch/arm/boards/gateworks-ventana/gsc.c +++ b/arch/arm/boards/gateworks-ventana/gsc.c @@ -1,17 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Gateworks Corporation +// SPDX-FileCopyrightText: 2014 Lucas Stach, Pengutronix + /* - * Copyright (C) 2013 Gateworks Corporation - * Copyright (C) 2014 Lucas Stach, Pengutronix * Author: Tim Harvey <tharvey@gateworks.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ /* diff --git a/arch/arm/boards/gateworks-ventana/gsc.h b/arch/arm/boards/gateworks-ventana/gsc.h index 13f226265c..c2fb535d15 100644 --- a/arch/arm/boards/gateworks-ventana/gsc.h +++ b/arch/arm/boards/gateworks-ventana/gsc.h @@ -1,17 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Gateworks Corporation +// SPDX-FileCopyrightText: 2014 Lucas Stach, Pengutronix + /* - * Copyright (C) 2013 Gateworks Corporation - * Copyright (C) 2014 Lucas Stach, Pengutronix * Author: Tim Harvey <tharvey@gateworks.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ /* i2c slave addresses */ diff --git a/arch/arm/boards/gk802/board.c b/arch/arm/boards/gk802/board.c index 0d1b07b0e0..2713d6e756 100644 --- a/arch/arm/boards/gk802/board.c +++ b/arch/arm/boards/gk802/board.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Philipp Zabel - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Philipp Zabel #include <asm/armlinux.h> #include <asm/io.h> diff --git a/arch/arm/boards/gk802/flash-header.imxcfg b/arch/arm/boards/gk802/flash-header.imxcfg index f26fe77b03..acc7a36785 100644 --- a/arch/arm/boards/gk802/flash-header.imxcfg +++ b/arch/arm/boards/gk802/flash-header.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/globalscale-guruplug/lowlevel.c b/arch/arm/boards/globalscale-guruplug/lowlevel.c index 92424cbd6b..964d3510ee 100644 --- a/arch/arm/boards/globalscale-guruplug/lowlevel.c +++ b/arch/arm/boards/globalscale-guruplug/lowlevel.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2014 - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/globalscale-mirabox/lowlevel.c b/arch/arm/boards/globalscale-mirabox/lowlevel.c index 69786c88fb..094792d461 100644 --- a/arch/arm/boards/globalscale-mirabox/lowlevel.c +++ b/arch/arm/boards/globalscale-mirabox/lowlevel.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2014 - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/grinn-liteboard/board.c b/arch/arm/boards/grinn-liteboard/board.c index 8e5a91e124..3e69ea520a 100644 --- a/arch/arm/boards/grinn-liteboard/board.c +++ b/arch/arm/boards/grinn-liteboard/board.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2018 Grinn - * - * Author: Marcin Niestroj <m.niestroj@grinn-global.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2018 Grinn + +/* Author: Marcin Niestroj <m.niestroj@grinn-global.com> */ #define pr_fmt(fmt) "liteboard: " fmt diff --git a/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h b/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h index 60a39f524b..82f5c627a3 100644 --- a/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h +++ b/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h @@ -1,7 +1,7 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/grinn-liteboard/lowlevel.c b/arch/arm/boards/grinn-liteboard/lowlevel.c index bb2e09016e..d3ee212ca9 100644 --- a/arch/arm/boards/grinn-liteboard/lowlevel.c +++ b/arch/arm/boards/grinn-liteboard/lowlevel.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2018 Grinn - * - * Author: Marcin Niestroj <m.niestroj@grinn-global.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2018 Grinn + +/* Author: Marcin Niestroj <m.niestroj@grinn-global.com> */ #include <debug_ll.h> #include <common.h> diff --git a/arch/arm/boards/guf-cupid/Makefile b/arch/arm/boards/guf-cupid/Makefile index 868d062220..86a27f301d 100644 --- a/arch/arm/boards/guf-cupid/Makefile +++ b/arch/arm/boards/guf-cupid/Makefile @@ -1,17 +1,5 @@ -# -# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Juergen Beisert <jbe@pengutronix.de> lwl-y += lowlevel.o obj-y += board.o diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c index 60175c14bb..0c62b573c9 100644 --- a/arch/arm/boards/guf-cupid/board.c +++ b/arch/arm/boards/guf-cupid/board.c @@ -1,20 +1,8 @@ -/* - * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (C) 2009 Pengutronix, Juergen Beisert <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * Board support for the Garz+Fricke Cupid board - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2009 Juergen Beisert <kernel@pengutronix.de>, Pengutronix + +/* Board support for the Garz+Fricke Cupid board */ #include <common.h> #include <command.h> diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c index 3684dacfc7..6b6590f5d8 100644 --- a/arch/arm/boards/guf-cupid/lowlevel.c +++ b/arch/arm/boards/guf-cupid/lowlevel.c @@ -1,18 +1,6 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + #include <common.h> #include <init.h> #include <mach/imx35-regs.h> diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c index 6846ba5793..9eb862db64 100644 --- a/arch/arm/boards/guf-neso/board.c +++ b/arch/arm/boards/guf-neso/board.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2010 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c index 07e426d537..df91bc329f 100644 --- a/arch/arm/boards/guf-neso/lowlevel.c +++ b/arch/arm/boards/guf-neso/lowlevel.c @@ -1,18 +1,6 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + #include <common.h> #include <init.h> #include <mach/imx27-regs.h> diff --git a/arch/arm/boards/guf-santaro/board.c b/arch/arm/boards/guf-santaro/board.c index e54110886b..34005ff7bf 100644 --- a/arch/arm/boards/guf-santaro/board.c +++ b/arch/arm/boards/guf-santaro/board.c @@ -1,16 +1,6 @@ -/* - * Copyright (C) 2014 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sascha Hauer <s.hauer@pengutronix.de> + #define pr_fmt(fmt) "Santaro: " fmt #include <common.h> diff --git a/arch/arm/boards/guf-santaro/flash-header.imxcfg b/arch/arm/boards/guf-santaro/flash-header.imxcfg index 2e85e13ba9..4505d81ea1 100644 --- a/arch/arm/boards/guf-santaro/flash-header.imxcfg +++ b/arch/arm/boards/guf-santaro/flash-header.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/guf-vincell/board.c b/arch/arm/boards/guf-vincell/board.c index 007b6dd347..c0bb9d9e74 100644 --- a/arch/arm/boards/guf-vincell/board.c +++ b/arch/arm/boards/guf-vincell/board.c @@ -1,18 +1,6 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix +// SPDX-FileCopyrightText: 2011 Marc Kleine-Budde <mkl@pengutronix.de> #include <common.h> #include <environment.h> diff --git a/arch/arm/boards/guf-vincell/flash-header.imxcfg b/arch/arm/boards/guf-vincell/flash-header.imxcfg index 8bfb5d0508..c17dcbab6e 100644 --- a/arch/arm/boards/guf-vincell/flash-header.imxcfg +++ b/arch/arm/boards/guf-vincell/flash-header.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x71000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 //============================================================================= //init script for i.MX53 DDR3 diff --git a/arch/arm/boards/haba-knx/init.c b/arch/arm/boards/haba-knx/init.c index 55441b63af..21ae63a64f 100644 --- a/arch/arm/boards/haba-knx/init.c +++ b/arch/arm/boards/haba-knx/init.c @@ -1,19 +1,6 @@ -/* - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD - * Copyright (C) 2014 Gregory Hermant <gregory.hermant@calao-systems.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011-2012 Jean-Christophe PLAGNIOL-VILLARD +// SPDX-FileCopyrightText: 2014 Gregory Hermant <gregory.hermant@calao-systems.com> #include <common.h> #include <net.h> diff --git a/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c b/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c index af548b3c53..14100747e0 100644 --- a/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c +++ b/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c @@ -1,20 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * (C) Copyright 2012 Fadil Berisha, <fadil.r.berisha@gmail.com> * based on falconwing.c & mx23-evk.c * * (C) Copyright 2010 Juergen Beisert - Pengutronix * (C) Copyright 2011 Wolfram Sang - Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> diff --git a/arch/arm/boards/karo-tx25/Makefile b/arch/arm/boards/karo-tx25/Makefile index 02044f162f..2960516c5a 100644 --- a/arch/arm/boards/karo-tx25/Makefile +++ b/arch/arm/boards/karo-tx25/Makefile @@ -1,17 +1,5 @@ -# -# (C) Copyright 2011 Sascha Hauer <s.hauer@pengutronix.de> -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Sascha Hauer <s.hauer@pengutronix.de> lwl-y += lowlevel.o obj-y += board.o diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c index e2a6dcc089..6086da53cc 100644 --- a/arch/arm/boards/karo-tx25/board.c +++ b/arch/arm/boards/karo-tx25/board.c @@ -1,18 +1,5 @@ -/* - * (C) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix #define pr_fmt(fmt) "tx25: " fmt diff --git a/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg b/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg index 2345f18e93..6f8eaf0fc5 100644 --- a/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg +++ b/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg @@ -4,7 +4,7 @@ # soc imx25 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0xb8001010 0x00000002 wm 32 0xb8001004 0x00095728 wm 32 0xb8001000 0x92116480 diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c index dff72be98c..f20c659d5d 100644 --- a/arch/arm/boards/karo-tx25/lowlevel.c +++ b/arch/arm/boards/karo-tx25/lowlevel.c @@ -1,18 +1,6 @@ -/* - * - * (c) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + #include <common.h> #include <init.h> #include <mach/imx25-regs.h> diff --git a/arch/arm/boards/karo-tx28/tx28-stk5.c b/arch/arm/boards/karo-tx28/tx28-stk5.c index 8628db2b25..56211d7a3a 100644 --- a/arch/arm/boards/karo-tx28/tx28-stk5.c +++ b/arch/arm/boards/karo-tx28/tx28-stk5.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2010 Juergen Beisert, Pengutronix <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Juergen Beisert <kernel@pengutronix.de>, Pengutronix #include <common.h> #include <init.h> @@ -33,6 +22,8 @@ #include <mach/iomux.h> #include <generated/mach-types.h> +#include "tx28.h" + static struct mxs_mci_platform_data mci_pdata = { .caps = MMC_CAP_4_BIT_DATA, .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, /* fixed to 3.3 V */ @@ -344,9 +335,7 @@ static int register_persistent_environment(void) /* use the full partition as our persistent environment storage */ cdev = devfs_add_partition("disk0.1", 0, cdev->size, DEVFS_PARTITION_FIXED, "env0"); - if (IS_ERR(cdev)) - return PTR_ERR(cdev); - return 0; + return PTR_ERR_OR_ZERO(cdev); } static void tx28_get_ethaddr(void) diff --git a/arch/arm/boards/karo-tx28/tx28.c b/arch/arm/boards/karo-tx28/tx28.c index d99083b190..8bd2252410 100644 --- a/arch/arm/boards/karo-tx28/tx28.c +++ b/arch/arm/boards/karo-tx28/tx28.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2010 Juergen Beisert, Pengutronix <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Juergen Beisert <kernel@pengutronix.de>, Pengutronix #include <common.h> #include <init.h> @@ -26,6 +15,8 @@ #include <mach/iomux.h> #include <asm/mmu.h> +#include "tx28.h" + /* setup the CPU card internal signals */ static const uint32_t tx28_pad_setup[] = { /* NAND interface */ @@ -72,8 +63,6 @@ static const uint32_t tx28_pad_setup[] = { }; -extern void base_board_init(void); - static int tx28_devices_init(void) { int i; diff --git a/arch/arm/boards/karo-tx28/tx28.h b/arch/arm/boards/karo-tx28/tx28.h new file mode 100644 index 0000000000..5fb1e13412 --- /dev/null +++ b/arch/arm/boards/karo-tx28/tx28.h @@ -0,0 +1,3 @@ + +void base_board_init(void); + diff --git a/arch/arm/boards/karo-tx51/flash-header-karo-tx51.imxcfg b/arch/arm/boards/karo-tx51/flash-header-karo-tx51.imxcfg index ebb7c4f396..4aaa75a0ea 100644 --- a/arch/arm/boards/karo-tx51/flash-header-karo-tx51.imxcfg +++ b/arch/arm/boards/karo-tx51/flash-header-karo-tx51.imxcfg @@ -1,6 +1,6 @@ soc imx51 loadaddr 0x90000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x83fd9000 0x80000000 wm 32 0x83fd9014 0x04008008 wm 32 0x83fd9014 0x00008010 diff --git a/arch/arm/boards/karo-tx51/tx51.c b/arch/arm/boards/karo-tx51/tx51.c index 913df68cc9..23088e62f2 100644 --- a/arch/arm/boards/karo-tx51/tx51.c +++ b/arch/arm/boards/karo-tx51/tx51.c @@ -1,19 +1,6 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * Copyright (C) 2012 Christian Kapeller, <christian.kapeller@cmotion.eu> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix +// SPDX-FileCopyrightText: 2012 Christian Kapeller <christian.kapeller@cmotion.eu> #include <common.h> #include <init.h> diff --git a/arch/arm/boards/karo-tx53/board.c b/arch/arm/boards/karo-tx53/board.c index 9f1485ad0b..738faf8f18 100644 --- a/arch/arm/boards/karo-tx53/board.c +++ b/arch/arm/boards/karo-tx53/board.c @@ -1,17 +1,6 @@ -/* - * Copyright (C) 2012 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Sascha Hauer, Pengutronix + #include <common.h> #include <bootsource.h> #include <environment.h> diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg index d5e6454b88..4bcb3b8b5e 100644 --- a/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg +++ b/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x71000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fd406c 0xffffffff wm 32 0x53fd4070 0xffffffff diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg index 6962abd5e6..a4e3fab9a3 100644 --- a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg +++ b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x71000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8004 0x00194005 /* set LDO to 1.3V */ diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg index 2b47d63bd4..5b6b79f705 100644 --- a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg +++ b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x71000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fd4068 0xffcc0fff wm 32 0x53fd406c 0x000fffc3 wm 32 0x53fd4070 0x0f3c0000 diff --git a/arch/arm/boards/karo-tx6x/board.c b/arch/arm/boards/karo-tx6x/board.c index 54b1e248f4..2a141be61a 100644 --- a/arch/arm/boards/karo-tx6x/board.c +++ b/arch/arm/boards/karo-tx6x/board.c @@ -1,19 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * Copyright (C) 2014 Steffen Trumtrar, Pengutronix * - * * with the PMIC init code taken from u-boot * Copyright (C) 2012,2013 Lothar Waßmann <LW@KARO-electronics.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #define pr_fmt(fmt) "Karo-tx6: " fmt diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg index b7a914fba5..7d77f54f00 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg index 3f6578e19c..eb63fa34d3 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg index 165b69fb19..e5a1ed2331 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg index fc00de957c..889416b849 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/karo-tx6x/lowlevel.c b/arch/arm/boards/karo-tx6x/lowlevel.c index f0ddac284c..a80862025a 100644 --- a/arch/arm/boards/karo-tx6x/lowlevel.c +++ b/arch/arm/boards/karo-tx6x/lowlevel.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2014 Steffen Trumtrar, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Steffen Trumtrar, Pengutronix #include <debug_ll.h> #include <common.h> diff --git a/arch/arm/boards/karo-tx6x/pmic-ltc3676.c b/arch/arm/boards/karo-tx6x/pmic-ltc3676.c index 7f594e2008..4e96fdeca7 100644 --- a/arch/arm/boards/karo-tx6x/pmic-ltc3676.c +++ b/arch/arm/boards/karo-tx6x/pmic-ltc3676.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2014 Lothar Waßmann <LW@KARO-electronics.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lothar Waßmann <LW@KARO-electronics.de> #include <common.h> #include <i2c/i2c.h> diff --git a/arch/arm/boards/karo-tx6x/pmic-rn5t567.c b/arch/arm/boards/karo-tx6x/pmic-rn5t567.c index db21b4de6f..fefb1f74fe 100644 --- a/arch/arm/boards/karo-tx6x/pmic-rn5t567.c +++ b/arch/arm/boards/karo-tx6x/pmic-rn5t567.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2014 Lothar Waßmann <LW@KARO-electronics.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lothar Waßmann <LW@KARO-electronics.de> #include <common.h> #include <i2c/i2c.h> diff --git a/arch/arm/boards/karo-tx6x/pmic-rn5t618.c b/arch/arm/boards/karo-tx6x/pmic-rn5t618.c index bdec02e9d4..4154ed23ad 100644 --- a/arch/arm/boards/karo-tx6x/pmic-rn5t618.c +++ b/arch/arm/boards/karo-tx6x/pmic-rn5t618.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2014 Lothar Waßmann <LW@KARO-electronics.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lothar Waßmann <LW@KARO-electronics.de> #include <common.h> #include <i2c/i2c.h> diff --git a/arch/arm/boards/kindle-mx50/board.c b/arch/arm/boards/kindle-mx50/board.c index bfcb9b83be..8fc5af8320 100644 --- a/arch/arm/boards/kindle-mx50/board.c +++ b/arch/arm/boards/kindle-mx50/board.c @@ -1,18 +1,6 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * Copyright (C) 2017 Alexander Kurz <akurz@blala.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix +// SPDX-FileCopyrightText: 2017 Alexander Kurz <akurz@blala.de> #include <common.h> #include <envfs.h> @@ -72,9 +60,9 @@ static const char *get_env_16char_tag(const char *tag) return value; } -BAREBOX_MAGICVAR_NAMED(global_atags_serial16, global.board.serial16, +BAREBOX_MAGICVAR(global.board.serial16, "Pass the kindle Serial as vendor-specific ATAG to linux"); -BAREBOX_MAGICVAR_NAMED(global_atags_revision16, global.board.revision16, +BAREBOX_MAGICVAR(global.board.revision16, "Pass the kindle BoardId as vendor-specific ATAG to linux"); /* The Kindle Kernel expects two custom ATAGs, ATAG_REVISION16 describing diff --git a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg index fae10423c5..b8a4e824ef 100644 --- a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg +++ b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg @@ -7,7 +7,7 @@ soc imx50 loadaddr 0x70020000 -dcdofs 0x400 +ivtofs 0x400 # Switch pll1_sw_clk to step_clk wm 32 0x53fd400c 0x00000004 diff --git a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg index 94436a7b54..527d91dc78 100644 --- a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg +++ b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg @@ -8,7 +8,7 @@ soc imx50 loadaddr 0x70020000 -dcdofs 0x400 +ivtofs 0x400 # Switch pll1_sw_clk to step_clk wm 32 0x53fd400c 0x00000004 diff --git a/arch/arm/boards/kindle3/flash-header.imxcfg b/arch/arm/boards/kindle3/flash-header.imxcfg index cb56acf9cd..74b65d6a5c 100644 --- a/arch/arm/boards/kindle3/flash-header.imxcfg +++ b/arch/arm/boards/kindle3/flash-header.imxcfg @@ -1,6 +1,6 @@ soc imx35 loadaddr 0x87eff400 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53f80004 0x00821000 wm 32 0x53f80004 0x00821000 diff --git a/arch/arm/boards/kindle3/kindle3.c b/arch/arm/boards/kindle3/kindle3.c index 7c0d60efe0..a593dc424d 100644 --- a/arch/arm/boards/kindle3/kindle3.c +++ b/arch/arm/boards/kindle3/kindle3.c @@ -1,19 +1,8 @@ -/* - * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (C) 2016 Alexander Kurz <akurz@blala.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Board support for the Amazon Kindle 3rd generation - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2016 Alexander Kurz <akurz@blala.de> + +/* Board support for the Amazon Kindle 3rd generation */ #include <common.h> #include <command.h> @@ -75,9 +64,9 @@ static const char *get_env_16char_tag(const char *tag) return value; } -BAREBOX_MAGICVAR_NAMED(global_atags_serial16, global.board.serial16, +BAREBOX_MAGICVAR(global.board.serial16, "Pass the kindle Serial as vendor-specific ATAG to linux"); -BAREBOX_MAGICVAR_NAMED(global_atags_revision16, global.board.revision16, +BAREBOX_MAGICVAR(global.board.revision16, "Pass the kindle BoardId as vendor-specific ATAG to linux"); /* The Kindle3 Kernel expects two custom ATAGs, ATAG_REVISION16 describing diff --git a/arch/arm/boards/kindle3/lowlevel.c b/arch/arm/boards/kindle3/lowlevel.c index 83a0ccc70e..251bcf9d42 100644 --- a/arch/arm/boards/kindle3/lowlevel.c +++ b/arch/arm/boards/kindle3/lowlevel.c @@ -1,19 +1,7 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (c) 2016 Alexander Kurz <akurz@blala.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2016 Alexander Kurz <akurz@blala.de> + #include <common.h> #include <init.h> #include <mach/imx35-regs.h> diff --git a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg index 9906617083..db1698d272 100644 --- a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg +++ b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020e0774 0x000c0000 wm 32 0x020e0754 0x00000000 diff --git a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg index 7e6ffd7983..99608d0fe8 100644 --- a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg +++ b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020e05a8 0x00000030 wm 32 0x020e05b0 0x00000030 diff --git a/arch/arm/boards/lenovo-ix4-300d/lowlevel.c b/arch/arm/boards/lenovo-ix4-300d/lowlevel.c index 40145b5cef..c0a695908f 100644 --- a/arch/arm/boards/lenovo-ix4-300d/lowlevel.c +++ b/arch/arm/boards/lenovo-ix4-300d/lowlevel.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2014, 2015 - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014, 2015 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <asm/barebox-arm.h> diff --git a/arch/arm/boards/lubbock/board.c b/arch/arm/boards/lubbock/board.c index 118de04c7e..2f3b6ad16b 100644 --- a/arch/arm/boards/lubbock/board.c +++ b/arch/arm/boards/lubbock/board.c @@ -1,17 +1,5 @@ -/* - * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Robert Jarzmik <robert.jarzmik@free.fr> #include <common.h> #include <driver.h> diff --git a/arch/arm/boards/lxa-mc1/board.c b/arch/arm/boards/lxa-mc1/board.c index 7f1f3ccd7e..9126973dcb 100644 --- a/arch/arm/boards/lxa-mc1/board.c +++ b/arch/arm/boards/lxa-mc1/board.c @@ -28,11 +28,9 @@ static int of_fixup_regulator_supply_disable(struct device_node *root, void *pat return 0; } -static int mc1_device_init(void) +static int mc1_probe(struct device_d *dev) { int flags; - if (!of_machine_is_compatible("lxa,stm32mp157c-mc1")) - return 0; flags = bootsource_get_instance() == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0; stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", flags); @@ -55,4 +53,15 @@ static int mc1_device_init(void) */ return of_register_fixup(of_fixup_regulator_supply_disable, "/regulator_3v3"); } -device_initcall(mc1_device_init); + +static const struct of_device_id mc1_of_match[] = { + { .compatible = "lxa,stm32mp157c-mc1" }, + { /* sentinel */ }, +}; + +static struct driver_d mc1_board_driver = { + .name = "board-lxa-mc1", + .probe = mc1_probe, + .of_compatible = mc1_of_match, +}; +device_platform_driver(mc1_board_driver); diff --git a/arch/arm/boards/mainstone/board.c b/arch/arm/boards/mainstone/board.c index 78c9bdc352..f95bf057a7 100644 --- a/arch/arm/boards/mainstone/board.c +++ b/arch/arm/boards/mainstone/board.c @@ -1,17 +1,5 @@ -/* - * (C) 2015 Robert Jarzmik <robert.jarzmik@free.fr> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Robert Jarzmik <robert.jarzmik@free.fr> #include <common.h> #include <driver.h> diff --git a/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c b/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c index e62627c324..43b1ba8c9a 100644 --- a/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c +++ b/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2014 - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/mioa701/board.c b/arch/arm/boards/mioa701/board.c index cd166efceb..963fefbf77 100644 --- a/arch/arm/boards/mioa701/board.c +++ b/arch/arm/boards/mioa701/board.c @@ -1,17 +1,5 @@ -/* - * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Robert Jarzmik <robert.jarzmik@free.fr> #include <common.h> #include <driver.h> diff --git a/arch/arm/boards/mioa701/gpio0_poweroff.c b/arch/arm/boards/mioa701/gpio0_poweroff.c index 4b34922507..41d886d74b 100644 --- a/arch/arm/boards/mioa701/gpio0_poweroff.c +++ b/arch/arm/boards/mioa701/gpio0_poweroff.c @@ -1,17 +1,5 @@ -/* - * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Robert Jarzmik <robert.jarzmik@free.fr> #include <clock.h> #include <common.h> @@ -73,7 +61,7 @@ static struct poller_struct gpio0_poller = { static int gpio0_poweroff_probe(void) { - return poller_register(&gpio0_poller); + return poller_register(&gpio0_poller, "power-button"); } device_initcall(gpio0_poweroff_probe); diff --git a/arch/arm/boards/mioa701/mioa701.h b/arch/arm/boards/mioa701/mioa701.h index ba94212b33..5f6d5e65f7 100644 --- a/arch/arm/boards/mioa701/mioa701.h +++ b/arch/arm/boards/mioa701/mioa701.h @@ -1,17 +1,6 @@ -/* - * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Robert Jarzmik <robert.jarzmik@free.fr> + #ifndef _MIOA701_H_ #define _MIOA701_H_ diff --git a/arch/arm/boards/module-mb7707/board.c b/arch/arm/boards/module-mb7707/board.c index 1ab6e7d7c1..c4f78a8135 100644 --- a/arch/arm/boards/module-mb7707/board.c +++ b/arch/arm/boards/module-mb7707/board.c @@ -1,18 +1,7 @@ -/* - * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com> - * - * This file is part of barebox. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Antony Pavlov <antonynpavlov@gmail.com> + +/* This file is part of barebox. */ #include <common.h> #include <init.h> diff --git a/arch/arm/boards/module-mb7707/lowlevel.c b/arch/arm/boards/module-mb7707/lowlevel.c index b388778f8a..3b529d1232 100644 --- a/arch/arm/boards/module-mb7707/lowlevel.c +++ b/arch/arm/boards/module-mb7707/lowlevel.c @@ -1,18 +1,7 @@ -/* - * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com> - * - * This file is part of barebox. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Antony Pavlov <antonynpavlov@gmail.com> + +/* This file is part of barebox. */ #define __LOWLEVEL_INIT__ diff --git a/arch/arm/boards/mx31moboard/Makefile b/arch/arm/boards/mx31moboard/Makefile index abc1f313ac..17f4aa47ee 100644 --- a/arch/arm/boards/mx31moboard/Makefile +++ b/arch/arm/boards/mx31moboard/Makefile @@ -1,17 +1,5 @@ -# -# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Juergen Beisert <jbe@pengutronix.de> lwl-y += lowlevel.o obj-y += mx31moboard.o diff --git a/arch/arm/boards/mx31moboard/lowlevel.c b/arch/arm/boards/mx31moboard/lowlevel.c index 967dcc48ee..cec98f34c1 100644 --- a/arch/arm/boards/mx31moboard/lowlevel.c +++ b/arch/arm/boards/mx31moboard/lowlevel.c @@ -1,19 +1,7 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (c) 2014 EPFL, Philippe Rétornaz <philippe.retornaz@epfl.ch> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2014 Philippe Rétornaz <philippe.retornaz@epfl.ch>, EPFL + #include <common.h> #include <init.h> #include <io.h> diff --git a/arch/arm/boards/mx31moboard/mx31moboard.c b/arch/arm/boards/mx31moboard/mx31moboard.c index d6329e5775..b53d70ab45 100644 --- a/arch/arm/boards/mx31moboard/mx31moboard.c +++ b/arch/arm/boards/mx31moboard/mx31moboard.c @@ -1,18 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2014 Philippe Rétornaz <philippe.retornaz@epfl.ch>, EPFL + /* - * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (C) 2014 EPFL, Philippe Rétornaz <philippe.retornaz@epfl.ch> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * * Board support for EPFL's, i.MX31 based CPU card * * Based on: diff --git a/arch/arm/boards/netgear-rn2120/lowlevel.c b/arch/arm/boards/netgear-rn2120/lowlevel.c index e05f2f4c17..c78d3644b5 100644 --- a/arch/arm/boards/netgear-rn2120/lowlevel.c +++ b/arch/arm/boards/netgear-rn2120/lowlevel.c @@ -1,15 +1,5 @@ -/* - * Copyright (C) 2015 Pengutronix, Uwe Kleine-König <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2015 Uwe Kleine-König <kernel@pengutronix.de>, Pengutronix #include <common.h> #include <asm/barebox-arm.h> diff --git a/arch/arm/boards/nhk8815/setup.c b/arch/arm/boards/nhk8815/setup.c index 0b6901001a..ed32218ac8 100644 --- a/arch/arm/boards/nhk8815/setup.c +++ b/arch/arm/boards/nhk8815/setup.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> #include <common.h> #include <init.h> diff --git a/arch/arm/boards/nvidia-beaver/Makefile b/arch/arm/boards/nvidia-beaver/Makefile index f0eb7b2de0..1b90eb13fd 100644 --- a/arch/arm/boards/nvidia-beaver/Makefile +++ b/arch/arm/boards/nvidia-beaver/Makefile @@ -1,4 +1,4 @@ -CFLAGS_pbl-entry.o := -mcpu=arm7tdmi -march=armv4t +CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t soc := tegra30 lwl-y += entry.o obj-y += board.o diff --git a/arch/arm/boards/nvidia-beaver/board.c b/arch/arm/boards/nvidia-beaver/board.c index bab0238779..0ef37780b4 100644 --- a/arch/arm/boards/nvidia-beaver/board.c +++ b/arch/arm/boards/nvidia-beaver/board.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lucas Stach <l.stach@pengutronix.de> #include <common.h> #include <dt-bindings/gpio/tegra-gpio.h> diff --git a/arch/arm/boards/nvidia-beaver/entry.c b/arch/arm/boards/nvidia-beaver/entry.c index 0f487bbd67..a89d419797 100644 --- a/arch/arm/boards/nvidia-beaver/entry.c +++ b/arch/arm/boards/nvidia-beaver/entry.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lucas Stach <l.stach@pengutronix.de> #include <common.h> #include <mach/lowlevel.h> diff --git a/arch/arm/boards/nvidia-jetson-tk1/Makefile b/arch/arm/boards/nvidia-jetson-tk1/Makefile index 5487f0289a..d38001c158 100644 --- a/arch/arm/boards/nvidia-jetson-tk1/Makefile +++ b/arch/arm/boards/nvidia-jetson-tk1/Makefile @@ -1,4 +1,4 @@ -CFLAGS_pbl-entry.o := -mcpu=arm7tdmi -march=armv4t +CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t soc := tegra124 lwl-y += entry.o obj-y += board.o diff --git a/arch/arm/boards/nvidia-jetson-tk1/board.c b/arch/arm/boards/nvidia-jetson-tk1/board.c index 939d18419a..fca3038170 100644 --- a/arch/arm/boards/nvidia-jetson-tk1/board.c +++ b/arch/arm/boards/nvidia-jetson-tk1/board.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lucas Stach <l.stach@pengutronix.de> #include <common.h> #include <dt-bindings/gpio/tegra-gpio.h> diff --git a/arch/arm/boards/nvidia-jetson-tk1/entry.c b/arch/arm/boards/nvidia-jetson-tk1/entry.c index da40f74e85..22b6c743ee 100644 --- a/arch/arm/boards/nvidia-jetson-tk1/entry.c +++ b/arch/arm/boards/nvidia-jetson-tk1/entry.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lucas Stach <l.stach@pengutronix.de> #include <common.h> #include <mach/lowlevel.h> diff --git a/arch/arm/boards/nxp-imx6ull-evk/board.c b/arch/arm/boards/nxp-imx6ull-evk/board.c index a0ca268f82..5959501a26 100644 --- a/arch/arm/boards/nxp-imx6ull-evk/board.c +++ b/arch/arm/boards/nxp-imx6ull-evk/board.c @@ -1,21 +1,5 @@ -/* - * Copyright (C) 2017 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2017 Sascha Hauer, Pengutronix #include <common.h> #include <init.h> diff --git a/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg b/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg index a507ab3e24..2538caea8a 100644 --- a/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg +++ b/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg @@ -9,7 +9,7 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 /* Enable all clocks */ wm 32 0x020c4068 0xffffffff diff --git a/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c b/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c index cc0b98e1d8..afef4c4498 100644 --- a/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c @@ -1,13 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/nxp-imx8mm-evk/board.c b/arch/arm/boards/nxp-imx8mm-evk/board.c index 59582276b2..4350abd157 100644 --- a/arch/arm/boards/nxp-imx8mm-evk/board.c +++ b/arch/arm/boards/nxp-imx8mm-evk/board.c @@ -1,21 +1,5 @@ -/* - * Copyright (C) 2018 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2018 Sascha Hauer, Pengutronix #include <asm/memory.h> #include <bootsource.h> @@ -71,7 +55,7 @@ static int nxp_imx8mm_evk_init(void) imx8mq_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", emmc_sd_flag); - imx8mq_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc2", + imx8mq_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag); phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, diff --git a/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg b/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg index 727439db7c..b013173113 100644 --- a/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg +++ b/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg @@ -2,4 +2,4 @@ soc imx8mm loadaddr 0x007e1000 max_load_size 0x3f000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c index cd1f7d168b..2297dc01e7 100644 --- a/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c @@ -28,11 +28,14 @@ extern char __dtb_imx8mm_evk_start[]; static void setup_uart(void) { + void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR); + imx8m_early_setup_uart_clock(); imx8mm_setup_pad(IMX8MM_PAD_UART2_TXD_UART2_TX | UART_PAD_CTRL); + imx8m_uart_setup(uart); - imx8m_uart_setup_ll(); + pbl_set_putc(imx_uart_putc, uart); putc_ll('>'); } @@ -157,8 +160,7 @@ static void start_atf(void) */ static __noreturn noinline void nxp_imx8mm_evk_start(void) { - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); + setup_uart(); start_atf(); diff --git a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c index b164bdec07..8d6cc389ba 100644 --- a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c +++ b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c @@ -118,7 +118,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = { { DDRC_FREQ2_INIT7(0), 0x0006004a }, /* boot start point */ - { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2 + { DDRC_MSTR2(0), 0x0 }, }; /* PHY Initialize Configuration */ @@ -1941,12 +1941,6 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { .fsp_cfg = lpddr4_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), }, { - /* P0 3000mts 2D */ - .drate = 3000, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = lpddr4_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), - }, { /* P1 400mts 1D */ .drate = 400, .fw_type = FW_1D_IMAGE, @@ -1958,6 +1952,12 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { .fw_type = FW_1D_IMAGE, .fsp_cfg = lpddr4_fsp2_cfg, .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), }, }; diff --git a/arch/arm/boards/nxp-imx8mp-evk/Makefile b/arch/arm/boards/nxp-imx8mp-evk/Makefile new file mode 100644 index 0000000000..4d0d989015 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o lpddr4-timing.o diff --git a/arch/arm/boards/nxp-imx8mp-evk/board.c b/arch/arm/boards/nxp-imx8mp-evk/board.c new file mode 100644 index 0000000000..d75eb1c697 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/board.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Oleksij Rempel, Pengutronix + */ + +#include <asm/memory.h> +#include <bootsource.h> +#include <common.h> +#include <init.h> +#include <linux/phy.h> +#include <linux/sizes.h> +#include <mach/bbu.h> +#include <mach/iomux-mx8mp.h> +#include <gpio.h> +#include <envfs.h> + +static int nxp_imx8mp_evk_init(void) +{ + int emmc_bbu_flag = 0; + int emmc_sd_flag = 0; + u32 val; + + if (!of_machine_is_compatible("fsl,imx8mp-evk")) + return 0; + + if (bootsource_get() == BOOTSOURCE_MMC) { + if (bootsource_get_instance() == 2) { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + of_device_enable_path("/chosen/environment-sd"); + emmc_sd_flag = BBU_HANDLER_FLAG_DEFAULT; + } + } else { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + imx8mq_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", + emmc_sd_flag); + imx8mq_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc2", + emmc_bbu_flag); + + val = readl(MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1); + val |= MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN; + writel(val, MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1); + + return 0; +} +coredevice_initcall(nxp_imx8mp_evk_init); diff --git a/arch/arm/boards/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg b/arch/arm/boards/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg new file mode 100644 index 0000000000..7739fe5be6 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg @@ -0,0 +1,5 @@ +soc imx8mp + +loadaddr 0x920000 +max_load_size 0x3f000 +ivtofs 0x0 diff --git a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c new file mode 100644 index 0000000000..e4f994a1d1 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <io.h> +#include <common.h> +#include <debug_ll.h> +#include <firmware.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/sections.h> +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> +#include <i2c/i2c-early.h> +#include <linux/sizes.h> +#include <mach/atf.h> +#include <mach/xload.h> +#include <mach/esdctl.h> +#include <mach/generic.h> +#include <mach/imx8mp-regs.h> +#include <mach/iomux-mx8mp.h> +#include <mach/imx8m-ccm-regs.h> +#include <mfd/pca9450.h> +#include <soc/imx8m/ddr.h> +#include <soc/fsl/fsl_udc.h> + +extern char __dtb_imx8mp_evk_start[]; + +#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_FSEL) + +#define I2C_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_HYS | \ + MX8MP_PAD_CTL_PUE | \ + MX8MP_PAD_CTL_PE) + +static void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mp_setup_pad(MX8MP_PAD_UART2_TXD__UART2_DCE_TX | UART_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_UART2_RXD__UART2_DCE_RX | UART_PAD_CTRL); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +static void pmic_reg_write(void *i2c, int reg, uint8_t val) +{ + int ret; + u8 buf[32]; + struct i2c_msg msgs[] = { + { + .addr = 0x25, + .buf = buf, + }, + }; + + buf[0] = reg; + buf[1] = val; + + msgs[0].len = 2; + + ret = i2c_fsl_xfer(i2c, msgs, ARRAY_SIZE(msgs)); + if (ret != 1) + pr_err("Failed to write to pmic\n"); +} + +static int power_init_board(void) +{ + void *i2c; + + imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL); + + imx8mm_early_clock_init(); + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + + i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR)); + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(i2c, PCA9450_BUCK123_DVS, 0x29); + + /* + * increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85v for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ + pmic_reg_write(i2c, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(i2c, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(i2c, PCA9450_BUCK1CTRL, 0x59); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(i2c, PCA9450_RESET_CTRL, 0xA1); + + return 0; +} + +extern struct dram_timing_info imx8mp_evk_dram_timing; + +static void start_atf(void) +{ + size_t bl31_size; + const u8 *bl31; + enum bootsource src; + int instance; + + /* + * If we are in EL3 we are running for the first time and need to + * initialize the DRAM and run TF-A (BL31). The TF-A will then jump + * to DRAM in EL2. + */ + if (current_el() != 3) + return; + + power_init_board(); + + imx8mm_ddr_init(&imx8mp_evk_dram_timing); + + imx8mp_get_boot_source(&src, &instance); + switch (src) { + case BOOTSOURCE_MMC: + imx8mp_esdhc_load_image(instance, false); + break; + default: + printf("Unhandled bootsource BOOTSOURCE_%d\n", src); + hang(); + } + + + /* + * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR + * in EL2. Copy the image there, but replace the PBL part of + * that image with ourselves. On a high assurance boot only the + * currently running code is validated and contains the checksum + * for the piggy data, so we need to ensure that we are running + * the same code in DRAM. + */ + memcpy((void *)MX8M_ATF_BL33_BASE_ADDR, + __image_start, barebox_pbl_size); + + get_builtin_firmware(imx8mp_bl31_bin, &bl31, &bl31_size); + + imx8mp_atf_load_bl31(bl31, bl31_size); + + /* not reached */ +} + +/* + * Power-on execution flow of start_nxp_imx8mp_evk() might not be + * obvious for a very first read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time. At entry the exception level is EL3. + * + * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL + * part is copied from OCRAM to the TF-A return address in DRAM. + * + * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us + * from EL3 to EL2. + * + * 4. Standard barebox boot flow continues + */ +static __noreturn noinline void nxp_imx8mp_evk_start(void) +{ + setup_uart(); + + start_atf(); + + /* + * Standard entry we hit once we initialized both DDR and ATF + */ + imx8mp_barebox_entry(__dtb_imx8mp_evk_start); +} + +ENTRY_FUNCTION(start_nxp_imx8mp_evk, r0, r1, r2) +{ + void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR); + + writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX8M_CCM_CCGRn_SET(IMX8M_CCM_CCGR_SCTR)); + + imx8mp_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + nxp_imx8mp_evk_start(); +} diff --git a/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c new file mode 100644 index 0000000000..bc4c10fe8d --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c @@ -0,0 +1,1848 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> +#include <soc/imx8m/lpddr4_define.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a0118 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x460048 }, + { 0x3d4000ec, 0x150048 }, + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x807bf }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x120 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49f820e }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1f0e }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x9121c1c }, + { 0x3d400200, 0x16 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x68070707 }, + { 0x3d40021c, 0xf08 }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x7d00 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x21 }, + { 0x3d403024, 0x30d400 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x18 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x3e8 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4846 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x15 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4846 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x15 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1500 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1500 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4846 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x15 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4846 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x15 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1500 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1500 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x448 }, + { 0x90169, 0x109 }, + { 0x9016a, 0xf }, + { 0x9016b, 0x7c0 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x0 }, + { 0x9016e, 0xe8 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x47 }, + { 0x90171, 0x630 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0x618 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0xe0 }, + { 0x90178, 0x109 }, + { 0x90179, 0x0 }, + { 0x9017a, 0x7c8 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x8 }, + { 0x9017d, 0x8140 }, + { 0x9017e, 0x10c }, + { 0x9017f, 0x0 }, + { 0x90180, 0x478 }, + { 0x90181, 0x109 }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x7d }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info imx8mp_evk_dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, 400, 100, }, +}; diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c index 299d056e27..19e640397c 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/board.c +++ b/arch/arm/boards/nxp-imx8mq-evk/board.c @@ -1,21 +1,5 @@ -/* - * Copyright (C) 2018 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2018 Sascha Hauer, Pengutronix #include <asm/memory.h> #include <bootsource.h> diff --git a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg index 11463fe850..80ce03e22c 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg +++ b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg @@ -2,5 +2,5 @@ soc imx8mq loadaddr 0x007E1000 max_load_size 0x3F000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index 39358afad1..564621abef 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -26,11 +26,14 @@ extern char __dtb_imx8mq_evk_start[]; static void setup_uart(void) { + void __iomem *uart = IOMEM(MX8M_UART1_BASE_ADDR); + imx8m_early_setup_uart_clock(); imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); + imx8m_uart_setup(uart); - imx8m_uart_setup_ll(); + pbl_set_putc(imx_uart_putc, uart); putc_ll('>'); } @@ -53,8 +56,7 @@ static void setup_uart(void) */ static __noreturn noinline void nxp_imx8mq_evk_start(void) { - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); + setup_uart(); /* * If we are in EL3 we are running for the first time and need to diff --git a/arch/arm/boards/omap343xdsp/board.c b/arch/arm/boards/omap343xdsp/board.c index 2fd0dee194..045a8b1bca 100644 --- a/arch/arm/boards/omap343xdsp/board.c +++ b/arch/arm/boards/omap343xdsp/board.c @@ -1,19 +1,5 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2006-2008 Nishanth Menon <x0nishan@ti.com>, Texas Instruments (http://www.ti.com/) #include <common.h> #include <console.h> diff --git a/arch/arm/boards/omap3evm/board.c b/arch/arm/boards/omap3evm/board.c index eefb540fc1..62b1a1c00f 100644 --- a/arch/arm/boards/omap3evm/board.c +++ b/arch/arm/boards/omap3evm/board.c @@ -1,3 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2009 Sanjeev Premi <premi@ti.com>, Texas Instruments Incorporated (http://www.ti.com/) + /** * @file * @brief Board Initialization routines for OMAP3EVM. @@ -22,22 +25,6 @@ * Originally from arch/arm/boards/omap/board-beagle.c */ -/* - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * Sanjeev Premi <premi@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - - #include <common.h> #include <console.h> #include <init.h> diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c index a321a8ff74..4fe445b17d 100644 --- a/arch/arm/boards/panda/lowlevel.c +++ b/arch/arm/boards/panda/lowlevel.c @@ -1,18 +1,6 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2004-2009 Richard Woodruff <r-woodruff2@ti.com>, Texas Instruments (http://www.ti.com/) + #include <common.h> #include <init.h> #include <io.h> diff --git a/arch/arm/boards/phytec-phycard-imx27/pca100.c b/arch/arm/boards/phytec-phycard-imx27/pca100.c index 7184a59c71..ed243fa01e 100644 --- a/arch/arm/boards/phytec-phycard-imx27/pca100.c +++ b/arch/arm/boards/phytec-phycard-imx27/pca100.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> diff --git a/arch/arm/boards/phytec-phycard-omap3/Makefile b/arch/arm/boards/phytec-phycard-omap3/Makefile index 7a4ab75f42..16f198b38c 100644 --- a/arch/arm/boards/phytec-phycard-omap3/Makefile +++ b/arch/arm/boards/phytec-phycard-omap3/Makefile @@ -1,15 +1,5 @@ -# (C) Copyright 2011 Juergen Kilb <j.kilb@phytec.de> -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Juergen Kilb <j.kilb@phytec.de> obj-y += pca-a-l1.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c index 930f3b9c7c..e3b148a0ed 100644 --- a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c +++ b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + /** * @file * @brief Board Initialization routines for the phyCARD-A-L1 @@ -27,15 +29,6 @@ * based on code from Texas Instruments / board-beagle.c * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ * Sanjeev Premi <premi@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> diff --git a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.h b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.h index f6f8996697..7e7dadc587 100644 --- a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.h +++ b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.h @@ -1,22 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2008 Raghavendra KH <r-khandenahally@ti.com>, Texas Instruments (http://www.ti.com/) + /** * @file * @brief exported generic APIs which various board files implement * * This file will not contain any board specific implementations. - * - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Raghavendra KH <r-khandenahally@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef __BOARD_OMAP_H_ diff --git a/arch/arm/boards/phytec-phycard-omap4/Makefile b/arch/arm/boards/phytec-phycard-omap4/Makefile index ad9f648ebe..0ac095becc 100644 --- a/arch/arm/boards/phytec-phycard-omap4/Makefile +++ b/arch/arm/boards/phytec-phycard-omap4/Makefile @@ -1,15 +1,6 @@ -# (C) Copyright 2012 Jan Weitzel <j.weitzel@phytec.de> -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jan Weitzel <j.weitzel@phytec.de> + obj-y += pca-a-xl2.o lwl-y += mux.o lowlevel.o bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-phytec-phycard-omap4 diff --git a/arch/arm/boards/phytec-phycard-omap4/lowlevel.c b/arch/arm/boards/phytec-phycard-omap4/lowlevel.c index 1907127198..6ccaf3e342 100644 --- a/arch/arm/boards/phytec-phycard-omap4/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-omap4/lowlevel.c @@ -1,18 +1,6 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2004-2009 Richard Woodruff <r-woodruff2@ti.com>, Texas Instruments (http://www.ti.com/) + #include <common.h> #include <init.h> #include <io.h> diff --git a/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c b/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c index c0e4448a00..ab5976ff8a 100644 --- a/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c +++ b/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2011 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Sascha Hauer, Pengutronix #include <common.h> #include <console.h> diff --git a/arch/arm/boards/phytec-phycore-imx27/lowlevel.c b/arch/arm/boards/phytec-phycore-imx27/lowlevel.c index 5f29aac94a..4e2f44d216 100644 --- a/arch/arm/boards/phytec-phycore-imx27/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx27/lowlevel.c @@ -1,18 +1,6 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + #include <common.h> #include <init.h> #include <mach/imx27-regs.h> diff --git a/arch/arm/boards/phytec-phycore-imx27/pcm038.c b/arch/arm/boards/phytec-phycore-imx27/pcm038.c index 008346faf1..90ce579684 100644 --- a/arch/arm/boards/phytec-phycore-imx27/pcm038.c +++ b/arch/arm/boards/phytec-phycore-imx27/pcm038.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #define pr_fmt(fmt) "pcm038: " fmt diff --git a/arch/arm/boards/phytec-phycore-imx27/pcm970.c b/arch/arm/boards/phytec-phycore-imx27/pcm970.c index b8faec0384..b7fad6dcbc 100644 --- a/arch/arm/boards/phytec-phycore-imx27/pcm970.c +++ b/arch/arm/boards/phytec-phycore-imx27/pcm970.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <gpio.h> diff --git a/arch/arm/boards/phytec-phycore-imx27/pll.h b/arch/arm/boards/phytec-phycore-imx27/pll.h index 8bdb76d111..cb34de1136 100644 --- a/arch/arm/boards/phytec-phycore-imx27/pll.h +++ b/arch/arm/boards/phytec-phycore-imx27/pll.h @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later /** * @file diff --git a/arch/arm/boards/phytec-phycore-imx31/Makefile b/arch/arm/boards/phytec-phycore-imx31/Makefile index 566ae81eaf..1a5be8e81f 100644 --- a/arch/arm/boards/phytec-phycore-imx31/Makefile +++ b/arch/arm/boards/phytec-phycore-imx31/Makefile @@ -1,17 +1,5 @@ -# -# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Juergen Beisert <jbe@pengutronix.de> lwl-y += lowlevel.o obj-y += pcm037.o diff --git a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c index a209907af7..7e1c6efd3f 100644 --- a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c @@ -1,18 +1,6 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + #include <common.h> #include <init.h> #include <io.h> diff --git a/arch/arm/boards/phytec-phycore-imx31/pcm037.c b/arch/arm/boards/phytec-phycore-imx31/pcm037.c index 35f8950479..52b97fe777 100644 --- a/arch/arm/boards/phytec-phycore-imx31/pcm037.c +++ b/arch/arm/boards/phytec-phycore-imx31/pcm037.c @@ -1,19 +1,7 @@ -/* - * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * Board support for Phytec's, i.MX31 based CPU card, called: PCM037 - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + +/* Board support for Phytec's, i.MX31 based CPU card, called: PCM037 */ #include <common.h> #include <init.h> diff --git a/arch/arm/boards/phytec-phycore-imx35/Makefile b/arch/arm/boards/phytec-phycore-imx35/Makefile index 0940a4b137..5029714421 100644 --- a/arch/arm/boards/phytec-phycore-imx35/Makefile +++ b/arch/arm/boards/phytec-phycore-imx35/Makefile @@ -1,17 +1,5 @@ -# -# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Juergen Beisert <jbe@pengutronix.de> lwl-y += lowlevel.o obj-y += pcm043.o diff --git a/arch/arm/boards/phytec-phycore-imx35/flash-header.imxcfg b/arch/arm/boards/phytec-phycore-imx35/flash-header.imxcfg index 36b68cd7ee..d3049369d9 100644 --- a/arch/arm/boards/phytec-phycore-imx35/flash-header.imxcfg +++ b/arch/arm/boards/phytec-phycore-imx35/flash-header.imxcfg @@ -1,5 +1,5 @@ soc imx35 -dcdofs 0x400 +ivtofs 0x400 loadaddr 0x80000000 wm 32 0x53f80004 0x00821000 wm 32 0x53f80004 0x00821000 diff --git a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c index d7b293eed5..73097eea10 100644 --- a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c @@ -1,18 +1,6 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + #include <common.h> #include <init.h> #include <mach/imx35-regs.h> diff --git a/arch/arm/boards/phytec-phycore-imx35/pcm043.c b/arch/arm/boards/phytec-phycore-imx35/pcm043.c index 0e9da16269..360a607bd5 100644 --- a/arch/arm/boards/phytec-phycore-imx35/pcm043.c +++ b/arch/arm/boards/phytec-phycore-imx35/pcm043.c @@ -1,20 +1,8 @@ -/* - * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (C) 2009 Pengutronix, Juergen Beisert <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * Board support for Phytec's, i.MX35 based CPU card, called: PCM043 - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2009 Juergen Beisert <kernel@pengutronix.de>, Pengutronix + +/* Board support for Phytec's, i.MX35 based CPU card, called: PCM043 */ #include <common.h> #include <command.h> diff --git a/arch/arm/boards/phytec-phycore-imx7/board.c b/arch/arm/boards/phytec-phycore-imx7/board.c index c3ebd1fadf..f173ee233f 100644 --- a/arch/arm/boards/phytec-phycore-imx7/board.c +++ b/arch/arm/boards/phytec-phycore-imx7/board.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2017 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2017 Sascha Hauer, Pengutronix #include <common.h> #include <init.h> diff --git a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg index 6e08b6c1b1..a18f3dbed1 100644 --- a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg +++ b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg @@ -11,7 +11,7 @@ soc imx7 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx7-ddr-regs.h> diff --git a/arch/arm/boards/phytec-phycore-omap4460/board.c b/arch/arm/boards/phytec-phycore-omap4460/board.c index b7aeeca6df..9e8b9e56a7 100644 --- a/arch/arm/boards/phytec-phycore-omap4460/board.c +++ b/arch/arm/boards/phytec-phycore-omap4460/board.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2011 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Sascha Hauer, Pengutronix #include <common.h> #include <console.h> diff --git a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c index 471e6108e4..2a65e40e6b 100644 --- a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c @@ -1,18 +1,6 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2004-2009 Richard Woodruff <r-woodruff2@ti.com>, Texas Instruments (http://www.ti.com/) + #include <common.h> #include <init.h> #include <io.h> diff --git a/arch/arm/boards/phytec-phycore-pxa270/board.c b/arch/arm/boards/phytec-phycore-pxa270/board.c index f4659e707f..9740a3a7af 100644 --- a/arch/arm/boards/phytec-phycore-pxa270/board.c +++ b/arch/arm/boards/phytec-phycore-pxa270/board.c @@ -1,19 +1,6 @@ -/* - * (C) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * 2010 by Marc Kleine-Budde <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2010 Marc Kleine-Budde <kernel@pengutronix.de> #include <common.h> #include <driver.h> diff --git a/arch/arm/boards/phytec-phycore-pxa270/config.h b/arch/arm/boards/phytec-phycore-pxa270/config.h index ca02b1140b..6aba53edea 100644 --- a/arch/arm/boards/phytec-phycore-pxa270/config.h +++ b/arch/arm/boards/phytec-phycore-pxa270/config.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Copyright (C) 2005 Phytec Messtechnik GmbH * Juergen Kilb, H. Klaholz <armlinux@phytec.de> @@ -5,18 +7,6 @@ * Copyright (C) 2006 Pengutronix * Sascha Hauer <s.hauer@pengutronix.de> * Robert Schwebel <r.schwebel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * */ #ifndef __CONFIG_H diff --git a/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S b/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S index 84599e40e2..9c6366cc2a 100644 --- a/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S +++ b/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * This was originally from the Lubbock u-boot port. * @@ -7,17 +9,6 @@ * running. See hal_platform_setup.h for the source. See * board/cradle/lowlevel_init.S for another PXA250 setup that is * much cleaner. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <config.h> diff --git a/arch/arm/boards/phytec-som-am335x/board.c b/arch/arm/boards/phytec-som-am335x/board.c index c25f33ae20..11acd06c53 100644 --- a/arch/arm/boards/phytec-som-am335x/board.c +++ b/arch/arm/boards/phytec-som-am335x/board.c @@ -1,21 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Wadim Egorov, PHYTEC Messtechnik GmbH + /* - * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH - * * Device initialization for the following modules and board variants: * - phyCORE: PCM-953, phyBOARD-MAIA, phyBOARD-WEGA * - phyFLEX: PBA-B-01 * - phyCARD: PCA-A-XS1 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <bootsource.h> diff --git a/arch/arm/boards/phytec-som-am335x/lowlevel.c b/arch/arm/boards/phytec-som-am335x/lowlevel.c index a028449fc0..bffb3ad880 100644 --- a/arch/arm/boards/phytec-som-am335x/lowlevel.c +++ b/arch/arm/boards/phytec-som-am335x/lowlevel.c @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Wadim Egorov, PHYTEC Messtechnik GmbH #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/phytec-som-am335x/ram-timings.h b/arch/arm/boards/phytec-som-am335x/ram-timings.h index d1947b588e..8a9bd32beb 100644 --- a/arch/arm/boards/phytec-som-am335x/ram-timings.h +++ b/arch/arm/boards/phytec-som-am335x/ram-timings.h @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Wadim Egorov, PHYTEC Messtechnik GmbH #ifndef __RAM_TIMINGS_H #define __RAM_TIMINGS_H diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c index 27a1ad4f66..bac3e8a8a1 100644 --- a/arch/arm/boards/phytec-som-imx6/board.c +++ b/arch/arm/boards/phytec-som-imx6/board.c @@ -1,23 +1,9 @@ -/* - * Copyright (C) 2013 Sascha Hauer, Pengutronix - * Copyright (C) 2015 PHYTEC Messtechnik GmbH, - * Author: Stefan Christ <s.christ@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer, Pengutronix +// SPDX-FileCopyrightText: 2015 PHYTEC Messtechnik GmbH + +/* Author: Stefan Christ <s.christ@phytec.de> */ + #define pr_fmt(fmt) "phySOM-i.MX6: " fmt #include <malloc.h> @@ -175,12 +161,18 @@ static int physom_imx6_devices_init(void) default_environment_path = "/chosen/environment-spinor"; default_envdev = "SPI NOR flash"; + imx6_bbu_internal_mmc_register_handler("mmc2", + "/dev/mmc2", 0); + } else if (of_machine_is_compatible("phytec,imx6q-pcaaxl3")) { barebox_set_hostname("phyCARD-i.MX6"); default_environment_path = "/chosen/environment-nand"; default_envdev = "NAND flash"; + imx6_bbu_internal_mmc_register_handler("mmc2", + "/dev/mmc2", 0); + } else if (of_machine_is_compatible("phytec,imx6q-pcm058-nand") || of_machine_is_compatible("phytec,imx6q-pcm058-emmc") || of_machine_is_compatible("phytec,imx6dl-pcm058-nand") @@ -194,6 +186,9 @@ static int physom_imx6_devices_init(void) default_environment_path = "/chosen/environment-spinor"; default_envdev = "SPI NOR flash"; + imx6_bbu_internal_mmc_register_handler("mmc0", + "/dev/mmc0", 0); + } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand") || of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) { barebox_set_hostname("phyCORE-i.MX6UL"); @@ -203,6 +198,9 @@ static int physom_imx6_devices_init(void) phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, ksz8081_phy_fixup); + imx6_bbu_internal_mmc_register_handler("mmc0", + "/dev/mmc0", 0); + } else return 0; @@ -241,10 +239,14 @@ static int physom_imx6_devices_init(void) imx6_bbu_internal_mmc_register_handler("mmc3", "/dev/mmc3", BBU_HANDLER_FLAG_DEFAULT); + imx6_bbu_internal_mmcboot_register_handler("mmc3-boot", + "mmc3", 0); } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) { imx6_bbu_internal_mmc_register_handler("mmc1", "/dev/mmc1", BBU_HANDLER_FLAG_DEFAULT); + imx6_bbu_internal_mmcboot_register_handler("mmc1-boot", + "mmc1", 0); } else { imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); } diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h index 06ba308fb8..1876a5aa9d 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.h index 26998c3fd8..c4122d245d 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.h @@ -7,4 +7,3 @@ wm 32 0x021B0000 0x84180000 #include "flash-header-phytec-pcl063.h" -#include <mach/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h index 5401e4243e..9a8f5f18e1 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h @@ -1,7 +1,7 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ul-512mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ul-512mb.imxcfg new file mode 100644 index 0000000000..f629a8e7b2 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ul-512mb.imxcfg @@ -0,0 +1,3 @@ + +#include "flash-header-phytec-pcl063-512mb.h" +#include <mach/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-256mb.imxcfg index b93e81fb4e..e6871d8534 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-256mb.imxcfg @@ -7,4 +7,4 @@ wm 32 0x021B0000 0x83180000 #include "flash-header-phytec-pcl063.h" -#include <mach/habv4-imx6-gencsf.h> +#include <mach/habv4-imx6ull-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-512mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-512mb.imxcfg new file mode 100644 index 0000000000..d2d7183843 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-512mb.imxcfg @@ -0,0 +1,3 @@ + +#include "flash-header-phytec-pcl063-512mb.h" +#include <mach/habv4-imx6ull-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h index 8b83aeae63..d32ee836a8 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h index da4708e4e3..e820cbf86b 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h index 6e7b740a6f..f3174f9bb7 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 /* NOC setup */ wm 32 0x00bb0008 0x00000000 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h index c5ed9b759f..4a9b179f59 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h index b0f3faa0b7..be4084c161 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c index 2e38baa45d..62a1c8de73 100644 --- a/arch/arm/boards/phytec-som-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -1,18 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de> +// SPDX-FileCopyrightText: 2015 PHYTEC Messtechnik GmbH + /* - * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de> - * Copyright (C) 2015 PHYTEC Messtechnik GmbH, * Author: Stefan Christ <s.christ@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <debug_ll.h> #include <common.h> @@ -119,6 +110,7 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6qp_som_nand_1gib, imx6qp_phytec_phycore_so PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true); +PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_emmc_512mb, imx6ul_phytec_phycore_som_emmc, SZ_512M, false); PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_nand_512mb, imx6ul_phytec_phycore_som_nand, SZ_512M, false); PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_nand_256mb, imx6ull_phytec_phycore_som_lc_nand, SZ_256M, false); PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_nand_512mb, imx6ull_phytec_phycore_som_nand, SZ_512M, false); diff --git a/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg b/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg index aff8321b9a..8921f32110 100644 --- a/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg +++ b/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg @@ -2,4 +2,4 @@ soc imx8mq loadaddr 0x007E1000 max_load_size 0x3F000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index f5b9b6c008..05226866f8 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -29,11 +29,15 @@ extern char __dtb_imx8mq_phytec_phycore_som_start[]; static void setup_uart(void) { + void __iomem *uart = IOMEM(MX8M_UART1_BASE_ADDR); + imx8m_early_setup_uart_clock(); imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); - imx8m_uart_setup_ll(); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); putc_ll('>'); } @@ -56,8 +60,7 @@ static void phytec_imx8mq_som_sram_setup(void) static __noreturn noinline void phytec_phycore_imx8mq_start(void) { - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); + setup_uart(); if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR) { /* diff --git a/arch/arm/boards/phytec-som-rk3288/board.c b/arch/arm/boards/phytec-som-rk3288/board.c index 8ea6c6c47c..43ed465f21 100644 --- a/arch/arm/boards/phytec-som-rk3288/board.c +++ b/arch/arm/boards/phytec-som-rk3288/board.c @@ -1,17 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2016 PHYTEC Messtechnik GmbH + /* - * Copyright (C) 2016 PHYTEC Messtechnik GmbH, * Author: Wadim Egorov <w.egorov@phytec.de> * * Device initialization for the phyCORE-RK3288 SoM - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> diff --git a/arch/arm/boards/phytec-som-rk3288/lowlevel.c b/arch/arm/boards/phytec-som-rk3288/lowlevel.c index 9def80ddb8..1a60959562 100644 --- a/arch/arm/boards/phytec-som-rk3288/lowlevel.c +++ b/arch/arm/boards/phytec-som-rk3288/lowlevel.c @@ -1,16 +1,7 @@ -/* - * Copyright (C) 2016 PHYTEC Messtechnik GmbH, - * Author: Wadim Egorov <w.egorov@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2016 PHYTEC Messtechnik GmbH + +/* Author: Wadim Egorov <w.egorov@phytec.de> */ #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/plathome-openblocks-a6/lowlevel.c b/arch/arm/boards/plathome-openblocks-a6/lowlevel.c index 31a28c8916..a480c966a4 100644 --- a/arch/arm/boards/plathome-openblocks-a6/lowlevel.c +++ b/arch/arm/boards/plathome-openblocks-a6/lowlevel.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c b/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c index f029bd1ba6..42b291df9f 100644 --- a/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c +++ b/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2014 - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c index 33c2a542b2..816635a23a 100644 --- a/arch/arm/boards/pm9261/init.c +++ b/arch/arm/boards/pm9261/init.c @@ -1,20 +1,6 @@ -/* - * Copyright (C) 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c index 30b3d26fbf..f9552b5bd2 100644 --- a/arch/arm/boards/pm9263/init.c +++ b/arch/arm/boards/pm9263/init.c @@ -1,20 +1,6 @@ -/* - * Copyright (C) 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c index 0565657a8c..48138558dd 100644 --- a/arch/arm/boards/pm9g45/init.c +++ b/arch/arm/boards/pm9g45/init.c @@ -1,20 +1,6 @@ -/* - * Copyright (C) 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> diff --git a/arch/arm/boards/pm9g45/lowlevel.c b/arch/arm/boards/pm9g45/lowlevel.c index fc0bfe405b..5f66b28254 100644 --- a/arch/arm/boards/pm9g45/lowlevel.c +++ b/arch/arm/boards/pm9g45/lowlevel.c @@ -10,7 +10,8 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_ddrsdrc.h> + #include <mach/hardware.h> void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) diff --git a/arch/arm/boards/protonic-imx6/Makefile b/arch/arm/boards/protonic-imx6/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/protonic-imx6/board.c b/arch/arm/boards/protonic-imx6/board.c new file mode 100644 index 0000000000..daae9a527c --- /dev/null +++ b/arch/arm/boards/protonic-imx6/board.c @@ -0,0 +1,1034 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2012 Steffen Trumtrar, Pengutronix +// SPDX-FileCopyrightText: 2014 Protonic Holland +// SPDX-FileCopyrightText: 2020 Oleksij Rempel, Pengutronix + +#include <bbu.h> +#include <common.h> +#include <environment.h> +#include <fcntl.h> +#include <gpio.h> +#include <i2c/i2c.h> +#include <mach/bbu.h> +#include <mach/imx6.h> +#include <net.h> +#include <of_device.h> +#include <sys/mount.h> +#include <sys/stat.h> +#include <unistd.h> +#include <usb/usb.h> + +#define GPIO_HW_REV_ID {\ + {IMX_GPIO_NR(2, 8), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "rev_id0"}, \ + {IMX_GPIO_NR(2, 9), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "rev_id1"}, \ + {IMX_GPIO_NR(2, 10), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "rev_id2"} \ +} + +#define GPIO_HW_TYPE_ID {\ + {IMX_GPIO_NR(2, 11), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "hw_id0"}, \ + {IMX_GPIO_NR(2, 12), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "hw_id1"}, \ + {IMX_GPIO_NR(2, 13), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "hw_id2"}, \ + {IMX_GPIO_NR(2, 14), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "hw_id3"}, \ + {IMX_GPIO_NR(2, 15), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "hw_id4"} \ +} + +enum { + HW_TYPE_PRTI6Q = 0, + HW_TYPE_PRTWD2 = 1, + HW_TYPE_ALTI6S = 2, + HW_TYPE_VICUT1 = 4, + HW_TYPE_ALTI6P = 6, + HW_TYPE_PRTMVT = 8, + HW_TYPE_PRTI6G = 10, + HW_TYPE_PRTRVT = 12, + HW_TYPE_VICUT2 = 16, + HW_TYPE_PLYM2M = 20, + HW_TYPE_PRTVT7 = 22, + HW_TYPE_LANMCU = 23, + HW_TYPE_PLYBAS = 24, + HW_TYPE_VICTGO = 28, +}; + +enum prt_imx6_kvg_pw_mode { + PW_MODE_KVG_WITH_YACO = 0, + PW_MODE_KVG_NEW = 1, + PW_MODE_KUBOTA = 2, +}; + +/* board specific flags */ +#define PRT_IMX6_BOOTCHOOSER BIT(3) +#define PRT_IMX6_USB_LONG_DELAY BIT(2) +#define PRT_IMX6_BOOTSRC_EMMC BIT(1) +#define PRT_IMX6_BOOTSRC_SPI_NOR BIT(0) + +static struct prt_imx6_priv *prt_priv; +struct prt_machine_data { + unsigned int hw_id; + unsigned int hw_rev; + unsigned int i2c_addr; + unsigned int i2c_adapter; + unsigned int flags; + int (*init)(struct prt_imx6_priv *priv); +}; + +struct prt_imx6_priv { + struct device_d *dev; + const struct prt_machine_data *dcfg; + unsigned int hw_id; + unsigned int hw_rev; + const char *name; + struct poller_async poller; + unsigned int usb_delay; +}; + +struct prti6q_rfid_contents { + u8 mac[6]; + char serial[10]; + u8 cs; +} __attribute__ ((packed)); + +#define GPIO_DIP1_FB IMX_GPIO_NR(4, 18) +#define GPIO_FORCE_ON1 IMX_GPIO_NR(2, 30) +#define GPIO_ON1_CTRL IMX_GPIO_NR(4, 21) +#define GPIO_ON2_CTRL IMX_GPIO_NR(4, 22) + +static const struct gpio prt_imx6_kvg_gpios[] = { + { + .gpio = GPIO_DIP1_FB, + .flags = GPIOF_IN, + .label = "DIP1_FB", + }, + { + .gpio = GPIO_FORCE_ON1, + .flags = GPIOF_OUT_INIT_HIGH, + .label = "FORCE_ON1", + }, + { + .gpio = GPIO_ON1_CTRL, + .flags = GPIOF_IN, + .label = "ON1_CTRL", + }, + { + .gpio = GPIO_ON2_CTRL, + .flags = GPIOF_IN, + .label = "ON2_CTRL", + }, +}; + +static int prt_imx6_read_rfid(struct prt_imx6_priv *priv, void *buf, + size_t size) +{ + const struct prt_machine_data *dcfg = priv->dcfg; + struct device_d *dev = priv->dev; + struct i2c_client cl; + int ret; + + cl.addr = dcfg->i2c_addr; + cl.adapter = i2c_get_adapter(dcfg->i2c_adapter); + if (!cl.adapter) { + dev_err(dev, "i2c bus not found\n"); + return -ENODEV; + } + + /* 0x6000 user storage in the RFID tag */ + ret = i2c_read_reg(&cl, 0x6000 | I2C_ADDR_16_BIT, buf, size); + if (ret < 0) { + dev_err(dev, "Failed to read the RFID: %i\n", ret); + return ret; + } + + return 0; +} + +static u8 prt_imx6_calc_rfid_cs(void *buf, size_t size) +{ + unsigned int cs = 0; + u8 *dat = buf; + int t; + + for (t = 0; t < size - 1; t++) { + cs += dat[t]; + } + + cs ^= 0xff; + + return cs & 0xff; + +} + +static int prt_imx6_set_mac(struct prt_imx6_priv *priv, + struct prti6q_rfid_contents *rfid) +{ + struct device_d *dev = priv->dev; + struct device_node *node; + + node = of_find_node_by_alias(of_get_root_node(), "ethernet0"); + if (!node) { + dev_err(dev, "Cannot find FEC!\n"); + return -ENODEV; + } + + if (!is_valid_ether_addr(&rfid->mac[0])) { + unsigned char ethaddr_str[sizeof("xx:xx:xx:xx:xx:xx")]; + + ethaddr_to_string(&rfid->mac[0], ethaddr_str); + dev_err(dev, "bad MAC addr: %s\n", ethaddr_str); + + return -EILSEQ; + } + + of_eth_register_ethaddr(node, &rfid->mac[0]); + + return 0; +} + +static int prt_of_fixup_serial(struct device_node *dstroot, void *arg) +{ + struct device_node *srcroot = arg; + const char *ser; + int len; + + ser = of_get_property(srcroot, "serial-number", &len); + return of_set_property(dstroot, "serial-number", ser, len, 1); +} + +static void prt_oftree_fixup_serial(const char *serial) +{ + struct device_node *root = of_get_root_node(); + + of_set_property(root, "serial-number", serial, strlen(serial) + 1, 1); + of_register_fixup(prt_of_fixup_serial, root); +} + +static int prt_imx6_set_serial(struct prt_imx6_priv *priv, + struct prti6q_rfid_contents *rfid) +{ + rfid->serial[9] = 0; /* Failsafe */ + dev_info(priv->dev, "Serial number: %s\n", rfid->serial); + prt_oftree_fixup_serial(rfid->serial); + + return 0; +} + +static int prt_imx6_read_i2c_mac_serial(struct prt_imx6_priv *priv) +{ + struct device_d *dev = priv->dev; + struct prti6q_rfid_contents rfid; + int ret; + + ret = prt_imx6_read_rfid(priv, &rfid, sizeof(rfid)); + if (ret) + return ret; + + if (rfid.cs != prt_imx6_calc_rfid_cs(&rfid, sizeof(rfid))) { + dev_err(dev, "RFID: bad checksum!\n"); + return -EBADMSG; + } + + ret = prt_imx6_set_mac(priv, &rfid); + if (ret) + return ret; + + ret = prt_imx6_set_serial(priv, &rfid); + if (ret) + return ret; + + return 0; +} + +static int prt_imx6_usb_mount(struct prt_imx6_priv *priv, char **usbdisk) +{ + struct device_d *dev = priv->dev; + const char *path; + struct stat s; + int ret; + + ret = mkdir("/usb", 0); + if (ret) { + dev_err(dev, "Cannot mkdir /usb\n"); + return ret; + } + + path = "/dev/disk0.0"; + ret = stat(path, &s); + if (!ret) { + ret = mount(path, NULL, "usb", NULL); + if (ret) + goto exit_usb_mount; + + *usbdisk = strdup("disk0.0"); + return 0; + } + + path = "/dev/disk0"; + ret = stat(path, &s); + if (!ret) { + ret = mount(path, NULL, "usb", NULL); + if (ret) + goto exit_usb_mount; + + *usbdisk = strdup("disk0"); + return 0; + } + +exit_usb_mount: + dev_err(dev, "Failed to mount %s with error (%i)\n", path, ret); + return ret; +} + +#define OTG_PORTSC1 (MX6_OTG_BASE_ADDR+0x184) + +static void prt_imx6_check_usb_boot(void *data) +{ + struct prt_imx6_priv *priv = data; + struct device_d *dev = priv->dev; + char *second_word, *bootsrc, *usbdisk; + char buf[sizeof("vicut1q recovery")] = {}; + unsigned int v; + ssize_t size; + int fd, ret; + + v = readl(OTG_PORTSC1); + if ((v & 0x0c00) == 0) /* LS == SE0 ==> nothing connected */ + return; + + usb_rescan(); + + ret = prt_imx6_usb_mount(priv, &usbdisk); + if (ret) + return; + + fd = open("/usb/boot_target", O_RDONLY); + if (fd < 0) { + dev_warn(dev, "Can't open /usb/boot_target file, continue with normal boot\n"); + ret = fd; + goto exit_usb_boot; + } + + size = read(fd, buf, sizeof(buf) - 1); + close(fd); + if (size < 0) { + ret = size; + goto exit_usb_boot; + } + + /* Length of "vicut1 usb", the shortest possible target. */ + if (size < strlen("vicut1 usb")) { + dev_err(dev, "Invalid boot target file!\n"); + ret = -EINVAL; + goto exit_usb_boot; + } + + second_word = strchr(buf, ' '); + if (!second_word) { + dev_err(dev, "Cant find boot target in the boot target file!\n"); + ret = -ENODEV; + goto exit_usb_boot; + } + + *second_word = 0; + + if (strcmp(buf, priv->name)) { + dev_err(dev, "Boot target for a different board! (got: %s expected: %s)\n", + buf, priv->name); + ret = -EINVAL; + goto exit_usb_boot; + } + + second_word++; + if (strncmp(second_word, "usb", 3) == 0) { + bootsrc = usbdisk; + } else if (strncmp(second_word, "recovery", 8) == 0) { + bootsrc = "recovery"; + } else { + dev_err(dev, "Unknown boot target!\n"); + ret = -ENODEV; + goto exit_usb_boot; + } + + dev_info(dev, "detected valid usb boot target file, overwriting boot to: %s\n", bootsrc); + ret = setenv("global.boot.default", bootsrc); + if (ret) + goto exit_usb_boot; + + free(usbdisk); + return; + +exit_usb_boot: + dev_err(dev, "Failed to run usb boot: %s\n", strerror(-ret)); + free(usbdisk); + + return; +} + +static int prt_imx6_env_init(struct prt_imx6_priv *priv) +{ + const struct prt_machine_data *dcfg = priv->dcfg; + struct device_d *dev = priv->dev; + char *delay, *bootsrc; + int ret; + + ret = setenv("global.linux.bootargs.base", "consoleblank=0 vt.color=0x00"); + if (ret) + goto exit_env_init; + + if (dcfg->flags & PRT_IMX6_USB_LONG_DELAY) + priv->usb_delay = 4; + else + priv->usb_delay = 1; + + /* the usb_delay value is used for poller_call_async() */ + delay = basprintf("%d", priv->usb_delay); + ret = setenv("global.autoboot_timeout", delay); + if (ret) + goto exit_env_init; + + if (dcfg->flags & PRT_IMX6_BOOTCHOOSER) + bootsrc = "bootchooser"; + else + bootsrc = "mmc2"; + + ret = setenv("global.boot.default", bootsrc); + if (ret) + goto exit_env_init; + + dev_info(dev, "Board specific env init is done\n"); + return 0; + +exit_env_init: + dev_err(dev, "Failed to set env: %i\n", ret); + + return ret; +} + +static int prt_imx6_bbu(struct prt_imx6_priv *priv) +{ + const struct prt_machine_data *dcfg = priv->dcfg; + u32 emmc_flags = 0; + int ret; + + if (dcfg->flags & PRT_IMX6_BOOTSRC_SPI_NOR) { + ret = imx6_bbu_internal_spi_i2c_register_handler("SPI", "/dev/m25p0.barebox", + BBU_HANDLER_FLAG_DEFAULT); + if (ret) + goto exit_bbu; + } else { + emmc_flags = BBU_HANDLER_FLAG_DEFAULT; + } + + ret = imx6_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", + emmc_flags); + if (ret) + goto exit_bbu; + + ret = imx6_bbu_internal_mmc_register_handler("SD", "/dev/mmc0", 0); + if (ret) + goto exit_bbu; + + return 0; +exit_bbu: + dev_err(priv->dev, "Failed to register bbu: %i\n", ret); + return ret; +} + +static int prt_imx6_devices_init(void) +{ + struct prt_imx6_priv *priv = prt_priv; + int ret; + + if (!priv) + return 0; + + if (priv->dcfg->init) + priv->dcfg->init(priv); + + prt_imx6_bbu(priv); + + prt_imx6_read_i2c_mac_serial(priv); + + prt_imx6_env_init(priv); + + ret = poller_async_register(&priv->poller, "usb-boot"); + if (ret) { + dev_err(priv->dev, "can't setup poller\n"); + return ret; + } + + poller_call_async(&priv->poller, priv->usb_delay * SECOND, + &prt_imx6_check_usb_boot, priv); + + return 0; +} +late_initcall(prt_imx6_devices_init); + +static int prt_imx6_init_kvg_set_ctrl(struct prt_imx6_priv *priv, bool val) +{ + int ret; + + ret = gpio_direction_output(GPIO_ON1_CTRL, val); + if (ret) + return ret; + + ret = gpio_direction_output(GPIO_ON2_CTRL, val); + if (ret) + return ret; + + return 0; +} + +static int prt_imx6_yaco_set_kvg_power_mode(struct prt_imx6_priv *priv, + const char *serial) +{ + static const char command[] = "{\"command\":\"mode\",\"value\":\"kvg\",\"on2\":true}"; + struct device_d *dev = priv->dev; + struct console_device *yccon; + int ret; + + yccon = of_console_get_by_alias(serial); + if (!yccon) { + dev_dbg(dev, "Cant find the %s node, try later\n", serial); + return -EPROBE_DEFER; + } + + ret = console_set_baudrate(yccon, 115200); + if (ret) + goto exit_yaco_set_kvg_power_mode; + + yccon->puts(yccon, command, sizeof(command)); + + dev_info(dev, "Send YaCO power init sequence to %s\n", serial); + return 0; + +exit_yaco_set_kvg_power_mode: + dev_err(dev, "Failed to set YaCO pw mode: %i", ret); + + return ret; +} + +static int prt_imx6_init_kvg_power(struct prt_imx6_priv *priv, + enum prt_imx6_kvg_pw_mode pw_mode) +{ + const char *mode; + int ret; + + ret = gpio_request_array(prt_imx6_kvg_gpios, + ARRAY_SIZE(prt_imx6_kvg_gpios)); + if (ret) + goto exit_init_kvg_vicut; + + mdelay(1); + + if (!gpio_get_value(GPIO_DIP1_FB)) + pw_mode = PW_MODE_KUBOTA; + + switch (pw_mode) { + case PW_MODE_KVG_WITH_YACO: + mode = "KVG (with YaCO)"; + + /* GPIO_ON1_CTRL and GPIO_ON2_CTRL are N.C. on the SoC for + * older revisions */ + + /* Inform YaCO of power mode */ + ret = prt_imx6_yaco_set_kvg_power_mode(priv, "serial0"); + break; + case PW_MODE_KVG_NEW: + mode = "KVG (new)"; + + ret = prt_imx6_init_kvg_set_ctrl(priv, true); + if (ret) + goto exit_init_kvg_vicut; + break; + case PW_MODE_KUBOTA: + mode = "Kubota"; + ret = prt_imx6_init_kvg_set_ctrl(priv, false); + if (ret) + goto exit_init_kvg_vicut; + break; + default: + ret = -ENODEV; + goto exit_init_kvg_vicut; + } + + dev_info(priv->dev, "Power mode: %s\n", mode); + + return 0; + +exit_init_kvg_vicut: + dev_err(priv->dev, "KvG power init failed: %i\n", ret); + + return ret; +} + +static int prt_imx6_init_victgo(struct prt_imx6_priv *priv) +{ + int ret = 0; + + /* Bit 1 of HW-REV is pulled low by 2k2, but must be high on some + * revisions + */ + if (priv->hw_rev & 2) { + ret = gpio_direction_output(IMX_GPIO_NR(2, 9), 1); + if (ret) { + dev_err(priv->dev, "Failed to set gpio up\n"); + return ret; + } + } + + return prt_imx6_init_kvg_power(priv, PW_MODE_KVG_NEW); +} + +static int prt_imx6_init_kvg_new(struct prt_imx6_priv *priv) +{ + return prt_imx6_init_kvg_power(priv, PW_MODE_KVG_NEW); +} + +static int prt_imx6_init_kvg_yaco(struct prt_imx6_priv *priv) +{ + return prt_imx6_init_kvg_power(priv, PW_MODE_KVG_WITH_YACO); +} + +static int prt_imx6_rfid_fixup(struct prt_imx6_priv *priv, + struct device_node *root) +{ + const struct prt_machine_data *dcfg = priv->dcfg; + struct device_node *node, *i2c_node; + char *eeprom_node_name, *alias; + int na, ns, len = 0; + int ret; + u8 *tmp; + + alias = basprintf("i2c%d", dcfg->i2c_adapter); + if (!alias) { + ret = -ENOMEM; + goto exit_error; + } + + i2c_node = of_find_node_by_alias(root, alias); + if (!i2c_node) { + dev_err(priv->dev, "Unsupported i2c adapter\n"); + ret = -ENODEV; + goto free_alias; + } + + eeprom_node_name = basprintf("/eeprom@%x", dcfg->i2c_addr); + if (!eeprom_node_name) { + ret = -ENOMEM; + goto free_alias; + } + + node = of_create_node(i2c_node, eeprom_node_name); + if (!node) { + dev_err(priv->dev, "Failed to create node %s\n", + eeprom_node_name); + ret = -ENOMEM; + goto free_eeprom; + } + + ret = of_property_write_string(node, "compatible", "atmel,24c256"); + if (ret) + goto free_eeprom; + + na = of_n_addr_cells(node); + ns = of_n_size_cells(node); + tmp = xzalloc((na + ns) * 4); + + of_write_number(tmp + len, dcfg->i2c_addr, na); + len += na * 4; + of_write_number(tmp + len, 0, ns); + len += ns * 4; + + ret = of_set_property(node, "reg", tmp, len, 1); + kfree(tmp); + if (ret) + goto free_eeprom; + + return 0; +free_eeprom: + kfree(eeprom_node_name); +free_alias: + kfree(alias); +exit_error: + dev_err(priv->dev, "Failed to apply fixup: %i\n", ret); + return ret; +} + +static int prt_imx6_of_fixup(struct device_node *root, void *data) +{ + struct prt_imx6_priv *priv = data; + int ret; + + if (!root) { + dev_err(priv->dev, "Unable to find the root node\n"); + dump_stack(); + return -ENODEV; + } + + ret = prt_imx6_rfid_fixup(priv, root); + if (ret) + goto exit_of_fixups; + + return 0; +exit_of_fixups: + dev_err(priv->dev, "Failed to apply OF fixups: %i\n", ret); + return ret; +} + +static int prt_imx6_get_id(struct prt_imx6_priv *priv) +{ + struct gpio gpios_type[] = GPIO_HW_TYPE_ID; + struct gpio gpios_rev[] = GPIO_HW_REV_ID; + int ret; + + ret = gpio_array_to_id(gpios_type, ARRAY_SIZE(gpios_type), &priv->hw_id); + if (ret) + goto exit_get_id; + + ret = gpio_array_to_id(gpios_rev, ARRAY_SIZE(gpios_rev), &priv->hw_rev); + if (ret) + goto exit_get_id; + + return 0; +exit_get_id: + dev_err(priv->dev, "Failed to read gpio ID: %i\n", ret); + return ret; +} + +static int prt_imx6_get_dcfg(struct prt_imx6_priv *priv) +{ + const struct prt_machine_data *dcfg, *found = NULL; + int ret; + + dcfg = of_device_get_match_data(priv->dev); + if (!dcfg) { + ret = -EINVAL; + goto exit_get_dcfg; + } + + for (; dcfg->hw_id != UINT_MAX; dcfg++) { + if (dcfg->hw_id != priv->hw_id) + continue; + if (dcfg->hw_rev > priv->hw_rev) + break; + found = dcfg; + } + + if (!found) { + ret = -ENODEV; + goto exit_get_dcfg; + } + + priv->dcfg = found; + + return 0; +exit_get_dcfg: + dev_err(priv->dev, "Failed to get dcfg: %i\n", ret); + return ret; +} + +static int prt_imx6_probe(struct device_d *dev) +{ + struct prt_imx6_priv *priv; + const char *name, *ptr; + struct param_d *p; + int ret; + + priv = xzalloc(sizeof(*priv)); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + name = of_device_get_match_compatible(priv->dev); + ptr = strchr(name, ','); + priv->name = ptr ? ptr + 1 : name; + + pr_info("Detected machine type: %s\n", priv->name); + + ret = prt_imx6_get_id(priv); + if (ret) + goto free_priv; + + pr_info(" HW type: %d\n", priv->hw_id); + pr_info(" HW revision: %d\n", priv->hw_rev); + + ret = prt_imx6_get_dcfg(priv); + if (ret) + goto free_priv; + + p = dev_add_param_uint32_ro(dev, "boardrev", &priv->hw_rev, "%u"); + if (IS_ERR(p)) { + ret = PTR_ERR(p); + goto free_priv; + } + + p = dev_add_param_uint32_ro(dev, "boardid", &priv->hw_id, "%u"); + if (IS_ERR(p)) { + ret = PTR_ERR(p); + goto free_priv; + } + + ret = prt_imx6_of_fixup(of_get_root_node(), priv); + if (ret) + goto free_priv; + + ret = of_register_fixup(prt_imx6_of_fixup, priv); + if (ret) { + dev_err(dev, "Failed to register fixup\n"); + goto free_priv; + } + + prt_priv = priv; + + return 0; +free_priv: + kfree(priv); + return ret; +} + +static const struct prt_machine_data prt_imx6_cfg_alti6p[] = { + { + .hw_id = HW_TYPE_ALTI6P, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .flags = PRT_IMX6_BOOTSRC_EMMC, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_victgo[] = { + { + .hw_id = HW_TYPE_VICTGO, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .init = prt_imx6_init_victgo, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_vicut1[] = { + { + .hw_id = HW_TYPE_VICUT1, + .hw_rev = 0, + .i2c_addr = 0x50, + .i2c_adapter = 1, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = HW_TYPE_VICUT1, + .hw_rev = 1, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .init = prt_imx6_init_kvg_yaco, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = HW_TYPE_VICUT2, + .hw_rev = 1, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .init = prt_imx6_init_kvg_new, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_vicut1q[] = { + { + .hw_id = HW_TYPE_VICUT1, + .hw_rev = 0, + .i2c_addr = 0x50, + .i2c_adapter = 1, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = HW_TYPE_VICUT1, + .hw_rev = 1, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .init = prt_imx6_init_kvg_yaco, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = HW_TYPE_VICUT2, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .init = prt_imx6_init_kvg_yaco, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = HW_TYPE_VICUT2, + .hw_rev = 1, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .init = prt_imx6_init_kvg_new, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_vicutp[] = { + { + .hw_id = HW_TYPE_VICUT2, + .hw_rev = 1, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .init = prt_imx6_init_kvg_new, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_lanmcu[] = { + { + .hw_id = HW_TYPE_LANMCU, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .flags = PRT_IMX6_BOOTSRC_EMMC | PRT_IMX6_BOOTCHOOSER, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_plybas[] = { + { + .hw_id = HW_TYPE_PLYBAS, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR | PRT_IMX6_USB_LONG_DELAY, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_plym2m[] = { + { + .hw_id = HW_TYPE_PLYM2M, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR | PRT_IMX6_USB_LONG_DELAY, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_prti6g[] = { + { + .hw_id = HW_TYPE_PRTI6G, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .flags = PRT_IMX6_BOOTSRC_EMMC, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_prti6q[] = { + { + .hw_id = HW_TYPE_PRTI6Q, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 2, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = HW_TYPE_PRTI6Q, + .hw_rev = 1, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_prtmvt[] = { + { + .hw_id = HW_TYPE_PRTMVT, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_prtrvt[] = { + { + .hw_id = HW_TYPE_PRTRVT, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_prtvt7[] = { + { + .hw_id = HW_TYPE_PRTVT7, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .flags = PRT_IMX6_BOOTSRC_EMMC | PRT_IMX6_BOOTCHOOSER, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_prtwd2[] = { + { + .hw_id = HW_TYPE_PRTWD2, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .flags = PRT_IMX6_BOOTSRC_EMMC, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_prtwd3[] = { + { + .hw_id = HW_TYPE_PRTWD2, + .hw_rev = 2, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .flags = PRT_IMX6_BOOTSRC_EMMC, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct of_device_id prt_imx6_of_match[] = { + { .compatible = "alt,alti6p", .data = &prt_imx6_cfg_alti6p }, + { .compatible = "kvg,victgo", .data = &prt_imx6_cfg_victgo }, + { .compatible = "kvg,vicut1", .data = &prt_imx6_cfg_vicut1 }, + { .compatible = "kvg,vicut1q", .data = &prt_imx6_cfg_vicut1q }, + { .compatible = "kvg,vicutp", .data = &prt_imx6_cfg_vicutp }, + { .compatible = "lan,lanmcu", .data = &prt_imx6_cfg_lanmcu }, + { .compatible = "ply,plybas", .data = &prt_imx6_cfg_plybas }, + { .compatible = "ply,plym2m", .data = &prt_imx6_cfg_plym2m }, + { .compatible = "prt,prti6g", .data = &prt_imx6_cfg_prti6g }, + { .compatible = "prt,prti6q", .data = &prt_imx6_cfg_prti6q }, + { .compatible = "prt,prtmvt", .data = &prt_imx6_cfg_prtmvt }, + { .compatible = "prt,prtrvt", .data = &prt_imx6_cfg_prtrvt }, + { .compatible = "prt,prtvt7", .data = &prt_imx6_cfg_prtvt7 }, + { .compatible = "prt,prtwd2", .data = &prt_imx6_cfg_prtwd2 }, + { .compatible = "prt,prtwd3", .data = &prt_imx6_cfg_prtwd3 }, + { /* sentinel */ }, +}; + +static struct driver_d prt_imx6_board_driver = { + .name = "board-protonic-imx6", + .probe = prt_imx6_probe, + .of_compatible = DRV_OF_COMPAT(prt_imx6_of_match), +}; +postcore_platform_driver(prt_imx6_board_driver); diff --git a/arch/arm/boards/protonic-imx6/ddr3-defines.imxcfg b/arch/arm/boards/protonic-imx6/ddr3-defines.imxcfg new file mode 100644 index 0000000000..65bd1bc3c6 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/ddr3-defines.imxcfg @@ -0,0 +1,350 @@ +/* + * Timing configuration: + * + * MDCFG0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tRFC 2Gb 400MHz 0x3f (64) 24 0x3f000000 + * 4Gb 400MHz 0x77 (120) 24 0x77000000 + * 8Gb 400MHz 0x8b (140) 24 0x8b000000 + * 2Gb 533MHz 0x55 (86) 24 0x55000000 + * 4Gb 533MHz 0x9f (160) 24 0x9f000000 + * 8Gb 533MHz 0xba (187) 24 0xba000000 + * tXS 2Gb 400MHz 0x43 (68) 16 0x00430000 + * 4Gb 400MHz 0x7b (124) 16 0x007b0000 + * 8Gb 400MHz 0x8f (144) 16 0x008f0000 + * 2Gb 533MHz 0x5b (92) 16 0x005b0000 + * 4Gb 533MHz 0xa5 (166) 16 0x00a50000 + * 8Gb 533MHz 0xc0 (193) 16 0x00c00000 + * tXP * 400MHz 0x2 (3) 13 0x00004000 + * * 533MHz 0x3 (4) 13 0x00006000 + * tXPDLL * 400MHz 0x9 (10) 9 0x00001200 + * * 533MHz 0xc (13) 9 0x00001800 + * tFAW * 400MHz 0x13 (20) 4 0x00000130 + * * 533MHz 0x1a (27) 4 0x000001a0 + * tCL * 400MHz 0x3 (6) 0 0x00000003 + * * 533MHz-CL7 0x4 (7) 0 0x00000004 + * * 533MHz-CL8 0x5 (8) 0 0x00000005 + * ---------------------------------------------------------------- + */ +#define MDCFG0_2G_400MHZ 0x3f435333 +#define MDCFG0_4G_400MHZ 0x777b5333 +#define MDCFG0_8G_400MHZ 0x8b8f5333 +#define MDCFG0_2G_533MHZ_CL8 0x555b79a5 +#define MDCFG0_2G_533MHZ_CL7 0x555b79a4 +#define MDCFG0_4G_533MHZ_CL8 0x9fa579a5 +#define MDCFG0_4G_533MHZ_CL7 0x9fa579a4 +#define MDCFG0_8G_533MHZ_CL8 0xbac079a5 +#define MDCFG0_8G_533MHZ_CL7 0xbac079a4 + +/* + * MDCFG1: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tRCD * 400MHz 0x5 (6) 28 0xa0000000 + * * 533MHz 0x7 (8) 28 0xe0000000 + * tRP * 400MHz 0x5 (6) 26 0x14000000 + * * 533MHz 0x7 (8) 26 0x1c000000 + * tRC * 400MHz 0x14 (21) 21 0x02800000 + * * 533MHz 0x1b (28) 21 0x03600000 + * tRAS * 400MHz 0x0e (15) 16 0x000e0000 + * * 533MHz 0x13 (20) 16 0x00130000 + * tRPA * 0x1 (tRP+1) 15 0x00008000 + * tWR * 400MHz 0x5 (6) 9 0x00000a00 + * * 533MHz 0x7 (8) 9 0x00000e00 + * tMRD * 0xb (12) 5 0x00000160 + * tCWL * 400MHz 0x3 (5) 0 0x00000003 + * * 533MHz 0x4 (6) 0 0x00000004 + * ---------------------------------------------------------------- + */ +#define MDCFG1_400MHZ 0xb68e8b63 +#define MDCFG1_533MHZ 0xff738f64 + +/* + * MDCFG2: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tDLLK * 0x1ff (512) 16 0x01ff0000 + * tRTP * 0x3 (4) 6 0x000000c0 + * tWTR * 0x3 (4) 3 0x00000018 + * tRRD * 400MHz 0x3 (4) 0 0x00000003 + * * 533MHz 0x5 (6) 0 0x00000005 + * ---------------------------------------------------------------- + */ +#define MDCFG2_400MHZ 0x01ff00db +#define MDCFG2_533MHZ 0x01ff00dd + +/* + * MDOR: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tXPR 2Gb 400MHz 0x43 (68) 16 0x00430000 + * 4Gb 400MHz 0x7b (124) 16 0x007b0000 + * 8Gb 400MHz 0x8f (144) 16 0x008f0000 + * 2Gb 533MHz 0x5b (92) 16 0x005b0000 + * 4Gb 533MHz 0xa5 (166) 16 0x00a50000 + * 8Gb 533MHz 0xc0 (193) 16 0x00c00000 + * SDE_to_RST * 0x10 (14) 8 0x00001000 + * RST_to_CKE * 0x23 (33) 0 0x00000023 + * ---------------------------------------------------------------- + */ +#define MDOR_2G_400MHZ 0x00431023 +#define MDOR_4G_400MHZ 0x007b1023 +#define MDOR_8G_400MHZ 0x008f1023 +#define MDOR_2G_533MHZ 0x005b1023 +#define MDOR_4G_533MHZ 0x00a51023 +#define MDOR_8G_533MHZ 0x00c01023 + +/* + * MDOTC ODT delays: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tAOFPD * 400MHz 0x0 (1) 27 0x00000000 + * * 533MHz 0x1 (2) 27 0x08000000 + * tAONPD * 400MHz 0x0 (1) 24 0x00000000 + * * 533MHz 0x1 (2) 24 0x01000000 + * tANPD * 400MHz 0x3 (4) 20 0x00300000 + * * 533MHz 0x4 (5) 20 0x00400000 + * tAXPD * 400MHz 0x3 (4) 16 0x00030000 + * * 533MHz 0x4 (5) 16 0x00040000 + * tODTLon * 400MHz 0x3 (3) 12 0x00003000 + * * 533MHz 0x4 (4) 12 0x00004000 + * tODTidle_off * 400MHz 0x3 (3) 4 0x00000030 + * * 533MHz 0x4 (4) 4 0x00000040 + * ---------------------------------------------------------------- + */ +#define MDOTC_400MHZ 0x00333030 +#define MDOTC_533MHZ 0x09444040 + +/* + * MDPDC: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * PRCT_1 * 0x0 28 0x00000000 + * PRCT_0 * 0x0 24 0x00000000 + * tCKE * 0x2 (3) 16 0x00020000 + * PWDT_1 * 0x5 (256) 12 0x00005000 + * PWDT_0 * 0x5 (256) 8 0x00000500 + * SLOW_PD * 0x0 (0) 7 0x00000000 + * BOTH_CS_PD * 0x1 (1) 6 0x00000040 + * tCKSRX * 400MHz 0x5 (5) 3 0x00000028 + * * 533MHz 0x6 (6) 3 0x00000030 + * tCKSRE * 400MHz 0x5 (5) 0 0x00000005 + * * 533MHz 0x6 (6) 0 0x00000006 + * ---------------------------------------------------------------- + */ +#define MDPDC_400MHZ 0x0002556d +#define MDPDC_533MHZ 0x00025576 + +/* + * MDCTL: + * 2Gb: CS0 enable, 14bit ROW, 10bit COL, BL=8, 64bit data + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * SDE_0 * 0x1 (1) 31 0x80000000 + * SDE_1 * 0x0 (0) 30 0x00000000 + * ROW 2Gb * 0x3 (14) 24 0x03000000 + * 4Gb * 0x4 (15) 24 0x04000000 + * 8Gb * 0x5 (16) 24 0x05000000 + * COL * 0x1 (10) 20 0x00100000 + * BL * 0x1 (8) 19 0x00080000 + * DSIZ 64bit 0x2 (64) 16 0x00020000 + * DSIZ 32bit 0x1 (32) 16 0x00010000 + * DSIZ 16bit 0x0 (16) 16 0x00000000 + * ---------------------------------------------------------------- + */ +#define MDCTL_2G_16BIT 0x83180000 +#define MDCTL_2G_32BIT 0x83190000 +#define MDCTL_2G 0x831a0000 +#define MDCTL_4G_16BIT 0x84180000 +#define MDCTL_4G_32BIT 0x84190000 +#define MDCTL_4G 0x841a0000 +#define MDCTL_8G 0x851a0000 + +/* + * MDASP Address space partitioning: + * + * At 0.25GiB, internal address space ends. Above that DDR3 should be + * located. The CS1/CS0 split-line determines where: + * + * For 1x2Gb chips (0.25GiB total on CS0): 0.5GiB + * For 2x4Gb chips (1GiB total on CS0): 1.25GiB + * For 4x2Gb chips (1GiB total on CS0): 1.25GiB + * For 4x4Gb chips (2GiB total on CS0): 2.25GiB + * For 4x8Gb chips (4GiB total on CS0): 4.00GiB (maximum possible, + * shadowed partially by internal address space). + * + * Register value Split + * --------------------------- + * 0x0000000f 0.5GiB + * 0x00000017 0.75GiB + * 0x00000027 1.25GiB + * 0x00000047 2.25GiB + * 0x0000007f 4.00GiB + */ +#define MDASP_512MIB 0x0000000f +#define MDASP_768MIB 0x00000017 +#define MDASP_1GIB25 0x00000027 +#define MDASP_2GIB25 0x00000047 +#define MDASP_4GIB00 0x0000007f + +/* + * Initialize DDR3 chips + * MDSCR: Value = 0xvvvv803n, with 0xvvvv = value, n = Reg. number (BA) + */ +/* + * DDR3 chip MR2, n = 2: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Rtt(wr) * 0x0 (disabled) 10, 9 0x0000 + * SR-Temp. * 0x1 (Extended) 7 0x0080 + * Auto-SR * 0x0 (Manual) 6 0x0000 + * CWL * 400MHz 0x0 (5tCK) 5, 4, 3 0x0000 + * * 533MHz 0x1 (6tCK) 5, 4, 3 0x0008 + * ---------------------------------------------------------------- + */ +#define DDR3_MR2_400MHZ_RTT_OFF 0x00808032 +#define DDR3_MR2_533MHZ_RTT_OFF 0x00888032 +#define DDR3_MR2_400MHZ_RTT_120 0x04808032 +#define DDR3_MR2_533MHZ_RTT_120 0x04888032 + +/* + * DDR3 chip MR1, n = 1: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Qoff * 0x0 (enabled) 12 0x0000 + * TDQS * 0x0 (disabled) 11 0x0000 + * Rtt * 0x0 (disabled) 9, 6, 2 0x0000 + * Write-levelling * 0x0 (disable) 7 0x0000 + * ODS * 0x0 (RZQ/6=40) 5, 1 0x0000 + * DLL * 0x0 (enable) 0 0x0000 + * ---------------------------------------------------------------- + */ +#define DDR3_MR1_RTT_OFF_ODS_40 0x00008031 +#define DDR3_MR1_RTT_120_ODS_40 0x00408031 +#define DDR3_MR1_RTT_60_ODS_40 0x00048031 +#define DDR3_MR1_RTT_OFF_ODS_34 0x00028031 +#define DDR3_MR1_RTT_120_ODS_34 0x00428031 +#define DDR3_MR1_RTT_60_ODS_34 0x00068031 + +/* + * DDR3 chip MR0, n = 0: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Precharge PD * 0x1 (fast exit) 12 0x1000 + * WR 400MHz 0x2 (6) 11,10,9 0x0400 + * 533MHz 0x4 (8) 11,10,9 0x0800 + * DLL reset * 0x1 (Yes) 8 0x0100 + * CL 400MHz 0x4 (6) 6,5,4,2 0x0020 + * 533MHz 0x6 (7) 6,5,4,2 0x0030 + * 533MHz 0x8 (8) 6,5,4,2 0x0040 + * RD burst type * 0x0 (seq.) 3 0x0000 + * BL * 0x0 (BL8) 0 0x0000 + * ---------------------------------------------------------------- + */ +#define DDR3_MR0_400MHZ 0x15208030 +#define DDR3_MR0_533MHZ_CL7 0x19308030 +#define DDR3_MR0_533MHZ_CL8 0x19408030 + + +/* + * MDREF: + * REF_SEL (bit 14,15): 0 (64kHz, needed for high-temp.) + * REFR (bit 11, 12, 13): 0x3 (4 refreshes) -> 0x00001800 + * 0x7 (8 refreshes) -> 0x00003800 + */ +#define MDREF_64KHZ 0x00001800 +#define MDREF_32KHZ 0x00007800 + +/* MPODTCTRL */ +#define MPODTCTRL_ODT_OFF 0x00000007 +#define MPODTCTRL_ODT_120 0x00011117 +#define MPODTCTRL_ODT_60 0x00022227 +#define MPODTCTRL_ODT_40 0x00033337 + +/* + * MPDGCTRL0: + * + * Channel 0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * RST_RD_FIFO * 0 31 0x00000000 + * DG_CMP_CYC * 1 30 0x40000000 + * DG_DIS * 0 29 0x00000000 + * HW_DG_EN * 0 28 0x00000000 + * DG_HC_DEL1 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_EXT_UP * 0 23 0x00000000 + * DG_DL_ABS_OFFS1 400MHz 0x35 16 0x00350000 + * 533MHz 0x4b 16 0x004b0000 + * DG_HC_DEL0 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS0 400MHz 0x35 0 0x00000031 + * 533MHz 0x4b 0 0x00000050 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL0_CH0_400MHZ 0x42350231 +#define MPDGCTRL0_CH0_533MHZ 0x434b0350 +/* + * + * Channel 1: + * + * DG_HC_DEL1 (5) 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS1 (5) 400MHz 0x35 16 0x00350000 + * 533MHz 0x4b 16 0x004b0000 + * DG_HC_DEL0 (4) 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS0 (4) 400MHz 0x35 0 0x00000031 + * 533MHz 0x4b 0 0x00000050 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL0_CH1_400MHZ 0x42350231 +#define MPDGCTRL0_CH1_533MHZ 0x434b0350 + +/* + * MPDGCTRL1: + * + * Channel 0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * DG_HC_DEL3 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS3 400MHz 0x1a 16 0x001a0000 + * 533MHz 0x4c 16 0x004c0000 + * DG_HC_DEL2 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS2 400MHz 0x18 0 0x00000018 + * 533MHz 0x59 0 0x00000059 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL1_CH0_400MHZ 0x021a0218 +#define MPDGCTRL1_CH0_533MHZ 0x034c0359 +/* + * + * Channel 1: + * + * DG_HC_DEL3 (7) 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS3 (7) 400MHz 0x1a 16 0x001a0000 + * 533MHz 0x65 16 0x00650000 + * DG_HC_DEL2 (6) 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS2 (6) 400MHz 0x18 0 0x00000018 + * 533MHz 0x48 0 0x00000048 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL1_CH1_400MHZ 0x021a0218 +#define MPDGCTRL1_CH1_533MHZ 0x03650348 diff --git a/arch/arm/boards/protonic-imx6/flash-header-alti6p.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-alti6p.imxcfg new file mode 100644 index 0000000000..c778391d75 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-alti6p.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_4G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_1GIB25 +wm 32 0x021b0000 MDCTL_4G_32BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x001f001f +wm 32 0x021b4810 0x001f001f + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: ALTI6P doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-lanmcu.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-lanmcu.imxcfg new file mode 100644 index 0000000000..b08e149834 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-lanmcu.imxcfg @@ -0,0 +1,115 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug 0 LED */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e060c 0x000130b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_512MIB +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ diff --git a/arch/arm/boards/protonic-imx6/flash-header-plybas.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-plybas.imxcfg new file mode 100644 index 0000000000..dbbb9818b6 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-plybas.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_512MIB +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-plym2m.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-plym2m.imxcfg new file mode 100644 index 0000000000..dbbb9818b6 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-plym2m.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_512MIB +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-prti6g.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prti6g.imxcfg new file mode 100644 index 0000000000..ec9fb84108 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prti6g.imxcfg @@ -0,0 +1,81 @@ +soc imx6 +loadaddr 0x80000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" +#include "padsetup-ul.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 0x00000047 /* MDASP_512MIB */ +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 0x00000117 /* MPODTCTRL_ODT_120 */ + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b0850 0x40404040 /* For now set all to 50%. */ + +/* MPWLDECTRL0 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Enable all clocks */ +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff diff --git a/arch/arm/boards/protonic-imx6/flash-header-prti6q.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prti6q.imxcfg new file mode 100644 index 0000000000..029edc248a --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prti6q.imxcfg @@ -0,0 +1,122 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e0228 0x00000005 +wm 32 0x020e0244 0x00000005 +wm 32 0x020e05f8 0x000130b0 +wm 32 0x020e0614 0x0001b0b0 + +#include "padsetup-q.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00000742 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 + +wm 32 0x021b000c MDCFG0_8G_533MHZ_CL7 +wm 32 0x021b0010 MDCFG1_533MHZ +wm 32 0x021b0014 MDCFG2_533MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_8G_533MHZ +wm 32 0x021b0008 MDOTC_533MHZ +wm 32 0x021b0004 MDPDC_533MHZ +wm 32 0x021b0040 MDASP_4GIB00 +wm 32 0x021b0000 MDCTL_8G + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_533MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_533MHZ_CL7 + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_60 +wm 32 0x021b4818 MPODTCTRL_ODT_60 + +wm 32 0x021b083c MPDGCTRL0_CH0_533MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_533MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_533MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_533MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x001f001f +wm 32 0x021b4810 0x001f001f + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00001006 /* Enable autorefresh */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* DEBUG leds */ +wm 32 0x020e0244 0x00000005 +wm 32 0x020e0614 0x000130b0 + +/* RGMII config */ +wm 32 0x020e0790 0x00080000 /* 1V2 DDR IO */ diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtmvt.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtmvt.imxcfg new file mode 100644 index 0000000000..1131174f70 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtmvt.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_4G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_1GIB25 +wm 32 0x021b0000 MDCTL_4G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtrvt.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtrvt.imxcfg new file mode 100644 index 0000000000..dbbb9818b6 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtrvt.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_512MIB +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtvt7.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtvt7.imxcfg new file mode 100644 index 0000000000..019696295d --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtvt7.imxcfg @@ -0,0 +1,115 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug 0 LED */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e060c 0x000130b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_768MIB +wm 32 0x021b0000 MDCTL_2G_32BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtwd2.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtwd2.imxcfg new file mode 100644 index 0000000000..5f847c004d --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtwd2.imxcfg @@ -0,0 +1,229 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "lpddr2-defines.imxcfg" + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* Set DDR clk to 400MHz. */ +wm 32 0x020c4018 0x00060324 + +/* #include "padsetup-q.imxcfg" */ + +/* LPDDR2 i.MX6D/Q pad setup */ +wm 32 0x020e0798 0x00080000 +wm 32 0x020e0758 0x00000000 + +wm 32 0x020e0588 0x00000030 +wm 32 0x020e0594 0x00000030 + +wm 32 0x020e056c 0x00000030 +wm 32 0x020e0578 0x00000030 +wm 32 0x020e074c 0x00000030 + +wm 32 0x020e057c 0x00000030 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000030 +wm 32 0x020e05a0 0x00000030 +wm 32 0x020e078c 0x00000030 + +wm 32 0x020e0750 0x00020000 +wm 32 0x020e05a8 0x00003030 +wm 32 0x020e05b0 0x00003030 +wm 32 0x020e0524 0x00003030 +wm 32 0x020e051c 0x00003030 +wm 32 0x020e0518 0x00003030 +wm 32 0x020e050c 0x00003030 +wm 32 0x020e05b8 0x00003030 +wm 32 0x020e05c0 0x00003030 + +wm 32 0x020e0774 0x00020000 +wm 32 0x020e0784 0x00000030 +wm 32 0x020e0788 0x00000030 +wm 32 0x020e0794 0x00000030 +wm 32 0x020e079c 0x00000030 +wm 32 0x020e07a0 0x00000030 +wm 32 0x020e07a4 0x00000030 +wm 32 0x020e07a8 0x00000030 +wm 32 0x020e0748 0x00000030 + +wm 32 0x020e05ac 0x00000030 +wm 32 0x020e05b4 0x00000030 +wm 32 0x020e0528 0x00000030 +wm 32 0x020e0520 0x00000030 +wm 32 0x020e0514 0x00000030 +wm 32 0x020e0510 0x00000030 +wm 32 0x020e05bc 0x00000030 +wm 32 0x020e05c4 0x00000030 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 +wm 32 0x021b401c 0x00008000 +/* check 32 until_any_bit_set 0x021b401c 0x00004000 */ + + +wm 32 0x021b085c 0x1b4700c7 +wm 32 0x021b485c 0x1b4700c7 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1380003 /* FIXME: Why different? */ + +wm 32 0x021b0890 0x00400000 +wm 32 0x021b4890 0x00400000 + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +wm 32 0x021b083c 0x20000000 +wm 32 0x021b0840 0x00000000 +wm 32 0x021b483c 0x20000000 +wm 32 0x021b4840 0x00000000 + + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* Set Write data delay 3 delay units for all bits */ +wm 32 0x021b082c 0xf3333333 +wm 32 0x021b0830 0xf3333333 +wm 32 0x021b0834 0xf3333333 +wm 32 0x021b0838 0xf3333333 +wm 32 0x021b482c 0xf3333333 +wm 32 0x021b4830 0xf3333333 +wm 32 0x021b4834 0xf3333333 +wm 32 0x021b4838 0xf3333333 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* + * Configure MMDC Channel 0 + */ + +/* MDMISC No addr mirror, 0 WALAT, 5 RALAT, LPDDR2 mode, RST */ +wm 32 0x021b0018 0x00001602 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +wm 32 0x021b0004 0x00020036 +wm 32 0x021b0008 0x12272000 /* FIXME: Why does script aid set this? */ +wm 32 0x021b000c MDCFG0_8G_LPDDR2_CL6 +wm 32 0x021b0010 MDCFG1_LPDDR2 +wm 32 0x021b0014 MDCFG2_LPDDR2 + +wm 32 0x021b0018 0x0000174c +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x0f9f26d2 /* MDRWD */ +wm 32 0x021b0030 MDOR_LPDDR2 +wm 32 0x021b0038 0x00190778 /* MDCFG3LP */ +wm 32 0x021b0040 0x0000004f /* NOTE: According to RM */ +wm 32 0x021b0400 0x11420000 /* MAARCR disable dyn jump */ +wm 32 0x021b0000 MDCTL_LPDDR2 + +/* + * Configure MMDC Channel 1 + */ + +/* MDMISC No addr mirror, 0 WALAT, 5 RALAT, LPDDR2 mode, RST */ +wm 32 0x021b4018 0x00001602 +check 32 until_all_bits_clear 0x021b4018 0x00000002 + +wm 32 0x021b4004 0x00020036 +wm 32 0x021b4008 0x12272000 /* FIXME: Why does script aid set this? */ +wm 32 0x021b400c MDCFG0_8G_LPDDR2_CL6 +wm 32 0x021b4010 MDCFG1_LPDDR2 +wm 32 0x021b4014 MDCFG2_LPDDR2 + +wm 32 0x021b4018 0x0000174c +wm 32 0x021b401c 0x00008000 +wm 32 0x021b402c 0x0f9f26d2 /* MDOR */ +wm 32 0x021b4030 MDOR_LPDDR2 +wm 32 0x021b4038 0x00190778 /* MDCFG3LP */ +wm 32 0x021b4040 MDASP_768MIB /* NOTE: According to RM */ +wm 32 0x021b4400 0x11420000 /* MAARCR disable dyn jump */ +wm 32 0x021b4000 MDCTL_LPDDR2 + +/* + * Configure LPDDR2 devices + */ + +wm 32 0x021b001c 0x00008010 /* Precharge all ch 0 */ +wm 32 0x021b401c 0x00008010 /* Precharge all ch 1 */ + +/* Channel 0 */ +wm 32 0x021b001c 0x003f8030 /* Reset */ +wm 32 0x021b001c 0xff0a8030 /* Calibrate */ +wm 32 0x021b001c 0x82018030 /* MR1: nWR=6, WC=0, BT=0, BL=BL4 */ +wm 32 0x021b001c 0x04028030 /* MR2: RL6/WL3 */ +wm 32 0x021b001c 0x02038030 /* MR3: DS = 40 Ohm */ + +/* Channel 1 */ +wm 32 0x021b401c 0x003f8030 +wm 32 0x021b401c 0xff0a8030 +wm 32 0x021b401c 0x82018030 +wm 32 0x021b401c 0x04028030 +wm 32 0x021b401c 0x02038030 + +/* MPDGCTRL disabled, reset fifos */ +wm 32 0x021b083c 0xa0000000 +wm 32 0x021b083c 0xa0000000 +check 32 until_all_bits_clear 0x021b083c 0x80000000 +wm 32 0x021b483c 0xa0000000 +wm 32 0x021b483c 0xa0000000 +check 32 until_all_bits_clear 0x021b483c 0x80000000 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1380003 /* FIXME: Why different? */ + +wm 32 0x021b0020 MDREF_64KHZ +wm 32 0x021b4020 MDREF_64KHZ + +wm 32 0x021b0818 0x00000000 /* LPDDR2: Disable ODT! */ +wm 32 0x021b4818 0x00000000 + +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b4004 MDPDC_400MHZ + +/* MAPSR */ +wm 32 0x021b0404 0x00011006 /* Enable autorefresh */ +wm 32 0x021b4404 0x00011006 /* Enable autorefresh */ + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ +wm 32 0x021b401c 0x00000000 /* Disable configuration req */ + + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* DEBUG leds */ +wm 32 0x020e0244 0x00000005 +wm 32 0x020e0614 0x000130b0 + +/* configure 100K pull down on USB_ETH_CHG -> ADC_ICHG */ +wm 32 0x020e06cc 0x000130f9 diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtwd3.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtwd3.imxcfg new file mode 100644 index 0000000000..054043cc80 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtwd3.imxcfg @@ -0,0 +1,280 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "lpddr2-defines.imxcfg" + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* Set DDR clk to 400MHz. */ +wm 32 0x020c4018 0x00060324 + +/* #include "padsetup-q.imxcfg" */ + +/* LPDDR2 i.MX6D/Q pad setup */ +wm 32 0x020e0798 0x00080000 +wm 32 0x020e0758 0x00000000 + +wm 32 0x020e0588 0x00000030 +wm 32 0x020e0594 0x00000030 + +wm 32 0x020e056c 0x00000030 +wm 32 0x020e0578 0x00000030 +wm 32 0x020e074c 0x00000030 + +wm 32 0x020e057c 0x00000030 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000030 +wm 32 0x020e05a0 0x00000030 +wm 32 0x020e078c 0x00000030 + +wm 32 0x020e0750 0x00020000 +wm 32 0x020e05a8 0x00003030 +wm 32 0x020e05b0 0x00003030 +wm 32 0x020e0524 0x00003030 +wm 32 0x020e051c 0x00003030 +wm 32 0x020e0518 0x00003030 +wm 32 0x020e050c 0x00003030 +wm 32 0x020e05b8 0x00003030 +wm 32 0x020e05c0 0x00003030 + +wm 32 0x020e0774 0x00020000 +wm 32 0x020e0784 0x00000030 +wm 32 0x020e0788 0x00000030 +wm 32 0x020e0794 0x00000030 +wm 32 0x020e079c 0x00000030 +wm 32 0x020e07a0 0x00000030 +wm 32 0x020e07a4 0x00000030 +wm 32 0x020e07a8 0x00000030 +wm 32 0x020e0748 0x00000030 + +wm 32 0x020e05ac 0x00000030 +wm 32 0x020e05b4 0x00000030 +wm 32 0x020e0528 0x00000030 +wm 32 0x020e0520 0x00000030 +wm 32 0x020e0514 0x00000030 +wm 32 0x020e0510 0x00000030 +wm 32 0x020e05bc 0x00000030 +wm 32 0x020e05c4 0x00000030 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 +wm 32 0x021b401c 0x00008000 +/* check 32 until_any_bit_set 0x021b401c 0x00004000 */ + + +wm 32 0x021b085c 0x1b4700c7 +wm 32 0x021b485c 0x1b4700c7 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1380003 /* FIXME: Why different? */ + +wm 32 0x021b0890 0x00400000 +wm 32 0x021b4890 0x00400000 + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +wm 32 0x021b083c 0x20000000 +wm 32 0x021b0840 0x00000000 +wm 32 0x021b483c 0x20000000 +wm 32 0x021b4840 0x00000000 + + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* Set Write data delay 3 delay units for all bits */ +wm 32 0x021b082c 0xf3333333 +wm 32 0x021b0830 0xf3333333 +wm 32 0x021b0834 0xf3333333 +wm 32 0x021b0838 0xf3333333 +wm 32 0x021b482c 0xf3333333 +wm 32 0x021b4830 0xf3333333 +wm 32 0x021b4834 0xf3333333 +wm 32 0x021b4838 0xf3333333 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* NOC: DDRCONF */ +/* Sabre-auto: wm 32 0x00bb0008 0x00000000 */ +/* Values (Address mapping for 64bit): + * 0 : 16 Row, 3 Bank, 10 Col interleave (11 Col for 32 bit) + * 1 : 15 Row, 3 Bank, 11 Col interleave (12 Col for 32 bit) + * 2 : 18 Row, 3 Bank, 8 Col interleave (9 Col for 32 bit) + * 3 : 17 Row, 3 Bank, 9 Col interleave (10 Col for 32 bit) + * 4 : 2 CS (?), 15 Row, 3 Bank, 10 Col, interleave + * ... + */ +wm 32 0x00bb0008 0x00000000 + +/* + * NOC DdrTiming: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * ActToAct 533MHz 0x1b (28) 0 0x0000001b + * LPDDR2 0x18 (24) 0 0x00000018 + * RdToMiss 533MHz 0x10 (16) 6 0x00000400 + * LPDDR2 0x11 (17) 6 0x00000440 + * WrToMiss * 0x1e (30) 12 0x0001e000 + * LPDDR2 0x19 (25) 12 0x00019000 + * BurstLen * 0x4 (8/2) 18 0x00100000 + * LPDDR2 0x2 (4/2) 18 0x00080000 + * RdToWr * 0x3 (3) 21 0x00600000 + * LPDDR2 0x5 (5) 21 0x00a00000 + * WrToRd * 0xa (10) 26 0x28000000 + * LPDDR2 0x6 (6) 26 0x18000000 + * BwRatio * 0x0 (0) 31 0x00000000 + * ---------------------------------------------------------------- + */ +/* Sabre-auto: wm 32 0x00bb000c 0x2891E41A */ +wm 32 0x00bb000c 0x18a99459 + +/* + * NOC Activate: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * Rrd * 0x6 (6) 0 0x00000006 + * LPDDR2 0x4 (4) 0 0x00000004 + * Faw * 0x1b (27) 4 0x000001b0 + * LPDDR2 0x14 (20) 4 0x00000140 + * FawBank * 0x0 (0) 10 0x00000000 + * ---------------------------------------------------------------- + */ +/* Sabre-auto: wm 32 0x00bb0038 0x00000564 */ +wm 32 0x00bb0038 0x00000144 + +/* + * NOC ReadLatency: (FIXME) + */ +wm 32 0x00bb0014 0x00000040 + +/* + * Configure MMDC Channel 0 + */ + +/* MDMISC No addr mirror, 0 WALAT, 5 RALAT, LPDDR2 mode, RST */ +wm 32 0x021b0018 0x00001602 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +wm 32 0x021b0004 0x00020036 +wm 32 0x021b0008 0x12272000 /* FIXME: Why does script aid set this? */ +wm 32 0x021b000c MDCFG0_8G_LPDDR2_CL6 +wm 32 0x021b0010 MDCFG1_LPDDR2 +wm 32 0x021b0014 MDCFG2_LPDDR2 + +wm 32 0x021b0018 0x0000174c +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x0f9f26d2 /* MDRWD */ +wm 32 0x021b0030 MDOR_LPDDR2 +wm 32 0x021b0038 0x00190778 /* MDCFG3LP */ +wm 32 0x021b0040 0x0000004f /* NOTE: According to RM */ +wm 32 0x021b0400 0x15420000 /* MAARCR disable dyn jump/reordering */ +wm 32 0x021b0000 MDCTL_LPDDR2 + +/* + * Configure MMDC Channel 1 + */ + +/* MDMISC No addr mirror, 0 WALAT, 5 RALAT, LPDDR2 mode, RST */ +wm 32 0x021b4018 0x00001602 +check 32 until_all_bits_clear 0x021b4018 0x00000002 + +wm 32 0x021b4004 0x00020036 +wm 32 0x021b4008 0x12272000 /* FIXME: Why does script aid set this? */ +wm 32 0x021b400c MDCFG0_8G_LPDDR2_CL6 +wm 32 0x021b4010 MDCFG1_LPDDR2 +wm 32 0x021b4014 MDCFG2_LPDDR2 + +wm 32 0x021b4018 0x0000174c +wm 32 0x021b401c 0x00008000 +wm 32 0x021b402c 0x0f9f26d2 /* MDRWD */ +wm 32 0x021b4030 MDOR_LPDDR2 +wm 32 0x021b4038 0x00190778 /* MDCFG3LP */ +wm 32 0x021b4040 MDASP_768MIB /* NOTE: According to RM */ +wm 32 0x021b4400 0x15420000 /* MAARCR disable dyn jump/reordering */ +wm 32 0x021b4000 MDCTL_LPDDR2 + +/* + * Configure LPDDR2 devices + */ + +wm 32 0x021b001c 0x00008010 /* Precharge all ch 0 */ +wm 32 0x021b401c 0x00008010 /* Precharge all ch 1 */ + +/* Channel 0 */ +wm 32 0x021b001c 0x003f8030 /* Reset */ +wm 32 0x021b001c 0xff0a8030 /* Calibrate */ +wm 32 0x021b001c 0x82018030 /* MR1: nWR=6, WC=0, BT=0, BL=BL4 */ +wm 32 0x021b001c 0x04028030 /* MR2: RL6/WL3 */ +wm 32 0x021b001c 0x02038030 /* MR3: DS = 40 Ohm */ + +/* Channel 1 */ +wm 32 0x021b401c 0x003f8030 +wm 32 0x021b401c 0xff0a8030 +wm 32 0x021b401c 0x82018030 +wm 32 0x021b401c 0x04028030 +wm 32 0x021b401c 0x02038030 + +/* MPDGCTRL disabled, reset fifos */ +wm 32 0x021b083c 0xa0000000 +wm 32 0x021b083c 0xa0000000 +check 32 until_all_bits_clear 0x021b083c 0x80000000 +wm 32 0x021b483c 0xa0000000 +wm 32 0x021b483c 0xa0000000 +check 32 until_all_bits_clear 0x021b483c 0x80000000 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1380003 /* FIXME: Why different? */ + +wm 32 0x021b0020 MDREF_64KHZ +wm 32 0x021b4020 MDREF_64KHZ + +wm 32 0x021b0818 0x00000000 /* LPDDR2: Disable ODT! */ +wm 32 0x021b4818 0x00000000 + +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b4004 MDPDC_400MHZ + +/* MAPSR */ +wm 32 0x021b0404 0x00011006 /* Enable autorefresh */ +wm 32 0x021b4404 0x00011006 /* Enable autorefresh */ + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ +wm 32 0x021b401c 0x00000000 /* Disable configuration req */ + + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* configure 100K pull down on USB_ETH_CHG -> ADC_ICHG */ +wm 32 0x020e06cc 0x000130f9 diff --git a/arch/arm/boards/protonic-imx6/flash-header-victgo.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-victgo.imxcfg new file mode 100644 index 0000000000..d3de7b6aab --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-victgo.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_4G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_1GIB25 +wm 32 0x021b0000 MDCTL_4G_32BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x001f001f +wm 32 0x021b4810 0x001f001f + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-vicut1.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-vicut1.imxcfg new file mode 100644 index 0000000000..9926fbf4a2 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-vicut1.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_4G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_2GIB25 +wm 32 0x021b0000 MDCTL_4G + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config */ +wm 32 0x020e0768 0x00080000 /* 1V2 DDR IO */ +wm 32 0x020e0788 0x00000200 /* 60 Ohm ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x0001f0b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-vicut1q.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-vicut1q.imxcfg new file mode 100644 index 0000000000..f7e75b47bf --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-vicut1q.imxcfg @@ -0,0 +1,126 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e0228 0x00000005 +/* wm 32 0x020e0244 0x00000005 */ +wm 32 0x020e05f8 0x000130b0 +/* wm 32 0x020e0614 0x000130b0 */ + +#include "padsetup-q.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011742 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 + +wm 32 0x021b000c MDCFG0_8G_533MHZ_CL7 +wm 32 0x021b0010 MDCFG1_533MHZ +wm 32 0x021b0014 MDCFG2_533MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_8G_533MHZ +wm 32 0x021b0008 MDOTC_533MHZ +wm 32 0x021b0004 MDPDC_533MHZ +wm 32 0x021b0040 MDASP_4GIB00 +wm 32 0x021b0000 MDCTL_8G +// check 32 until_any_bit_set 0x021b0018 0x80000000 + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_533MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_533MHZ_CL7 + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_60 +wm 32 0x021b4818 MPODTCTRL_ODT_60 + +/* DQS gating calibration measured on UT2 and UTC boards */ +wm 32 0x021b083c 0x43000300 +wm 32 0x021b483c 0x430a0310 + +wm 32 0x021b0840 0x030002b0 +wm 32 0x021b4840 0x02b00255 + +/* MPRDDLCTL, MPWRDLCTL */ +/* Measured on UT2 and UTC, good averages */ +wm 32 0x021b0848 0x453a3a3a +wm 32 0x021b4848 0x403b3947 +wm 32 0x021b0850 0x40444540 +wm 32 0x021b4850 0x46404840 + +/* MPWLDECTRL0,1 */ +/* Measured and averaged on UT2 and UTC boards */ +wm 32 0x021b080c 0x00200020 +wm 32 0x021b0810 0x0026001e +wm 32 0x021b480c 0x00100028 +wm 32 0x021b4810 0x0012001b + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00001006 /* Enable autorefresh */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* DEBUG leds */ +wm 32 0x020e0244 0x00000005 +wm 32 0x020e0614 0x000130b0 + +/* RGMII config */ +wm 32 0x020e0790 0x00080000 /* 1V2 DDR IO */ diff --git a/arch/arm/boards/protonic-imx6/flash-header-vicutp.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-vicutp.imxcfg new file mode 100644 index 0000000000..e218279239 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-vicutp.imxcfg @@ -0,0 +1,173 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e0228 0x00000005 +/* wm 32 0x020e0244 0x00000005 */ +wm 32 0x020e05f8 0x000130b0 +/* wm 32 0x020e0614 0x000130b0 */ + +#include "padsetup-q.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00001742 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 + +wm 32 0x021b000c MDCFG0_4G_533MHZ_CL7 +wm 32 0x021b0010 MDCFG1_533MHZ +wm 32 0x021b0014 MDCFG2_533MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_533MHZ +wm 32 0x021b0008 MDOTC_533MHZ +wm 32 0x021b0004 MDPDC_533MHZ +wm 32 0x021b0040 MDASP_2GIB25 + +/* Dual-Plus specific configuration */ +/* MMDC: MAARCR: Disable reordering */ +wm 32 0x021b0400 0x14420000 +/* MMDC: MPPDCMPR2: ZQ Offset setting (TODO) */ +wm 32 0x021b0890 0x00400008 /* Freescale sabre-auto: 0x00400C58 */ + +/* NOC: DDRCONF */ +/* Sabre-auto: wm 32 0x00bb0008 0x00000000 */ +/* Values (Address mapping for 64bit): + * 0 : 16 Row, 3 Bank, 10 Col interleave (11 Col for 32 bit) + * 1 : 15 Row, 3 Bank, 11 Col interleave (12 Col for 32 bit) + * 2 : 18 Row, 3 Bank, 8 Col interleave (9 Col for 32 bit) + * 3 : 17 Row, 3 Bank, 9 Col interleave (10 Col for 32 bit) + * 4 : 2 CS (?), 15 Row, 3 Bank, 10 Col, interleave + * ... + */ +wm 32 0x00bb0008 0x00000000 + +/* + * NOC DdrTiming: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * ActToAct 533MHz 0x1b (28) 0 0x0000001b + * RdToMiss 533MHz 0x10 (16) 6 0x00000400 + * WrToMiss * 0x1e (30) 12 0x0001e000 + * BurstLen * 0x4 (8/2) 18 0x00100000 + * RdToWr * 0x3 (3) 21 0x00600000 + * WrToRd * 0xa (10) 26 0x28000000 + * BwRatio * 0x0 (0) 31 0x00000000 + * ---------------------------------------------------------------- + */ +/* Sabre-auto: wm 32 0x00bb000c 0x2891E41A */ +wm 32 0x00bb000c 0x2871e41c + +/* + * NOC Activate: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * Rrd * 0x6 (6) 0 0x00000006 + * Faw * 0x1b (27) 4 0x000001b0 + * FawBank * 0x0 (0) 10 0x00000000 + * ---------------------------------------------------------------- + */ +/* Sabre-auto: wm 32 0x00bb0038 0x00000564 */ +wm 32 0x00bb0038 0x000001b6 + +/* + * NOC ReadLatency: (FIXME) + */ +wm 32 0x00bb0014 0x00000040 + +/* + * NOC IPU1/IPU2 aging: (FIXME) + */ +wm 32 0x00bb0028 0x00000020 +wm 32 0x00bb002c 0x00000020 + +wm 32 0x021b0000 MDCTL_4G +// check 32 until_any_bit_set 0x021b0018 0x80000000 + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_533MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_533MHZ_CL7 + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_60 +wm 32 0x021b4818 MPODTCTRL_ODT_60 + +wm 32 0x021b083c MPDGCTRL0_CH0_533MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_533MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_533MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_533MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x001f001f +wm 32 0x021b4810 0x001f001f + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00001006 /* Enable autorefresh */ + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* DEBUG leds */ +wm 32 0x020e0244 0x00000005 +wm 32 0x020e0614 0x000130b0 + +/* RGMII config */ +wm 32 0x020e0790 0x00080000 /* 1V2 DDR IO */ diff --git a/arch/arm/boards/protonic-imx6/lowlevel.c b/arch/arm/boards/protonic-imx6/lowlevel.c new file mode 100644 index 0000000000..f5784cc6b1 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/lowlevel.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 Protonic Holland + * Copyright (C) 2020 Oleksij Rempel, Pengutronix + */ + +#include <asm/barebox-arm.h> +#include <common.h> +#include <mach/esdctl.h> +#include <mach/generic.h> + +extern char __dtb_z_imx6q_prti6q_start[]; +extern char __dtb_z_imx6q_prtwd2_start[]; +extern char __dtb_z_imx6q_vicut1_start[]; +extern char __dtb_z_imx6dl_alti6p_start[]; +extern char __dtb_z_imx6dl_lanmcu_start[]; +extern char __dtb_z_imx6dl_plybas_start[]; +extern char __dtb_z_imx6dl_plym2m_start[]; +extern char __dtb_z_imx6dl_prtmvt_start[]; +extern char __dtb_z_imx6dl_prtrvt_start[]; +extern char __dtb_z_imx6dl_prtvt7_start[]; +extern char __dtb_z_imx6dl_victgo_start[]; +extern char __dtb_z_imx6dl_vicut1_start[]; +extern char __dtb_z_imx6qp_prtwd3_start[]; +extern char __dtb_z_imx6qp_vicutp_start[]; +extern char __dtb_z_imx6ul_prti6g_start[]; + +ENTRY_FUNCTION(start_imx6q_prti6q, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6q_prti6q_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6q_prtwd2, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6q_prtwd2_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6q_vicut1, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6q_vicut1_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_alti6p, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_alti6p_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_lanmcu, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_lanmcu_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_plybas, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_plybas_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_plym2m, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_plym2m_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_prtmvt, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_prtmvt_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_prtrvt, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_prtrvt_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_prtvt7, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_prtvt7_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_victgo, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_victgo_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_vicut1, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_vicut1_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6qp_prtwd3, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6qp_prtwd3_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6qp_vicutp, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6qp_vicutp_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6ul_prti6g, r0, r1, r2) +{ + void *fdt; + + imx6ul_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6ul_prti6g_start + get_runtime_offset(); + + imx6ul_barebox_entry(fdt); +} diff --git a/arch/arm/boards/protonic-imx6/lpddr2-defines.imxcfg b/arch/arm/boards/protonic-imx6/lpddr2-defines.imxcfg new file mode 100644 index 0000000000..29c42cc697 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/lpddr2-defines.imxcfg @@ -0,0 +1,384 @@ +/* + * Timing configuration: + * + * MDCFG0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tRFC 2Gb 400MHz 0x3f (64) 24 0x3f000000 + * 4Gb 400MHz 0x77 (120) 24 0x77000000 + * 8Gb 400MHz 0x8b (140) 24 0x8b000000 + * 2Gb 533MHz 0x55 (86) 24 0x55000000 + * 4Gb 533MHz 0x9f (160) 24 0x9f000000 + * 8Gb 533MHz 0xba (187) 24 0xba000000 + * 4Gb LPDDR2 0x33 (52) 24 0x33000000 + * tXS 2Gb 400MHz 0x43 (68) 16 0x00430000 + * 4Gb 400MHz 0x7b (124) 16 0x007b0000 + * 8Gb 400MHz 0x8f (144) 16 0x008f0000 + * 2Gb 533MHz 0x5b (92) 16 0x005b0000 + * 4Gb 533MHz 0xa5 (166) 16 0x00a50000 + * 8Gb 533MHz 0xc0 (193) 16 0x00c00000 + * 4Gb LPDDR2 0x37 (56) 16 0x00370000 + * tXP * 400MHz 0x2 (3) 13 0x00004000 + * * 533MHz 0x3 (4) 13 0x00006000 + * * LPDDR2 0x2 (3) 13 0x00004000 + * tXPDLL * 400MHz 0x9 (10) 9 0x00001200 + * * 533MHz 0xc (13) 9 0x00001800 + * * LPDDR2 0x1 (-) 9 0x00000200 + * tFAW * 400MHz 0x13 (20) 4 0x00000130 + * * 533MHz 0x1a (27) 4 0x000001a0 + * * LPDDR2 0x13 (20) 4 0x00000130 + * tCL * 400MHz 0x3 (6) 0 0x00000003 + * * 533MHz-CL7 0x4 (7) 0 0x00000004 + * * 533MHz-CL8 0x5 (8) 0 0x00000005 + * * LPDDR2 0x3 (6) 0 0x00000003 + * ---------------------------------------------------------------- + */ +#define MDCFG0_2G_400MHZ 0x3f435333 +#define MDCFG0_4G_400MHZ 0x777b5333 +#define MDCFG0_8G_400MHZ 0x8b8f5333 +#define MDCFG0_2G_533MHZ_CL8 0x555b79a5 +#define MDCFG0_2G_533MHZ_CL7 0x555b79a4 +#define MDCFG0_4G_533MHZ_CL8 0x9fa579a5 +#define MDCFG0_4G_533MHZ_CL7 0x9fa579a4 +#define MDCFG0_8G_533MHZ_CL8 0xbac079a5 +#define MDCFG0_8G_533MHZ_CL7 0xbac079a4 +#define MDCFG0_4G_LPDDR2_CL6 0x33374133 +#define MDCFG0_8G_LPDDR2_CL6 0x53574133 + + +/* + * MDCFG1: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tRCD * 400MHz 0x5 (6) 28 0xa0000000 + * * 533MHz 0x7 (8) 28 0xe0000000 + * * LPDDR2 0x5 (-) 28 0xa0000000 + * tRP * 400MHz 0x5 (6) 26 0x14000000 + * * 533MHz 0x7 (8) 26 0x1c000000 + * * LPDDR2 0x5 (-) 26 0x14000000 + * tRC * 400MHz 0x14 (21) 21 0x02800000 + * * 533MHz 0x1b (28) 21 0x03600000 + * * LPDDR2 0x15 (-) 21 0x02a00000 + * tRAS * 400MHz 0x0e (15) 16 0x000e0000 + * * 533MHz 0x13 (20) 16 0x00130000 + * * LPDDR2 0x10 (17) 16 0x00100000 + * tRPA * 0x1 (tRP+1) 15 0x00008000 + * RM rev 4: unused, read-only! 15 0x00000000 + * tWR * 400MHz 0x5 (6) 9 0x00000a00 + * * 533MHz 0x7 (8) 9 0x00000e00 + * * LPDDR2 0x5 (6) 9 0x00000a00 + * tMRD * 0x3 (4) 5 0x00000060 + * max(tMRR,tMRW) LPDDR2 0x4 (5) 5 0x00000080 + * tCWL * 400MHz 0x3 (5) 0 0x00000003 + * * 533MHz 0x4 (6) 0 0x00000004 + * tWL * LPDDR2 0x2 (3) 0 0x00000002 + * ---------------------------------------------------------------- + */ +#define MDCFG1_400MHZ 0xb68e8a63 +#define MDCFG1_533MHZ 0xff738e64 +#define MDCFG1_LPDDR2 0x00100a82 + +/* + * MDCFG2: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tDLLK * 0x1ff (512) 16 0x01ff0000 + * LPDDR2 0x0c7 (-) 16 0x00c70000 + * tRTP * 0x3 (4) 6 0x000000c0 + * LPDDR2 0x2 (3) 6 0x00000080 + * tWTR * 0x3 (4) 3 0x00000018 + * LPDDR2 0x2 (3) 3 0x00000010 + * tRRD * 400MHz 0x3 (4) 0 0x00000003 + * * 533MHz 0x5 (6) 0 0x00000005 + * LPDDR2 0x3 (4) 0 0x00000003 + * ---------------------------------------------------------------- + */ +#define MDCFG2_400MHZ 0x01ff00db +#define MDCFG2_533MHZ 0x01ff00dd +#define MDCFG2_LPDDR2 0x00000093 + +/* + * MDOR: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tXPR 2Gb 400MHz 0x43 (68) 16 0x00430000 + * 4Gb 400MHz 0x7b (124) 16 0x007b0000 + * 8Gb 400MHz 0x8f (144) 16 0x008f0000 + * 2Gb 533MHz 0x5b (92) 16 0x005b0000 + * 4Gb 533MHz 0xa5 (166) 16 0x00a50000 + * 8Gb 533MHz 0xc0 (193) 16 0x00c00000 + * * LPDDR2 0x9f (-) 16 0x009f0000 + * SDE_to_RST * 0x10 (14) 8 0x00001000 + * * LPDDR2 0xe (-) 8 0x00000e00 + * RST_to_CKE * 0x23 (33) 0 0x00000023 + * * LPDDR2 0x10 (14) 0 0x00000010 + * ---------------------------------------------------------------- + */ +#define MDOR_2G_400MHZ 0x00431023 +#define MDOR_4G_400MHZ 0x007b1023 +#define MDOR_8G_400MHZ 0x008f1023 +#define MDOR_2G_533MHZ 0x005b1023 +#define MDOR_4G_533MHZ 0x00a51023 +#define MDOR_8G_533MHZ 0x00c01023 +#define MDOR_LPDDR2 0x009f0e10 + +/* + * MDOTC ODT delays: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tAOFPD * 400MHz 0x3 (4) 27 0x18000000 + * * 533MHz 0x4 (5) 27 0x20000000 + * tAONPD * 400MHz 0x3 (4) 24 0x03000000 + * * 533MHz 0x4 (5) 24 0x04000000 + * tANPD * 400MHz 0x3 (4) 20 0x00300000 + * * 533MHz 0x4 (5) 20 0x00400000 + * tAXPD * 400MHz 0x3 (4) 16 0x00030000 + * * 533MHz 0x4 (5) 16 0x00040000 + * tODTLon * 400MHz 0x3 (3) 12 0x00003000 + * * 533MHz 0x4 (4) 12 0x00004000 + * tODTidle_off * 400MHz 0x3 (3) 4 0x00000030 + * * 533MHz 0x4 (4) 4 0x00000040 + * ---------------------------------------------------------------- + */ +#define MDOTC_400MHZ 0x1b333030 +#define MDOTC_533MHZ 0x24444040 +/* LPDDR2: not relevant, leave in reset state!! */ + +/* + * MDPDC: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * PRCT_1 * 0x0 28 0x00000000 + * PRCT_0 * 0x0 24 0x00000000 + * tCKE * 0x2 (3) 16 0x00020000 + * PWDT_1 * 0x5 (256) 12 0x00005000 + * PWDT_0 * 0x5 (256) 8 0x00000500 + * SLOW_PD * 0x0 (0) 7 0x00000000 + * BOTH_CS_PD * 0x1 (1) 6 0x00000040 + * tCKSRX * 400MHz 0x5 (5) 3 0x00000028 + * * 533MHz 0x6 (6) 3 0x00000030 + * tCKSRE * 400MHz 0x5 (5) 0 0x00000005 + * * 533MHz 0x6 (6) 0 0x00000006 + * ---------------------------------------------------------------- + */ +#define MDPDC_400MHZ 0x0002556d +#define MDPDC_533MHZ 0x00025576 +#define MDPDC_LPDDR2 0x00025576 /* FIXME? */ + +/* + * MDCTL: + * 2Gb: CS0 enable, 14bit ROW, 10bit COL, BL=8, 64bit data + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * SDE_0 * 0x1 (1) 31 0x80000000 + * SDE_1 * 0x0 (0) 30 0x00000000 + * SDE_1 LPDDR2 0x1 (1) 30 0x40000000 + * ROW 2Gb * 0x3 (14) 24 0x03000000 + * 4Gb * 0x4 (15) 24 0x04000000 + * 8Gb * 0x5 (16) 24 0x05000000 + * * LPDDR2 0x3 (14) 24 0x03000000 + * COL * 0x1 (10) 20 0x00100000 + * BL * 0x1 (8) 19 0x00080000 + * LPDDR2 0x0 (4) 19 0x00000000 + * DSIZ 64bit 0x2 (64) 16 0x00020000 + * DSIZ 32bit 0x1 (32) 16 0x00010000 + * DSIZ 16bit 0x0 (16) 16 0x00000000 + * ---------------------------------------------------------------- + */ +#define MDCTL_2G_16BIT 0x83180000 +#define MDCTL_2G_32BIT 0x83190000 +#define MDCTL_2G 0x831a0000 +#define MDCTL_4G_16BIT 0x84180000 +#define MDCTL_4G_32BIT 0x84190000 +#define MDCTL_4G 0x841a0000 +#define MDCTL_8G 0x851a0000 +#define MDCTL_LPDDR2 0x83110000 + + +/* + * MDASP Address space partitioning: + * + * At 0.25GiB, internal address space ends. Above that DDR3 should be + * located. The CS1/CS0 split-line determines where: + * + * For 1x2Gb chips (0.25GiB total on CS0): 0.5GiB + * For 2x4Gb chips (1GiB total on CS0): 1.25GiB + * For 4x2Gb chips (1GiB total on CS0): 1.25GiB + * For 4x4Gb chips (2GiB total on CS0): 2.25GiB + * For 4x8Gb chips (4GiB total on CS0): 4.00GiB (maximum possible, + * shadowed partially by internal address space). + * + * Register value Split + * --------------------------- + * 0x0000000f 0.5GiB + * 0x00000017 0.75GiB + * 0x00000027 1.25GiB + * 0x00000047 2.25GiB + * 0x0000007f 4.00GiB + */ +#define MDASP_512MIB 0x0000000f +#define MDASP_768MIB 0x00000017 +#define MDASP_1GIB25 0x00000027 +#define MDASP_2GIB25 0x00000047 +#define MDASP_4GIB00 0x0000007f + +/* + * Initialize DDR3 chips + * MDSCR: Value = 0xvvvv803n, with 0xvvvv = value, n = Reg. number (BA) + */ +/* + * DDR3 chip MR2, n = 2: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Rtt(wr) * 0x0 (disabled) 10, 9 0x0000 + * SR-Temp. * 0x1 (Extended) 7 0x0080 + * Auto-SR * 0x0 (Manual) 6 0x0000 + * CWL * 400MHz 0x0 (5tCK) 5, 4, 3 0x0000 + * * 533MHz 0x1 (6tCK) 5, 4, 3 0x0008 + * ---------------------------------------------------------------- + */ +#define DDR3_MR2_400MHZ_RTT_OFF 0x00808032 +#define DDR3_MR2_533MHZ_RTT_OFF 0x00888032 +#define DDR3_MR2_400MHZ_RTT_120 0x04808032 +#define DDR3_MR2_533MHZ_RTT_120 0x04888032 + +/* + * DDR3 chip MR1, n = 1: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Qoff * 0x0 (enabled) 12 0x0000 + * TDQS * 0x0 (disabled) 11 0x0000 + * Rtt * 0x0 (disabled) 9, 6, 2 0x0000 + * Write-levelling * 0x0 (disable) 7 0x0000 + * ODS * 0x0 (RZQ/6=40) 5, 1 0x0000 + * DLL * 0x0 (enable) 0 0x0000 + * ---------------------------------------------------------------- + */ +#define DDR3_MR1_RTT_OFF_ODS_40 0x00008031 +#define DDR3_MR1_RTT_120_ODS_40 0x00408031 +#define DDR3_MR1_RTT_60_ODS_40 0x00048031 +#define DDR3_MR1_RTT_OFF_ODS_34 0x00028031 +#define DDR3_MR1_RTT_120_ODS_34 0x00428031 +#define DDR3_MR1_RTT_60_ODS_34 0x00068031 + +/* + * DDR3 chip MR0, n = 0: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Precharge PD * 0x1 (fast exit) 12 0x1000 + * WR 400MHz 0x2 (6) 11,10,9 0x0400 + * 533MHz 0x4 (8) 11,10,9 0x0800 + * DLL reset * 0x1 (Yes) 8 0x0100 + * CL 400MHz 0x4 (6) 6,5,4,2 0x0020 + * 533MHz 0x6 (7) 6,5,4,2 0x0030 + * 533MHz 0x8 (8) 6,5,4,2 0x0040 + * RD burst type * 0x0 (seq.) 3 0x0000 + * BL * 0x0 (BL8) 0 0x0000 + * ---------------------------------------------------------------- + */ +#define DDR3_MR0_400MHZ 0x15208030 +#define DDR3_MR0_533MHZ_CL7 0x19308030 +#define DDR3_MR0_533MHZ_CL8 0x19408030 + + +/* + * MDREF: + * REF_SEL (bit 14,15): 0 (64kHz, needed for high-temp.) + * REFR (bit 11, 12, 13): 0x3 (4 refreshes) -> 0x00001800 + * 0x7 (8 refreshes) -> 0x00003800 + */ +#define MDREF_64KHZ 0x00001800 +#define MDREF_32KHZ 0x00007800 + +/* MPODTCTRL */ +#define MPODTCTRL_ODT_OFF 0x00000007 +#define MPODTCTRL_ODT_120 0x00011117 +#define MPODTCTRL_ODT_60 0x00022227 +#define MPODTCTRL_ODT_40 0x00033337 + +/* + * MPDGCTRL0: + * + * Channel 0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * RST_RD_FIFO * 0 31 0x00000000 + * DG_CMP_CYC * 1 30 0x40000000 + * DG_DIS * 0 29 0x00000000 + * HW_DG_EN * 0 28 0x00000000 + * DG_HC_DEL1 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_EXT_UP * 0 23 0x00000000 + * DG_DL_ABS_OFFS1 400MHz 0x35 16 0x00350000 + * 533MHz 0x4b 16 0x004b0000 + * DG_HC_DEL0 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS0 400MHz 0x35 0 0x00000031 + * 533MHz 0x4b 0 0x00000050 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL0_CH0_400MHZ 0x42350231 +#define MPDGCTRL0_CH0_533MHZ 0x434b0350 +/* + * + * Channel 1: + * + * DG_HC_DEL1 (5) 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS1 (5) 400MHz 0x35 16 0x00350000 + * 533MHz 0x4b 16 0x004b0000 + * DG_HC_DEL0 (4) 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS0 (4) 400MHz 0x35 0 0x00000031 + * 533MHz 0x4b 0 0x00000050 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL0_CH1_400MHZ 0x42350231 +#define MPDGCTRL0_CH1_533MHZ 0x434b0350 + +/* + * MPDGCTRL1: + * + * Channel 0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * DG_HC_DEL3 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS3 400MHz 0x1a 16 0x001a0000 + * 533MHz 0x4c 16 0x004c0000 + * DG_HC_DEL2 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS2 400MHz 0x18 0 0x00000018 + * 533MHz 0x59 0 0x00000059 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL1_CH0_400MHZ 0x021a0218 +#define MPDGCTRL1_CH0_533MHZ 0x034c0359 +/* + * + * Channel 1: + * + * DG_HC_DEL3 (7) 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS3 (7) 400MHz 0x1a 16 0x001a0000 + * 533MHz 0x65 16 0x00650000 + * DG_HC_DEL2 (6) 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS2 (6) 400MHz 0x18 0 0x00000018 + * 533MHz 0x48 0 0x00000048 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL1_CH1_400MHZ 0x021a0218 +#define MPDGCTRL1_CH1_533MHZ 0x03650348 diff --git a/arch/arm/boards/protonic-imx6/padsetup-dl.imxcfg b/arch/arm/boards/protonic-imx6/padsetup-dl.imxcfg new file mode 100644 index 0000000000..f60d37f63e --- /dev/null +++ b/arch/arm/boards/protonic-imx6/padsetup-dl.imxcfg @@ -0,0 +1,70 @@ + +/* + * Some defines for PAD setup: + * Unfortunately we don't have a powerful pre-processor, so we need to + * define explicit 32-bit hex values. + */ +#define PAD_DSE_48 0x00000028 +#define PAD_DSE_40 0x00000030 + +#define PAD_DIFF_IN_DSE_48 0x00020028 +#define PAD_DIFF_IN_DSE_40 0x00020030 +#define PAD_DIFF_IN_DSE_34 0x00020038 + +/* Disable ISB LED ASAP */ +wm 32 0x020e04a8 0x000130b0 + +#define PAD_SDQS PAD_DSE_48 +wm 32 0x020e04bc PAD_SDQS /* SDQS0_P */ +wm 32 0x020e04c0 PAD_SDQS /* SDQS1_P */ +wm 32 0x020e04c4 PAD_SDQS /* SDQS2_P */ +wm 32 0x020e04c8 PAD_SDQS /* SDQS3_P */ +wm 32 0x020e04cc PAD_SDQS /* SDQS4_P */ +wm 32 0x020e04d0 PAD_SDQS /* SDQS5_P */ +wm 32 0x020e04d4 PAD_SDQS /* SDQS6_P */ +wm 32 0x020e04d8 PAD_SDQS /* SDQS7_P */ + +#define PAD_DQM_CTRL PAD_DIFF_IN_DSE_48 +#define PAD_SDCLK PAD_DIFF_IN_DSE_40 +wm 32 0x020e0470 PAD_DQM_CTRL /* DQM0 */ +wm 32 0x020e0474 PAD_DQM_CTRL /* DQM1 */ +wm 32 0x020e0478 PAD_DQM_CTRL /* DQM2 */ +wm 32 0x020e047c PAD_DQM_CTRL /* DQM3 */ +wm 32 0x020e0480 PAD_DQM_CTRL /* DQM4 */ +wm 32 0x020e0484 PAD_DQM_CTRL /* DQM5 */ +wm 32 0x020e0488 PAD_DQM_CTRL /* DQM6 */ +wm 32 0x020e048c PAD_DQM_CTRL /* DQM7 */ +wm 32 0x020e0464 PAD_DQM_CTRL /* CAS */ +wm 32 0x020e0490 PAD_DQM_CTRL /* RAS */ +wm 32 0x020e04ac PAD_SDCLK /* SDCLK0_P */ +wm 32 0x020e04b0 PAD_SDCLK /* SDCLK1_P */ +wm 32 0x020e0494 PAD_DQM_CTRL /* RESET */ + +/* 0x00003000 = 100k PU */ +wm 32 0x020e04a4 0x00003000 /* SDCKE0 */ +wm 32 0x020e04a8 0x00003000 /* SDCKE1 */ +wm 32 0x020e04a0 0x00000000 /* SDBA2: disable PU */ + +/* 0x00003030 = PU + 40 Ohm drive */ +wm 32 0x020e04b4 0x00003030 /* ODT0 */ +wm 32 0x020e04b8 0x00003030 /* ODT1 */ + +#define PAD_BxDS PAD_DSE_48 +wm 32 0x020e0764 PAD_BxDS /* B0DS */ +wm 32 0x020e0770 PAD_BxDS /* B1DS */ +wm 32 0x020e0778 PAD_BxDS /* B2DS */ +wm 32 0x020e077c PAD_BxDS /* B3DS */ +wm 32 0x020e0780 PAD_BxDS /* B4DS */ +wm 32 0x020e0784 PAD_BxDS /* B5DS */ +wm 32 0x020e078c PAD_BxDS /* B6DS */ +wm 32 0x020e0748 PAD_BxDS /* B7DS */ +wm 32 0x020e074c PAD_DSE_48 /* ADDDS */ + +wm 32 0x020e0750 0x00020000 /* DDRMODE_CTL */ +wm 32 0x020e0754 0x00000000 /* DDRPKE disable PU */ +wm 32 0x020e0760 0x00020000 /* DDRMODE data */ + +wm 32 0x020e076c 0x00000030 /* CTLDS 40 Ohm */ + +wm 32 0x020e0774 0x000c0000 /* DDR_TYPE DDR3 */ + diff --git a/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg b/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg new file mode 100644 index 0000000000..f5fa3e8d28 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg @@ -0,0 +1,69 @@ + +/* + * Some defines for PAD setup: + * Unfortunately we don't have a powerful pre-processor, so we need to + * define explicit 32-bit hex values. + */ +#define PAD_DSE_48 0x00000028 +#define PAD_DSE_40 0x00000030 + +#define PAD_DIFF_IN_DSE_48 0x00020028 +#define PAD_DIFF_IN_DSE_40 0x00020030 +#define PAD_DIFF_IN_DSE_34 0x00020038 + +/* Disable ISB LED ASAP */ +wm 32 0x020e0420 0x000130b0 + +#define PAD_SDQS PAD_DSE_48 +wm 32 0x020e05a8 PAD_SDQS /* SDQS0_P */ +wm 32 0x020e05b0 PAD_SDQS /* SDQS1_P */ +wm 32 0x020e0524 PAD_SDQS /* SDQS2_P */ +wm 32 0x020e051c PAD_SDQS /* SDQS3_P */ +wm 32 0x020e0518 PAD_SDQS /* SDQS4_P */ +wm 32 0x020e050c PAD_SDQS /* SDQS5_P */ +wm 32 0x020e05b8 PAD_SDQS /* SDQS6_P */ +wm 32 0x020e05c0 PAD_SDQS /* SDQS7_P */ + +#define PAD_DQM_CTRL PAD_DIFF_IN_DSE_48 +#define PAD_SDCLK PAD_DIFF_IN_DSE_40 +wm 32 0x020e05ac PAD_DQM_CTRL /* DQM0 */ +wm 32 0x020e05b4 PAD_DQM_CTRL /* DQM1 */ +wm 32 0x020e0528 PAD_DQM_CTRL /* DQM2 */ +wm 32 0x020e0520 PAD_DQM_CTRL /* DQM3 */ +wm 32 0x020e0514 PAD_DQM_CTRL /* DQM4 */ +wm 32 0x020e0510 PAD_DQM_CTRL /* DQM5 */ +wm 32 0x020e05bc PAD_DQM_CTRL /* DQM6 */ +wm 32 0x020e05c4 PAD_DQM_CTRL /* DQM7 */ +wm 32 0x020e056c PAD_DQM_CTRL /* CAS */ +wm 32 0x020e0578 PAD_DQM_CTRL /* RAS */ +wm 32 0x020e0588 PAD_SDCLK /* SDCLK0_P */ +wm 32 0x020e0594 PAD_SDCLK /* SDCLK1_P */ +wm 32 0x020e057c PAD_DQM_CTRL /* RESET */ + +/* 0x00003000 = 100k PU */ +wm 32 0x020e0590 0x00003000 /* SDCKE0 */ +wm 32 0x020e0598 0x00003000 /* SDCKE1 */ +wm 32 0x020e058c 0x00000000 /* SDBA2: disable PU */ + +/* 0x00003030 = PU + 40 Ohm drive */ +wm 32 0x020e059c 0x00003030 /* ODT0 */ +wm 32 0x020e05a0 0x00003030 /* ODT1 */ + +#define PAD_BxDS PAD_DSE_48 +wm 32 0x020e0784 PAD_BxDS /* B0DS */ +wm 32 0x020e0788 PAD_BxDS /* B1DS */ +wm 32 0x020e0794 PAD_BxDS /* B2DS */ +wm 32 0x020e079c PAD_BxDS /* B3DS */ +wm 32 0x020e07a0 PAD_BxDS /* B4DS */ +wm 32 0x020e07a4 PAD_BxDS /* B5DS */ +wm 32 0x020e07a8 PAD_BxDS /* B6DS */ +wm 32 0x020e0748 PAD_BxDS /* B7DS */ +wm 32 0x020e074c PAD_DSE_48 /* ADDDS */ + +wm 32 0x020e0750 0x00020000 /* DDRMODE_CTL */ +wm 32 0x020e0758 0x00000000 /* DDRPKE disable PU */ +wm 32 0x020e0774 0x00020000 /* DDRMODE data */ + +wm 32 0x020e078c 0x00000030 /* CTLDS 40 Ohm */ + +wm 32 0x020e0798 0x000c0000 /* DDR_TYPE DDR3 */ diff --git a/arch/arm/boards/protonic-imx6/padsetup-ul.imxcfg b/arch/arm/boards/protonic-imx6/padsetup-ul.imxcfg new file mode 100644 index 0000000000..e36601942d --- /dev/null +++ b/arch/arm/boards/protonic-imx6/padsetup-ul.imxcfg @@ -0,0 +1,42 @@ + +/* + * Some defines for PAD setup: + * Unfortunately we don't have a powerful pre-processor, so we need to + * define explicit 32-bit hex values. + */ + +#define PAD_DSE_48 0x00000028 +#define PAD_DSE_40 0x00000030 + +#define PAD_SDQS PAD_DSE_48 +wm 32 0x020e0280 PAD_SDQS /* SDQS0_P */ +wm 32 0x020e0284 PAD_SDQS /* SDQS1_P */ + +#define PAD_DQM_CTRL PAD_DSE_48 +#define PAD_SDCLK PAD_DSE_48 + +wm 32 0x020e0244 PAD_DQM_CTRL /* DQM0 */ +wm 32 0x020e0248 PAD_DQM_CTRL /* DQM1 */ +wm 32 0x020e024c PAD_DQM_CTRL /* RAS */ +wm 32 0x020e0250 PAD_DQM_CTRL /* CAS */ +wm 32 0x020e027c PAD_SDCLK /* SDCLK0_P */ +wm 32 0x020e0288 PAD_DQM_CTRL /* RESET */ + +wm 32 0x020e0270 0x00000000 /* SDBA2: disable PU */ + +wm 32 0x020e0260 PAD_DSE_48 /* ODT0 */ +wm 32 0x020e0264 PAD_DSE_48 /* ODT1 */ + +#define PAD_BxDS PAD_DSE_48 +wm 32 0x020e0498 PAD_BxDS /* B0DS */ +wm 32 0x020e04a4 PAD_BxDS /* B1DS */ + +wm 32 0x020e0490 PAD_DSE_48 /* ADDDS */ + +wm 32 0x020e0494 0x00020000 /* DDRMODE_CTL */ +wm 32 0x020e04ac 0x00000000 /* DDRPKE disable PU */ +wm 32 0x020e04b0 0x00020000 /* DDRMODE data */ + +wm 32 0x020e04a0 0x00000030 /* CTLDS 40 Ohm */ + +wm 32 0x020e04b4 0x000c0000 /* DDR_TYPE DDR3 */ diff --git a/arch/arm/boards/radxa-rock/board.c b/arch/arm/boards/radxa-rock/board.c index d45e8a9c52..5c87f64897 100644 --- a/arch/arm/boards/radxa-rock/board.c +++ b/arch/arm/boards/radxa-rock/board.c @@ -1,15 +1,5 @@ -/* - * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Beniamino Galvani <b.galvani@gmail.com> #include <common.h> #include <init.h> diff --git a/arch/arm/boards/radxa-rock/lowlevel.c b/arch/arm/boards/radxa-rock/lowlevel.c index 611dc938cf..982090e08c 100644 --- a/arch/arm/boards/radxa-rock/lowlevel.c +++ b/arch/arm/boards/radxa-rock/lowlevel.c @@ -1,15 +1,5 @@ -/* - * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Beniamino Galvani <b.galvani@gmail.com> #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c index 45961b52ee..d5995fb86d 100644 --- a/arch/arm/boards/raspberry-pi/rpi-common.c +++ b/arch/arm/boards/raspberry-pi/rpi-common.c @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2009 Carlo Caione <carlo@carlocaione.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Carlo Caione <carlo@carlocaione.org> #include <common.h> #include <init.h> diff --git a/arch/arm/boards/sama5d27-giantboard/Makefile b/arch/arm/boards/sama5d27-giantboard/Makefile index b08c4a93ca..f5869c4839 100644 --- a/arch/arm/boards/sama5d27-giantboard/Makefile +++ b/arch/arm/boards/sama5d27-giantboard/Makefile @@ -1 +1,3 @@ lwl-y += lowlevel.o +obj-y += board.o +bbenv-y += defaultenv-giantboard diff --git a/arch/arm/boards/sama5d27-giantboard/board.c b/arch/arm/boards/sama5d27-giantboard/board.c new file mode 100644 index 0000000000..006c6ffad5 --- /dev/null +++ b/arch/arm/boards/sama5d27-giantboard/board.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <init.h> +#include <envfs.h> +#include <bbu.h> +#include <of.h> + +static int giantboard_device_init(void) +{ + if (!of_machine_is_compatible("groboards,sama5d27-giantboard")) + return 0; + + bbu_register_std_file_update("microSD", BBU_HANDLER_FLAG_DEFAULT, + "/mnt/mmc1.0/barebox.bin", + filetype_arm_barebox); + + defaultenv_append_directory(defaultenv_giantboard); + + return 0; +} +device_initcall(giantboard_device_init); diff --git a/arch/arm/boards/sama5d27-giantboard/defaultenv-giantboard/nv/boot.default b/arch/arm/boards/sama5d27-giantboard/defaultenv-giantboard/nv/boot.default new file mode 100644 index 0000000000..646f435652 --- /dev/null +++ b/arch/arm/boards/sama5d27-giantboard/defaultenv-giantboard/nv/boot.default @@ -0,0 +1 @@ +mmc1 diff --git a/arch/arm/boards/sama5d27-giantboard/lowlevel.c b/arch/arm/boards/sama5d27-giantboard/lowlevel.c index 0236c424c1..ee8297fa45 100644 --- a/arch/arm/boards/sama5d27-giantboard/lowlevel.c +++ b/arch/arm/boards/sama5d27-giantboard/lowlevel.c @@ -5,59 +5,44 @@ #include <common.h> #include <init.h> - -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> -#include <mach/at91_pmc_ll.h> - -#include <mach/hardware.h> +#include <mach/barebox-arm.h> +#include <mach/sama5d2_ll.h> +#include <mach/xload.h> +#include <mach/sama5d2-sip-ddramc.h> #include <mach/iomux.h> #include <debug_ll.h> -#include <mach/at91_dbgu.h> /* PCK = 492MHz, MCK = 164MHz */ #define MASTER_CLOCK 164000000 -static inline void sama5d2_pmc_enable_periph_clock(int clk) +SAMA5_ENTRY_FUNCTION(start_sama5d27_giantboard_xload_mmc, r4) { - at91_pmc_sam9x5_enable_periph_clock(IOMEM(SAMA5D2_BASE_PMC), clk); -} + void __iomem *dbgu_base; -static void dbgu_init(void) -{ - unsigned mck = MASTER_CLOCK / 2; + sama5d2_lowlevel_init(); - sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_PIOD); - - at91_mux_pio4_set_A_periph(IOMEM(SAMA5D2_BASE_PIOD), - pin_to_mask(AT91_PIN_PD3)); /* DBGU TXD */ + dbgu_base = sama5d2_resetup_uart_console(MASTER_CLOCK); + putc_ll('>'); - sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_UART1); + relocate_to_current_adr(); + setup_c(); - at91_dbgu_setup_ll(IOMEM(SAMA5D2_BASE_UART1), mck, 115200); + pbl_set_putc(at91_dbgu_putc, dbgu_base); - putc_ll('>'); + sama5d2_udelay_init(MASTER_CLOCK); + sama5d2_d1g_ddrconf(); + sama5d2_sdhci_start_image(r4); } extern char __dtb_z_at91_sama5d27_giantboard_start[]; -static noinline void giantboard_entry(void) +SAMA5_ENTRY_FUNCTION(start_sama5d27_giantboard, r4) { void *fdt; - if (IS_ENABLED(CONFIG_DEBUG_LL)) - dbgu_init(); + putc_ll('>'); fdt = __dtb_z_at91_sama5d27_giantboard_start + get_runtime_offset(); - barebox_arm_entry(SAMA5_DDRCS, SZ_128M, fdt); -} - -ENTRY_FUNCTION(start_sama5d27_giantboard, r0, r1, r2) -{ - arm_cpu_lowlevel_init(); - - arm_setup_stack(SAMA5D2_SRAM_BASE + SAMA5D2_SRAM_SIZE); - - giantboard_entry(); + sama5d2_barebox_entry(r4, fdt); } diff --git a/arch/arm/boards/sama5d27-som1/Makefile b/arch/arm/boards/sama5d27-som1/Makefile index b08c4a93ca..092c31d6b2 100644 --- a/arch/arm/boards/sama5d27-som1/Makefile +++ b/arch/arm/boards/sama5d27-som1/Makefile @@ -1 +1,2 @@ lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/sama5d27-som1/board.c b/arch/arm/boards/sama5d27-som1/board.c new file mode 100644 index 0000000000..00c0e92a5d --- /dev/null +++ b/arch/arm/boards/sama5d27-som1/board.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <linux/sizes.h> +#include <init.h> +#include <asm/memory.h> +#include <bbu.h> +#include <bootsource.h> +#include <of.h> + +static int ek_device_init(void) +{ + int flags_sd = 0, flags_usd = 0; + if (!of_machine_is_compatible("atmel,sama5d27-som1-ek")) + return 0; + + if (bootsource_get() == BOOTSOURCE_MMC) { + if (bootsource_get_instance() == 0) { + flags_sd = BBU_HANDLER_FLAG_DEFAULT; + of_device_enable_path("/chosen/environment-sd"); + } else { + flags_usd = BBU_HANDLER_FLAG_DEFAULT; + of_device_enable_path("/chosen/environment-microsd"); + } + } else { + of_device_enable_path("/chosen/environment-qspi"); + } + + bbu_register_std_file_update("SD", flags_sd, "/mnt/mmc0.0/barebox.bin", + filetype_arm_barebox); + bbu_register_std_file_update("microSD", flags_usd, "/mnt/mmc1.0/barebox.bin", + filetype_arm_barebox); + return 0; +} +device_initcall(ek_device_init); diff --git a/arch/arm/boards/sama5d27-som1/lowlevel.c b/arch/arm/boards/sama5d27-som1/lowlevel.c index 62d35be912..b093711918 100644 --- a/arch/arm/boards/sama5d27-som1/lowlevel.c +++ b/arch/arm/boards/sama5d27-som1/lowlevel.c @@ -5,15 +5,12 @@ #include <common.h> #include <init.h> - -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> -#include <mach/at91_pmc_ll.h> - -#include <mach/hardware.h> +#include <mach/barebox-arm.h> +#include <mach/sama5d2_ll.h> #include <mach/iomux.h> +#include <mach/xload.h> #include <debug_ll.h> -#include <mach/at91_dbgu.h> +#include <mach/sama5d2-sip-ddramc.h> #define RGB_LED_GREEN (1 << 0) #define RGB_LED_RED (1 << 1) @@ -22,15 +19,10 @@ /* PCK = 492MHz, MCK = 164MHz */ #define MASTER_CLOCK 164000000 -static inline void sama5d2_pmc_enable_periph_clock(int clk) -{ - at91_pmc_sam9x5_enable_periph_clock(IOMEM(SAMA5D2_BASE_PMC), clk); -} - static void ek_turn_led(unsigned color) { struct { - unsigned long pio; + void __iomem *pio; unsigned bit; unsigned color; } *led, leds[] = { @@ -41,48 +33,41 @@ static void ek_turn_led(unsigned color) }; for (led = leds; led->pio; led++) { - at91_mux_gpio4_enable(IOMEM(led->pio), BIT(led->bit)); - at91_mux_gpio4_input(IOMEM(led->pio), BIT(led->bit), false); - at91_mux_gpio4_set(IOMEM(led->pio), BIT(led->bit), led->color); + at91_mux_gpio4_enable(led->pio, BIT(led->bit)); + at91_mux_gpio4_input(led->pio, BIT(led->bit), false); + at91_mux_gpio4_set(led->pio, BIT(led->bit), led->color); } } -static void ek_dbgu_init(void) +SAMA5_ENTRY_FUNCTION(start_sama5d27_som1_ek_xload_mmc, r4) { - unsigned mck = MASTER_CLOCK / 2; - - sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_PIOD); + void __iomem *dbgu_base; + sama5d2_lowlevel_init(); - at91_mux_pio4_set_A_periph(IOMEM(SAMA5D2_BASE_PIOD), - pin_to_mask(AT91_PIN_PD3)); /* DBGU TXD */ + dbgu_base = sama5d2_resetup_uart_console(MASTER_CLOCK); + putc_ll('>'); - sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_UART1); + relocate_to_current_adr(); + setup_c(); - at91_dbgu_setup_ll(IOMEM(SAMA5D2_BASE_UART1), mck, 115200); + pbl_set_putc(at91_dbgu_putc, dbgu_base); - putc_ll('>'); + ek_turn_led(RGB_LED_RED | RGB_LED_GREEN); /* Yellow */ + sama5d2_udelay_init(MASTER_CLOCK); + sama5d2_d1g_ddrconf(); + sama5d2_sdhci_start_image(r4); } extern char __dtb_z_at91_sama5d27_som1_ek_start[]; -static noinline void som1_entry(void) +SAMA5_ENTRY_FUNCTION(start_sama5d27_som1_ek, r4) { void *fdt; - if (IS_ENABLED(CONFIG_DEBUG_LL)) - ek_dbgu_init(); + putc_ll('>'); fdt = __dtb_z_at91_sama5d27_som1_ek_start + get_runtime_offset(); ek_turn_led(RGB_LED_GREEN); - barebox_arm_entry(SAMA5_DDRCS, SZ_128M, fdt); -} - -ENTRY_FUNCTION(start_sama5d27_som1_ek, r0, r1, r2) -{ - arm_cpu_lowlevel_init(); - - arm_setup_stack(SAMA5D2_SRAM_BASE + SAMA5D2_SRAM_SIZE); - - som1_entry(); + sama5d2_barebox_entry(r4, fdt); } diff --git a/arch/arm/boards/sama5d3_xplained/init.c b/arch/arm/boards/sama5d3_xplained/init.c index 2433e25f16..ccddd01dea 100644 --- a/arch/arm/boards/sama5d3_xplained/init.c +++ b/arch/arm/boards/sama5d3_xplained/init.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2014 Bo Shen <voice.shen@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Bo Shen <voice.shen@gmail.com> #include <common.h> #include <net.h> diff --git a/arch/arm/boards/sama5d3_xplained/lowlevel.c b/arch/arm/boards/sama5d3_xplained/lowlevel.c index 8653c48c69..28c07d5053 100644 --- a/arch/arm/boards/sama5d3_xplained/lowlevel.c +++ b/arch/arm/boards/sama5d3_xplained/lowlevel.c @@ -10,7 +10,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_ddrsdrc.h> #include <mach/hardware.h> void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) diff --git a/arch/arm/boards/sama5d3xek/hw_version.c b/arch/arm/boards/sama5d3xek/hw_version.c index e5077854e3..03c8df2cad 100644 --- a/arch/arm/boards/sama5d3xek/hw_version.c +++ b/arch/arm/boards/sama5d3xek/hw_version.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <fs.h> diff --git a/arch/arm/boards/sama5d3xek/hw_version.h b/arch/arm/boards/sama5d3xek/hw_version.h index ed9ea88d42..d90c751629 100644 --- a/arch/arm/boards/sama5d3xek/hw_version.h +++ b/arch/arm/boards/sama5d3xek/hw_version.h @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #ifndef __HW_REVISION_H__ #define __HW_REVISION_H__ diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c index c768e98d26..4892c09b2f 100644 --- a/arch/arm/boards/sama5d3xek/init.c +++ b/arch/arm/boards/sama5d3xek/init.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <net.h> @@ -408,7 +395,7 @@ static void ek_add_device_hdmi(void) hdmi_reset_start = get_time_ns(); hdmi_poller.func = hdmi_off_poller; - poller_register(&hdmi_poller); + poller_register(&hdmi_poller, "hdmi-reset"); } #else static void ek_add_device_hdmi(void) diff --git a/arch/arm/boards/sama5d3xek/lowlevel.c b/arch/arm/boards/sama5d3xek/lowlevel.c index 8653c48c69..28c07d5053 100644 --- a/arch/arm/boards/sama5d3xek/lowlevel.c +++ b/arch/arm/boards/sama5d3xek/lowlevel.c @@ -10,7 +10,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_ddrsdrc.h> #include <mach/hardware.h> void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) diff --git a/arch/arm/boards/sama5d4_xplained/lowlevel.c b/arch/arm/boards/sama5d4_xplained/lowlevel.c index 9a6a767e5f..3c58a08f3b 100644 --- a/arch/arm/boards/sama5d4_xplained/lowlevel.c +++ b/arch/arm/boards/sama5d4_xplained/lowlevel.c @@ -10,7 +10,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_ddrsdrc.h> #include <mach/hardware.h> void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) diff --git a/arch/arm/boards/sama5d4ek/lowlevel.c b/arch/arm/boards/sama5d4ek/lowlevel.c index 9a6a767e5f..3c58a08f3b 100644 --- a/arch/arm/boards/sama5d4ek/lowlevel.c +++ b/arch/arm/boards/sama5d4ek/lowlevel.c @@ -10,7 +10,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_ddrsdrc.h> #include <mach/hardware.h> void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) diff --git a/arch/arm/boards/scb9328/lowlevel_init.S b/arch/arm/boards/scb9328/lowlevel_init.S index e20e3b92da..eff5a5088f 100644 --- a/arch/arm/boards/scb9328/lowlevel_init.S +++ b/arch/arm/boards/scb9328/lowlevel_init.S @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2004 Sascha Hauer, Synertronixx GmbH #include <mach/imx1-regs.h> #include <asm/barebox-arm-head.h> diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c index 87fb6affbd..1c78fac441 100644 --- a/arch/arm/boards/scb9328/scb9328.c +++ b/arch/arm/boards/scb9328/scb9328.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2004 Sascha Hauer, Synertronixx GmbH #include <common.h> #include <net.h> diff --git a/arch/arm/boards/stm32mp157c-dk2/Makefile b/arch/arm/boards/seeed-odyssey/Makefile index 092c31d6b2..092c31d6b2 100644 --- a/arch/arm/boards/stm32mp157c-dk2/Makefile +++ b/arch/arm/boards/seeed-odyssey/Makefile diff --git a/arch/arm/boards/seeed-odyssey/board.c b/arch/arm/boards/seeed-odyssey/board.c new file mode 100644 index 0000000000..8c011898a3 --- /dev/null +++ b/arch/arm/boards/seeed-odyssey/board.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <linux/sizes.h> +#include <init.h> +#include <asm/memory.h> +#include <mach/bbu.h> +#include <bootsource.h> +#include <of.h> + +static int odyssey_som_probe(struct device_d *dev) +{ + int flags; + int instance = bootsource_get_instance(); + + flags = instance == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0; + stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", flags); + + flags = instance == 1 ? BBU_HANDLER_FLAG_DEFAULT : 0; + stm32mp_bbu_mmc_register_handler("emmc", "/dev/mmc1.ssbl", flags); + + + if (instance == 0) + of_device_enable_path("/chosen/environment-sd"); + else + of_device_enable_path("/chosen/environment-emmc"); + + return 0; +} + +static const struct of_device_id odyssey_som_of_match[] = { + { .compatible = "seeed,stm32mp157c-odyssey-som" }, + { /* sentinel */ }, +}; + +static struct driver_d odyssey_som_driver = { + .name = "odyssey-som", + .probe = odyssey_som_probe, + .of_compatible = odyssey_som_of_match, +}; +device_platform_driver(odyssey_som_driver); diff --git a/arch/arm/boards/seeed-odyssey/lowlevel.c b/arch/arm/boards/seeed-odyssey/lowlevel.c new file mode 100644 index 0000000000..5ab1639dfe --- /dev/null +++ b/arch/arm/boards/seeed-odyssey/lowlevel.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <mach/entry.h> +#include <debug_ll.h> + +extern char __dtb_z_stm32mp157c_odyssey_start[]; + +ENTRY_FUNCTION(start_stm32mp157c_seeed_odyssey, r0, r1, r2) +{ + void *fdt; + + stm32mp_cpu_lowlevel_init(); + + putc_ll('>'); + + fdt = __dtb_z_stm32mp157c_odyssey_start + get_runtime_offset(); + + stm32mp1_barebox_entry(fdt); +} diff --git a/arch/arm/boards/solidrun-cubox/board.c b/arch/arm/boards/solidrun-cubox/board.c index aac93afb0c..f3cb5c92f5 100644 --- a/arch/arm/boards/solidrun-cubox/board.c +++ b/arch/arm/boards/solidrun-cubox/board.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2013 - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <init.h> diff --git a/arch/arm/boards/solidrun-cubox/lowlevel.c b/arch/arm/boards/solidrun-cubox/lowlevel.c index ec63986b38..94ed9a4fd7 100644 --- a/arch/arm/boards/solidrun-cubox/lowlevel.c +++ b/arch/arm/boards/solidrun-cubox/lowlevel.c @@ -1,19 +1,6 @@ -/* - * Copyright (C) 2013 - * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> +// SPDX-FileCopyrightText: 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/solidrun-microsom/1066mhz-4x128mx16.imxcfg b/arch/arm/boards/solidrun-microsom/1066mhz-4x128mx16.imxcfg index 453de7491a..eb34d8b54c 100644 --- a/arch/arm/boards/solidrun-microsom/1066mhz-4x128mx16.imxcfg +++ b/arch/arm/boards/solidrun-microsom/1066mhz-4x128mx16.imxcfg @@ -1,18 +1,7 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices +// SPDX-FileCopyrightText: 2013 SolidRun ltd. +// SPDX-FileCopyrightText: 2013 Jon Nettleton <jon.nettleton@gmail.com> wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1390003 diff --git a/arch/arm/boards/solidrun-microsom/1066mhz-4x256mx16.imxcfg b/arch/arm/boards/solidrun-microsom/1066mhz-4x256mx16.imxcfg index 29ef0987cb..6fd7ac903b 100644 --- a/arch/arm/boards/solidrun-microsom/1066mhz-4x256mx16.imxcfg +++ b/arch/arm/boards/solidrun-microsom/1066mhz-4x256mx16.imxcfg @@ -1,18 +1,7 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices +// SPDX-FileCopyrightText: 2013 SolidRun ltd. +// SPDX-FileCopyrightText: 2013 Jon Nettleton <jon.nettleton@gmail.com> wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1390003 diff --git a/arch/arm/boards/solidrun-microsom/1066mhz-64b.imxcfg b/arch/arm/boards/solidrun-microsom/1066mhz-64b.imxcfg index 73de49d27f..4f4bebc4b2 100644 --- a/arch/arm/boards/solidrun-microsom/1066mhz-64b.imxcfg +++ b/arch/arm/boards/solidrun-microsom/1066mhz-64b.imxcfg @@ -1,18 +1,7 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices +// SPDX-FileCopyrightText: 2013 SolidRun ltd. +// SPDX-FileCopyrightText: 2013 Jon Nettleton <jon.nettleton@gmail.com> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/solidrun-microsom/800mhz-2x128mx16.imxcfg b/arch/arm/boards/solidrun-microsom/800mhz-2x128mx16.imxcfg index 9749bb1abc..5db0c91816 100644 --- a/arch/arm/boards/solidrun-microsom/800mhz-2x128mx16.imxcfg +++ b/arch/arm/boards/solidrun-microsom/800mhz-2x128mx16.imxcfg @@ -1,18 +1,7 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices +// SPDX-FileCopyrightText: 2013 SolidRun ltd. +// SPDX-FileCopyrightText: 2013 Jon Nettleton <jon.nettleton@gmail.com> wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1390003 diff --git a/arch/arm/boards/solidrun-microsom/800mhz-32b.imxcfg b/arch/arm/boards/solidrun-microsom/800mhz-32b.imxcfg index d7ca913db2..20e5b2782b 100644 --- a/arch/arm/boards/solidrun-microsom/800mhz-32b.imxcfg +++ b/arch/arm/boards/solidrun-microsom/800mhz-32b.imxcfg @@ -1,18 +1,7 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices +// SPDX-FileCopyrightText: 2013 SolidRun ltd. +// SPDX-FileCopyrightText: 2013 Jon Nettleton <jon.nettleton@gmail.com> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/solidrun-microsom/800mhz-4x128mx16.imxcfg b/arch/arm/boards/solidrun-microsom/800mhz-4x128mx16.imxcfg index 9c04ea674c..6144864c1a 100644 --- a/arch/arm/boards/solidrun-microsom/800mhz-4x128mx16.imxcfg +++ b/arch/arm/boards/solidrun-microsom/800mhz-4x128mx16.imxcfg @@ -1,18 +1,7 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices +// SPDX-FileCopyrightText: 2013 SolidRun ltd. +// SPDX-FileCopyrightText: 2013 Jon Nettleton <jon.nettleton@gmail.com> wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x0045004D diff --git a/arch/arm/boards/solidrun-microsom/800mhz-64b.imxcfg b/arch/arm/boards/solidrun-microsom/800mhz-64b.imxcfg index 78b7a234ad..5f00cd900d 100644 --- a/arch/arm/boards/solidrun-microsom/800mhz-64b.imxcfg +++ b/arch/arm/boards/solidrun-microsom/800mhz-64b.imxcfg @@ -1,18 +1,7 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices +// SPDX-FileCopyrightText: 2013 SolidRun ltd. +// SPDX-FileCopyrightText: 2013 Jon Nettleton <jon.nettleton@gmail.com> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/solidrun-microsom/board.c b/arch/arm/boards/solidrun-microsom/board.c index 155199ff78..85e1ab4250 100644 --- a/arch/arm/boards/solidrun-microsom/board.c +++ b/arch/arm/boards/solidrun-microsom/board.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Lucas Stach <l.stach@pengutronix.de> #include <asm/armlinux.h> #include <asm/io.h> diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg index eb7bc8486d..2c6a32eed4 100644 --- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg index 8930012885..7f9b2a3988 100644 --- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg index 4eb937a717..7f75a17a35 100644 --- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg index 438bd8ea4d..9d5bc03c96 100644 --- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/stm32mp157c-dk2/board.c b/arch/arm/boards/stm32mp157c-dk2/board.c deleted file mode 100644 index 4636603121..0000000000 --- a/arch/arm/boards/stm32mp157c-dk2/board.c +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include <common.h> -#include <init.h> -#include <mach/bbu.h> - -static int dk2_postcore_init(void) -{ - if (!of_machine_is_compatible("st,stm32mp157c-dk2")) - return 0; - - stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", - BBU_HANDLER_FLAG_DEFAULT); - - barebox_set_model("STM32MP157C-DK2"); - - return 0; -} -postcore_initcall(dk2_postcore_init); diff --git a/arch/arm/boards/stm32mp157c-dk2/lowlevel.c b/arch/arm/boards/stm32mp157c-dk2/lowlevel.c deleted file mode 100644 index 7261d7a8bc..0000000000 --- a/arch/arm/boards/stm32mp157c-dk2/lowlevel.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include <common.h> -#include <mach/entry.h> -#include <debug_ll.h> - -extern char __dtb_z_stm32mp157c_dk2_start[]; - -static void setup_uart(void) -{ - /* first stage has set up the UART, so nothing to do here */ - putc_ll('>'); -} - -ENTRY_FUNCTION(start_stm32mp157c_dk2, r0, r1, r2) -{ - void *fdt; - - stm32mp_cpu_lowlevel_init(); - - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); - - fdt = __dtb_z_stm32mp157c_dk2_start + get_runtime_offset(); - - stm32mp1_barebox_entry(fdt); -} diff --git a/arch/arm/boards/stm32mp15xx-dkx/Makefile b/arch/arm/boards/stm32mp15xx-dkx/Makefile new file mode 100644 index 0000000000..092c31d6b2 --- /dev/null +++ b/arch/arm/boards/stm32mp15xx-dkx/Makefile @@ -0,0 +1,2 @@ +lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/stm32mp15xx-dkx/board.c b/arch/arm/boards/stm32mp15xx-dkx/board.c new file mode 100644 index 0000000000..1ddfee698d --- /dev/null +++ b/arch/arm/boards/stm32mp15xx-dkx/board.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <init.h> +#include <mach/bbu.h> + +static int dkx_probe(struct device_d *dev) +{ + const void *model; + + stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", + BBU_HANDLER_FLAG_DEFAULT); + + if (dev_get_drvdata(dev, &model) == 0) + barebox_set_model(model); + + barebox_set_hostname("stm32mp15xx-dkx"); + + return 0; +} + +static const struct of_device_id dkx_of_match[] = { + { .compatible = "st,stm32mp157a-dk1", .data = "STM32MP157A-DK1" }, + { .compatible = "st,stm32mp157c-dk2", .data = "STM32MP157C-DK2" }, + { /* sentinel */ }, +}; + +static struct driver_d dkx_board_driver = { + .name = "board-stm32mp15xx-dkx", + .probe = dkx_probe, + .of_compatible = dkx_of_match, +}; +postcore_platform_driver(dkx_board_driver); diff --git a/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c b/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c new file mode 100644 index 0000000000..65f4bbb4da --- /dev/null +++ b/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <mach/entry.h> +#include <debug_ll.h> +#include <mach/revision.h> + +extern char __dtb_z_stm32mp157c_dk2_start[]; +extern char __dtb_z_stm32mp157a_dk1_start[]; + +static void setup_uart(void) +{ + /* first stage has set up the UART, so nothing to do here */ + putc_ll('>'); +} + +ENTRY_FUNCTION(start_stm32mp15xx_dkx, r0, r1, r2) +{ + void *fdt; + u32 cputype; + int err; + + stm32mp_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + err = __stm32mp_get_cpu_type(&cputype); + if (!err && cputype == CPU_STM32MP157Axx) + fdt = __dtb_z_stm32mp157a_dk1_start; + else + fdt = __dtb_z_stm32mp157c_dk2_start; + + stm32mp1_barebox_entry(fdt + get_runtime_offset()); +} diff --git a/arch/arm/boards/technexion-pico-hobbit/board.c b/arch/arm/boards/technexion-pico-hobbit/board.c index f52f827f46..a190959d0a 100644 --- a/arch/arm/boards/technexion-pico-hobbit/board.c +++ b/arch/arm/boards/technexion-pico-hobbit/board.c @@ -1,21 +1,5 @@ -/* - * Copyright (C) 2017 Michael Grzeschik, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2017 Michael Grzeschik, Pengutronix #include <asm/armlinux.h> #include <asm/io.h> diff --git a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg index 12cda04e60..6d2d37de59 100644 --- a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg +++ b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg index 0a1915b982..201493e6a3 100644 --- a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg +++ b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/technexion-wandboard/board.c b/arch/arm/boards/technexion-wandboard/board.c index 2e1f6254c2..8d63b9fff7 100644 --- a/arch/arm/boards/technexion-wandboard/board.c +++ b/arch/arm/boards/technexion-wandboard/board.c @@ -1,13 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only #include <asm/armlinux.h> #include <asm/io.h> diff --git a/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg b/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg index 68cb08e200..5f91bed6f3 100644 --- a/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg +++ b/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg @@ -1,4 +1,4 @@ loadaddr 0x00907000 soc imx6 max_load_size 0x11000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/technexion-wandboard/lowlevel.c b/arch/arm/boards/technexion-wandboard/lowlevel.c index af04eadc9f..33babbbb2f 100644 --- a/arch/arm/boards/technexion-wandboard/lowlevel.c +++ b/arch/arm/boards/technexion-wandboard/lowlevel.c @@ -1,13 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only #include <debug_ll.h> #include <common.h> diff --git a/arch/arm/boards/telit-evk-pro3/init.c b/arch/arm/boards/telit-evk-pro3/init.c index f6ee715bb1..be0973dcd9 100644 --- a/arch/arm/boards/telit-evk-pro3/init.c +++ b/arch/arm/boards/telit-evk-pro3/init.c @@ -1,17 +1,6 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * Copyright (C) 2013 Fabio Porcedda <fabio.porcedda@gmail.com>, Telit - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix +// SPDX-FileCopyrightText: 2013 Fabio Porcedda <fabio.porcedda@gmail.com>, Telit #include <asm/armlinux.h> #include <common.h> diff --git a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c index 80cb270313..1458e76ba8 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c +++ b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c @@ -29,7 +29,7 @@ #include <mach/cyclone5-scan-manager.h> -static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, 0x00000000, 0x0FF00000, @@ -56,7 +56,7 @@ static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCAN 0x00001000, }; -static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { 0x00100000, 0x300C0000, 0x300000C0, @@ -113,7 +113,7 @@ static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000080, }; -static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { 0x300C0300, 0x00000000, 0x0FF00000, @@ -146,7 +146,7 @@ static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000800, }; -static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { 0x0C420D80, 0x082000FF, 0x0A804001, diff --git a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c index 46f6477a0f..deac0e9cb2 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c +++ b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c @@ -1,5 +1,3 @@ -#define SECT(name) __attribute__((section("terasic_de0_nano_soc_" #name))) name - #include "sdram_config.h" #include "pinmux_config.c" #include "pll_config.h" diff --git a/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c b/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c index c061901814..9c5c7f18ba 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c +++ b/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c @@ -29,7 +29,7 @@ #include <common.h> -static unsigned long SECT(sys_mgr_init_table)[] = { +static unsigned long sys_mgr_init_table[] = { 0, /* EMACIO0 */ 2, /* EMACIO1 */ 2, /* EMACIO2 */ diff --git a/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c index 1efe4f99c2..52be44f897 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c +++ b/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c @@ -27,7 +27,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ static const uint32_t ac_rom_init_size = 36; -static const uint32_t SECT(ac_rom_init)[36] = +static const uint32_t ac_rom_init[36] = { 0x20700000, 0x20780000, diff --git a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c index c2ccc46d9b..9367b0d110 100644 --- a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c +++ b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c @@ -29,7 +29,7 @@ #include <mach/cyclone5-scan-manager.h> -static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, 0x00000000, 0x0FF00000, @@ -56,7 +56,7 @@ static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCAN 0x00001000, }; -static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { 0x00100000, 0x300C0000, 0x300000C0, @@ -113,7 +113,7 @@ static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000080, }; -static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { 0x300C0300, 0x00000000, 0x0FF00000, @@ -146,7 +146,7 @@ static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000800, }; -static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { 0x0C420D80, 0x082000FF, 0x0A804001, diff --git a/arch/arm/boards/terasic-sockit/lowlevel.c b/arch/arm/boards/terasic-sockit/lowlevel.c index 585c786598..1dd7940aeb 100644 --- a/arch/arm/boards/terasic-sockit/lowlevel.c +++ b/arch/arm/boards/terasic-sockit/lowlevel.c @@ -1,5 +1,3 @@ -#define SECT(name) __attribute__((section("terasic_sockit_" #name))) name - #include "sdram_config.h" #include "pinmux_config.c" #include "pll_config.h" diff --git a/arch/arm/boards/terasic-sockit/pinmux_config.c b/arch/arm/boards/terasic-sockit/pinmux_config.c index 9a1316d0df..bcf27dbe1e 100644 --- a/arch/arm/boards/terasic-sockit/pinmux_config.c +++ b/arch/arm/boards/terasic-sockit/pinmux_config.c @@ -29,7 +29,7 @@ #include <common.h> -static unsigned long SECT(sys_mgr_init_table)[] = { +static unsigned long sys_mgr_init_table[] = { 0, /* EMACIO0 */ 2, /* EMACIO1 */ 2, /* EMACIO2 */ diff --git a/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c index 8044477e01..fe0764b0ce 100644 --- a/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c +++ b/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c @@ -28,7 +28,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ static const uint32_t ac_rom_init_size = 36; -static const uint32_t SECT(ac_rom_init)[36] = +static const uint32_t ac_rom_init[36] = { 0x20700000, 0x20780000, diff --git a/arch/arm/boards/tny-a926x/init.c b/arch/arm/boards/tny-a926x/init.c index dab373009f..0598fe74da 100644 --- a/arch/arm/boards/tny-a926x/init.c +++ b/arch/arm/boards/tny-a926x/init.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <net.h> diff --git a/arch/arm/boards/toradex-colibri-t20/Makefile b/arch/arm/boards/toradex-colibri-t20/Makefile index 644a8e5269..cdce48d1f8 100644 --- a/arch/arm/boards/toradex-colibri-t20/Makefile +++ b/arch/arm/boards/toradex-colibri-t20/Makefile @@ -1,4 +1,4 @@ -CFLAGS_pbl-entry.o := -mcpu=arm7tdmi -march=armv4t +CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t soc := tegra20 lwl-y += entry.o obj-y += board.o diff --git a/arch/arm/boards/toradex-colibri-t20/board.c b/arch/arm/boards/toradex-colibri-t20/board.c index 706198105c..0025e70614 100644 --- a/arch/arm/boards/toradex-colibri-t20/board.c +++ b/arch/arm/boards/toradex-colibri-t20/board.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lucas Stach <l.stach@pengutronix.de> #include <common.h> #include <init.h> diff --git a/arch/arm/boards/toradex-colibri-t20/entry.c b/arch/arm/boards/toradex-colibri-t20/entry.c index 9557b13f95..955052f03f 100644 --- a/arch/arm/boards/toradex-colibri-t20/entry.c +++ b/arch/arm/boards/toradex-colibri-t20/entry.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2013 Lucas Stach <l.stach@pengutronix.de> #include <common.h> #include <mach/lowlevel.h> diff --git a/arch/arm/boards/toshiba-ac100/Makefile b/arch/arm/boards/toshiba-ac100/Makefile index 4ef18c0ce9..e8158cb253 100644 --- a/arch/arm/boards/toshiba-ac100/Makefile +++ b/arch/arm/boards/toshiba-ac100/Makefile @@ -1,3 +1,3 @@ -CFLAGS_pbl-entry.o := -mcpu=arm7tdmi -march=armv4t +CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t lwl-y += entry.o obj-y += board.o diff --git a/arch/arm/boards/toshiba-ac100/board.c b/arch/arm/boards/toshiba-ac100/board.c index af69ba0b09..01aaf47034 100644 --- a/arch/arm/boards/toshiba-ac100/board.c +++ b/arch/arm/boards/toshiba-ac100/board.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com> - * - * This file is part of barebox. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2011 Antony Pavlov <antonynpavlov@gmail.com> + +/* This file is part of barebox. */ #include <common.h> #include <init.h> diff --git a/arch/arm/boards/toshiba-ac100/entry.c b/arch/arm/boards/toshiba-ac100/entry.c index 56979c9ba1..918ca4b9d8 100644 --- a/arch/arm/boards/toshiba-ac100/entry.c +++ b/arch/arm/boards/toshiba-ac100/entry.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2013 Lucas Stach <l.stach@pengutronix.de> #include <common.h> #include <mach/lowlevel.h> diff --git a/arch/arm/boards/tqma53/board.c b/arch/arm/boards/tqma53/board.c index 055ceeb03e..14e514ee78 100644 --- a/arch/arm/boards/tqma53/board.c +++ b/arch/arm/boards/tqma53/board.c @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2011 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Sascha Hauer, Pengutronix #include <environment.h> #include <bootsource.h> diff --git a/arch/arm/boards/tqma53/flash-header-tq-tqma53.h b/arch/arm/boards/tqma53/flash-header-tq-tqma53.h index 4d16b0667a..b9492bbcb3 100644 --- a/arch/arm/boards/tqma53/flash-header-tq-tqma53.h +++ b/arch/arm/boards/tqma53/flash-header-tq-tqma53.h @@ -1,6 +1,6 @@ soc imx53 loadaddr 0x70000000 -dcdofs 0x400 +ivtofs 0x400 /* IOMUX */ wm 32 0x53fa8554 0x00300000 diff --git a/arch/arm/boards/tqma53/flash-header.imxcfg b/arch/arm/boards/tqma53/flash-header.imxcfg index 3d52ff1dec..bbe2300ece 100644 --- a/arch/arm/boards/tqma53/flash-header.imxcfg +++ b/arch/arm/boards/tqma53/flash-header.imxcfg @@ -1,6 +1,6 @@ soc imx53 loadaddr 0x70000000 -dcdofs 0x400 +ivtofs 0x400 /* IOMUX */ wm 32 0x53fa8554 0x00300000 diff --git a/arch/arm/boards/tqma6x/board.c b/arch/arm/boards/tqma6x/board.c index ecf8fa06af..10faadf5a1 100644 --- a/arch/arm/boards/tqma6x/board.c +++ b/arch/arm/boards/tqma6x/board.c @@ -1,21 +1,5 @@ -/* - * Copyright (C) 2013 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer, Pengutronix #include <generated/mach-types.h> #include <environment.h> diff --git a/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg b/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg index 192ebda743..4f557d5db5 100644 --- a/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg +++ b/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg b/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg index 1fd75a24b2..deda53b464 100644 --- a/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg +++ b/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/tqma6x/lowlevel.c b/arch/arm/boards/tqma6x/lowlevel.c index afbc1691eb..845390642b 100644 --- a/arch/arm/boards/tqma6x/lowlevel.c +++ b/arch/arm/boards/tqma6x/lowlevel.c @@ -1,17 +1,6 @@ -/* - * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de> + #include <debug_ll.h> #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c index f79f491ecc..99dcf1eff7 100644 --- a/arch/arm/boards/tqmls1046a/lowlevel.c +++ b/arch/arm/boards/tqmls1046a/lowlevel.c @@ -14,152 +14,8 @@ #include <mach/xload.h> #include <mach/layerscape.h> -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ - {1, 2100, 0, 8, 9, 0x09080806, 0x07060606,}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -static void ddr_board_options(memctl_options_t *popts, - struct dimm_params *pdimm, - struct fsl_ddr_controller *c) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - unsigned long ddr_freq; - - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* - * Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = c->ddr_freq / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for %lu MT/s\n", - ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); - - popts->data_bus_width = 0; /* 64-bit data bus */ - popts->bstopre = 0; /* enable auto precharge */ - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR4_CDR_ODT_60ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR4_CDR_ODT_60ohm) | - DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x48; -} - -static struct dimm_params dimm_params[] = { - { - .n_ranks = 1, - .rank_density = 2147483648u, - .capacity = 2147483648u, - .primary_sdram_width = 64, - .ec_sdram_width = 8, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .bank_addr_bits = 2, - .bank_group_bits = 0, - .edc_config = 2, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 833, - .tckmax_ps = 1900, - .caslat_x = 0x000DFA00, // - .taa_ps = 13320, - .trcd_ps = 13320, - .trp_ps = 13320, - .tras_ps = 32000, - .trc_ps = 45320, - .trfc1_ps = 260000, - .trfc2_ps = 160000, - .trfc4_ps = 110000, - .tfaw_ps = 21000, - .trrds_ps = 3300, - .trrdl_ps = 4900, - .tccdl_ps = 5000, - .trfc_slr_ps = 3500000, - .refresh_rate_ps = 7800000, - }, -}; - static struct fsl_ddr_controller ddrc[] = { { - .dimm_slots_per_ctrl = ARRAY_SIZE(dimm_params), - .dimm_params = dimm_params, .memctl_opts.ddrtype = SDRAM_TYPE_DDR4, .base = IOMEM(LSCH2_DDR_ADDR), .ddr_freq = LS1046A_DDR_FREQ, @@ -169,7 +25,6 @@ static struct fsl_ddr_controller ddrc[] = { .erratum_A009801 = 1, .erratum_A009942 = 1, .chip_selects_per_ctrl = 4, - .board_options = ddr_board_options, .fsl_ddr_config_reg = { .cs[0].bnds = 0x0000007F, .cs[0].config = 0x80010312, diff --git a/arch/arm/boards/turris-omnia/lowlevel.c b/arch/arm/boards/turris-omnia/lowlevel.c index 7236211c40..b6520b5775 100644 --- a/arch/arm/boards/turris-omnia/lowlevel.c +++ b/arch/arm/boards/turris-omnia/lowlevel.c @@ -1,15 +1,5 @@ -/* - * Copyright (C) 2017 Pengutronix, Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2017 Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>, Pengutronix #include <common.h> #include <asm/barebox-arm.h> diff --git a/arch/arm/boards/udoo-neo/board.c b/arch/arm/boards/udoo-neo/board.c index 9bf480305d..5964e92159 100644 --- a/arch/arm/boards/udoo-neo/board.c +++ b/arch/arm/boards/udoo-neo/board.c @@ -1,15 +1,5 @@ -/* - * Copyright (C) 2014 Pengutronix, Sascha Hauer - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Sascha Hauer, Pengutronix #include <common.h> #include <init.h> diff --git a/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg b/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg index 39f2a8a221..a349b1022b 100644 --- a/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg +++ b/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg @@ -7,7 +7,7 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 /* Enable all clocks */ wm 32 0x020c4068 0xffffffff diff --git a/arch/arm/boards/udoo/board.c b/arch/arm/boards/udoo/board.c index f0befaf3a9..36dd58cc98 100644 --- a/arch/arm/boards/udoo/board.c +++ b/arch/arm/boards/udoo/board.c @@ -1,19 +1,8 @@ -/* - * Copyright (C) 2014 Raphaël Poggi - * Copyright (C) 2012 Steffen Trumtrar, Pengutronix - * - * based on arch/arm/boards/freescale-mx6-arm2/board.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Raphaël Poggi +// SPDX-FileCopyrightText: 2012 Steffen Trumtrar, Pengutronix + +/* based on arch/arm/boards/freescale-mx6-arm2/board.c */ #include <common.h> #include <init.h> diff --git a/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg b/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg index a0647a71a8..fc88a0b8b4 100644 --- a/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg +++ b/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c index 8969cbd3a8..fd99de2ffc 100644 --- a/arch/arm/boards/usb-a926x/init.c +++ b/arch/arm/boards/usb-a926x/init.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <net.h> diff --git a/arch/arm/boards/usi-topkick/lowlevel.c b/arch/arm/boards/usi-topkick/lowlevel.c index 4202138986..0193deadbe 100644 --- a/arch/arm/boards/usi-topkick/lowlevel.c +++ b/arch/arm/boards/usi-topkick/lowlevel.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2014 - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/variscite-mx6/board.c b/arch/arm/boards/variscite-mx6/board.c index 267f68c6da..99cd15b1c0 100644 --- a/arch/arm/boards/variscite-mx6/board.c +++ b/arch/arm/boards/variscite-mx6/board.c @@ -1,22 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * Copyright (C) 2013 Michael Burkey * Based on code (C) Sascha Hauer, Pengutronix * Based on code (C) Variscite, Ltd. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * */ #define pr_fmt(fmt) "var-som-mx6: " fmt diff --git a/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg b/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg index 2c82f2316f..50968d7940 100644 --- a/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg +++ b/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/variscite-mx6/lowlevel.c b/arch/arm/boards/variscite-mx6/lowlevel.c index d75d770a7e..99455b2a45 100644 --- a/arch/arm/boards/variscite-mx6/lowlevel.c +++ b/arch/arm/boards/variscite-mx6/lowlevel.c @@ -1,19 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* - * * Copyright (C) 2013 Michael Burkey * Based on code by Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ + #include <debug_ll.h> #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/versatile/versatilepb.c b/arch/arm/boards/versatile/versatilepb.c index 8691a171e1..ac6ea9951a 100644 --- a/arch/arm/boards/versatile/versatilepb.c +++ b/arch/arm/boards/versatile/versatilepb.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + /* * Copyright (C) 2010 B Labs Ltd, * http://l4dev.org @@ -5,18 +7,6 @@ * * Based on mach-nomadik * Copyright (C) 2009-2010 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * */ #include <common.h> diff --git a/arch/arm/boards/virt2real/board.c b/arch/arm/boards/virt2real/board.c index 451cbf29ff..caa2b53a68 100644 --- a/arch/arm/boards/virt2real/board.c +++ b/arch/arm/boards/virt2real/board.c @@ -1,18 +1,7 @@ -/* - * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com> - * - * This file is part of barebox. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Antony Pavlov <antonynpavlov@gmail.com> + +/* This file is part of barebox. */ #include <common.h> #include <init.h> diff --git a/arch/arm/boards/virt2real/lowlevel.c b/arch/arm/boards/virt2real/lowlevel.c index bbde5d8cd7..d14907b768 100644 --- a/arch/arm/boards/virt2real/lowlevel.c +++ b/arch/arm/boards/virt2real/lowlevel.c @@ -1,18 +1,7 @@ -/* - * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com> - * - * This file is part of barebox. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Antony Pavlov <antonynpavlov@gmail.com> + +/* This file is part of barebox. */ #define __LOWLEVEL_INIT__ diff --git a/arch/arm/boards/vscom-baltos/board.c b/arch/arm/boards/vscom-baltos/board.c index 3f9b7d76bb..59782d2990 100644 --- a/arch/arm/boards/vscom-baltos/board.c +++ b/arch/arm/boards/vscom-baltos/board.c @@ -1,20 +1,6 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Raghavendra KH <r-khandenahally@ti.com> - * - * Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2008 Raghavendra KH <r-khandenahally@ti.com>, Texas Instruments (http://www.ti.com/) +// SPDX-FileCopyrightText: 2012 Jan Luebbe <j.luebbe@pengutronix.de> /** * @file @@ -59,6 +45,43 @@ struct bsp_vs_hwparam { uint8_t MAC3[6]; } __attribute__ ((packed)); +static uint8_t get_dip_switch(uint16_t id, uint32_t rev) +{ + uint16_t maj, min; + uint8_t dip = 0; + + maj = rev >> 16; + min = rev & 0xffff; + + if ((id == 220 || id == 222) && (maj == 1 && min == 2)) + id = 214; + + switch(id) { + case 214: + case 215: + dip = !gpio_get_value(44); + dip += !gpio_get_value(45) << 1; + dip += !gpio_get_value(46) << 2; + dip += !gpio_get_value(47) << 3; + break; + case 212: + case 221: + case 223: + case 224: + case 225: + case 226: + case 227: + case 230: + dip = !gpio_get_value(82); + dip += !gpio_get_value(83) << 1; + dip += !gpio_get_value(105) << 2; + dip += !gpio_get_value(106) << 3; + break; + } + + return dip; +} + static int baltos_read_eeprom(void) { struct bsp_vs_hwparam hw_param; @@ -66,6 +89,7 @@ static int baltos_read_eeprom(void) char *buf, var_buf[32]; int rc; unsigned char mac_addr[6]; + uint8_t dip; if (!of_machine_is_compatible("vscom,onrisc")) return 0; @@ -123,6 +147,10 @@ static int baltos_read_eeprom(void) gpio_direction_output(135, 0); } + dip = get_dip_switch(hw_param.SystemId, hw_param.HwRev); + sprintf(var_buf, "%02x", dip); + globalvar_add_simple("board.dip", var_buf); + return 0; } environment_initcall(baltos_read_eeprom); diff --git a/arch/arm/boards/webasto-ccbv2/Makefile b/arch/arm/boards/webasto-ccbv2/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/webasto-ccbv2/board.c b/arch/arm/boards/webasto-ccbv2/board.c new file mode 100644 index 0000000000..a78258ea6a --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/board.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Rouven Czerwinski, Pengutronix + */ + +#include <common.h> +#include <init.h> +#include <mach/generic.h> +#include <mach/bbu.h> +#include <of.h> +#include <string.h> + +#include "ccbv2.h" + +static int ccbv2_probe(struct device_d *dev) +{ + struct device_node *overlay; + struct fdt_header *fdt; + int ret; + + /* the bootloader is stored in one of the two boot partitions */ + imx6_bbu_internal_mmcboot_register_handler("emmc", "/dev/mmc1", + BBU_HANDLER_FLAG_DEFAULT); + + barebox_set_hostname("weabsto-ccbv2"); + + if(!IS_ENABLED(CONFIG_FIRMWARE_CCBV2_OPTEE)) + return 0; + + fdt = (void*)OPTEE_OVERLAY_LOCATION; + overlay = of_unflatten_dtb(fdt); + + if (IS_ERR(overlay)) + return PTR_ERR(overlay); + + ret = of_register_overlay(overlay); + if (ret) { + printf("cannot apply oftree overlay: %s\n", strerror(-ret)); + goto err; + } + + return 0; +err: + of_delete_node(overlay); + return ret; + +} + +static const struct of_device_id ccbv2_of_match[] = { + { .compatible = "webasto,imx6ul-ccbv2" }, + { /* sentinel */ }, +}; + +static struct driver_d ccbv2_board_driver = { + .name = "board-imx6ul-ccbv2", + .probe = ccbv2_probe, + .of_compatible = ccbv2_of_match, +}; +postcore_platform_driver(ccbv2_board_driver); diff --git a/arch/arm/boards/webasto-ccbv2/ccbv2.h b/arch/arm/boards/webasto-ccbv2/ccbv2.h new file mode 100644 index 0000000000..bf43fe8410 --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/ccbv2.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ccbv2.h - common defines between OP-TEE and barebox + * + * Copyright (c) 2019 Rouven Czerwinski <r.czerwinski@pengutronix.de>, Pengutronix + * + */ +#ifndef __CCBV2_H_ +#define __CCBV2_H_ + +/* MX6UL_MMDC_PORT0_BASE_ADDR + SZ_64M */ +#define OPTEE_OVERLAY_LOCATION 0x84000000 + + +#endif // __CCBV2_H_ diff --git a/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2.imxcfg b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2.imxcfg new file mode 100644 index 0000000000..ea327b2630 --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2.imxcfg @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +loadaddr 0x80000000 +soc imx6 +ivtofs 0x400 + +/* Enable all clocks */ +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff + +/* IOMUX */ +/* DDR IO type */ +wm 32 0x020E04B4 0x000C0000 +wm 32 0x020E04AC 0x00000000 +/* Clock */ +wm 32 0x020E027C 0x00000028 +/* Control */ +wm 32 0x020E0250 0x00000028 +wm 32 0x020E024C 0x00000028 +wm 32 0x020E0490 0x00000028 +wm 32 0x020E0288 0x00000028 +wm 32 0x020E0270 0x00000000 +wm 32 0x020E0260 0x00000028 +wm 32 0x020E0264 0x00000028 +wm 32 0x020E04A0 0x00000028 +/* Data strobe */ +wm 32 0x020E0494 0x00020000 +wm 32 0x020E0280 0x00000028 +wm 32 0x020E0284 0x00000028 +/* Data */ +wm 32 0x020E04B0 0x00020000 +wm 32 0x020E0498 0x00000028 +wm 32 0x020E04A4 0x00000028 +wm 32 0x020E0244 0x00000028 +wm 32 0x020E0248 0x00000028 + +/* DDR Controller registers */ +wm 32 0x021B001C 0x00008000 +wm 32 0x021B0800 0xA1390003 +/* Calibration values */ +wm 32 0x021B080C 0x000C0000 +wm 32 0x021B083C 0x01610162 +wm 32 0x021B0848 0x40405050 +wm 32 0x021B0850 0x4040544C +wm 32 0x021B081C 0x33333333 +wm 32 0x021B0820 0x33333333 +wm 32 0x021B082C 0xf3333333 +wm 32 0x021B0830 0xf3333333 +/* END of calibration values */ +wm 32 0x021B08C0 0x00921012 +wm 32 0x021B08b8 0x00000800 + +/* MMDC init */ +wm 32 0x021B0004 0x0002002D +wm 32 0x021B0008 0x1b333030 +wm 32 0x021B000C 0x3F4352F3 +wm 32 0x021B0010 0xB66D0B63 +wm 32 0x021B0014 0x01FF00DB +/* Consider reducing RALAT (currently set to 5) */ +wm 32 0x021B0018 0x00211740 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B002C 0x000026D2 +wm 32 0x021B0030 0x00431023 +wm 32 0x021B0040 0x00000047 +wm 32 0x021B0000 0x83180000 + +/* Mode registers writes for CS0 */ +wm 32 0x021B001C 0x02008032 +wm 32 0x021B001C 0x00008033 +wm 32 0x021B001C 0x00048031 +wm 32 0x021B001C 0x15208030 +wm 32 0x021B001C 0x04008040 + +/* Final DDR setup */ +wm 32 0x021B0020 0x00007800 +wm 32 0x021B0818 0x00000227 +wm 32 0x021B0004 0x0002556D +wm 32 0x021B0404 0x00011006 +wm 32 0x021B001C 0x00000000 + +/* Disable TZASC bypass */ +wm 32 0x020E4024 0x00000001 + +#include <mach/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/webasto-ccbv2/lowlevel.c b/arch/arm/boards/webasto-ccbv2/lowlevel.c new file mode 100644 index 0000000000..8529ea3735 --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/lowlevel.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Rouven Czerwinski, Pengutronix + */ + +#include <common.h> +#include <debug_ll.h> +#include <firmware.h> +#include <mach/generic.h> +#include <asm/barebox-arm.h> +#include <mach/esdctl.h> +#include <mach/iomux-mx6ul.h> +#include <asm/cache.h> +#include <tee/optee.h> + +#include "ccbv2.h" + +extern char __dtb_z_imx6ul_webasto_ccbv2_start[]; + +static void configure_uart(void) +{ + void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; + + imx6_ungate_all_peripherals(); + + imx_setup_pad(iomuxbase, MX6_PAD_LCD_DATA16__UART7_DCE_TX); + imx_setup_pad(iomuxbase, MX6_PAD_LCD_DATA17__UART7_DCE_RX); + + imx6_uart_setup((void *)MX6_UART7_BASE_ADDR); + + putc_ll('>'); + +} + +static void noinline start_ccbv2(u32 r0) +{ + int tee_size; + void *tee; + + /* Enable normal/secure r/w for TZC380 region0 */ + writel(0xf0000000, 0x021D0108); + + configure_uart(); + + /* + * Chainloading barebox will pass a device tree within the RAM in r0, + * skip OP-TEE early loading in this case + */ + if(IS_ENABLED(CONFIG_FIRMWARE_CCBV2_OPTEE) + && !(r0 > MX6_MMDC_P0_BASE_ADDR + && r0 < MX6_MMDC_P0_BASE_ADDR + SZ_256M)) { + get_builtin_firmware(ccbv2_optee_bin, &tee, &tee_size); + + memset((void *)OPTEE_OVERLAY_LOCATION, 0, 0x1000); + + start_optee_early(NULL, tee); + } + + imx6ul_barebox_entry(__dtb_z_imx6ul_webasto_ccbv2_start); +} + +ENTRY_FUNCTION(start_imx6ul_ccbv2, r0, r1, r2) +{ + + imx6ul_cpu_lowlevel_init(); + + arm_setup_stack(0x00910000); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + start_ccbv2(r0); +} diff --git a/arch/arm/boards/zii-common/board.c b/arch/arm/boards/zii-common/board.c index 08e2f8b9bd..5d81bd51e9 100644 --- a/arch/arm/boards/zii-common/board.c +++ b/arch/arm/boards/zii-common/board.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2019 Zodiac Inflight Innovation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2019 Zodiac Inflight Innovation #include <common.h> #include <fs.h> diff --git a/arch/arm/boards/zii-common/pn-fixup.c b/arch/arm/boards/zii-common/pn-fixup.c index a665199917..80785285b7 100644 --- a/arch/arm/boards/zii-common/pn-fixup.c +++ b/arch/arm/boards/zii-common/pn-fixup.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2019 Zodiac Inflight Innovation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2019 Zodiac Inflight Innovation #include <common.h> #include <init.h> diff --git a/arch/arm/boards/zii-common/pn-fixup.h b/arch/arm/boards/zii-common/pn-fixup.h index 925e8ad634..657221dc2e 100644 --- a/arch/arm/boards/zii-common/pn-fixup.h +++ b/arch/arm/boards/zii-common/pn-fixup.h @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2019 Zodiac Inflight Innovation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2019 Zodiac Inflight Innovation #ifndef __ZII_PN_FIXUP__ #define __ZII_PN_FIXUP__ diff --git a/arch/arm/boards/zii-common/switch-cmd.c b/arch/arm/boards/zii-common/switch-cmd.c index cf5554e2e9..df6ed66b23 100644 --- a/arch/arm/boards/zii-common/switch-cmd.c +++ b/arch/arm/boards/zii-common/switch-cmd.c @@ -1,16 +1,6 @@ -/* - * Copyright (C) 2018 Zodiac Inflight Innovation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2018 Zodiac Inflight Innovation + #include <command.h> #include <common.h> #include <i2c/i2c.h> diff --git a/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg b/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg index 76f4c6b59b..5674e7a6e1 100644 --- a/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg +++ b/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg @@ -1,6 +1,6 @@ soc imx51 loadaddr 0x90000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x73fa88a0 0x00000200 wm 32 0x73fa850c 0x000020c5 diff --git a/arch/arm/boards/zii-imx6q-rdu2/board.c b/arch/arm/boards/zii-imx6q-rdu2/board.c index 0f298d6a42..b915a05dd2 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/board.c +++ b/arch/arm/boards/zii-imx6q-rdu2/board.c @@ -1,18 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2016 Zodiac Inflight Innovation -/* - * Copyright (C) 2016 Zodiac Inflight Innovation - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* Author: Andrey Smirnov <andrew.smirnov@gmail.com> */ #include <common.h> #include <envfs.h> diff --git a/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg b/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg index a4abe197e4..fcfef9c234 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg +++ b/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg @@ -1,4 +1,4 @@ soc imx6 loadaddr 0x00907000 max_load_size 0x31000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c index 87e634509f..a80ce0afc5 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c +++ b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2016 Zodiac Inflight Innovation - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2016 Zodiac Inflight Innovation + +/* Author: Andrey Smirnov <andrew.smirnov@gmail.com> */ #include <debug_ll.h> #include <common.h> diff --git a/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg b/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg index 46f3d95048..022f9711b2 100644 --- a/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg +++ b/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg @@ -1,6 +1,6 @@ soc imx7 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/flash-header/imx7d-ddr-sabresd.imxcfg> diff --git a/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg b/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg index aff8321b9a..8921f32110 100644 --- a/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg +++ b/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg @@ -2,4 +2,4 @@ soc imx8mq loadaddr 0x007E1000 max_load_size 0x3F000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c index 6400833809..311e61fb1d 100644 --- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c @@ -28,11 +28,14 @@ static void setup_uart(void) { + void __iomem *uart = IOMEM(MX8M_UART1_BASE_ADDR); + imx8m_early_setup_uart_clock(); imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); + imx8m_uart_setup(uart); - imx8m_uart_setup_ll(); + pbl_set_putc(imx_uart_putc, uart); putc_ll('>'); } @@ -118,6 +121,8 @@ static __noreturn noinline void zii_imx8mq_dev_start(void) unsigned int system_type; void *fdt; + setup_uart(); + if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR) { /* * We assume that we were just loaded by MaskROM into @@ -194,9 +199,6 @@ ENTRY_FUNCTION(start_zii_imx8mq_dev, r0, r1, r2) imx8mq_cpu_lowlevel_init(); relocate_to_current_adr(); setup_c(); - - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); zii_imx8mq_dev_start(); } diff --git a/arch/arm/boards/zii-vf610-dev/board.c b/arch/arm/boards/zii-vf610-dev/board.c index 6445025b2e..3a3ba2d58c 100644 --- a/arch/arm/boards/zii-vf610-dev/board.c +++ b/arch/arm/boards/zii-vf610-dev/board.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2016 Zodiac Inflight Innovation - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2016 Zodiac Inflight Innovation + +/* Author: Andrey Smirnov <andrew.smirnov@gmail.com> */ #include <common.h> #include <init.h> diff --git a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg index 7076a6431f..4b73da4c19 100644 --- a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg +++ b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg @@ -1,6 +1,6 @@ soc vf610 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/vf610-iomux-regs.h> #include <mach/vf610-ddrmc-regs.h> diff --git a/arch/arm/boards/zii-vf610-dev/lowlevel.c b/arch/arm/boards/zii-vf610-dev/lowlevel.c index 9b57581d1b..a05515db16 100644 --- a/arch/arm/boards/zii-vf610-dev/lowlevel.c +++ b/arch/arm/boards/zii-vf610-dev/lowlevel.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2016 Zodiac Inflight Innovation - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2016 Zodiac Inflight Innovation + +/* Author: Andrey Smirnov <andrew.smirnov@gmail.com> */ #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/zylonite/board.c b/arch/arm/boards/zylonite/board.c index e90e7dfdb8..eb69b37549 100644 --- a/arch/arm/boards/zylonite/board.c +++ b/arch/arm/boards/zylonite/board.c @@ -1,17 +1,5 @@ -/* - * (C) 2014 Robert Jarzmik <robert.jarzmik@free.fr> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Robert Jarzmik <robert.jarzmik@free.fr> #include <common.h> diff --git a/arch/arm/configs/at91_multi_defconfig b/arch/arm/configs/at91_multi_defconfig new file mode 100644 index 0000000000..e6a554e87f --- /dev/null +++ b/arch/arm/configs/at91_multi_defconfig @@ -0,0 +1,144 @@ +CONFIG_AT91_MULTI_BOARDS=y +CONFIG_MACH_AT91SAM9263EK=y +CONFIG_MACH_AT91SAM9X5EK=y +CONFIG_MACH_MICROCHIP_KSZ9477_EVB=y +CONFIG_MACH_SAMA5D27_SOM1=y +CONFIG_MACH_SAMA5D27_GIANTBOARD=y +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_RELOCATABLE=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_BOOTM_SHOW_TYPE=y +CONFIG_BOOTM_INITRD=y +CONFIG_BOOTM_OFTREE=y +CONFIG_BOOTM_OFTREE_UIMAGE=y +CONFIG_BLSPEC=y +CONFIG_CONSOLE_ACTIVATE_NONE=y +CONFIG_CONSOLE_ALLOW_COLOR=y +CONFIG_PBL_CONSOLE=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW_REBOOT_MODE=y +CONFIG_STATE=y +CONFIG_STATE_CRYPTO=y +CONFIG_BOOTCHOOSER=y +CONFIG_RESET_SOURCE=y +CONFIG_FASTBOOT_SPARSE=y +CONFIG_FASTBOOT_CMD_OEM=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_POLLER=y +CONFIG_CMD_SLICE=y +CONFIG_CMD_AT91_BOOT_TEST=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_GO=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_UBIFORMAT=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_DEFAULTENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_READF=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LED=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_USBGADGET=y +CONFIG_CMD_WD=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_OF_DIFF=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y +CONFIG_NET_NFS=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_OF_BAREBOX_ENV_IN_FS=y +CONFIG_DRIVER_NET_MACB=y +CONFIG_DRIVER_NET_MICREL=y +CONFIG_I2C=y +CONFIG_I2C_AT91=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_ECC_BCH=y +CONFIG_NAND_ECC_HW_OOB_FIRST=y +CONFIG_NAND_ATMEL=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_USB_HOST=y +CONFIG_USB_OHCI_AT91=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DFU=y +CONFIG_USB_GADGET_SERIAL=y +CONFIG_USB_GADGET_FASTBOOT=y +CONFIG_VIDEO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_DRIVER_VIDEO_ATMEL_HLCD=y +CONFIG_DRIVER_VIDEO_SIMPLE_PANEL=y +CONFIG_MCI=y +CONFIG_MCI_MMC_BOOT_PARTITIONS=y +CONFIG_MCI_MMC_GPP_PARTITIONS=y +CONFIG_MCI_ATMEL=y +CONFIG_MCI_ATMEL_SDHCI=y +CONFIG_MFD_ATMEL_FLEXCOM=y +CONFIG_STATE_DRV=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y +CONFIG_LED_GPIO_RGB=y +CONFIG_LED_GPIO_BICOLOR=y +CONFIG_LED_TRIGGERS=y +CONFIG_EEPROM_AT25=y +CONFIG_EEPROM_AT24=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_QT1070=y +CONFIG_KEYBOARD_USB=y +CONFIG_INPUT_SPECIALKEYS=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_AT91SAM9=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED=y +CONFIG_GENERIC_PHY=y +CONFIG_USB_NOP_XCEIV=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_LFN=y +CONFIG_FS_UBIFS=y +CONFIG_FS_UBIFS_COMPRESSION_LZO=y diff --git a/arch/arm/configs/at91sam9263ek_defconfig b/arch/arm/configs/at91sam9263ek_defconfig deleted file mode 100644 index 45c6f79de4..0000000000 --- a/arch/arm/configs/at91sam9263ek_defconfig +++ /dev/null @@ -1,89 +0,0 @@ -CONFIG_ARCH_AT91SAM9263=y -CONFIG_AT91_MULTI_BOARDS=y -CONFIG_MACH_AT91SAM9263EK=y -CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_MMU=y -CONFIG_EXPERIMENTAL=y -CONFIG_MALLOC_TLSF=y -CONFIG_RELOCATABLE=y -CONFIG_PROMPT="9263-EK:" -CONFIG_GLOB=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_BOOTM_SHOW_TYPE=y -CONFIG_BOOTM_INITRD=y -CONFIG_BOOTM_OFTREE=y -CONFIG_BOOTM_OFTREE_UIMAGE=y -CONFIG_CONSOLE_ACTIVATE_ALL=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -CONFIG_CMD_DMESG=y -CONFIG_LONGHELP=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_GO=y -CONFIG_CMD_LOADB=y -CONFIG_CMD_RESET=y -CONFIG_CMD_UIMAGE=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_HOST=y -CONFIG_NET_CMD_IFUP=y -CONFIG_CMD_MIITOOL=y -CONFIG_CMD_PING=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SPLASH=y -CONFIG_CMD_FBTEST=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DETECT=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_LED=y -CONFIG_CMD_LED_TRIGGER=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OF_DISPLAY_TIMINGS=y -CONFIG_CMD_OF_FIXUP_STATUS=y -CONFIG_CMD_OFTREE=y -CONFIG_NET=y -CONFIG_NET_NFS=y -CONFIG_OF_BAREBOX_DRIVERS=y -CONFIG_DRIVER_NET_MACB=y -CONFIG_DAVICOM_PHY=y -# CONFIG_SPI is not set -CONFIG_MTD=y -# CONFIG_MTD_OOB_DEVICE is not set -CONFIG_DRIVER_CFI=y -# CONFIG_DRIVER_CFI_INTEL is not set -# CONFIG_DRIVER_CFI_BANK_WIDTH_4 is not set -CONFIG_NAND=y -# CONFIG_NAND_ECC_HW is not set -# CONFIG_NAND_ECC_HW_SYNDROME is not set -# CONFIG_NAND_ECC_HW_NONE is not set -CONFIG_NAND_ATMEL=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DFU=y -CONFIG_USB_GADGET_SERIAL=y -CONFIG_VIDEO=y -CONFIG_DRIVER_VIDEO_ATMEL=y -CONFIG_MCI=y -CONFIG_MCI_ATMEL=y -CONFIG_SRAM=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_LED_GPIO_OF=y -CONFIG_LED_TRIGGERS=y -CONFIG_KEYBOARD_GPIO=y -CONFIG_FS_TFTP=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_LFN=y -CONFIG_PNG=y diff --git a/arch/arm/configs/at91sam9x5ek_defconfig b/arch/arm/configs/at91sam9x5ek_defconfig deleted file mode 100644 index 11d1e4511e..0000000000 --- a/arch/arm/configs/at91sam9x5ek_defconfig +++ /dev/null @@ -1,92 +0,0 @@ -CONFIG_ARCH_AT91SAM9X5=y -CONFIG_AT91_MULTI_BOARDS=y -CONFIG_MACH_AT91SAM9X5EK=y -CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 -CONFIG_AEABI=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_MMU=y -CONFIG_MALLOC_SIZE=0xa00000 -CONFIG_EXPERIMENTAL=y -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_RELOCATABLE=y -CONFIG_PROMPT="9G20-EK:" -CONFIG_GLOB=y -CONFIG_PROMPT_HUSH_PS2="y" -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_BOOTM_SHOW_TYPE=y -CONFIG_BOOTM_INITRD=y -CONFIG_BOOTM_OFTREE=y -CONFIG_BOOTM_OFTREE_UIMAGE=y -CONFIG_CONSOLE_ACTIVATE_ALL=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -# CONFIG_CMD_ARM_CPUINFO is not set -CONFIG_LONGHELP=y -CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_GO=y -CONFIG_CMD_LOADB=y -CONFIG_CMD_RESET=y -CONFIG_CMD_UIMAGE=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_LED=y -CONFIG_CMD_LED_TRIGGER=y -CONFIG_CMD_OFTREE=y -CONFIG_NET=y -CONFIG_NET_NFS=y -CONFIG_NET_NETCONSOLE=y -CONFIG_OF_BAREBOX_DRIVERS=y -CONFIG_DRIVER_NET_MACB=y -CONFIG_NET_USB=y -CONFIG_NET_USB_ASIX=y -CONFIG_DRIVER_SPI_ATMEL=y -CONFIG_I2C=y -CONFIG_I2C_GPIO=y -CONFIG_MTD=y -# CONFIG_MTD_OOB_DEVICE is not set -CONFIG_MTD_DATAFLASH=y -CONFIG_MTD_M25P80=y -CONFIG_NAND=y -# CONFIG_NAND_ECC_SOFT is not set -# CONFIG_NAND_ECC_HW_SYNDROME is not set -# CONFIG_NAND_ECC_HW_NONE is not set -CONFIG_NAND_ATMEL=y -CONFIG_NAND_ATMEL_PMECC=y -CONFIG_USB_HOST=y -CONFIG_USB_EHCI=y -CONFIG_USB_EHCI_ATMEL=y -CONFIG_USB_STORAGE=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -CONFIG_MCI_ATMEL=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_LED_GPIO_OF=y -CONFIG_LED_TRIGGERS=y -CONFIG_EEPROM_AT24=y -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_QT1070=y -CONFIG_W1=y -CONFIG_W1_MASTER_GPIO=y -CONFIG_W1_SLAVE_DS2431=y -CONFIG_W1_SLAVE_DS2433=y -CONFIG_FS_TFTP=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/eukrea_cpuimx35_defconfig b/arch/arm/configs/eukrea_cpuimx35_defconfig index bd19fc45aa..b3d5741c69 100644 --- a/arch/arm/configs/eukrea_cpuimx35_defconfig +++ b/arch/arm/configs/eukrea_cpuimx35_defconfig @@ -74,7 +74,6 @@ CONFIG_MTD_RAW_DEVICE=y CONFIG_NAND=y CONFIG_NAND_ALLOW_ERASE_BAD=y CONFIG_NAND_IMX=y -CONFIG_NAND_IMX_BBM=y CONFIG_USB_HOST=y CONFIG_USB_IMX_CHIPIDEA=y CONFIG_USB_EHCI=y diff --git a/arch/arm/configs/freescale-mx21-ads_defconfig b/arch/arm/configs/freescale-mx21-ads_defconfig index 7dc8cb1426..b1d37f76a8 100644 --- a/arch/arm/configs/freescale-mx21-ads_defconfig +++ b/arch/arm/configs/freescale-mx21-ads_defconfig @@ -1,6 +1,5 @@ CONFIG_TEXT_BASE=0xc3000000 CONFIG_ARCH_IMX=y -CONFIG_MACH_IMX21ADS=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_MALLOC_SIZE=0x2000000 CONFIG_CMDLINE_EDITING=y @@ -36,5 +35,4 @@ CONFIG_DRIVER_CFI=y CONFIG_CFI_BUFFER_WRITE=y CONFIG_NAND=y CONFIG_NAND_IMX=y -CONFIG_NAND_IMX_BBM=y CONFIG_FS_TFTP=y diff --git a/arch/arm/configs/imx23_defconfig b/arch/arm/configs/imx23_defconfig index bff9c08c40..48bf14a390 100644 --- a/arch/arm/configs/imx23_defconfig +++ b/arch/arm/configs/imx23_defconfig @@ -22,6 +22,7 @@ CONFIG_BLSPEC=y CONFIG_CONSOLE_ALLOW_COLOR=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_RESET_SOURCE=y +CONFIG_FASTBOOT_CMD_OEM=y CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y @@ -90,7 +91,6 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DFU=y CONFIG_USB_GADGET_SERIAL=y CONFIG_USB_GADGET_FASTBOOT=y -CONFIG_USB_GADGET_FASTBOOT_CMD_OEM=y CONFIG_VIDEO=y CONFIG_DRIVER_VIDEO_STM=y CONFIG_MCI=y diff --git a/arch/arm/configs/imx28_defconfig b/arch/arm/configs/imx28_defconfig index 4442c79cc4..beb0bc2f76 100644 --- a/arch/arm/configs/imx28_defconfig +++ b/arch/arm/configs/imx28_defconfig @@ -25,6 +25,7 @@ CONFIG_CONSOLE_ALLOW_COLOR=y CONFIG_PBL_CONSOLE=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_RESET_SOURCE=y +CONFIG_FASTBOOT_CMD_OEM=y CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y @@ -105,7 +106,6 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DFU=y CONFIG_USB_GADGET_SERIAL=y CONFIG_USB_GADGET_FASTBOOT=y -CONFIG_USB_GADGET_FASTBOOT_CMD_OEM=y CONFIG_VIDEO=y CONFIG_DRIVER_VIDEO_STM=y CONFIG_MCI=y diff --git a/arch/arm/configs/imx_defconfig b/arch/arm/configs/imx_defconfig index ede70d7eaf..e6333220b6 100644 --- a/arch/arm/configs/imx_defconfig +++ b/arch/arm/configs/imx_defconfig @@ -13,7 +13,6 @@ CONFIG_MMU=y CONFIG_MALLOC_SIZE=0x0 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y -CONFIG_RELOCATABLE=y CONFIG_PANIC_HANG=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y @@ -90,7 +89,6 @@ CONFIG_NAND=y # CONFIG_NAND_ECC_HW_SYNDROME is not set CONFIG_NAND_ALLOW_ERASE_BAD=y CONFIG_NAND_IMX=y -CONFIG_NAND_IMX_BBM=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_USB_HOST=y diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 5bf908ee85..16e109464b 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -12,6 +12,7 @@ CONFIG_MACH_TQMA53=y CONFIG_MACH_FREESCALE_MX53_VMX53=y CONFIG_MACH_TX53=y CONFIG_MACH_PHYTEC_SOM_IMX6=y +CONFIG_MACH_PROTONIC_IMX6=y CONFIG_MACH_KONTRON_SAMX6I=y CONFIG_MACH_DFI_FS700_M60=y CONFIG_MACH_GUF_SANTARO=y @@ -30,19 +31,23 @@ CONFIG_MACH_TECHNEXION_WANDBOARD=y CONFIG_MACH_EMBEST_MARSBOARD=y CONFIG_MACH_EMBEST_RIOTBOARD=y CONFIG_MACH_UDOO=y +CONFIG_MACH_UDOO_NEO=y CONFIG_MACH_VARISCITE_MX6=y CONFIG_MACH_GW_VENTANA=y CONFIG_MACH_CM_FX6=y CONFIG_MACH_ADVANTECH_ROM_742X=y CONFIG_MACH_WARP7=y +CONFIG_MACH_WEBASTO_CCBV2=y CONFIG_MACH_VF610_TWR=y CONFIG_MACH_ZII_RDU1=y CONFIG_MACH_ZII_RDU2=y CONFIG_MACH_ZII_VF610_DEV=y +CONFIG_MACH_ZII_IMX7D_DEV=y CONFIG_MACH_PHYTEC_PHYCORE_IMX7=y CONFIG_MACH_FREESCALE_MX7_SABRESD=y CONFIG_MACH_NXP_IMX6ULL_EVK=y CONFIG_MACH_GRINN_LITEBOARD=y +CONFIG_MACH_DIGI_CCIMX6ULSBCPRO=y CONFIG_IMX_IIM_FUSE_BLOW=y CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y @@ -65,7 +70,10 @@ CONFIG_BLSPEC=y CONFIG_CONSOLE_ACTIVATE_NONE=y CONFIG_PARTITION_DISK_EFI=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_STATE=y +CONFIG_BOOTCHOOSER=y CONFIG_RESET_SOURCE=y +CONFIG_FASTBOOT_CMD_OEM=y CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y @@ -126,6 +134,8 @@ CONFIG_CMD_OF_NODE=y CONFIG_CMD_OF_PROPERTY=y CONFIG_CMD_OFTREE=y CONFIG_CMD_TIME=y +CONFIG_CMD_STATE=y +CONFIG_CMD_BOOTCHOOSER=y CONFIG_NET=y CONFIG_NET_NETCONSOLE=y CONFIG_OF_BAREBOX_DRIVERS=y @@ -143,7 +153,6 @@ CONFIG_MTD_SST25L=y CONFIG_NAND=y CONFIG_NAND_ALLOW_ERASE_BAD=y CONFIG_NAND_IMX=y -CONFIG_NAND_IMX_BBM=y CONFIG_NAND_MXS=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_FASTMAP=y @@ -160,7 +169,6 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DFU=y CONFIG_USB_GADGET_SERIAL=y CONFIG_USB_GADGET_FASTBOOT=y -CONFIG_USB_GADGET_FASTBOOT_CMD_OEM=y CONFIG_VIDEO=y CONFIG_DRIVER_VIDEO_IMX_IPUV3=y CONFIG_DRIVER_VIDEO_IMX_IPUV3_LVDS=y @@ -174,6 +182,7 @@ CONFIG_MFD_DA9063=y CONFIG_MFD_MC34704=y CONFIG_MFD_MC9SDZ60=y CONFIG_MFD_STMPE=y +CONFIG_STATE_DRV=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_LED_GPIO_OF=y diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig index 06fb406084..06d79f594d 100644 --- a/arch/arm/configs/imx_v8_defconfig +++ b/arch/arm/configs/imx_v8_defconfig @@ -2,6 +2,7 @@ CONFIG_ARCH_IMX=y CONFIG_IMX_MULTI_BOARDS=y CONFIG_MACH_ZII_IMX8MQ_DEV=y CONFIG_MACH_NXP_IMX8MM_EVK=y +CONFIG_MACH_NXP_IMX8MP_EVK=y CONFIG_MACH_NXP_IMX8MQ_EVK=y CONFIG_MACH_PHYTEC_SOM_IMX8MQ=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y @@ -9,7 +10,6 @@ CONFIG_MMU=y CONFIG_MALLOC_SIZE=0x0 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y -CONFIG_RELOCATABLE=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y @@ -25,6 +25,7 @@ CONFIG_CONSOLE_RATP=y CONFIG_PARTITION_DISK_EFI=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_RESET_SOURCE=y +CONFIG_FASTBOOT_SPARSE=y CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y @@ -87,6 +88,7 @@ CONFIG_SERIAL_DEV_BUS=y CONFIG_DRIVER_NET_FEC_IMX=y CONFIG_DP83867_PHY=y CONFIG_MICREL_PHY=y +CONFIG_REALTEK_PHY=y CONFIG_NET_DSA_MV88E6XXX=y CONFIG_MDIO_BITBANG=y CONFIG_MDIO_GPIO=y @@ -106,7 +108,6 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_SERIAL=y CONFIG_USB_GADGET_FASTBOOT=y -CONFIG_USB_GADGET_FASTBOOT_SPARSE=y CONFIG_MCI=y CONFIG_MCI_MMC_BOOT_PARTITIONS=y CONFIG_MCI_IMX_ESDHC=y @@ -128,7 +129,6 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_GENERIC_PHY=y CONFIG_USB_NOP_XCEIV=y -CONFIG_PHY_FSL_IMX8MQ_USB=y CONFIG_FS_EXT4=y CONFIG_FS_TFTP=y CONFIG_FS_NFS=y diff --git a/arch/arm/configs/kindle-mx50_defconfig b/arch/arm/configs/kindle-mx50_defconfig index 855daef71a..95fafd56e6 100644 --- a/arch/arm/configs/kindle-mx50_defconfig +++ b/arch/arm/configs/kindle-mx50_defconfig @@ -9,7 +9,6 @@ CONFIG_MMU=y CONFIG_MALLOC_SIZE=0x0 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y -CONFIG_RELOCATABLE=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y @@ -20,6 +19,7 @@ CONFIG_BOOTM_OFTREE=y CONFIG_CONSOLE_ACTIVATE_ALL=y CONFIG_CONSOLE_ALLOW_COLOR=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_FASTBOOT_CMD_OEM=y CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y CONFIG_CMD_MEMINFO=y @@ -50,7 +50,6 @@ CONFIG_USB_EHCI=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_SERIAL=y CONFIG_USB_GADGET_FASTBOOT=y -CONFIG_USB_GADGET_FASTBOOT_CMD_OEM=y CONFIG_MCI=y CONFIG_MCI_STARTUP=y CONFIG_MCI_MMC_BOOT_PARTITIONS=y diff --git a/arch/arm/configs/layerscape_defconfig b/arch/arm/configs/layerscape_defconfig index b36f1944ec..394cd95c98 100644 --- a/arch/arm/configs/layerscape_defconfig +++ b/arch/arm/configs/layerscape_defconfig @@ -78,7 +78,6 @@ CONFIG_CMD_OFTREE=y CONFIG_CMD_TIME=y CONFIG_NET=y CONFIG_NET_NETCONSOLE=y -CONFIG_OFDEVICE=y CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_DRIVER_NET_FSL_FMAN=y @@ -105,7 +104,6 @@ CONFIG_EEPROM_AT24=y CONFIG_WATCHDOG=y CONFIG_WATCHDOG_IMX=y CONFIG_GPIO_PCA953X=y -CONFIG_NVMEM=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED=y CONFIG_FS_EXT4=y diff --git a/arch/arm/configs/microchip_ksz9477_evb_defconfig b/arch/arm/configs/microchip_ksz9477_evb_defconfig deleted file mode 100644 index 4189b2c039..0000000000 --- a/arch/arm/configs/microchip_ksz9477_evb_defconfig +++ /dev/null @@ -1,73 +0,0 @@ -CONFIG_ARCH_SAMA5D3=y -CONFIG_AT91_MULTI_BOARDS=y -CONFIG_MACH_MICROCHIP_KSZ9477_EVB=y -CONFIG_AEABI=y -CONFIG_MMU=y -CONFIG_MALLOC_SIZE=0x0 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_RELOCATABLE=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_BOOTM_SHOW_TYPE=y -CONFIG_BOOTM_OFTREE=y -CONFIG_BOOTM_OFTREE_UIMAGE=y -CONFIG_CONSOLE_ALLOW_COLOR=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_CMD_DMESG=y -CONFIG_LONGHELP=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_AT91_BOOT_TEST=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_GO=y -CONFIG_CMD_RESET=y -CONFIG_CMD_UIMAGE=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_DEFAULTENV=y -CONFIG_CMD_LOADENV=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_FILETYPE=y -CONFIG_CMD_LN=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_LET=y -CONFIG_CMD_MSLEEP=y -CONFIG_CMD_READF=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_CRC=y -CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_MM=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DETECT=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_BAREBOX_UPDATE=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_TIME=y -CONFIG_NET=y -CONFIG_NET_NFS=y -CONFIG_OF_BAREBOX_DRIVERS=y -CONFIG_OF_BAREBOX_ENV_IN_FS=y -CONFIG_DRIVER_NET_MACB=y -CONFIG_DRIVER_NET_MICREL=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -CONFIG_MCI_MMC_BOOT_PARTITIONS=y -CONFIG_MCI_ATMEL=y -CONFIG_FS_TFTP=y -CONFIG_FS_NFS=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/omap_defconfig b/arch/arm/configs/omap_defconfig index 9d71d02744..59892cb231 100644 --- a/arch/arm/configs/omap_defconfig +++ b/arch/arm/configs/omap_defconfig @@ -34,6 +34,7 @@ CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_STATE=y CONFIG_BOOTCHOOSER=y CONFIG_RESET_SOURCE=y +CONFIG_FASTBOOT_CMD_OEM=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y CONFIG_CMD_MEMINFO=y @@ -121,7 +122,6 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DFU=y CONFIG_USB_GADGET_SERIAL=y CONFIG_USB_GADGET_FASTBOOT=y -CONFIG_USB_GADGET_FASTBOOT_CMD_OEM=y CONFIG_USB_MUSB=y CONFIG_USB_MUSB_AM335X=y CONFIG_USB_MUSB_HOST=y diff --git a/arch/arm/configs/socfpga-arria10_defconfig b/arch/arm/configs/socfpga-arria10_defconfig index e47a0ab183..a37bae6217 100644 --- a/arch/arm/configs/socfpga-arria10_defconfig +++ b/arch/arm/configs/socfpga-arria10_defconfig @@ -18,7 +18,6 @@ CONFIG_BOOTM_INITRD=y CONFIG_BOOTM_OFTREE=y CONFIG_DEFAULT_COMPRESSION_LZO=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_POLLER=y CONFIG_STATE=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y diff --git a/arch/arm/configs/stm32mp_defconfig b/arch/arm/configs/stm32mp_defconfig index 4b902e1741..e9f89e69d9 100644 --- a/arch/arm/configs/stm32mp_defconfig +++ b/arch/arm/configs/stm32mp_defconfig @@ -1,6 +1,7 @@ CONFIG_ARCH_STM32MP=y -CONFIG_MACH_STM32MP157C_DK2=y +CONFIG_MACH_STM32MP15XX_DKX=y CONFIG_MACH_LXA_MC1=y +CONFIG_MACH_SEEED_ODYSSEY=y CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_BOARD_APPEND_ATAG=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y @@ -11,7 +12,6 @@ CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y CONFIG_RELOCATABLE=y CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y CONFIG_BOOTM_SHOW_TYPE=y @@ -23,10 +23,14 @@ CONFIG_BLSPEC=y CONFIG_CONSOLE_ACTIVATE_NONE=y CONFIG_CONSOLE_ALLOW_COLOR=y CONFIG_PBL_CONSOLE=y +CONFIG_CONSOLE_RATP=y +CONFIG_RATP_CMD_I2C=y +CONFIG_RATP_CMD_GPIO=y CONFIG_PARTITION_DISK_EFI=y # CONFIG_PARTITION_DISK_EFI_GPT_NO_FORCE is not set # CONFIG_PARTITION_DISK_EFI_GPT_COMPARE is not set CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW_REBOOT_MODE=y CONFIG_RESET_SOURCE=y CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y @@ -36,6 +40,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_ARM_MMUINFO=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_MMC=y +CONFIG_CMD_MMC_EXTCSD=y # CONFIG_CMD_BOOTU is not set CONFIG_CMD_GO=y CONFIG_CMD_RESET=y @@ -81,10 +86,12 @@ CONFIG_CMD_BAREBOX_UPDATE=y CONFIG_CMD_OF_DIFF=y CONFIG_CMD_OF_NODE=y CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OF_OVERLAY=y CONFIG_CMD_OFTREE=y CONFIG_CMD_TIME=y CONFIG_NET=y CONFIG_NET_NETCONSOLE=y +CONFIG_NET_FASTBOOT=y CONFIG_OFDEVICE=y CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_DRIVER_SERIAL_STM32=y @@ -109,6 +116,7 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_LED_PWM=y CONFIG_LED_GPIO_OF=y +CONFIG_LED_TRIGGERS=y CONFIG_EEPROM_AT24=y CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_SPECIALKEYS=y @@ -130,11 +138,17 @@ CONFIG_STM32_REMOTEPROC=y CONFIG_RESET_STM32=y CONFIG_GENERIC_PHY=y CONFIG_PHY_STM32_USBPHYC=y +CONFIG_SYSCON_REBOOT_MODE=y CONFIG_FS_EXT4=y CONFIG_FS_TFTP=y CONFIG_FS_NFS=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y +CONFIG_FS_PSTORE=y +CONFIG_FS_PSTORE_CONSOLE=y +CONFIG_FS_PSTORE_RAMOOPS=y +CONFIG_FS_SQUASHFS=y +CONFIG_FS_RATP=y CONFIG_ZLIB=y CONFIG_CRC8=y diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig index 149ba17321..caa9f512d6 100644 --- a/arch/arm/configs/vexpress_defconfig +++ b/arch/arm/configs/vexpress_defconfig @@ -3,6 +3,7 @@ CONFIG_AEABI=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_MALLOC_SIZE=0x0 CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y CONFIG_PROMPT="vexpress: " CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y diff --git a/arch/arm/configs/virt2real_defconfig b/arch/arm/configs/virt2real_defconfig index 814fe69e42..62315b8cb3 100644 --- a/arch/arm/configs/virt2real_defconfig +++ b/arch/arm/configs/virt2real_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_LED=y CONFIG_CMD_OF_NODE=y CONFIG_CMD_OF_PROPERTY=y CONFIG_CMD_OFTREE=y -CONFIG_OFDEVICE=y CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_DRIVER_SERIAL_NS16550=y # CONFIG_SPI is not set diff --git a/arch/arm/configs/zii_vf610_dev_defconfig b/arch/arm/configs/zii_vf610_dev_defconfig index 7161d740ac..3ed5d37458 100644 --- a/arch/arm/configs/zii_vf610_dev_defconfig +++ b/arch/arm/configs/zii_vf610_dev_defconfig @@ -8,7 +8,6 @@ CONFIG_MMU=y CONFIG_MALLOC_SIZE=0x0 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y -CONFIG_RELOCATABLE=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y @@ -22,6 +21,7 @@ CONFIG_CONSOLE_RATP=y CONFIG_PARTITION_DISK_EFI=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_RESET_SOURCE=y +CONFIG_FASTBOOT_CMD_OEM=y CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y @@ -113,7 +113,6 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DFU=y CONFIG_USB_GADGET_SERIAL=y CONFIG_USB_GADGET_FASTBOOT=y -CONFIG_USB_GADGET_FASTBOOT_CMD_OEM=y CONFIG_MCI=y CONFIG_MCI_MMC_BOOT_PARTITIONS=y CONFIG_MCI_IMX_ESDHC=y diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig index 6b4fed5269..f9f52a6252 100644 --- a/arch/arm/cpu/Kconfig +++ b/arch/arm/cpu/Kconfig @@ -6,6 +6,7 @@ config PHYS_ADDR_T_64BIT config CPU_32 bool select HAS_MODULES + select HAVE_MOD_ARCH_SPECIFIC select HAS_DMA select HAVE_PBL_IMAGE diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index 63cf35c299..e7a6e3e6fb 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -6,9 +6,10 @@ obj-pbl-y += lowlevel$(S64).o obj-pbl-$(CONFIG_MMU) += mmu-early$(S64).o obj-pbl-$(CONFIG_CPU_32v7) += hyp.o AFLAGS_hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all -AFLAGS_pbl-hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all +AFLAGS_hyp.pbl.o :=-Wa,-march=armv7-a -Wa,-mcpu=all obj-y += start.o entry.o entry_ll$(S64).o +KASAN_SANITIZE_start.o := n pbl-$(CONFIG_BOARD_ARM_GENERIC_DT) += board-dt-2nd.o pbl-$(CONFIG_BOARD_ARM_GENERIC_DT_AARCH64) += board-dt-2nd-aarch64.o @@ -32,22 +33,23 @@ obj-$(CONFIG_ARM_PSCI) += psci.o obj-$(CONFIG_ARM_PSCI_OF) += psci-of.o obj-pbl-$(CONFIG_ARM_SMCCC) += smccc-call$(S64).o AFLAGS_smccc-call$(S64).o :=-Wa,-march=armv$(if $(S64),8,7)-a -AFLAGS_pbl-smccc-call$(S64).o :=-Wa,-march=armv$(if $(S64),8,7)-a +AFLAGS_smccc-call$(S64).pbl.o :=-Wa,-march=armv$(if $(S64),8,7)-a obj-$(CONFIG_ARM_SECURE_MONITOR) += sm.o sm_as.o AFLAGS_sm_as.o :=-Wa,-march=armv7-a obj-pbl-$(CONFIG_CPU_32v4T) += cache-armv4.o obj-pbl-$(CONFIG_CPU_32v5) += cache-armv5.o obj-pbl-$(CONFIG_CPU_32v6) += cache-armv6.o -AFLAGS_cache-armv7.o :=-Wa,-march=armv7-a obj-pbl-$(CONFIG_CPU_32v7) += cache-armv7.o -AFLAGS_pbl-cache-armv7.o :=-Wa,-march=armv7-a +AFLAGS_cache-armv7.o :=-Wa,-march=armv7-a +AFLAGS_cache-armv7.pbl.o :=-Wa,-march=armv7-a obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o -AFLAGS_cache-armv8.o :=-Wa,-march=armv8-a obj-pbl-$(CONFIG_CPU_64v8) += cache-armv8.o -AFLAGS_pbl-cache-armv8.o :=-Wa,-march=armv8-a +AFLAGS_cache-armv8.o :=-Wa,-march=armv8-a +AFLAGS-cache-armv8.pbl.o :=-Wa,-march=armv8-a pbl-y += entry.o entry_ll$(S64).o pbl-y += uncompress.o obj-pbl-y += common.o sections.o +KASAN_SANITIZE_common.o := n diff --git a/arch/arm/cpu/cache_64.c b/arch/arm/cpu/cache_64.c index 6e18d981a4..cb7bc0945c 100644 --- a/arch/arm/cpu/cache_64.c +++ b/arch/arm/cpu/cache_64.c @@ -1,13 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only #include <common.h> #include <init.h> diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c index bc5d9b5882..8cfcc8f6ce 100644 --- a/arch/arm/cpu/common.c +++ b/arch/arm/cpu/common.c @@ -1,16 +1,5 @@ -/* - * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2010 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix #include <common.h> #include <init.h> @@ -131,7 +120,7 @@ void relocate_to_current_adr(void) dstart += sizeof(*rel); } - memset(dynsym, 0, (unsigned long)dynend - (unsigned long)dynsym); + __memset(dynsym, 0, (unsigned long)dynend - (unsigned long)dynsym); #else #error "Architecture not specified" #endif diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c index 0db852b33d..5b79dd2a8f 100644 --- a/arch/arm/cpu/cpu.c +++ b/arch/arm/cpu/cpu.c @@ -1,17 +1,5 @@ -/* - * cpu.c - A few helper functions for ARM - * - * Copyright (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix /** * @file diff --git a/arch/arm/cpu/cpuinfo.c b/arch/arm/cpu/cpuinfo.c index dd67b51ac2..a08fc253ef 100644 --- a/arch/arm/cpu/cpuinfo.c +++ b/arch/arm/cpu/cpuinfo.c @@ -1,17 +1,7 @@ -/* - * cpuinfo.c - Show information about cp15 registers - * - * Copyright (c) 2009 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2009 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + +/* cpuinfo.c - Show information about cp15 registers */ #include <common.h> #include <command.h> diff --git a/arch/arm/cpu/dtb.c b/arch/arm/cpu/dtb.c index 1d126a827d..35f251d99a 100644 --- a/arch/arm/cpu/dtb.c +++ b/arch/arm/cpu/dtb.c @@ -1,16 +1,6 @@ -/* - * Copyright (c) 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + #include <common.h> #include <init.h> #include <of.h> @@ -36,13 +26,7 @@ static int of_arm_init(void) return 0; } - root = of_unflatten_dtb(fdt); - if (!IS_ERR(root)) { - of_set_root_node(root); - of_fix_tree(root); - if (IS_ENABLED(CONFIG_OFDEVICE)) - of_probe(); - } + barebox_register_fdt(fdt); return 0; } diff --git a/arch/arm/cpu/interrupts.c b/arch/arm/cpu/interrupts.c index 703a5a3ba7..a1728eb353 100644 --- a/arch/arm/cpu/interrupts.c +++ b/arch/arm/cpu/interrupts.c @@ -1,18 +1,5 @@ -/* - * interrupts.c - Interrupt Support Routines - * - * Copyright (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix /** * @file diff --git a/arch/arm/cpu/interrupts_64.c b/arch/arm/cpu/interrupts_64.c index f462835ffd..f54fdcd3dd 100644 --- a/arch/arm/cpu/interrupts_64.c +++ b/arch/arm/cpu/interrupts_64.c @@ -1,18 +1,7 @@ -/* - * interrupts_64.c - Interrupt Support Routines - * - * Copyright (c) 2018 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2018 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + +/* interrupts_64.c - Interrupt Support Routines */ #include <common.h> #include <abort.h> diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c index 2aa53229b3..6af228505d 100644 --- a/arch/arm/cpu/mmu.c +++ b/arch/arm/cpu/mmu.c @@ -1,16 +1,5 @@ -/* - * Copyright (c) 2009-2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2009-2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix #define pr_fmt(fmt) "mmu: " fmt diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c index 8324cedb25..7e9ae84810 100644 --- a/arch/arm/cpu/mmu_64.c +++ b/arch/arm/cpu/mmu_64.c @@ -1,17 +1,6 @@ -/* - * Copyright (c) 2009-2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * Copyright (c) 2016 Raphaël Poggi <poggi.raph@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2009-2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2016 Raphaël Poggi <poggi.raph@gmail.com> #define pr_fmt(fmt) "mmu: " fmt diff --git a/arch/arm/cpu/mmuinfo.c b/arch/arm/cpu/mmuinfo.c index 1db6eb3869..1147c0a305 100644 --- a/arch/arm/cpu/mmuinfo.c +++ b/arch/arm/cpu/mmuinfo.c @@ -1,17 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2012 Jan Luebbe <j.luebbe@pengutronix.de>, Pengutronix /* * mmuinfo.c - Show MMU/cache information from cp15 registers - * - * Copyright (c) Jan Luebbe <j.luebbe@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> diff --git a/arch/arm/cpu/no-mmu.c b/arch/arm/cpu/no-mmu.c index 7268fa9b9d..be3cfaf12b 100644 --- a/arch/arm/cpu/no-mmu.c +++ b/arch/arm/cpu/no-mmu.c @@ -1,17 +1,7 @@ -/* - * Copyright (c) 2015 Zodiac Inflight Innovation - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2015 Zodiac Inflight Innovation + +/* Author: Andrey Smirnov <andrew.smirnov@gmail.com> */ #define pr_fmt(fmt) "nommu: " fmt diff --git a/arch/arm/cpu/psci.c b/arch/arm/cpu/psci.c index 5a69aaa810..d1056e0659 100644 --- a/arch/arm/cpu/psci.c +++ b/arch/arm/cpu/psci.c @@ -1,13 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only #define pr_fmt(fmt) "psci: " fmt @@ -98,7 +89,7 @@ static unsigned long psci_cpu_suspend(u32 power_state, unsigned long entry, { psci_printf("%s\n", __func__); - if (psci_ops->cpu_off) + if (psci_ops->cpu_suspend) return psci_ops->cpu_suspend(power_state, entry, context_id); return ARM_PSCI_RET_NOT_SUPPORTED; diff --git a/arch/arm/cpu/setupc.S b/arch/arm/cpu/setupc.S index 8ae7c89a2c..55aa105b21 100644 --- a/arch/arm/cpu/setupc.S +++ b/arch/arm/cpu/setupc.S @@ -21,12 +21,12 @@ ENTRY(setup_c) ldr r2,=__bss_start sub r2, r2, r0 add r1, r0, r4 - bl memcpy /* memcpy(_text, _text + offset, __bss_start - _text) */ + bl __memcpy /* memcpy(_text, _text + offset, __bss_start - _text) */ 1: ldr r0, =__bss_start mov r1, #0 ldr r2, =__bss_stop sub r2, r2, r0 - bl memset /* clear bss */ + bl __memset /* clear bss */ bl sync_caches_for_execution sub lr, r5, r4 /* adjust return address to new location */ pop {r4, r5} @@ -67,7 +67,7 @@ ENTRY(relocate_to_adr) sub r7, r7, r1 /* sub address where we are actually running */ add r7, r7, r0 /* add address where we are going to run */ - bl memcpy /* copy binary */ + bl __memcpy /* copy binary */ bl sync_caches_for_execution diff --git a/arch/arm/cpu/smccc-call.S b/arch/arm/cpu/smccc-call.S index b6bdc8b3b5..9875e1f947 100644 --- a/arch/arm/cpu/smccc-call.S +++ b/arch/arm/cpu/smccc-call.S @@ -1,16 +1,6 @@ -/* - * Copyright (c) 2015, Linaro Limited - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2015 Linaro Limited */ + #include <linux/linkage.h> #include <asm/unwind.h> diff --git a/arch/arm/cpu/smccc-call_64.S b/arch/arm/cpu/smccc-call_64.S index 44888fb594..c2959050d2 100644 --- a/arch/arm/cpu/smccc-call_64.S +++ b/arch/arm/cpu/smccc-call_64.S @@ -1,16 +1,6 @@ -/* - * Copyright (c) 2015, Linaro Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License Version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2015 Linaro Limited */ + #include <linux/linkage.h> #include <linux/arm-smccc.h> #include <asm/asm-offsets.h> diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c index 2cf21459da..f48f5beea8 100644 --- a/arch/arm/cpu/start.c +++ b/arch/arm/cpu/start.c @@ -1,16 +1,6 @@ -/* - * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2010 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + #define pr_fmt(fmt) "start.c: " fmt #include <common.h> @@ -25,6 +15,7 @@ #include <asm/unaligned.h> #include <asm/cache.h> #include <asm/mmu.h> +#include <linux/kasan.h> #include <memory.h> #include <uncompress.h> #include <malloc.h> @@ -145,7 +136,7 @@ static int barebox_memory_areas_init(void) } device_initcall(barebox_memory_areas_init); -__noreturn void barebox_non_pbl_start(unsigned long membase, +__noreturn __no_sanitize_address void barebox_non_pbl_start(unsigned long membase, unsigned long memsize, void *boarddata) { unsigned long endmem = membase + memsize; @@ -243,6 +234,8 @@ __noreturn void barebox_non_pbl_start(unsigned long membase, pr_debug("initializing malloc pool at 0x%08lx (size 0x%08lx)\n", malloc_start, malloc_end - malloc_start); + kasan_init(membase, memsize, malloc_start - (memsize >> KASAN_SHADOW_SCALE_SHIFT)); + mem_malloc_init((void *)malloc_start, (void *)malloc_end - 1); if (IS_ENABLED(CONFIG_BOOTM_OPTEE)) @@ -269,7 +262,7 @@ void start(unsigned long membase, unsigned long memsize, void *boarddata); * First function in the uncompressed image. We get here from * the pbl. The stack already has been set up by the pbl. */ -void NAKED __section(.text_entry) start(unsigned long membase, +void NAKED __no_sanitize_address __section(.text_entry) start(unsigned long membase, unsigned long memsize, void *boarddata) { barebox_non_pbl_start(membase, memsize, boarddata); diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c index 3eb0132d53..db0fe98e0d 100644 --- a/arch/arm/cpu/uncompress.c +++ b/arch/arm/cpu/uncompress.c @@ -1,19 +1,9 @@ -/* - * uncompress.c - uncompressor code for self extracing pbl image - * - * Copyright (c) 2010-2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * Copyright (c) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2010-2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +/* uncompress.c - uncompressor code for self extracing pbl image */ + #define pr_fmt(fmt) "uncompress.c: " fmt #include <common.h> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1aeaa61e01..a1e0bb6a41 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -2,49 +2,49 @@ # created. obj- += dummy.o -lwl-dtb-$(CONFIG_MACH_ADVANTECH_ROM_742X) += imx6dl-advantech-rom-7421.dtb.o -lwl-dtb-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o -lwl-dtb-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o -lwl-dtb-$(CONFIG_MACH_CANON_A1100) += canon-a1100.dtb.o -lwl-dtb-$(CONFIG_MACH_CM_FX6) += imx6dl-cm-fx6.dtb.o imx6q-cm-fx6.dtb.o imx6q-utilite.dtb.o -lwl-dtb-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o -lwl-dtb-$(CONFIG_MACH_DUCKBILL) += imx28-duckbill.dtb.o -lwl-dtb-$(CONFIG_MACH_KINDLE_MX50) += imx50-kindle-d01100.dtb.o imx50-kindle-d01200.dtb.o imx50-kindle-ey21.dtb.o -lwl-dtb-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o -lwl-dtb-$(CONFIG_MACH_ELTEC_HIPERCAM) += imx6dl-eltec-hipercam.dtb.o -lwl-dtb-$(CONFIG_MACH_EMBEST_MARSBOARD) += imx6q-marsboard.dtb.o -lwl-dtb-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o -lwl-dtb-$(CONFIG_MACH_EMBEDSKY_E9) += imx6q-embedsky-e9.dtb.o -lwl-dtb-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o -lwl-dtb-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o -lwl-dtb-$(CONFIG_MACH_TX53) += imx53-tx53-xx30.dtb.o imx53-tx53-1011.dtb.o -lwl-dtb-$(CONFIG_MACH_CCMX51) += imx51-ccxmx51.dtb.o -lwl-dtb-$(CONFIG_MACH_CCMX53) += imx53-ccxmx53.dtb.o -lwl-dtb-$(CONFIG_MACH_DIGI_CCIMX6ULSBCPRO) += imx6ul-ccimx6ulsbcpro.dtb.o -lwl-dtb-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o -lwl-dtb-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += imx7d-sdb.dtb.o -lwl-dtb-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o -lwl-dtb-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o -lwl-dtb-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o -lwl-dtb-$(CONFIG_MACH_GRINN_LITEBOARD) += imx6ul-liteboard.dtb.o -lwl-dtb-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o -lwl-dtb-$(CONFIG_MACH_GUF_VINCELL) += imx53-guf-vincell.dtb.o imx53-guf-vincell-lt.dtb.o -lwl-dtb-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o -lwl-dtb-$(CONFIG_MACH_KONTRON_SAMX6I) += imx6q-samx6i.dtb.o \ +lwl-$(CONFIG_MACH_ADVANTECH_ROM_742X) += imx6dl-advantech-rom-7421.dtb.o +lwl-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o +lwl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o +lwl-$(CONFIG_MACH_CANON_A1100) += canon-a1100.dtb.o +lwl-$(CONFIG_MACH_CM_FX6) += imx6dl-cm-fx6.dtb.o imx6q-cm-fx6.dtb.o imx6q-utilite.dtb.o +lwl-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o +lwl-$(CONFIG_MACH_DUCKBILL) += imx28-duckbill.dtb.o +lwl-$(CONFIG_MACH_KINDLE_MX50) += imx50-kindle-d01100.dtb.o imx50-kindle-d01200.dtb.o imx50-kindle-ey21.dtb.o +lwl-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o +lwl-$(CONFIG_MACH_ELTEC_HIPERCAM) += imx6dl-eltec-hipercam.dtb.o +lwl-$(CONFIG_MACH_EMBEST_MARSBOARD) += imx6q-marsboard.dtb.o +lwl-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o +lwl-$(CONFIG_MACH_EMBEDSKY_E9) += imx6q-embedsky-e9.dtb.o +lwl-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o +lwl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o +lwl-$(CONFIG_MACH_TX53) += imx53-tx53-xx30.dtb.o imx53-tx53-1011.dtb.o +lwl-$(CONFIG_MACH_CCMX51) += imx51-ccxmx51.dtb.o +lwl-$(CONFIG_MACH_CCMX53) += imx53-ccxmx53.dtb.o +lwl-$(CONFIG_MACH_DIGI_CCIMX6ULSBCPRO) += imx6ul-ccimx6ulsbcpro.dtb.o +lwl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o +lwl-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += imx7d-sdb.dtb.o +lwl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o +lwl-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o +lwl-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o +lwl-$(CONFIG_MACH_GRINN_LITEBOARD) += imx6ul-liteboard.dtb.o +lwl-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o +lwl-$(CONFIG_MACH_GUF_VINCELL) += imx53-guf-vincell.dtb.o imx53-guf-vincell-lt.dtb.o +lwl-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o +lwl-$(CONFIG_MACH_KONTRON_SAMX6I) += imx6q-samx6i.dtb.o \ imx6dl-samx6i.dtb.o -lwl-dtb-$(CONFIG_MACH_LENOVO_IX4_300D) += armada-xp-lenovo-ix4-300d-bb.dtb.o -lwl-dtb-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o -lwl-dtb-$(CONFIG_MACH_MARVELL_ARMADA_XP_DB) += armada-xp-db-bb.dtb.o -lwl-dtb-$(CONFIG_MACH_MB7707) += module-mb7707.dtb.o -lwl-dtb-$(CONFIG_MACH_MX28EVK) += imx28-evk.dtb.o -lwl-dtb-$(CONFIG_MACH_NETGEAR_RN104) += armada-370-rn104-bb.dtb.o -lwl-dtb-$(CONFIG_MACH_NETGEAR_RN2120) += armada-xp-rn2120-bb.dtb.o -lwl-dtb-$(CONFIG_MACH_NITROGEN6) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o imx6qp-nitrogen6_max.dtb.o -lwl-dtb-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o -lwl-dtb-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o -lwl-dtb-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o -lwl-dtb-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o -lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += am335x-phytec-phyflex-som.dtb.o am335x-phytec-phyflex-som-mlo.dtb.o \ +lwl-$(CONFIG_MACH_LENOVO_IX4_300D) += armada-xp-lenovo-ix4-300d-bb.dtb.o +lwl-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o +lwl-$(CONFIG_MACH_MARVELL_ARMADA_XP_DB) += armada-xp-db-bb.dtb.o +lwl-$(CONFIG_MACH_MB7707) += module-mb7707.dtb.o +lwl-$(CONFIG_MACH_MX28EVK) += imx28-evk.dtb.o +lwl-$(CONFIG_MACH_NETGEAR_RN104) += armada-370-rn104-bb.dtb.o +lwl-$(CONFIG_MACH_NETGEAR_RN2120) += armada-xp-rn2120-bb.dtb.o +lwl-$(CONFIG_MACH_NITROGEN6) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o imx6qp-nitrogen6_max.dtb.o +lwl-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o +lwl-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o +lwl-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o +lwl-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o +lwl-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += am335x-phytec-phyflex-som.dtb.o am335x-phytec-phyflex-som-mlo.dtb.o \ am335x-phytec-phyflex-som-no-spi.dtb.o am335x-phytec-phyflex-som-no-eeprom.dtb.o \ am335x-phytec-phyflex-som-no-spi-no-eeprom.dtb.o \ am335x-phytec-phycore-som-mlo.dtb.o \ @@ -52,7 +52,7 @@ lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += am335x-phytec-phyflex-som.dtb.o am33 am335x-phytec-phycore-som-nand-no-eeprom.dtb.o am335x-phytec-phycore-som-nand-no-spi-no-eeprom.dtb.o \ am335x-phytec-phycore-som-emmc.dtb.o \ am335x-phytec-phycard-som.dtb.o am335x-phytec-phycard-som-mlo.dtb.o -lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-phycard.dtb.o \ +lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-phycard.dtb.o \ imx6s-phytec-pbab01.dtb.o \ imx6dl-phytec-pbab01.dtb.o \ imx6q-phytec-pbab01.dtb.o \ @@ -67,68 +67,88 @@ lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-phycard.dtb.o \ imx6dl-phytec-phycore-som-emmc.dtb.o \ imx6dl-phytec-phycore-som-lc-emmc.dtb.o \ imx6ul-phytec-phycore-som-nand.dtb.o \ + imx6ul-phytec-phycore-som-emmc.dtb.o \ imx6ull-phytec-phycore-som-lc-nand.dtb.o \ imx6ull-phytec-phycore-som-nand.dtb.o \ imx6ull-phytec-phycore-som-emmc.dtb.o -lwl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o -lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o -lwl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o -lwl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o -lwl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o -lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o -lwl-dtb-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o -lwl-dtb-$(CONFIG_MACH_RPI) += bcm2835-rpi.dtb.o -lwl-dtb-$(CONFIG_MACH_RPI2) += bcm2836-rpi-2.dtb.o -lwl-dtb-$(CONFIG_MACH_RPI3) += bcm2837-rpi-3.dtb.o -lwl-dtb-$(CONFIG_MACH_RPI_CM3) += bcm2837-rpi-cm3.dtb.o -lwl-dtb-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o -lwl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o -lwl-dtb-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o -lwl-dtb-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o -lwl-dtb-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o -lwl-dtb-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += socfpga_arria10_achilles.dtb.o -lwl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o -lwl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o -lwl-dtb-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o -lwl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o \ +lwl-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o +lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o +lwl-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o +lwl-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o +lwl-$(CONFIG_MACH_PROTONIC_IMX6) += \ + imx6q-prti6q.dtb.o \ + imx6q-prtwd2.dtb.o \ + imx6q-vicut1.dtb.o \ + imx6dl-alti6p.dtb.o \ + imx6dl-lanmcu.dtb.o \ + imx6dl-plybas.dtb.o \ + imx6dl-plym2m.dtb.o \ + imx6dl-prtmvt.dtb.o \ + imx6dl-prtrvt.dtb.o \ + imx6dl-prtvt7.dtb.o \ + imx6dl-victgo.dtb.o \ + imx6dl-vicut1.dtb.o \ + imx6qp-prtwd3.dtb.o \ + imx6qp-vicutp.dtb.o \ + imx6ul-prti6g.dtb.o +lwl-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o +lwl-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o +lwl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o +lwl-$(CONFIG_MACH_RPI) += bcm2835-rpi.dtb.o +lwl-$(CONFIG_MACH_RPI2) += bcm2836-rpi-2.dtb.o +lwl-$(CONFIG_MACH_RPI3) += bcm2837-rpi-3.dtb.o +lwl-$(CONFIG_MACH_RPI_CM3) += bcm2837-rpi-cm3.dtb.o +lwl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o +lwl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o +lwl-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o +lwl-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o +lwl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o +lwl-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += socfpga_arria10_achilles.dtb.o +lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o +lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o +lwl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o +lwl-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o \ imx6dl-hummingboard2.dtb.o imx6q-hummingboard2.dtb.o \ imx6q-h100.dtb.o -lwl-dtb-$(CONFIG_MACH_STM32MP157C_DK2) += stm32mp157c-dk2.dtb.o -lwl-dtb-$(CONFIG_MACH_LXA_MC1) += stm32mp157c-lxa-mc1.dtb.o -lwl-dtb-$(CONFIG_MACH_SCB9328) += imx1-scb9328.dtb.o -lwl-dtb-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o -lwl-dtb-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o -lwl-dtb-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += imx6ull-14x14-evk.dtb.o -lwl-dtb-$(CONFIG_MACH_NXP_IMX8MM_EVK) += imx8mm-evk.dtb.o -lwl-dtb-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += imx8mq-evk.dtb.o -lwl-dtb-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o -lwl-dtb-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o -lwl-dtb-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o -lwl-dtb-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o -lwl-dtb-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o -lwl-dtb-$(CONFIG_MACH_TX6X) += imx6dl-tx6u.dtb.o -lwl-dtb-$(CONFIG_MACH_TX6X) += imx6q-tx6q.dtb.o -lwl-dtb-$(CONFIG_MACH_TURRIS_OMNIA) += armada-385-turris-omnia-bb.dtb.o -lwl-dtb-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o -lwl-dtb-$(CONFIG_MACH_UDOO_NEO) += imx6sx-udoo-neo-full.dtb.o -lwl-dtb-$(CONFIG_MACH_USI_TOPKICK) += kirkwood-topkick-bb.dtb.o -lwl-dtb-$(CONFIG_MACH_VARISCITE_MX6) += imx6q-var-custom.dtb.o -lwl-dtb-$(CONFIG_MACH_VERSATILEPB) += versatile-pb.dtb.o -lwl-dtb-$(CONFIG_MACH_VEXPRESS) += vexpress-v2p-ca9.dtb.o -lwl-dtb-$(CONFIG_MACH_VEXPRESS) += vexpress-v2p-ca15.dtb.o -lwl-dtb-$(CONFIG_MACH_VIRT2REAL) += virt2real.dtb.o -lwl-dtb-$(CONFIG_MACH_VSCOM_BALTOS) += am335x-baltos-minimal.dtb.o -lwl-dtb-$(CONFIG_MACH_WARP7) += imx7s-warp.dtb.o -lwl-dtb-$(CONFIG_MACH_VF610_TWR) += vf610-twr.dtb.o -lwl-dtb-$(CONFIG_MACH_ZII_RDU1) += \ +lwl-$(CONFIG_MACH_SEEED_ODYSSEY) += stm32mp157c-odyssey.dtb.o +lwl-$(CONFIG_MACH_STM32MP15XX_DKX) += stm32mp157c-dk2.dtb.o stm32mp157a-dk1.dtb.o +lwl-$(CONFIG_MACH_LXA_MC1) += stm32mp157c-lxa-mc1.dtb.o +lwl-$(CONFIG_MACH_SCB9328) += imx1-scb9328.dtb.o +lwl-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o +lwl-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o +lwl-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += imx6ull-14x14-evk.dtb.o +lwl-$(CONFIG_MACH_NXP_IMX8MM_EVK) += imx8mm-evk.dtb.o +lwl-$(CONFIG_MACH_NXP_IMX8MP_EVK) += imx8mp-evk.dtb.o +lwl-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += imx8mq-evk.dtb.o +lwl-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o +lwl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o +lwl-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o +lwl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o +lwl-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o +lwl-$(CONFIG_MACH_TX6X) += imx6dl-tx6u.dtb.o +lwl-$(CONFIG_MACH_TX6X) += imx6q-tx6q.dtb.o +lwl-$(CONFIG_MACH_TURRIS_OMNIA) += armada-385-turris-omnia-bb.dtb.o +lwl-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o +lwl-$(CONFIG_MACH_UDOO_NEO) += imx6sx-udoo-neo-full.dtb.o +lwl-$(CONFIG_MACH_USI_TOPKICK) += kirkwood-topkick-bb.dtb.o +lwl-$(CONFIG_MACH_VARISCITE_MX6) += imx6q-var-custom.dtb.o +lwl-$(CONFIG_MACH_VERSATILEPB) += versatile-pb.dtb.o +lwl-$(CONFIG_MACH_VEXPRESS) += vexpress-v2p-ca9.dtb.o +lwl-$(CONFIG_MACH_VEXPRESS) += vexpress-v2p-ca15.dtb.o +lwl-$(CONFIG_MACH_VIRT2REAL) += virt2real.dtb.o +lwl-$(CONFIG_MACH_VSCOM_BALTOS) += am335x-baltos-minimal.dtb.o +lwl-$(CONFIG_MACH_WARP7) += imx7s-warp.dtb.o +lwl-$(CONFIG_MACH_VF610_TWR) += vf610-twr.dtb.o +lwl-$(CONFIG_MACH_WEBASTO_CCBV2) += imx6ul-webasto-ccbv2.dtb.o +lwl-$(CONFIG_MACH_ZII_RDU1) += \ imx51-zii-rdu1.dtb.o \ imx51-zii-scu2-mezz.dtb.o \ imx51-zii-scu3-esb.dtb.o -lwl-dtb-$(CONFIG_MACH_ZII_RDU2) += imx6q-zii-rdu2.dtb.o imx6qp-zii-rdu2.dtb.o -lwl-dtb-$(CONFIG_MACH_ZII_IMX8MQ_DEV) += \ +lwl-$(CONFIG_MACH_ZII_RDU2) += imx6q-zii-rdu2.dtb.o imx6qp-zii-rdu2.dtb.o +lwl-$(CONFIG_MACH_ZII_IMX8MQ_DEV) += \ imx8mq-zii-ultra-rmb3.dtb.o \ imx8mq-zii-ultra-zest.dtb.o -lwl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \ +lwl-$(CONFIG_MACH_ZII_VF610_DEV) += \ vf610-zii-dev-rev-b.dtb.o \ vf610-zii-dev-rev-c.dtb.o \ vf610-zii-cfu1.dtb.o \ @@ -136,17 +156,18 @@ lwl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \ vf610-zii-scu4-aib.dtb.o \ vf610-zii-spb4.dtb.o \ vf610-zii-ssmb-dtu.dtb.o -lwl-dtb-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o -lwl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o -lwl-dtb-$(CONFIG_MACH_SAMA5D27_SOM1) += at91-sama5d27_som1_ek.dtb.o -lwl-dtb-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += at91-sama5d27_giantboard.dtb.o -lwl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o -lwl-dtb-$(CONFIG_MACH_XILINX_ZCU104) += zynqmp-zcu104-revA.dtb.o +lwl-$(CONFIG_MACH_AC_SXB) += ac-sxb.dtb.o +lwl-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o +lwl-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o +lwl-$(CONFIG_MACH_SAMA5D27_SOM1) += at91-sama5d27_som1_ek.dtb.o +lwl-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += at91-sama5d27_giantboard.dtb.o +lwl-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o +lwl-$(CONFIG_MACH_XILINX_ZCU104) += zynqmp-zcu104-revA.dtb.o -lwl-dtb-$(CONFIG_MACH_ZII_IMX7D_DEV) += imx7d-zii-rpu2.dtb.o imx7d-zii-rmu2.dtb.o -lwl-dtb-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o -lwl-dtb-$(CONFIG_MACH_LS1046ARDB) += fsl-ls1046a-rdb.dtb.o -lwl-dtb-$(CONFIG_MACH_TQMLS1046A) += fsl-tqmls1046a-mbls10xxa.dtb.o -lwl-dtb-$(CONFIG_MACH_ZEDBOARD) += zynq-zed.dtb.o +lwl-$(CONFIG_MACH_ZII_IMX7D_DEV) += imx7d-zii-rpu2.dtb.o imx7d-zii-rmu2.dtb.o +lwl-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o +lwl-$(CONFIG_MACH_LS1046ARDB) += fsl-ls1046a-rdb.dtb.o +lwl-$(CONFIG_MACH_TQMLS1046A) += fsl-tqmls1046a-mbls10xxa.dtb.o +lwl-$(CONFIG_MACH_ZEDBOARD) += zynq-zed.dtb.o clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo diff --git a/arch/arm/dts/ac-sxb.dts b/arch/arm/dts/ac-sxb.dts new file mode 100644 index 0000000000..8f2eec0fa0 --- /dev/null +++ b/arch/arm/dts/ac-sxb.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright (C) 2017 Atlas Copco Industrial Technique + */ + +#include "imx7d-ac-sxb.dtsi" +#include "imx7d-ddrc.dtsi" + +/ { + chosen { + stdout-path = &uart1; + }; + + state: state { + #address-cells = <1>; + #size-cells = <1>; + magic = <0x27031977>; + compatible = "barebox,state"; + backend-type = "raw"; + backend-storage-type = "direct"; + backend-stridesize = <0x500>; + backend = <&usdhc1_sdcard>; + + bootstate { + #address-cells = <1>; + #size-cells = <1>; + + last_chosen@0 { + reg = <0x0 0x4>; + type = "uint32"; + default = <0x1>; + }; + + fs1.remaining_attempts@4 { + reg = <0x4 0x4>; + type = "uint32"; + default = <3>; + }; + + fs1.priority@8 { + reg = <0x8 0x4>; + type = "uint32"; + default= <3>; + }; + + fs2.remaining_attempts@c { + reg = <0xc 0x4>; + type = "uint32"; + default = <3>; + }; + + fs2.priority@10 { + reg = <0x10 0x4>; + type = "uint32"; + default= <2>; + }; + + rescue.remaining_attempts@14 { + reg = <0x14 0x4>; + type = "uint32"; + default = <3>; + }; + + rescue.priority@18 { + reg = <0x18 0x4>; + type = "uint32"; + default= <1>; + }; + + last_chosen_sucessfull@1c { + reg = <0x1c 0x4>; + type = "uint32"; + default = <0>; + }; + }; + }; + + aliases { + state = &state; + }; +}; + +/* FIXME: barebox serial is broken when barebox applies requested reparenting */ +&uart1 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; +}; diff --git a/arch/arm/dts/am335x-afi-gf.dts b/arch/arm/dts/am335x-afi-gf.dts index 961fe2e241..54059dbfce 100644 --- a/arch/arm/dts/am335x-afi-gf.dts +++ b/arch/arm/dts/am335x-afi-gf.dts @@ -29,7 +29,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 128 MB */ }; @@ -370,186 +370,186 @@ &am33xx_pinmux { dcan0_pins: pinmux_dcan0_pins { pinctrl-single,pins = < - 0x11c (PIN_OUTPUT_PULLUP | MUX_MODE1) /* mii1_txd3.dcan0_tx_mux0, OUTPUT_PULLUP | MODE1 */ - 0x120 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_txd2.dcan0_rx_mux0, INPUT_PULLUP | MODE1 */ + 0x11c PIN_OUTPUT_PULLUP MUX_MODE1 /* mii1_txd3.dcan0_tx_mux0, OUTPUT_PULLUP | MODE1 */ + 0x120 PIN_INPUT_PULLUP MUX_MODE1 /* mii1_txd2.dcan0_rx_mux0, INPUT_PULLUP | MODE1 */ >; }; eth_pins: pinmux_eth_pins { pinctrl-single,pins = < /* RMII2 (mezzanine) */ - 0x040 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a0.rmii2_txen, OUTPUT_PULLDOWN | MODE3 */ - 0x050 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a4.rmii2_txd1, INPUT_PULLDOWN | MODE3 */ - 0x054 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a5.rmii2_txd0, INPUT_PULLDOWN | MODE3 */ - 0x068 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a10.rmii2_rxd1, INPUT_PULLDOWN | MODE3 */ - 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a11.rmii2_rxd0, INPUT_PULLDOWN | MODE3 */ - 0x070 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv, INPUT_PULLUP | MODE3 */ /* PHYAD pin */ - 0x074 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wpn.rmii2_rxer, INPUT_PULLUP | MODE3 */ - 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_col.rmii2_refclk, INPUT_PULLDOWN | MODE1 */ + 0x040 PIN_OUTPUT_PULLDOWN MUX_MODE3 /* gpmc_a0.rmii2_txen, OUTPUT_PULLDOWN | MODE3 */ + 0x050 PIN_INPUT_PULLDOWN MUX_MODE3 /* gpmc_a4.rmii2_txd1, INPUT_PULLDOWN | MODE3 */ + 0x054 PIN_INPUT_PULLDOWN MUX_MODE3 /* gpmc_a5.rmii2_txd0, INPUT_PULLDOWN | MODE3 */ + 0x068 PIN_INPUT_PULLDOWN MUX_MODE3 /* gpmc_a10.rmii2_rxd1, INPUT_PULLDOWN | MODE3 */ + 0x06c PIN_INPUT_PULLDOWN MUX_MODE3 /* gpmc_a11.rmii2_rxd0, INPUT_PULLDOWN | MODE3 */ + 0x070 PIN_INPUT_PULLUP MUX_MODE3 /* gpmc_wait0.rmii2_crs_dv, INPUT_PULLUP | MODE3 */ /* PHYAD pin */ + 0x074 PIN_INPUT_PULLUP MUX_MODE3 /* gpmc_wpn.rmii2_rxer, INPUT_PULLUP | MODE3 */ + 0x108 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_col.rmii2_refclk, INPUT_PULLDOWN | MODE1 */ /* RMII1 (board) */ - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv, INPUT_PULLDOWN | MODE1 */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rx_er.rmii1_rxer, INPUT_PULLDOWN | MODE1 */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen, OUTPUT_PULLDOWN | MODE1 */ - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1, INPUT_PULLDOWN | MODE1 */ - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0, INPUT_PULLDOWN | MODE1 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1, INPUT_PULLDOWN | MODE1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0, INPUT_PULLDOWN | MODE1 */ - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk, INPUT_PULLDOWN | MODE0 */ + 0x10c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_crs.rmii1_crs_dv, INPUT_PULLDOWN | MODE1 */ + 0x110 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rx_er.rmii1_rxer, INPUT_PULLDOWN | MODE1 */ + 0x114 PIN_OUTPUT_PULLDOWN MUX_MODE1 /* mii1_tx_en.rmii1_txen, OUTPUT_PULLDOWN | MODE1 */ + 0x124 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_txd1.rmii1_txd1, INPUT_PULLDOWN | MODE1 */ + 0x128 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_txd0.rmii1_txd0, INPUT_PULLDOWN | MODE1 */ + 0x13c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd1.rmii1_rxd1, INPUT_PULLDOWN | MODE1 */ + 0x140 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd0.rmii1_rxd0, INPUT_PULLDOWN | MODE1 */ + 0x144 PIN_INPUT_PULLDOWN MUX_MODE0 /* rmii1_ref_clk.rmii1_refclk, INPUT_PULLDOWN | MODE0 */ /* MDIO (board & mezzanine) */ - 0x148 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio.mdio_data, INPUT_PULLUP | MODE0 */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdc.mdio_clk, OUTPUT_PULLUP | MODE0 */ + 0x148 PIN_INPUT_PULLUP MUX_MODE0 /* mdio.mdio_data, INPUT_PULLUP | MODE0 */ + 0x14c PIN_OUTPUT_PULLUP MUX_MODE0 /* mdc.mdio_clk, OUTPUT_PULLUP | MODE0 */ >; }; spi0_pins: pinmux_spi0_pins { /* SPI NOR-Flash & FRAM */ pinctrl-single,pins = < - 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk, INPUT_PULLUP | MODE0 */ - 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0, INPUT_PULLUP | MODE0 */ - 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1, INPUT_PULLUP | MODE0 */ - 0x15c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs0, OUTPUT_PULLUP | MODE0 */ - 0x160 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs1, OUTPUT_PULLUP | MODE0 */ + 0x150 PIN_INPUT_PULLUP MUX_MODE0 /* spi0_sclk, INPUT_PULLUP | MODE0 */ + 0x154 PIN_INPUT_PULLUP MUX_MODE0 /* spi0_d0, INPUT_PULLUP | MODE0 */ + 0x158 PIN_INPUT_PULLUP MUX_MODE0 /* spi0_d1, INPUT_PULLUP | MODE0 */ + 0x15c PIN_OUTPUT_PULLUP MUX_MODE0 /* spi0_cs0, OUTPUT_PULLUP | MODE0 */ + 0x160 PIN_OUTPUT_PULLUP MUX_MODE0 /* spi0_cs1, OUTPUT_PULLUP | MODE0 */ >; }; spi1_pins: pinmux_spi1_pins { /* SPI (mezzanine) */ pinctrl-single,pins = < - 0x170 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* uart0_rxd.spi1_cs0_mux3, OUTPUT_PULLUP | MODE1 */ - 0x174 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* uart0_txd.spi1_cs1_mux3, OUTPUT_PULLUP | MODE1 */ - 0x190 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk_mux2, INPUT_PULLUP | MODE3 */ - 0x194 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_fsx.spi1_d0_mux2, INPUT_PULLUP | MODE3 */ - 0x198 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_axr0.spi1_d1_mux2, INPUT_PULLUP | MODE3 */ + 0x170 PIN_OUTPUT_PULLUP MUX_MODE1 /* uart0_rxd.spi1_cs0_mux3, OUTPUT_PULLUP | MODE1 */ + 0x174 PIN_OUTPUT_PULLUP MUX_MODE1 /* uart0_txd.spi1_cs1_mux3, OUTPUT_PULLUP | MODE1 */ + 0x190 PIN_INPUT_PULLUP MUX_MODE3 /* mcasp0_aclkx.spi1_sclk_mux2, INPUT_PULLUP | MODE3 */ + 0x194 PIN_INPUT_PULLUP MUX_MODE3 /* mcasp0_fsx.spi1_d0_mux2, INPUT_PULLUP | MODE3 */ + 0x198 PIN_INPUT_PULLUP MUX_MODE3 /* mcasp0_axr0.spi1_d1_mux2, INPUT_PULLUP | MODE3 */ >; }; usb0_pins: pinmux_usb0_pins { /* USB-HOST (mezzanine) */ pinctrl-single,pins = < - 0x208 (PIN_INPUT | MUX_MODE0) /* usb0_dm, INPUT | MODE0 */ - 0x20c (PIN_INPUT | MUX_MODE0) /* usb0_dp, INPUT | MODE0 */ - 0x210 (PIN_INPUT | MUX_MODE0) /* usb0_ce, INPUT | MODE0 */ - 0x214 (PIN_INPUT | MUX_MODE0) /* usb0_id, INPUT | MODE0 */ - 0x218 (PIN_INPUT | MUX_MODE0) /* usb0_vbus, INPUT | MODE0 */ - 0x21c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb0_drvvbus, OUTPUT_PULLDOWN | MODE0 */ + 0x208 PIN_INPUT MUX_MODE0 /* usb0_dm, INPUT | MODE0 */ + 0x20c PIN_INPUT MUX_MODE0 /* usb0_dp, INPUT | MODE0 */ + 0x210 PIN_INPUT MUX_MODE0 /* usb0_ce, INPUT | MODE0 */ + 0x214 PIN_INPUT MUX_MODE0 /* usb0_id, INPUT | MODE0 */ + 0x218 PIN_INPUT MUX_MODE0 /* usb0_vbus, INPUT | MODE0 */ + 0x21c PIN_OUTPUT_PULLDOWN MUX_MODE0 /* usb0_drvvbus, OUTPUT_PULLDOWN | MODE0 */ >; }; usb1_pins: pinmux_usb1_pins { /* USB-OTG (front) */ pinctrl-single,pins = < - 0x220 (PIN_INPUT | MUX_MODE0) /* usb1_dm, INPUT | MODE0 */ - 0x224 (PIN_INPUT | MUX_MODE0) /* usb1_dp, INPUT | MODE0 */ - 0x228 (PIN_INPUT | MUX_MODE0) /* usb1_ce, INPUT | MODE0 */ - 0x22c (PIN_INPUT | MUX_MODE0) /* usb1_id, INPUT | MODE0 */ - 0x230 (PIN_INPUT | MUX_MODE0) /* usb1_vbus, INPUT | MODE0 */ - 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus, OUTPUT_PULLDOWN | MODE0 */ + 0x220 PIN_INPUT MUX_MODE0 /* usb1_dm, INPUT | MODE0 */ + 0x224 PIN_INPUT MUX_MODE0 /* usb1_dp, INPUT | MODE0 */ + 0x228 PIN_INPUT MUX_MODE0 /* usb1_ce, INPUT | MODE0 */ + 0x22c PIN_INPUT MUX_MODE0 /* usb1_id, INPUT | MODE0 */ + 0x230 PIN_INPUT MUX_MODE0 /* usb1_vbus, INPUT | MODE0 */ + 0x234 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* usb1_drvvbus, OUTPUT_PULLDOWN | MODE0 */ >; }; uart0_pins: pinmux_uart0_pins { /* debug, later spi1 CS1/2 */ pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd */ + 0x170 PIN_INPUT_PULLUP MUX_MODE0 /* uart0_rxd */ + 0x174 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* uart0_txd */ >; }; uart1_pins: pinmux_uart1_pins { /* UART1 (PRU) */ pinctrl-single,pins = < - 0x180 (PIN_INPUT | MUX_MODE5) /* uart1_rxd.pr1_uart0_rxd_mux1, INPUT | MODE5 (RS485_RXD)*/ - 0x184 (PIN_OUTPUT | MUX_MODE5) /* uart1_txd.pr1_uart0_txd_mux1, OUTPUT | MODE5 (RS485_TXD) */ + 0x180 PIN_INPUT MUX_MODE5 /* uart1_rxd.pr1_uart0_rxd_mux1, INPUT | MODE5 (RS485_RXD)*/ + 0x184 PIN_OUTPUT MUX_MODE5 /* uart1_txd.pr1_uart0_txd_mux1, OUTPUT | MODE5 (RS485_TXD) */ >; }; uart2_pins: pinmux_uart2_pins { /* UART2 (console) */ pinctrl-single,pins = < - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_clk.uart2_rxd_mux0, INPUT_PULLDOWN | MODE1 (UART2_RXD) */ - 0x130 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rx_clk.uart2_txd_mux0, OUTPUT_PULLDOWN | MODE1 (UART2_TXD) */ + 0x12c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_tx_clk.uart2_rxd_mux0, INPUT_PULLDOWN | MODE1 (UART2_RXD) */ + 0x130 PIN_OUTPUT_PULLDOWN MUX_MODE1 /* mii1_rx_clk.uart2_txd_mux0, OUTPUT_PULLDOWN | MODE1 (UART2_TXD) */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */ + 0x188 PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */ + 0x18c PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */ >; }; i2c1_pins: pinmux_i2c1_pins { /* 1-wire */ pinctrl-single,pins = < - 0x168 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_ctsn.i2c1_sda_mux1, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ - 0x16c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_rtsn.i2c1_scl_mux1, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ + 0x168 PIN_INPUT_PULLUP MUX_MODE3 /* uart0_ctsn.i2c1_sda_mux1, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ + 0x16c PIN_INPUT_PULLUP MUX_MODE3 /* uart0_rtsn.i2c1_scl_mux1, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ >; }; i2c2_pins: pinmux_i2c2_pins { /* (mezzanine) */ pinctrl-single,pins = < - 0x178 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda_mux0, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ - 0x17c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl_mux0, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ + 0x178 PIN_INPUT_PULLUP MUX_MODE3 /* uart1_ctsn.i2c2_sda_mux0, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ + 0x17c PIN_INPUT_PULLUP MUX_MODE3 /* uart1_rtsn.i2c2_scl_mux0, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ >; }; gpio0_pins: pinmux_gpio0_pins { pinctrl-single,pins = < - 0x020 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.gpio0[22], OUTPUT_PULLDOWN | MODE7 (LED3) */ /* PWM later */ - 0x024 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.gpio0[23], INPUT_PULLDOWN | MODE7 (RMII2_INTRP) */ - 0x028 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad10.gpio0[26], INPUT_PULLUP | MODE7 (BUTTON0) */ - 0x02c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.gpio0[27], INPUT_PULLDOWN | MODE7 (PWR_INT)*/ - 0x0d0 (PIN_INPUT | MUX_MODE7) /* lcd_data12.gpio0[8], INPUT | MODE7 (SYSBOOT12) */ - 0x0d4 (PIN_INPUT | MUX_MODE7) /* lcd_data13.gpio0[9], INPUT | MODE7 (SYSBOOT13) */ - 0x0d8 (PIN_INPUT | MUX_MODE7) /* lcd_data14.gpio0[10], INPUT | MODE7 (SYSBOOT14) */ - 0x0dc (PIN_INPUT | MUX_MODE7) /* lcd_data15.gpio0[11], INPUT | MODE7 (SYSBOOT15) */ - 0x164 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* ecap0_in_pwm0_out.gpio0[7], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO0) */ - 0x1b4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* xdma_event_intr1.gpio0[20], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO3) */ + 0x020 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad8.gpio0[22], OUTPUT_PULLDOWN | MODE7 (LED3) */ /* PWM later */ + 0x024 PIN_INPUT_PULLDOWN MUX_MODE7 /* gpmc_ad9.gpio0[23], INPUT_PULLDOWN | MODE7 (RMII2_INTRP) */ + 0x028 PIN_INPUT_PULLUP MUX_MODE7 /* gpmc_ad10.gpio0[26], INPUT_PULLUP | MODE7 (BUTTON0) */ + 0x02c PIN_INPUT_PULLDOWN MUX_MODE7 /* gpmc_ad11.gpio0[27], INPUT_PULLDOWN | MODE7 (PWR_INT)*/ + 0x0d0 PIN_INPUT MUX_MODE7 /* lcd_data12.gpio0[8], INPUT | MODE7 (SYSBOOT12) */ + 0x0d4 PIN_INPUT MUX_MODE7 /* lcd_data13.gpio0[9], INPUT | MODE7 (SYSBOOT13) */ + 0x0d8 PIN_INPUT MUX_MODE7 /* lcd_data14.gpio0[10], INPUT | MODE7 (SYSBOOT14) */ + 0x0dc PIN_INPUT MUX_MODE7 /* lcd_data15.gpio0[11], INPUT | MODE7 (SYSBOOT15) */ + 0x164 PIN_INPUT_PULLDOWN MUX_MODE7 /* ecap0_in_pwm0_out.gpio0[7], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO0) */ + 0x1b4 PIN_INPUT_PULLDOWN MUX_MODE7 /* xdma_event_intr1.gpio0[20], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO3) */ >; }; gpio1_pins: pinmux_gpio1_pins { pinctrl-single,pins = < - 0x000 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1[0], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x004 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1[1], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x008 (PIN_INPUT | MUX_MODE7) /* gpmc_ad2.gpio1[2], INPUT | MODE7 (BOARD_REV1) */ - 0x00c (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad3.gpio1[3], INPUT_PULLUP | MODE7 (1WIRE_INT) */ - 0x010 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1[4], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x014 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1[5], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x018 (PIN_INPUT | MUX_MODE7) /* gpmc_ad6.gpio1[6], INPUT | MODE7 (BOARD_REV0) */ - 0x01c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1[7], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x030 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad12.gpio1[12], INPUT_PULLUP | MODE7 (PG_24V) */ - 0x034 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x038 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad14.gpio1[14], INPUT_PULLUP | MODE7 (SDCARD_CD) */ - 0x03c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x044 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.gpio1[17], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x048 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.gpio1[18], OUTPUT_PULLDOWN | MODE7 (LED1) */ /* PWM later */ - 0x04c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.gpio1[19], OUTPUT_PULLDOWN | MODE7 (LED2) */ /* PWM later */ - 0x058 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1[22], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x05c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1[23], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x060 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a8.gpio1[24], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x064 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1[25], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28], INPUT_PULLUP | MODE7 (USB1_OCn) */ - 0x07c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn0.gpio1[29], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x080 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1[30], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x084 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1[31], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x000 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad0.gpio1[0], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x004 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad1.gpio1[1], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x008 PIN_INPUT MUX_MODE7 /* gpmc_ad2.gpio1[2], INPUT | MODE7 (BOARD_REV1) */ + 0x00c PIN_INPUT_PULLUP MUX_MODE7 /* gpmc_ad3.gpio1[3], INPUT_PULLUP | MODE7 (1WIRE_INT) */ + 0x010 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad4.gpio1[4], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x014 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad5.gpio1[5], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x018 PIN_INPUT MUX_MODE7 /* gpmc_ad6.gpio1[6], INPUT | MODE7 (BOARD_REV0) */ + 0x01c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad7.gpio1[7], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x030 PIN_INPUT_PULLUP MUX_MODE7 /* gpmc_ad12.gpio1[12], INPUT_PULLUP | MODE7 (PG_24V) */ + 0x034 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad13.gpio1[13], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x038 PIN_INPUT_PULLUP MUX_MODE7 /* gpmc_ad14.gpio1[14], INPUT_PULLUP | MODE7 (SDCARD_CD) */ + 0x03c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad15.gpio1[15], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x044 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a1.gpio1[17], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x048 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a2.gpio1[18], OUTPUT_PULLDOWN | MODE7 (LED1) */ /* PWM later */ + 0x04c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a3.gpio1[19], OUTPUT_PULLDOWN | MODE7 (LED2) */ /* PWM later */ + 0x058 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a6.gpio1[22], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x05c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a7.gpio1[23], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x060 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a8.gpio1[24], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x064 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a9.gpio1[25], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x078 PIN_INPUT_PULLUP MUX_MODE7 /* gpmc_ben1.gpio1[28], INPUT_PULLUP | MODE7 (USB1_OCn) */ + 0x07c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_csn0.gpio1[29], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x080 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_csn1.gpio1[30], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x084 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_csn2.gpio1[31], OUTPUT_PULLDOWN | MODE7 (NC) */ >; }; gpio2_pins: pinmux_gpio2_pins { pinctrl-single,pins = < - 0x088 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2[0], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x08c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.gpio2[1], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x090 (PIN_INPUT | MUX_MODE7) /* gpmc_advn_ale.gpio2[2], INPUT | MODE7 (BOARD_REV2) */ - 0x094 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2[3], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x098 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_wen.gpio2[4], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2[5], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x0a0 (PIN_INPUT | MUX_MODE7) /* lcd_data0.gpio2[6], INPUT | MODE7 (SYSBOOT0) */ - 0x0a4 (PIN_INPUT | MUX_MODE7) /* lcd_data1.gpio2[7], INPUT | MODE7 (SYSBOOT1) */ - 0x0a8 (PIN_INPUT | MUX_MODE7) /* lcd_data2.gpio2[8], INPUT | MODE7 (SYSBOOT2) */ - 0x0ac (PIN_INPUT | MUX_MODE7) /* lcd_data3.gpio2[9], INPUT | MODE7 (SYSBOOT3) */ - 0x0b0 (PIN_INPUT | MUX_MODE7) /* lcd_data4.gpio2[10], INPUT | MODE7 (SYSBOOT4) */ - 0x0b4 (PIN_INPUT | MUX_MODE7) /* lcd_data5.gpio2[11], INPUT | MODE7 (SYSBOOT5) */ - 0x0b8 (PIN_INPUT | MUX_MODE7) /* lcd_data6.gpio2[12], INPUT | MODE7 (SYSBOOT6) */ - 0x0bc (PIN_INPUT | MUX_MODE7) /* lcd_data7.gpio2[13], INPUT | MODE7 (SYSBOOT7) */ - 0x0c0 (PIN_INPUT | MUX_MODE7) /* lcd_data8.gpio2[14], INPUT | MODE7 (SYSBOOT8) */ - 0x0c4 (PIN_INPUT | MUX_MODE7) /* lcd_data9.gpio2[15], INPUT | MODE7 (SYSBOOT9) */ - 0x0c8 (PIN_INPUT | MUX_MODE7) /* lcd_data10.gpio2[16], INPUT | MODE7 (SYSBOOT10) */ - 0x0cc (PIN_INPUT | MUX_MODE7) /* lcd_data11.gpio2[17], INPUT | MODE7 (SYSBOOT11) */ - 0x0e0 (PIN_INPUT | MUX_MODE7) /* lcd_vsync.gpio2[22], INPUT | MODE7 (BOARD_CONF1) */ - 0x0e4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x0e8 (PIN_INPUT | MUX_MODE7) /* lcd_pclk.gpio2[24], INPUT | MODE7 (BOARD_CONF0) */ - 0x0ec (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x134 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_rxd3.gpio2[18], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_rxd2.gpio2[19], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x088 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_csn3.gpio2[0], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x08c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_clk.gpio2[1], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x090 PIN_INPUT MUX_MODE7 /* gpmc_advn_ale.gpio2[2], INPUT | MODE7 (BOARD_REV2) */ + 0x094 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_oen_ren.gpio2[3], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x098 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_wen.gpio2[4], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x09c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ben0_cle.gpio2[5], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x0a0 PIN_INPUT MUX_MODE7 /* lcd_data0.gpio2[6], INPUT | MODE7 (SYSBOOT0) */ + 0x0a4 PIN_INPUT MUX_MODE7 /* lcd_data1.gpio2[7], INPUT | MODE7 (SYSBOOT1) */ + 0x0a8 PIN_INPUT MUX_MODE7 /* lcd_data2.gpio2[8], INPUT | MODE7 (SYSBOOT2) */ + 0x0ac PIN_INPUT MUX_MODE7 /* lcd_data3.gpio2[9], INPUT | MODE7 (SYSBOOT3) */ + 0x0b0 PIN_INPUT MUX_MODE7 /* lcd_data4.gpio2[10], INPUT | MODE7 (SYSBOOT4) */ + 0x0b4 PIN_INPUT MUX_MODE7 /* lcd_data5.gpio2[11], INPUT | MODE7 (SYSBOOT5) */ + 0x0b8 PIN_INPUT MUX_MODE7 /* lcd_data6.gpio2[12], INPUT | MODE7 (SYSBOOT6) */ + 0x0bc PIN_INPUT MUX_MODE7 /* lcd_data7.gpio2[13], INPUT | MODE7 (SYSBOOT7) */ + 0x0c0 PIN_INPUT MUX_MODE7 /* lcd_data8.gpio2[14], INPUT | MODE7 (SYSBOOT8) */ + 0x0c4 PIN_INPUT MUX_MODE7 /* lcd_data9.gpio2[15], INPUT | MODE7 (SYSBOOT9) */ + 0x0c8 PIN_INPUT MUX_MODE7 /* lcd_data10.gpio2[16], INPUT | MODE7 (SYSBOOT10) */ + 0x0cc PIN_INPUT MUX_MODE7 /* lcd_data11.gpio2[17], INPUT | MODE7 (SYSBOOT11) */ + 0x0e0 PIN_INPUT MUX_MODE7 /* lcd_vsync.gpio2[22], INPUT | MODE7 (BOARD_CONF1) */ + 0x0e4 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* lcd_hsync.gpio2[23], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x0e8 PIN_INPUT MUX_MODE7 /* lcd_pclk.gpio2[24], INPUT | MODE7 (BOARD_CONF0) */ + 0x0ec PIN_OUTPUT_PULLDOWN MUX_MODE7 /* lcd_ac_bias_en.gpio2[25], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x134 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* mii1_rxd3.gpio2[18], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x138 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* mii1_rxd2.gpio2[19], OUTPUT_PULLDOWN | MODE7 (NC) */ >; }; gpio3_pins: pinmux_gpio3_pins { pinctrl-single,pins = < - 0x118 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_rx_dv.gpio3[4], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x19c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkr.gpio3[17], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO1) */ - 0x1a0 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], OUTPUT_PULLUP | MODE7 (DCAN0_LBK) */ /* enable loopback by default */ - 0x1a4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_fsr.gpio3[19], OUTPUT_PULLDOWN | MODE7 (RS485_DE) */ - 0x1a8 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mcasp0_axr1.gpio3[20], OUTPUT_PULLUP | MODE7 (1WIRE_SLEEP) */ - 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3[21], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO2) */ + 0x118 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* mii1_rx_dv.gpio3[4], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x19c PIN_INPUT_PULLDOWN MUX_MODE7 /* mcasp0_ahclkr.gpio3[17], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO1) */ + 0x1a0 PIN_OUTPUT_PULLUP MUX_MODE7 /* mcasp0_aclkr.gpio3[18], OUTPUT_PULLUP | MODE7 (DCAN0_LBK) */ /* enable loopback by default */ + 0x1a4 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* mcasp0_fsr.gpio3[19], OUTPUT_PULLDOWN | MODE7 (RS485_DE) */ + 0x1a8 PIN_OUTPUT_PULLUP MUX_MODE7 /* mcasp0_axr1.gpio3[20], OUTPUT_PULLUP | MODE7 (1WIRE_SLEEP) */ + 0x1ac PIN_INPUT_PULLDOWN MUX_MODE7 /* mcasp0_ahclkx.gpio3[21], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO2) */ >; }; }; diff --git a/arch/arm/dts/am335x-baltos-minimal.dts b/arch/arm/dts/am335x-baltos-minimal.dts index 137c177b2f..dff901f050 100644 --- a/arch/arm/dts/am335x-baltos-minimal.dts +++ b/arch/arm/dts/am335x-baltos-minimal.dts @@ -22,6 +22,11 @@ chosen { stdout-path = &uart0; + + environment-nand { + compatible = "barebox,environment"; + device-path = &environment_nand; + }; }; cpus { @@ -42,25 +47,25 @@ &am33xx_pinmux { mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */ - 0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */ - 0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */ - 0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */ - 0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */ - 0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */ + 0xf0 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat3.mmc0_dat3 */ + 0xf4 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat2.mmc0_dat2 */ + 0xf8 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat1.mmc0_dat1 */ + 0xfc (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat0.mmc0_dat0 */ + 0x100 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_clk.mmc0_clk */ + 0x104 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_cmd.mmc0_cmd */ >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < - 0x158 0x2a /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */ - 0x15c 0x2a /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */ + 0x158 0x2a 0 /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */ + 0x15c 0x2a 0 /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */ >; }; tps65910_pins: pinmux_tps65910_pins { pinctrl-single,pins = < - 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */ + 0x078 PIN_INPUT_PULLUP MUX_MODE7 /* gpmc_ben1.gpio1[28] */ >; }; @@ -72,99 +77,99 @@ uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + 0x170 PIN_INPUT_PULLUP MUX_MODE0 /* uart0_rxd.uart0_rxd */ + 0x174 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* uart0_txd.uart0_txd */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ + 0x10c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_crs.rmii1_crs_dv */ + 0x114 PIN_OUTPUT_PULLDOWN MUX_MODE1 /* mii1_tx_en.rmii1_txen */ + 0x124 PIN_OUTPUT_PULLDOWN MUX_MODE1 /* mii1_txd1.rmii1_txd1 */ + 0x128 PIN_OUTPUT_PULLDOWN MUX_MODE1 /* mii1_txd0.rmii1_txd0 */ + 0x13c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd1.rmii1_rxd1 */ + 0x140 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd0.rmii1_rxd0 */ + 0x144 PIN_INPUT_PULLDOWN MUX_MODE0 /* rmii1_ref_clk.rmii1_refclk */ /* Slave 2 */ - 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + 0x40 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* gpmc_a0.rgmii2_tctl */ + 0x44 PIN_INPUT_PULLDOWN MUX_MODE2 /* gpmc_a1.rgmii2_rctl */ + 0x48 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* gpmc_a2.rgmii2_td3 */ + 0x4c PIN_OUTPUT_PULLDOWN MUX_MODE2 /* gpmc_a3.rgmii2_td2 */ + 0x50 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* gpmc_a4.rgmii2_td1 */ + 0x54 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* gpmc_a5.rgmii2_td0 */ + 0x58 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* gpmc_a6.rgmii2_tclk */ + 0x5c PIN_INPUT_PULLDOWN MUX_MODE2 /* gpmc_a7.rgmii2_rclk */ + 0x60 PIN_INPUT_PULLDOWN MUX_MODE2 /* gpmc_a8.rgmii2_rd3 */ + 0x64 PIN_INPUT_PULLDOWN MUX_MODE2 /* gpmc_a9.rgmii2_rd2 */ + 0x68 PIN_INPUT_PULLDOWN MUX_MODE2 /* gpmc_a10.rgmii2_rd1 */ + 0x6c PIN_INPUT_PULLDOWN MUX_MODE2 /* gpmc_a11.rgmii2_rd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x10c PIN_INPUT_PULLDOWN MUX_MODE7 + 0x114 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x124 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x128 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x13c PIN_INPUT_PULLDOWN MUX_MODE7 + 0x140 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x144 PIN_INPUT_PULLDOWN MUX_MODE7 /* Slave 2 reset value*/ - 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x40 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x44 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x48 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x4c PIN_INPUT_PULLDOWN MUX_MODE7 + 0x50 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x54 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x58 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x5c PIN_INPUT_PULLDOWN MUX_MODE7 + 0x60 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x64 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x68 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x6c PIN_INPUT_PULLDOWN MUX_MODE7 >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST) MUX_MODE0 /* mdio_data.mdio_data */ + 0x14c PIN_OUTPUT_PULLUP MUX_MODE0 /* mdio_clk.mdio_clk */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x148 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x14c PIN_INPUT_PULLDOWN MUX_MODE7 >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < - 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + 0x0 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad0.gpmc_ad0 */ + 0x4 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad1.gpmc_ad1 */ + 0x8 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad2.gpmc_ad2 */ + 0xc PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad3.gpmc_ad3 */ + 0x10 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad4.gpmc_ad4 */ + 0x14 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad5.gpmc_ad5 */ + 0x18 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad6.gpmc_ad6 */ + 0x1c PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad7.gpmc_ad7 */ + 0x70 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_wait0.gpmc_wait0 */ + 0x74 PIN_INPUT_PULLUP MUX_MODE7 /* gpmc_wpn.gpio0_30 */ + 0x7c PIN_OUTPUT MUX_MODE0 /* gpmc_csn0.gpmc_csn0 */ + 0x90 PIN_OUTPUT MUX_MODE0 /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 PIN_OUTPUT MUX_MODE0 /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 PIN_OUTPUT MUX_MODE0 /* gpmc_wen.gpmc_wen */ + 0x9c PIN_OUTPUT MUX_MODE0 /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; }; @@ -179,7 +184,7 @@ ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ status = "okay"; - nand@0,0 { + nand: nand@0,0 { reg = <0 0 0>; /* CS0, offset 0 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; @@ -226,8 +231,8 @@ label = "SPL.backup2"; reg = <0x40000 0x20000>; }; - boot@60000 { - label = "SPL.backup3"; + environment_nand: boot@60000 { + label = "bareboxenv"; reg = <0x60000 0x20000>; }; boot@80000 { diff --git a/arch/arm/dts/am335x-bone-common-strip.dtsi b/arch/arm/dts/am335x-bone-common-strip.dtsi index e03ae2a8d3..5be246bd6f 100644 --- a/arch/arm/dts/am335x-bone-common-strip.dtsi +++ b/arch/arm/dts/am335x-bone-common-strip.dtsi @@ -66,105 +66,105 @@ user_leds_s0: user_leds_s0 { pinctrl-single,pins = < - 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ - 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + 0x54 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a5.gpio1_21 */ + 0x58 PIN_OUTPUT_PULLUP MUX_MODE7 /* gpmc_a6.gpio1_22 */ + 0x5c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a7.gpio1_23 */ + 0x60 PIN_OUTPUT_PULLUP MUX_MODE7 /* gpmc_a8.gpio1_24 */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + 0x188 PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_sda.i2c0_sda */ + 0x18c PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_scl.i2c0_scl */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + 0x170 PIN_INPUT_PULLUP MUX_MODE0 /* uart0_rxd.uart0_rxd */ + 0x174 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* uart0_txd.uart0_txd */ >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < - 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + 0x1b4 PIN_OUTPUT_PULLDOWN MUX_MODE3 /* xdma_event_intr1.clkout2 */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ - 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ - 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ - 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ - 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ - 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ - 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ - 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ - 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ - 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + 0x110 PIN_INPUT_PULLUP MUX_MODE0 /* mii1_rxerr.mii1_rxerr */ + 0x114 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* mii1_txen.mii1_txen */ + 0x118 PIN_INPUT_PULLUP MUX_MODE0 /* mii1_rxdv.mii1_rxdv */ + 0x11c PIN_OUTPUT_PULLDOWN MUX_MODE0 /* mii1_txd3.mii1_txd3 */ + 0x120 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* mii1_txd2.mii1_txd2 */ + 0x124 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* mii1_txd1.mii1_txd1 */ + 0x128 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* mii1_txd0.mii1_txd0 */ + 0x12c PIN_INPUT_PULLUP MUX_MODE0 /* mii1_txclk.mii1_txclk */ + 0x130 PIN_INPUT_PULLUP MUX_MODE0 /* mii1_rxclk.mii1_rxclk */ + 0x134 PIN_INPUT_PULLUP MUX_MODE0 /* mii1_rxd3.mii1_rxd3 */ + 0x138 PIN_INPUT_PULLUP MUX_MODE0 /* mii1_rxd2.mii1_rxd2 */ + 0x13c PIN_INPUT_PULLUP MUX_MODE0 /* mii1_rxd1.mii1_rxd1 */ + 0x140 PIN_INPUT_PULLUP MUX_MODE0 /* mii1_rxd0.mii1_rxd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x110 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x114 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x118 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x11c PIN_INPUT_PULLDOWN MUX_MODE7 + 0x120 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x124 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x128 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x12c PIN_INPUT_PULLDOWN MUX_MODE7 + 0x130 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x134 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x138 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x13c PIN_INPUT_PULLDOWN MUX_MODE7 + 0x140 PIN_INPUT_PULLDOWN MUX_MODE7 >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST) MUX_MODE0 /* mdio_data.mdio_data */ + 0x14c PIN_OUTPUT_PULLUP MUX_MODE0 /* mdio_clk.mdio_clk */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x148 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x14c PIN_INPUT_PULLDOWN MUX_MODE7 >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ + 0x160 PIN_INPUT MUX_MODE7 /* GPIO0_6 */ >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < - 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + 0x80 PIN_INPUT_PULLUP MUX_MODE2 /* gpmc_csn1.mmc1_clk */ + 0x84 PIN_INPUT_PULLUP MUX_MODE2 /* gpmc_csn2.mmc1_cmd */ + 0x00 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad0.mmc1_dat0 */ + 0x04 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad1.mmc1_dat1 */ + 0x08 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad2.mmc1_dat2 */ + 0x0c PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad3.mmc1_dat3 */ + 0x10 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad4.mmc1_dat4 */ + 0x14 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad5.mmc1_dat5 */ + 0x18 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad6.mmc1_dat6 */ + 0x1c PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad7.mmc1_dat7 */ >; }; }; diff --git a/arch/arm/dts/am335x-bone.dts b/arch/arm/dts/am335x-bone.dts index a2e62a3b1c..df044a5738 100644 --- a/arch/arm/dts/am335x-bone.dts +++ b/arch/arm/dts/am335x-bone.dts @@ -13,11 +13,10 @@ / { model = "TI AM335x BeagleBone"; compatible = "ti,am335x-bone", "ti,am33xx"; +}; - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; +&{/memory@80000000} { + reg = <0x80000000 0x10000000>; /* 256 MB */ }; &ldo3_reg { diff --git a/arch/arm/dts/am335x-boneblack.dts b/arch/arm/dts/am335x-boneblack.dts index f79a6bc8a4..3c286c71bf 100644 --- a/arch/arm/dts/am335x-boneblack.dts +++ b/arch/arm/dts/am335x-boneblack.dts @@ -13,11 +13,10 @@ / { model = "TI AM335x BeagleBone black"; compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; +&{/memory@80000000} { + reg = <0x80000000 0x20000000>; /* 512 MB */ }; &ldo3_reg { @@ -42,32 +41,32 @@ &am33xx_pinmux { nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { pinctrl-single,pins = < - 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ - 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ - 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ - 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ - 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + 0x1b0 0x03 0 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ + 0xa0 0x08 0 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xa4 0x08 0 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xa8 0x08 0 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xac 0x08 0 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xb0 0x08 0 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xb4 0x08 0 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xb8 0x08 0 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xbc 0x08 0 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xc0 0x08 0 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xc4 0x08 0 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xc8 0x08 0 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xcc 0x08 0 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xd0 0x08 0 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xd4 0x08 0 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xd8 0x08 0 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xdc 0x08 0 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xe0 0x00 0 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + 0xe4 0x00 0 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + 0xe8 0x00 0 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + 0xec 0x00 0 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ >; }; nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { pinctrl-single,pins = < - 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ + 0x1b0 0x03 0 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ >; }; }; @@ -86,3 +85,13 @@ status = "okay"; }; }; + +&tscadc { + status = "okay"; + adc { + /* Ch 0-6 are on connector P9. Ch 7 measures the 3.3V rail + * divided by 2 (e.g., it should read 1650). + */ + ti,adc-channels = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>; + }; +}; diff --git a/arch/arm/dts/am335x-phytec-phycard-som.dtsi b/arch/arm/dts/am335x-phytec-phycard-som.dtsi index 1d45d60dc0..e459824a77 100644 --- a/arch/arm/dts/am335x-phytec-phycard-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phycard-som.dtsi @@ -14,73 +14,73 @@ i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + 0x188 PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_sda.i2c0_sda */ + 0x18c PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_scl.i2c0_scl */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + 0x170 PIN_INPUT_PULLUP MUX_MODE0 /* uart0_rxd.uart0_rxd */ + 0x174 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* uart0_txd.uart0_txd */ >; }; uart3_pins: pinmux_uart3 { pinctrl-single,pins = < - 0x134 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd3.uart3_rxd */ - 0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd2.uart3_txd */ + 0x134 PIN_INPUT_PULLUP MUX_MODE1 /* mii1_rxd3.uart3_rxd */ + 0x138 PIN_OUTPUT_PULLDOWN MUX_MODE1 /* mii1_rxd2.uart3_txd */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */ - 0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */ - 0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */ - 0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */ - 0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */ - 0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */ + 0xf0 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat3.mmc0_dat3 */ + 0xf4 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat2.mmc0_dat2 */ + 0xf8 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat1.mmc0_dat1 */ + 0xfc (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat0.mmc0_dat0 */ + 0x100 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_clk.mmc0_clk */ + 0x104 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_cmd.mmc0_cmd */ >; }; emac_rmii1_pins: pinmux_emac_rmii1_pins { pinctrl-single,pins = < - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */ - 0x124 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - 0x128 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ + 0x10c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_crs.rmii1_crs_dv */ + 0x110 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxerr.rmii1_rxerr */ + 0x114 PIN_OUTPUT MUX_MODE1 /* mii1_txen.rmii1_txen */ + 0x124 PIN_OUTPUT MUX_MODE1 /* mii1_txd1.rmii1_txd1 */ + 0x128 PIN_OUTPUT MUX_MODE1 /* mii1_txd0.rmii1_txd0 */ + 0x13c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd1.rmii1_rxd1 */ + 0x140 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd0.rmii1_rxd0 */ + 0x144 PIN_INPUT_PULLDOWN MUX_MODE0 /* rmii1_refclk.rmii1_refclk */ >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < - 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + 0x0 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad0.gpmc_ad0 */ + 0x4 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad1.gpmc_ad1 */ + 0x8 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad2.gpmc_ad2 */ + 0xc PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad3.gpmc_ad3 */ + 0x10 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad4.gpmc_ad4 */ + 0x14 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad5.gpmc_ad5 */ + 0x18 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad6.gpmc_ad6 */ + 0x1c PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad7.gpmc_ad7 */ + 0x70 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_wait0.gpmc_wait0 */ + 0x7c PIN_OUTPUT MUX_MODE0 /* gpmc_csn0.gpmc_csn0 */ + 0x90 PIN_OUTPUT MUX_MODE0 /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 PIN_OUTPUT MUX_MODE0 /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 PIN_OUTPUT MUX_MODE0 /* gpmc_wen.gpmc_wen */ + 0x9c PIN_OUTPUT MUX_MODE0 /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST) MUX_MODE0 /* mdio_data.mdio_data */ + 0x14c PIN_OUTPUT_PULLUP MUX_MODE0 /* mdio_clk.mdio_clk */ >; }; }; diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dtsi b/arch/arm/dts/am335x-phytec-phycore-som.dtsi index ae3f70acdd..4b2ff9b2ea 100644 --- a/arch/arm/dts/am335x-phytec-phycore-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phycore-som.dtsi @@ -19,111 +19,111 @@ &am33xx_pinmux { usb_pins: pinmux_usb_pins { pinctrl-single,pins = < - 0x21c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ - 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ + 0x21c PIN_OUTPUT_PULLDOWN MUX_MODE0 /* usb0_drvvbus.usb0_drvvbus */ + 0x234 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* usb1_drvvbus.usb1_drvvbus */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + 0x188 PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_sda.i2c0_sda */ + 0x18c PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_scl.i2c0_scl */ >; }; spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < - 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */ - 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */ - 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ - 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + 0x150 PIN_INPUT_PULLDOWN MUX_MODE0 /* spi0_clk.spi0_clk */ + 0x154 PIN_INPUT_PULLDOWN MUX_MODE0 /* spi0_d0.spi0_d0 */ + 0x158 PIN_INPUT_PULLUP MUX_MODE0 /* spi0_d1.spi0_d1 */ + 0x15c PIN_INPUT_PULLUP MUX_MODE0 /* spi0_cs0.spi0_cs0 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + 0x170 PIN_INPUT_PULLUP MUX_MODE0 /* uart0_rxd.uart0_rxd */ + 0x174 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* uart0_txd.uart0_txd */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */ - 0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */ - 0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */ - 0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */ - 0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */ - 0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */ + 0xf0 MUX_MODE0 (INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */ + 0xf4 MUX_MODE0 (INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */ + 0xf8 MUX_MODE0 (INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */ + 0xfc MUX_MODE0 (INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */ + 0x100 MUX_MODE0 (INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */ + 0x104 MUX_MODE0 (INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */ >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < - 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + 0x80 PIN_INPUT_PULLUP MUX_MODE2 /* gpmc_csn1.mmc1_clk */ + 0x84 PIN_INPUT_PULLUP MUX_MODE2 /* gpmc_csn2.mmc1_cmd */ + 0x00 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad0.mmc1_dat0 */ + 0x04 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad1.mmc1_dat1 */ + 0x08 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad2.mmc1_dat2 */ + 0x0c PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad3.mmc1_dat3 */ + 0x10 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad4.mmc1_dat4 */ + 0x14 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad5.mmc1_dat5 */ + 0x18 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad6.mmc1_dat6 */ + 0x1c PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad7.mmc1_dat7 */ >; }; emac_rmii1_pins: pinmux_emac_rmii1_pins { pinctrl-single,pins = < - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */ - 0x124 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - 0x128 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ + 0x10c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_crs.rmii1_crs_dv */ + 0x110 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxerr.rmii1_rxerr */ + 0x114 PIN_OUTPUT MUX_MODE1 /* mii1_txen.rmii1_txen */ + 0x124 PIN_OUTPUT MUX_MODE1 /* mii1_txd1.rmii1_txd1 */ + 0x128 PIN_OUTPUT MUX_MODE1 /* mii1_txd0.rmii1_txd0 */ + 0x13c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd1.rmii1_rxd1 */ + 0x140 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd0.rmii1_rxd0 */ + 0x144 PIN_INPUT_PULLDOWN MUX_MODE0 /* rmii1_refclk.rmii1_refclk */ >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < - 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + 0x0 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad0.gpmc_ad0 */ + 0x4 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad1.gpmc_ad1 */ + 0x8 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad2.gpmc_ad2 */ + 0xc PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad3.gpmc_ad3 */ + 0x10 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad4.gpmc_ad4 */ + 0x14 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad5.gpmc_ad5 */ + 0x18 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad6.gpmc_ad6 */ + 0x1c PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad7.gpmc_ad7 */ + 0x70 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_wait0.gpmc_wait0 */ + 0x7c PIN_OUTPUT MUX_MODE0 /* gpmc_csn0.gpmc_csn0 */ + 0x90 PIN_OUTPUT MUX_MODE0 /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 PIN_OUTPUT MUX_MODE0 /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 PIN_OUTPUT MUX_MODE0 /* gpmc_wen.gpmc_wen */ + 0x9c PIN_OUTPUT MUX_MODE0 /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST) MUX_MODE0 /* mdio_data.mdio_data */ + 0x14c PIN_OUTPUT_PULLUP MUX_MODE0 /* mdio_clk.mdio_clk */ >; }; pcm051_led_pins: pinmux_pcm051_led_pins { pinctrl-single,pins = < - 0x80 (MUX_MODE7) - 0x84 (MUX_MODE7) + 0x80 0 MUX_MODE7 + 0x84 0 MUX_MODE7 >; }; pcm051_user_pins: pinmux_pcm051_user_pins { pinctrl-single,pins = < - 0x1e4 (PULL_UP |INPUT_EN |MUX_MODE7) - 0x1e8 (PULL_UP |INPUT_EN |MUX_MODE7) + 0x1e4 (PULL_UP |INPUT_EN) MUX_MODE7 + 0x1e8 (PULL_UP |INPUT_EN) MUX_MODE7 >; }; }; diff --git a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi index 0325c81346..29776f4556 100644 --- a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi @@ -35,90 +35,90 @@ &am33xx_pinmux { i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl */ + 0x188 PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_sda */ + 0x18c PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_scl */ >; }; spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < - 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */ - 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */ - 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ - 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + 0x150 PIN_INPUT_PULLDOWN MUX_MODE0 /* spi0_clk.spi0_clk */ + 0x154 PIN_INPUT_PULLDOWN MUX_MODE0 /* spi0_d0.spi0_d0 */ + 0x158 PIN_INPUT_PULLUP MUX_MODE0 /* spi0_d1.spi0_d1 */ + 0x15c PIN_INPUT_PULLUP MUX_MODE0 /* spi0_cs0.spi0_cs0 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd */ + 0x170 PIN_INPUT_PULLUP MUX_MODE0 /* uart0_rxd */ + 0x174 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* uart0_txd */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0x0f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ - 0x0f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ - 0x0f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ - 0x0fc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ - 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ - 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ + 0x0f0 PIN_INPUT_PULLUP MUX_MODE0 /* mmc0_dat3 */ + 0x0f4 PIN_INPUT_PULLUP MUX_MODE0 /* mmc0_dat2 */ + 0x0f8 PIN_INPUT_PULLUP MUX_MODE0 /* mmc0_dat1 */ + 0x0fc PIN_INPUT_PULLUP MUX_MODE0 /* mmc0_dat0 */ + 0x100 PIN_INPUT_PULLUP MUX_MODE0 /* mmc0_clk */ + 0x104 PIN_INPUT_PULLUP MUX_MODE0 /* mmc0_cmd */ >; }; emac_rgmii1_pins: pinmux_emac_rgmii1_pins { pinctrl-single,pins = < - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_tx_en.rgmii1_tctl */ - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rx_dv.rgmii1_rctl */ - 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_tx_clk.rgmii1_tclk */ - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rx_clk.rgmii1_rclk */ - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + 0x114 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* mii1_tx_en.rgmii1_tctl */ + 0x118 PIN_INPUT_PULLDOWN MUX_MODE2 /* mii1_rx_dv.rgmii1_rctl */ + 0x11c PIN_OUTPUT_PULLDOWN MUX_MODE2 /* mii1_txd3.rgmii1_td3 */ + 0x120 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* mii1_txd2.rgmii1_td2 */ + 0x124 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* mii1_txd1.rgmii1_td1 */ + 0x128 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* mii1_txd0.rgmii1_td0 */ + 0x12c PIN_OUTPUT_PULLDOWN MUX_MODE2 /* mii1_tx_clk.rgmii1_tclk */ + 0x130 PIN_INPUT_PULLDOWN MUX_MODE2 /* mii1_rx_clk.rgmii1_rclk */ + 0x134 PIN_INPUT_PULLDOWN MUX_MODE2 /* mii1_rxd3.rgmii1_rd3 */ + 0x138 PIN_INPUT_PULLDOWN MUX_MODE2 /* mii1_rxd2.rgmii1_rd2 */ + 0x13c PIN_INPUT_PULLDOWN MUX_MODE2 /* mii1_rxd1.rgmii1_rd1 */ + 0x140 PIN_INPUT_PULLDOWN MUX_MODE2 /* mii1_rxd0.rgmii1_rd0 */ >; }; emac_rmii2_pins: pinmux_emac_rmii2_pins { pinctrl-single,pins = < - 0x040 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a0.rmii2_txen */ - 0x050 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ - 0x054 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ - 0x068 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ - 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ - 0x074 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wpn.rmii2_rxer */ - 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_col.rmii2_refclk */ + 0x040 PIN_OUTPUT_PULLDOWN MUX_MODE3 /* gpmc_a0.rmii2_txen */ + 0x050 PIN_OUTPUT_PULLDOWN MUX_MODE3 /* gpmc_a4.rmii2_txd1 */ + 0x054 PIN_OUTPUT_PULLDOWN MUX_MODE3 /* gpmc_a5.rmii2_txd0 */ + 0x068 PIN_INPUT_PULLDOWN MUX_MODE3 /* gpmc_a10.rmii2_rxd1 */ + 0x06c PIN_INPUT_PULLDOWN MUX_MODE3 /* gpmc_a11.rmii2_rxd0 */ + 0x074 PIN_INPUT_PULLUP MUX_MODE3 /* gpmc_wpn.rmii2_rxer */ + 0x108 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_col.rmii2_refclk */ >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST) MUX_MODE0 /* mdio_data */ + 0x14c PIN_OUTPUT_PULLUP MUX_MODE0 /* mdio_clk */ >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < - 0x000 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0 */ - 0x004 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1 */ - 0x008 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2 */ - 0x00c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3 */ - 0x010 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4 */ - 0x014 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5 */ - 0x018 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6 */ - 0x01c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7 */ - 0x070 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ - 0x07c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_csn0 */ - 0x090 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_advn_ale */ - 0x094 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_oen_ren */ - 0x098 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_wen */ - 0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_be0n_cle */ + 0x000 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad0 */ + 0x004 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad1 */ + 0x008 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad2 */ + 0x00c PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad3 */ + 0x010 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad4 */ + 0x014 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad5 */ + 0x018 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad6 */ + 0x01c PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad7 */ + 0x070 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_wait0 */ + 0x07c PIN_OUTPUT_PULLDOWN MUX_MODE0 /* gpmc_csn0 */ + 0x090 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* gpmc_advn_ale */ + 0x094 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* gpmc_oen_ren */ + 0x098 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* gpmc_wen */ + 0x09c PIN_OUTPUT_PULLDOWN MUX_MODE0 /* gpmc_be0n_cle */ >; }; }; diff --git a/arch/arm/dts/am35xx-pfc-750_820x.dts b/arch/arm/dts/am35xx-pfc-750_820x.dts index 707778dfac..55c883944b 100644 --- a/arch/arm/dts/am35xx-pfc-750_820x.dts +++ b/arch/arm/dts/am35xx-pfc-750_820x.dts @@ -20,7 +20,7 @@ stdout-path = &uart3; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/dts/armada-370-mirabox-bb.dts b/arch/arm/dts/armada-370-mirabox-bb.dts index 315678151a..99263d4854 100644 --- a/arch/arm/dts/armada-370-mirabox-bb.dts +++ b/arch/arm/dts/armada-370-mirabox-bb.dts @@ -9,14 +9,8 @@ chosen { stdout-path = "/soc/internal-regs/serial@12000"; }; +}; - soc { - internal-regs { - gpio_leds { - green_pwr_led { - barebox,default-trigger = "heartbeat"; - }; - }; - }; - }; +&{/soc/internal-regs/gpio_leds/green_pwr_led} { + barebox,default-trigger = "heartbeat"; }; diff --git a/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts b/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts index 5f1a607381..b43bac37dd 100644 --- a/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts +++ b/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts @@ -5,10 +5,6 @@ #include "arm/armada-xp-lenovo-ix4-300d.dts" -/ { - gpio-leds { - power-led { - linux,default-trigger = "heartbeat"; - }; - }; +&{/gpio-leds/power-led} { + linux,default-trigger = "heartbeat"; }; diff --git a/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts b/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts index e88f1dc781..e57cd8f0ce 100644 --- a/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts +++ b/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts @@ -9,14 +9,4 @@ chosen { stdout-path = "/soc/internal-regs/serial@12000"; }; - - soc { - internal-regs { - gpio_leds { - red_led { - barebox,default-trigger = "heartbeat"; - }; - }; - }; - }; }; diff --git a/arch/arm/dts/at91-microchip-ksz9477-evb.dts b/arch/arm/dts/at91-microchip-ksz9477-evb.dts index 075cdcd088..3eb2017942 100644 --- a/arch/arm/dts/at91-microchip-ksz9477-evb.dts +++ b/arch/arm/dts/at91-microchip-ksz9477-evb.dts @@ -27,10 +27,10 @@ file-path = "barebox.env"; }; }; +}; - memory { - reg = <0x20000000 0x10000000>; - }; +&{/memory@20000000} { + reg = <0x20000000 0x10000000>; }; &pinctrl { diff --git a/arch/arm/dts/at91-sama5d27_giantboard.dts b/arch/arm/dts/at91-sama5d27_giantboard.dts index 7e48fa18ae..2ba3ff2171 100644 --- a/arch/arm/dts/at91-sama5d27_giantboard.dts +++ b/arch/arm/dts/at91-sama5d27_giantboard.dts @@ -25,6 +25,12 @@ chosen { stdout-path = &uart1; + + environment { + compatible = "barebox,environment"; + device-path = &sdmmc1; + file-path = "barebox.env"; + }; }; leds { @@ -38,10 +44,6 @@ linux,default-trigger = "mmc0"; }; }; - - memory { - reg = <0x20000000 0x8000000>; - }; }; &slow_xtal { diff --git a/arch/arm/dts/at91-sama5d27_som1_ek.dts b/arch/arm/dts/at91-sama5d27_som1_ek.dts index cd038dc7c1..97a326dd2b 100644 --- a/arch/arm/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/dts/at91-sama5d27_som1_ek.dts @@ -8,30 +8,51 @@ / { chosen { - environment { + environment-qspi { compatible = "barebox,environment"; device-path = &barebox_env; + status = "disabled"; }; - }; - memory { - reg = <0x20000000 0x8000000>; + environment-sd { + compatible = "barebox,environment"; + device-path = &sdmmc0; + file-path = "barebox.env"; + status = "disabled"; + }; + + environment-microsd { + compatible = "barebox,environment"; + device-path = &sdmmc1; + file-path = "barebox.env"; + status = "disabled"; + }; }; }; &qspi1 { + /delete-node/ flash@0; + flash@0 { - #address-cells = <1>; - #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + m25p,fast-read; - partition@0 { - label = "barebox"; - reg = <0x0 0x80000>; - }; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + barebox@40000 { + label = "barebox"; + reg = <0x40000 0xc0000>; + }; - barebox_env: partition@80000 { - label = "barebox-environment"; - reg = <0x80000 0x80000>; + barebox_env: barebox-env@100000 { + label = "barebox-environment"; + reg = <0x100000 0x40000>; + }; }; }; }; diff --git a/arch/arm/dts/at91sam9263ek.dts b/arch/arm/dts/at91sam9263ek.dts index 7fe283ced7..29a615f482 100644 --- a/arch/arm/dts/at91sam9263ek.dts +++ b/arch/arm/dts/at91sam9263ek.dts @@ -3,37 +3,65 @@ chosen { environment { compatible = "barebox,environment"; - device-path = &nand_controller, "partname:bareboxenv"; + device-path = &environment_nand; }; }; - ahb { - apb { - mmc1: mmc@fff84000 { - pinctrl-0 = < - &pinctrl_board_mmc1 - &pinctrl_mmc1_clk - &pinctrl_mmc1_slot0_cmd_dat0 - &pinctrl_mmc1_slot0_dat1_3>; - cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>; - wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>; - }; +}; + +&nand_controller { + nand@3 { + /delete-node/ partitions; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x100000>; + }; + + environment_nand: bareboxenv@120000 { + label = "barebox-environment"; + reg = <0x120000 0x20000>; + }; + + rootfs@140000 { + label = "root"; + reg = <0x140000 0x0>; }; }; }; +}; - - pinctrl@fffff200 { - pinctrl_board_mmc1: mmc1-board { - atmel,pins = - <AT91_PIOE 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PE18 gpio CD pin pull up and deglitch */ - AT91_PIOE 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PE19 gpio WP pin pull up */ +&{/ahb/apb/mmc@fff84000} { + pinctrl-0 = < + &pinctrl_board_mmc1 + &pinctrl_mmc1_clk + &pinctrl_mmc1_slot0_cmd_dat0 + &pinctrl_mmc1_slot0_dat1_3>; + cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>; + wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>; }; +}; + +&{/ahb/apb/pinctrl@fffff200} { + pinctrl_board_mmc1: mmc1-board { + atmel,pins = + <AT91_PIOE 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PE18 gpio CD pin pull up and deglitch */ + AT91_PIOE 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PE19 gpio WP pin pull up */ }; }; diff --git a/arch/arm/dts/at91sam9x5ek.dts b/arch/arm/dts/at91sam9x5ek.dts index bc2a279709..3a6976a7d9 100644 --- a/arch/arm/dts/at91sam9x5ek.dts +++ b/arch/arm/dts/at91sam9x5ek.dts @@ -14,25 +14,23 @@ mmc0 = &mmc0; mmc1 = &mmc1; }; +}; - i2c-gpio-0 { - status = "okay"; - }; +&{/i2c-gpio-0} { + status = "okay"; +}; - leds { - /* - * PB18 has a resource conflict since it is both used - * as a heartbeat LED and 1-wire bus in the kernel - * device tree. Because 1-wire EEPROMs contains - * importatnt revision information we move heartbeat - * to PD21 and remove the original pb18 node - */ - /delete-node/ pb18; - - pd21 { - linux,default-trigger = "heartbeat"; - }; - }; +/* + * PB18 has a resource conflict since it is both used + * as a heartbeat LED and 1-wire bus in the kernel + * device tree. Because 1-wire EEPROMs contains + * importatnt revision information we move heartbeat + * to PD21 and remove the original pb18 node + */ +/delete-node/ &{/leds/pb18}; + +&{/leds/pd21} { + linux,default-trigger = "heartbeat"; }; &spi0 { @@ -56,6 +54,38 @@ phy-mode = "rmii"; }; +&nand_controller { + nand@3 { + /delete-node/ partitions; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x100000>; + }; + + environment_nand: bareboxenv@120000 { + label = "barebox-environment"; + reg = <0x120000 0x20000>; + }; + + rootfs@140000 { + label = "root"; + reg = <0x140000 0x0>; + }; + }; + }; +}; + &{/ahb/apb/pinctrl@fffff400} { spi0 { pinctrl_board_spi: spi-board { diff --git a/arch/arm/dts/bcm2835-rpi.dts b/arch/arm/dts/bcm2835-rpi.dts index c23e7c7c14..4f22750801 100644 --- a/arch/arm/dts/bcm2835-rpi.dts +++ b/arch/arm/dts/bcm2835-rpi.dts @@ -4,10 +4,10 @@ chosen { stdout-path = &uart0; }; +}; - memory { - reg = <0x0 0x0>; - }; +&{/memory@0} { + reg = <0x0 0x0>; }; &sdhci { diff --git a/arch/arm/dts/bcm2836-rpi-2.dts b/arch/arm/dts/bcm2836-rpi-2.dts index 42b6abb180..c9c3892d6a 100644 --- a/arch/arm/dts/bcm2836-rpi-2.dts +++ b/arch/arm/dts/bcm2836-rpi-2.dts @@ -4,8 +4,8 @@ chosen { stdout-path = &uart0; }; +}; - memory { - reg = <0x0 0x0>; - }; +&{/memory@0} { + reg = <0x0 0x0>; }; diff --git a/arch/arm/dts/bcm2837-rpi-3.dts b/arch/arm/dts/bcm2837-rpi-3.dts index 420525b9e8..d66beddb22 100644 --- a/arch/arm/dts/bcm2837-rpi-3.dts +++ b/arch/arm/dts/bcm2837-rpi-3.dts @@ -4,10 +4,10 @@ chosen { stdout-path = &uart1; }; +}; - memory { - reg = <0x0 0x0>; - }; +&{/memory@0} { + reg = <0x0 0x0>; }; &sdhci { diff --git a/arch/arm/dts/bcm2837-rpi-cm3.dts b/arch/arm/dts/bcm2837-rpi-cm3.dts index 01c1f9a677..85a6ac4661 100644 --- a/arch/arm/dts/bcm2837-rpi-cm3.dts +++ b/arch/arm/dts/bcm2837-rpi-cm3.dts @@ -4,8 +4,8 @@ chosen { stdout-path = &uart0; }; +}; - memory { - reg = <0x0 0x0>; - }; +&{/memory@0} { + reg = <0x0 0x0>; }; diff --git a/arch/arm/dts/dove-cubox-bb.dts b/arch/arm/dts/dove-cubox-bb.dts index 83e1d5df50..06966d9c2e 100644 --- a/arch/arm/dts/dove-cubox-bb.dts +++ b/arch/arm/dts/dove-cubox-bb.dts @@ -9,10 +9,8 @@ chosen { stdout-path = &uart0; }; +}; - leds { - power { - barebox,default-trigger = "heartbeat"; - }; - }; +&{/leds/power} { + barebox,default-trigger = "heartbeat"; }; diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts index 23e43701f3..d842387fa0 100644 --- a/arch/arm/dts/fsl-ls1046a-rdb.dts +++ b/arch/arm/dts/fsl-ls1046a-rdb.dts @@ -7,6 +7,7 @@ / { aliases { eeprom = &eeprom; + mmc0 = &esdhc; }; chosen { @@ -17,10 +18,6 @@ device-path = &environment_sd; }; }; - - aliases { - mmc0 = &esdhc; - }; }; &esdhc { @@ -61,72 +58,52 @@ /delete-node/ &non_existent_eeprom; -&fman0 { - ethernet@e0000 { - status = "disabled"; - }; - - ethernet@e2000 { - status = "disabled"; - }; - - ethernet@e4000 { - phy-mode = "rgmii-id"; - }; - - ethernet@e6000 { - phy-mode = "rgmii-id"; - }; - - ethernet@e8000 { - }; - - ethernet@ea000 { - }; - - ethernet@f0000 { - }; +&enet0 { + status = "disabled"; +}; - ethernet@f2000 { - }; +&enet1 { + status = "disabled"; +}; - mdio@fc000 { - }; +&enet2 { + phy-mode = "rgmii-id"; +}; - mdio@fd000 { - }; +&enet3 { + phy-mode = "rgmii-id"; +}; - mdio@e1000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@e1000} { + status = "disabled"; +}; - mdio@e3000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@e3000} { + status = "disabled"; +}; - mdio@e5000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@e5000} { + status = "disabled"; +}; - mdio@e7000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@e7000} { + status = "disabled"; +}; - mdio@e9000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@e9000} { + status = "disabled"; +}; - mdio@eb000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@eb000} { + status = "disabled"; +}; - mdio@f1000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@f1000} { + status = "disabled"; +}; - mdio@f3000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@f3000} { + status = "disabled"; }; &usb0 { @@ -143,16 +120,14 @@ dr_mode = "host"; }; -&soc { - pcie1: pcie@3400000 { - status = "okay"; - }; +&{/soc/pcie@3400000} { + status = "okay"; +}; - pcie2: pcie@3500000 { - status = "okay"; - }; +&{/soc/pcie@3500000} { + status = "okay"; +}; - pcie3: pcie@3600000 { - status = "okay"; - }; +&{/soc/pcie@3600000} { + status = "okay"; }; diff --git a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts index 7b17fe2210..7f9a764a82 100644 --- a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts +++ b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts @@ -225,121 +225,120 @@ &fman0 { status = "okay"; +}; - ethernet@e0000 { /* EMAC.1 */ - phy-connection-type = "sgmii"; +&enet0 { /* EMAC.1 */ + phy-connection-type = "sgmii"; +}; - }; +&enet1 { /* EMAC.2 */ + phy-connection-type = "sgmii"; +}; - ethernet@e2000 { /* EMAC.2 */ - phy-connection-type = "sgmii"; - }; +&enet2 { /* EMAC.3 */ + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii"; + phy-mode = "rgmii-id"; +}; - ethernet@e4000 { /* EMAC.3 */ - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii"; - phy-mode = "rgmii-id"; - }; +&enet3 { /* EMAC.4 */ + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii"; + phy-mode = "rgmii-id"; +}; - ethernet@e6000 { /* EMAC.4 */ - phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii"; - phy-mode = "rgmii-id"; - }; +&enet4 { /* EMAC.5 */ + phy-connection-type = "sgmii"; +}; - ethernet@e8000 { /* EMAC.5 */ - phy-connection-type = "sgmii"; - }; +&enet5 { /* EMAC.6 */ + phy-connection-type = "sgmii"; +}; - ethernet@ea000 { /* EMAC.6 */ - phy-connection-type = "sgmii"; - }; +&enet6 { /* EMAC.9 */ + phy-connection-type = "sgmii"; +}; - ethernet@f0000 { /* EMAC.9 */ - phy-connection-type = "sgmii"; - }; +&enet7 { /* EMAC.10 */ + phy-connection-type = "sgmii"; +}; - ethernet@f2000 { /* EMAC.10 */ - phy-connection-type = "sgmii"; - }; +&{/soc/fman@1a00000/mdio@e1000} { + status = "disabled"; +}; - mdio@e1000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@e3000} { + status = "disabled"; +}; - mdio@e3000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@e5000} { + status = "disabled"; +}; - mdio@e5000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@e7000} { + status = "disabled"; +}; - mdio@e7000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@e9000} { + status = "disabled"; +}; - mdio@e9000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@eb000} { + status = "disabled"; +}; - mdio@eb000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@f1000} { + status = "disabled"; +}; - mdio@f1000 { - status = "disabled"; - }; +&{/soc/fman@1a00000/mdio@f3000} { + status = "disabled"; +}; - mdio@f3000 { - status = "disabled"; +&mdio0 { + rgmii_phy1: ethernet-phy@0e { + reg = <0x0e>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; }; - mdio@fc000 { - rgmii_phy1: ethernet-phy@0e { - reg = <0x0e>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; - }; - - rgmii_phy2: ethernet-phy@0c { - reg = <0x0c>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; - }; - - qsgmii1_phy1: ethernet-phy@1c { - reg = <0x1c>; - }; + rgmii_phy2: ethernet-phy@0c { + reg = <0x0c>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + }; - qsgmii1_phy2: ethernet-phy@1d { - reg = <0x1d>; - }; + qsgmii1_phy1: ethernet-phy@1c { + reg = <0x1c>; + }; - qsgmii2_phy1: ethernet-phy@00 { - reg = <0x00>; - }; + qsgmii1_phy2: ethernet-phy@1d { + reg = <0x1d>; + }; - qsgmii2_phy2: ethernet-phy@01 { - reg = <0x01>; - }; + qsgmii2_phy1: ethernet-phy@00 { + reg = <0x00>; + }; - qsgmii2_phy3: ethernet-phy@02 { - reg = <0x02>; - }; + qsgmii2_phy2: ethernet-phy@01 { + reg = <0x01>; + }; - qsgmii2_phy4: ethernet-phy@03 { - reg = <0x03>; - }; + qsgmii2_phy3: ethernet-phy@02 { + reg = <0x02>; }; - mdio@fd000 { - status = "disabled"; + qsgmii2_phy4: ethernet-phy@03 { + reg = <0x03>; }; }; +&xmdio0 { + status = "disabled"; +}; + &qflash0 { partitions { #address-cells = <1>; diff --git a/arch/arm/dts/imx50.dtsi b/arch/arm/dts/imx50.dtsi index 68edd37b13..b5def2e4f6 100644 --- a/arch/arm/dts/imx50.dtsi +++ b/arch/arm/dts/imx50.dtsi @@ -1,22 +1,18 @@ #include <arm/imx50.dtsi> -/ { - soc { - aips@50000000 { /* AIPS1 */ - usbphy1: usbphy@1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; - clock-names = "main_clk"; - status = "okay"; - }; +&{/soc/bus@50000000} { /* AIPS1 */ + usbphy1: usbphy@1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; + clock-names = "main_clk"; + status = "okay"; + }; - usbmisc: usbmisc@53f80800 { - #index-cells = <1>; - compatible = "fsl,imx53-usbmisc"; - reg = <0x53f80800 0x200>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - }; - }; + usbmisc: usbmisc@53f80800 { + #index-cells = <1>; + compatible = "fsl,imx53-usbmisc"; + reg = <0x53f80800 0x200>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; }; }; diff --git a/arch/arm/dts/imx51-genesi-efika-sb.dts b/arch/arm/dts/imx51-genesi-efika-sb.dts index 23e6ea4165..7e3017f981 100644 --- a/arch/arm/dts/imx51-genesi-efika-sb.dts +++ b/arch/arm/dts/imx51-genesi-efika-sb.dts @@ -35,7 +35,8 @@ }; }; - memory { + memory@90000000 { + device_type = "memory"; reg = <0x90000000 0x20000000>; }; @@ -93,7 +94,7 @@ backlight: backlight { compatible = "pwm-backlight"; enable-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; - pwms = <&pwm1 0 78770>; + pwms = <&pwm1 0 78770 0>; brightness-levels = <0 1 2 4 8 16 32 64 128 255>; default-brightness-level = <9>; pinctrl-names = "default"; diff --git a/arch/arm/dts/imx53-guf-vincell-lt.dts b/arch/arm/dts/imx53-guf-vincell-lt.dts index 4c6205135a..d14c0dbf9c 100644 --- a/arch/arm/dts/imx53-guf-vincell-lt.dts +++ b/arch/arm/dts/imx53-guf-vincell-lt.dts @@ -30,12 +30,6 @@ }; }; - clocks { - ckih1 { - clock-frequency = <0>; - }; - }; - panel: panel { compatible = "giantplus,gpg482739qs5", "simple-panel"; power-supply = <®_panel>; @@ -73,7 +67,7 @@ backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm1 0 50000>; + pwms = <&pwm1 0 50000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; power-supply = <&ldo3>; @@ -119,6 +113,10 @@ }; }; +&{/clocks/ckih1} { + clock-frequency = <0>; +}; + &audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; diff --git a/arch/arm/dts/imx53-guf-vincell.dts b/arch/arm/dts/imx53-guf-vincell.dts index d34b59f4d3..a5f86ccf7e 100644 --- a/arch/arm/dts/imx53-guf-vincell.dts +++ b/arch/arm/dts/imx53-guf-vincell.dts @@ -25,12 +25,6 @@ stdout-path = &uart2; }; - clocks { - ckih1 { - clock-frequency = <0>; - }; - }; - panel: panel { compatible = "ampire,am800480r3tmqwa1h", "simple-panel"; enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; @@ -55,7 +49,7 @@ backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm2 0 50000>; + pwms = <&pwm2 0 50000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; @@ -74,6 +68,10 @@ }; }; +&{/clocks/ckih1} { + clock-frequency = <0>; +}; + &audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; diff --git a/arch/arm/dts/imx53-qsb-common.dtsi b/arch/arm/dts/imx53-qsb-common.dtsi index 24bbd6741a..5c692523c2 100644 --- a/arch/arm/dts/imx53-qsb-common.dtsi +++ b/arch/arm/dts/imx53-qsb-common.dtsi @@ -19,24 +19,6 @@ device-path = &bareboxenv; }; }; - - /* - * The buttons are marked as active high in the upstream dts. - * Remove these once fixed upstream. - */ - gpio-keys { - power { - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - volume-up { - gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - }; - - volume-down { - gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; - }; - }; }; &esdhc1 { diff --git a/arch/arm/dts/imx53-tqma53.dtsi b/arch/arm/dts/imx53-tqma53.dtsi index 860fb64df2..6efc0f1003 100644 --- a/arch/arm/dts/imx53-tqma53.dtsi +++ b/arch/arm/dts/imx53-tqma53.dtsi @@ -18,10 +18,10 @@ status = "disabled"; }; }; +}; - memory { - reg = <0x70000000 0x0>; /* Up to 1GiB */ - }; +&{/memory@70000000} { + reg = <0x70000000 0x0>; /* Up to 1GiB */ }; &esdhc3 { /* EMMC */ diff --git a/arch/arm/dts/imx6dl-alti6p.dts b/arch/arm/dts/imx6dl-alti6p.dts new file mode 100644 index 0000000000..8d53100bea --- /dev/null +++ b/arch/arm/dts/imx6dl-alti6p.dts @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-prti6q.dtsi" + +/ { + model = "Altesco I6P Board"; + compatible = "alt,alti6p", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c1>; + status = "okay"; +}; + +/* DDC */ +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c3 { + rtc: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>; + clock-names = "ipg", "ahb"; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f058 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + /* NOTE: DDC is done via I2C2, so DON'T configure DDC pins for HDMI! */ + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x4001f8b1 + MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x4001f8b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-eltec-hipercam.dts b/arch/arm/dts/imx6dl-eltec-hipercam.dts index 41af229835..ce2af4051c 100644 --- a/arch/arm/dts/imx6dl-eltec-hipercam.dts +++ b/arch/arm/dts/imx6dl-eltec-hipercam.dts @@ -7,7 +7,8 @@ model = "ELTEC HiPerCam"; compatible = "eltec,hipercam-rev01", "fsl,imx6dl"; - memory { + memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x10000000>; }; diff --git a/arch/arm/dts/imx6dl-lanmcu.dts b/arch/arm/dts/imx6dl-lanmcu.dts new file mode 100644 index 0000000000..d50e6afe7e --- /dev/null +++ b/arch/arm/dts/imx6dl-lanmcu.dts @@ -0,0 +1,464 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2019 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "LANMCU"; + compatible = "lan,lanmcu", "fsl,imx6dl"; + + chosen { + stdout-path = &uart4; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &usdhc3, "partname:barebox-environment"; + }; + }; + + memory { + reg = <0x10000000 0x10000000>; + }; + + reg_usb_otg_vbus: otg-vbus-regulator { + compatible = "regulator-fixed"; + regulator-name = "regulator-OTG-VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_npd>; + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; + + display: display0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_disp>; + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "bgr666"; + status = "okay"; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel { + compatible = "edt,etm0700g0bdh6"; + backlight = <&backlight_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + backlight_lcd: backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 5 7 9 12 15 20 27 35 47 62 81 107 142 188 248 + 328 433 573 757 1000>; + default-brightness-level = <20>; + status = "okay"; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + debug0 { + label = "debug0"; + gpios = <&gpio1 8 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + clk50m_phy: phy_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + prti6q { + pinctrl_hog: hoggrp { + fsl,pins = < + /* HW revision detect */ + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* REV_ID0 */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* REV_ID1 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* REV_ID2 */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 /* REV_ID3 */ + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 /* REV_ID4 */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_ipu1_disp: ipudisp1grp { + fsl,pins = < + /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */ + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_wlan_npd: wlan_npd { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x130b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x130b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 + >; + }; + + pinctrl_ts_edt: ts1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + >; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display_in>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clk50m_phy>; + clock-names = "ipg", "ahb", "ptp"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio5 23 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + rtc: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + touchscreen: edt_ft5406@38 { + compatible = "edt,edt-ft5406"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts_edt>; + reg = <0x38>; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + + touchscreen-fuzz-x = <0>; + touchscreen-fuzz-y = <0>; + + /* Touch screen calibration */ + threshold = <50>; + gain = <5>; + offset = <10>; + }; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc2_pwrseq>; + pm-ignore-notify; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + status = "okay"; + + partitions { + /* + * Map a partition at the last 64k of the area available for + * the second stage bootloader. + */ + compatible = "fixed-partitions"; + #size-cells = <1>; + #address-cells = <1>; + + partition@100000 { + label = "barebox-environment"; + reg = <0x100000 0x100000>; + }; + + partition@200000 { + label = "state"; + reg = <0x200000 0x100000>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6dl-mba6x.dts b/arch/arm/dts/imx6dl-mba6x.dts index cdb0334260..dddc3d384c 100644 --- a/arch/arm/dts/imx6dl-mba6x.dts +++ b/arch/arm/dts/imx6dl-mba6x.dts @@ -21,7 +21,8 @@ stdout-path = &uart2; }; - memory { + memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x20000000>; }; }; diff --git a/arch/arm/dts/imx6dl-plybas.dts b/arch/arm/dts/imx6dl-plybas.dts new file mode 100644 index 0000000000..de0ba05e13 --- /dev/null +++ b/arch/arm/dts/imx6dl-plybas.dts @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-vicut1.dtsi" + +/ { + model = "Plymovent BAS board"; + compatible = "ply,plybas", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x10000000>; + }; + + backlight_lcd { + status = "disabled"; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@20 { + label = "START"; + linux,code = <31>; + gpios = <&gpio5 8 1>; + }; + button@21 { + label = "CLEAN"; + linux,code = <46>; + gpios = <&gpio5 9 1>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + debug0 { + label = "debug0"; + gpios = <&gpio1 8 0>; + }; + + debug1 { + label = "debug1"; + gpios = <&gpio1 9 0>; + }; + + light_tower1 { + label = "light_tower1"; + gpios = <&gpio4 22 0>; + linux,default-trigger = "heartbeat"; + }; + + light_tower2 { + label = "light_tower2"; + gpios = <&gpio4 23 0>; + }; + + light_tower3 { + label = "light_tower3"; + gpios = <&gpio4 24 0>; + }; + + light_tower4 { + label = "light_tower4"; + gpios = <&gpio4 25 0>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>; + clock-names = "ipg", "ahb"; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 20>; + status = "okay"; +}; + +&iomuxc { + pinctrl_hog: hoggrp { + fsl,pins = < + /* CAN1_SR + CAN2_SR GPIO outputs */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070 + + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* YACO_nIRQ */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 /* YACO_BOOT0 */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* YACO_nRESET */ + + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x13070 /* BUZZER */ + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x13070 /* ANA_OUT_SD */ + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 /* ANA_OUT_ERR */ + + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x13070 /* RELAY1 */ + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x13070 /* RELAY2 */ + + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 /* IN1 */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 /* IN2 */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b0 /* IN3 */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b0 /* IN4 */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 /* IN5 */ + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 /* IN6 */ + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 /* IN7 */ + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 /* IN8 */ + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 /* IN9 */ + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 /* IN10 */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* IN11 */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 /* IN12 */ + + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1a0b0 /* HMI */ + + /* HW revision detect */ + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* REV_ID0 */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* REV_ID1 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* REV_ID2 */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 /* REV_ID3 */ + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 /* REV_ID4 */ + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* DEBUG0 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* DEBUG1 */ + + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x13070 /* LED1 (lighttower) */ + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x13070 /* LED2 (lighttower) */ + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x13070 /* LED3 (lighttower) */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x13070 /* LED4 (lighttower) */ + >; + }; + + /* RS485 UART */ + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x130b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-plym2m.dts b/arch/arm/dts/imx6dl-plym2m.dts new file mode 100644 index 0000000000..e944a14dce --- /dev/null +++ b/arch/arm/dts/imx6dl-plym2m.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-prti6q.dtsi" +#include "imx6qdl-prti6q-nor.dtsi" + +/ { + model = "Plymovent M2M board"; + compatible = "ply,plym2m", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x10000000>; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + debug0 { + label = "debug0"; + gpios = <&gpio1 8 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + clk50m_phy: phy_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clk50m_phy>; + clock-names = "ipg", "ahb", "ptp"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio5 23 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&iomuxc { + pinctrl_hog: hoggrp { + fsl,pins = < + /* CAN1_SR GPIO output */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CAN1_TERM */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 /* TSC_BUSY */ + + /* HW revision detect */ + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* REV_ID0 */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* REV_ID1 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* REV_ID2 */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 /* REV_ID3 */ + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 /* REV_ID4 */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_ipu1_disp: ipudisp1grp { + fsl,pins = < + /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */ + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_backlight_m2m: backlightm2mgrp { + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-prtmvt.dts b/arch/arm/dts/imx6dl-prtmvt.dts new file mode 100644 index 0000000000..05fce7178f --- /dev/null +++ b/arch/arm/dts/imx6dl-prtmvt.dts @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-vicut1.dtsi" + +/ { + model = "Protonic MVT board"; + compatible = "prt,prtmvt", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x20000000>; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + button@20 { + label = "GPIO Key F1"; + linux,code = <59>; + gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>; + }; + button@21 { + label = "GPIO Key F2"; + linux,code = <60>; + gpios = <&pca_gpio 1 GPIO_ACTIVE_LOW>; + }; + button@22 { + label = "GPIO Key F3"; + linux,code = <61>; + gpios = <&pca_gpio 2 GPIO_ACTIVE_LOW>; + }; + button@23 { + label = "GPIO Key F4"; + linux,code = <62>; + gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>; + }; + button@24 { + label = "GPIO Key F5"; + linux,code = <63>; + gpios = <&pca_gpio 4 GPIO_ACTIVE_LOW>; + }; + + // Center + button@25 { + label = "GPIO Key CYCLE"; + linux,code = <154>; + gpios = <&pca_gpio 5 GPIO_ACTIVE_LOW>; + }; + button@26 { + label = "GPIO Key ESC"; + linux,code = <1>; + gpios = <&pca_gpio 6 GPIO_ACTIVE_LOW>; + }; + button@27 { + label = "GPIO Key UP"; + linux,code = <103>; + gpios = <&pca_gpio 7 GPIO_ACTIVE_LOW>; + }; + button@28 { + label = "GPIO Key DOWN"; + linux,code = <108>; + gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>; + }; + button@29 { + label = "GPIO Key OK"; + linux,code = <0x160>; + gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>; + }; + + button@2a { + label = "GPIO Key F6"; + linux,code = <64>; + gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>; + }; + button@2b { + label = "GPIO Key F7"; + linux,code = <65>; + gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>; + }; + button@2c { + label = "GPIO Key F8"; + linux,code = <66>; + gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>; + }; + button@2d { + label = "GPIO Key F9"; + linux,code = <67>; + gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>; + }; + button@2e { + label = "GPIO Key F10"; + linux,code = <68>; + gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>; + clock-names = "ipg", "ahb"; + status = "okay"; +}; + +&pwm2 { + status = "disabled"; +}; + +&pcie { + status = "disabled"; +}; + +&i2c1 { + pca_gpio: gpio@74 { + #gpio-cells = <2>; + compatible = "nxp,pca9539"; + reg = <0x74>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9539>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + }; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_pca9539: pca9539 { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-prtrvt.dts b/arch/arm/dts/imx6dl-prtrvt.dts new file mode 100644 index 0000000000..c403ba3ea7 --- /dev/null +++ b/arch/arm/dts/imx6dl-prtrvt.dts @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-prti6q.dtsi" +#include "imx6qdl-prti6q-nor.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + model = "Protonic RVT board"; + compatible = "prt,prtrvt", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x10000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can1 { + pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + nfc@0 { + compatible = "ti,trf7970a"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + spi-max-frequency = <2000000>; + interrupts-extended = <&gpio5 14 IRQ_TYPE_LEVEL_LOW>; + ti,enable-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>, + <&gpio5 11 GPIO_ACTIVE_LOW>; + vin-supply = <®_3v3>; + vin-voltage-override = <3100000>; + autosuspend-delay = <30000>; + irq-status-read-quirk; + en2-rf-quirk; + t5t-rmb-extra-byte-quirk; + status = "okay"; + }; +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* nc */ + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* nc */ + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_l */ + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_h */ + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&pcie { + status = "okay"; +}; + +&usbh1 { + status = "disabled"; +}; + +&vpu { + status = "disabled"; +}; + +&iomuxc { + pinctrl_can1phy: can1phy { + fsl,pins = < + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + /* NFC_ASK_OOK */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x100b1 + /* NFC_PWR_EN */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x100b1 + /* NFC_EN2 */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x100b1 + /* NFC_EN */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + /* NFC_MOD */ + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 + /* NFC_IRQ */ + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-prtvt7.dts b/arch/arm/dts/imx6dl-prtvt7.dts new file mode 100644 index 0000000000..27daa3e15f --- /dev/null +++ b/arch/arm/dts/imx6dl-prtvt7.dts @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-prti6q.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + model = "Protonic VT7"; + compatible = "prt,prtvt7", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 0>; + brightness-levels = <0 20 81 248 1000>; + default-brightness-level = <20>; + num-interpolated-steps = <21>; + power-supply = <®_12v_bl>; + enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + }; + + display { + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_disp>; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + status = "okay"; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + keys { + compatible = "gpio-keys"; + autorepeat; + + esc { + label = "GPIO Key ESC"; + linux,code = <KEY_ESC>; + gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; + }; + + up { + label = "GPIO Key UP"; + linux,code = <KEY_UP>; + gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; + }; + + down { + label = "GPIO Key DOWN"; + linux,code = <KEY_DOWN>; + gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; + }; + + enter { + label = "GPIO Key Enter"; + linux,code = <KEY_ENTER>; + gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; + }; + + cycle { + label = "GPIO Key CYCLE"; + linux,code = <KEY_CYCLEWINDOWS>; + gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; + }; + + f1 { + label = "GPIO Key F1"; + linux,code = <KEY_F1>; + gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; + }; + + f2 { + label = "GPIO Key F2"; + linux,code = <KEY_F2>; + gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; + }; + + f3 { + label = "GPIO Key F3"; + linux,code = <KEY_F3>; + gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; + }; + + f4 { + label = "GPIO Key F4"; + linux,code = <KEY_F4>; + gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; + }; + + f5 { + label = "GPIO Key F5"; + linux,code = <KEY_F5>; + gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; + }; + + f6 { + label = "GPIO Key F6"; + linux,code = <KEY_F6>; + gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; + }; + + f7 { + label = "GPIO Key F7"; + linux,code = <KEY_F7>; + gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; + }; + + f8 { + label = "GPIO Key F8"; + linux,code = <KEY_F8>; + gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; + }; + + f9 { + label = "GPIO Key F9"; + linux,code = <KEY_F9>; + gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; + }; + + f10 { + label = "GPIO Key F10"; + linux,code = <KEY_F10>; + gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + panel { + compatible = "innolux,g070y2t0ec"; + backlight = <&backlight_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + reg_12v_bl: regulator-bl-12v { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_12v_bl>; + regulator-name = "12v-bl"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + bitclock-master; + frame-master; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + tsc@0 { + compatible = "ti,tsc2046"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + spi-max-frequency = <100000>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; + pendown-gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + vcc-supply = <®_3v3>; + + ti,vref-delay-usecs = /bits/ 16 <100>; + + ti,x-min = /bits/ 16 <0>; + ti,x-max = /bits/ 16 <8000>; + ti,y-min = /bits/ 16 <0>; + ti,y-max = /bits/ 16 <4800>; + ti,x-plate-ohms = /bits/ 16 <800>; + ti,y-plate-ohms = /bits/ 16 <300>; + ti,pressure-max = /bits/ 16 <4095>; + + ti,skip-samples = <2>; + ti,sample-period-msecs = <10>; + ti,report-period-msecs = <30>; + + ti,filter-tolerance = <80>; + ti,touch-resistance-threshold = <3500>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux_ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux_pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can1 { + pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; +}; + +&i2c1 { + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; +}; + +&i2c3 { + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + gpio_pca: gpio@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + interrupts-extended = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&ipu1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + status = "okay"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display_in>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&ssi1 { + #sound-dai-cells = <0>; + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&usbh1 { + status = "disabled"; +}; + +&vpu { + status = "disabled"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_can1phy: can1phy { + fsl,pins = < + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_codec: codecgrp { + fsl,pins = < + /* AUDIO_nRESET */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + /* ITU656_nRESET */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + /* ITU656_nPDN */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + >; + }; + + pinctrl_ipu1_disp: ipudisp1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xb0 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xb0 + + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xb0 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xb0 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xb0 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xb0 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xb0 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xb0 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xb0 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xb0 + + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xb0 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xb0 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xb0 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xb0 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xb0 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xb0 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xb0 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xb0 + + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xb0 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xb0 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xb0 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xb0 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xb0 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xb0 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xb0 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xb0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_reg_12v_bl: 12blgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-victgo.dts b/arch/arm/dts/imx6dl-victgo.dts new file mode 100644 index 0000000000..55bc4c8d41 --- /dev/null +++ b/arch/arm/dts/imx6dl-victgo.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-vicut1.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "Kverneland Tellus GO"; + compatible = "kvg,victgo", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x20000000>; + }; + + rotary-encoder { + compatible = "rotary-encoder"; + pinctrl-0 = <&pinctrl_rotary_ch>; + gpios = <&gpio2 3 0>, <&gpio2 4 0>; + linux,axis = <8>; /* REL_WHEEL */ + rotary-encoder,steps-per-period = <4>; + rotary-encoder,relative-axis; + rotary-encoder,rollover; + wakeup-source; + }; + + rotary-button { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_rotary_btn>; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "Rotary Key"; + gpios = <&gpio2 05 1>; + linux,code = <KEY_ENTER>; + gpio-key,wakeup; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>; + clock-names = "ipg", "ahb"; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&i2c1 { + ht16k33: ht16k33@70 { + compatible = "holtek,ht16k33"; + pinctrl-0 = <&pinctrl_ht16k33>; + reg = <0x70>; + refresh-rate-hz = <20>; + debounce-delay-ms = <50>; + interrupt-parent = <&gpio4>; + interrupts = <5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; + keypad,num-rows = <12>; + keypad,num-columns = <3>; + linux,keymap = < + MATRIX_KEY(2, 0, KEY_F6) + MATRIX_KEY(3, 0, KEY_F8) + MATRIX_KEY(4, 0, KEY_F10) + MATRIX_KEY(5, 0, KEY_F4) + MATRIX_KEY(6, 0, KEY_F2) + MATRIX_KEY(2, 1, KEY_F5) + MATRIX_KEY(3, 1, KEY_F7) + MATRIX_KEY(4, 1, KEY_F9) + MATRIX_KEY(5, 1, KEY_F3) + MATRIX_KEY(6, 1, KEY_F1) + >; + }; +}; + +&pwm2 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 + >; + }; + + pinctrl_rotary_ch: rotarygrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 /* ROTARY_A */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 /* ROTARY_B */ + >; + }; + + pinctrl_rotary_btn: rotarygrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 /* ROTARY_BTN */ + >; + }; + + pinctrl_ht16k33: ht16k33grp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* IRQ */ + >; + }; + + pinctrl_tsc2046e: tsc2046egrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-vicut1.dts b/arch/arm/dts/imx6dl-vicut1.dts new file mode 100644 index 0000000000..725acbefc5 --- /dev/null +++ b/arch/arm/dts/imx6dl-vicut1.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-vicut1.dtsi" + +/ { + model = "Kverneland UT1 Board"; + compatible = "kvg,vicut1", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP_RGMII_MD(0x1b030, 0x10030) */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-wandboard.dts b/arch/arm/dts/imx6dl-wandboard.dts index 0a7a7182a5..c4695fb8d8 100644 --- a/arch/arm/dts/imx6dl-wandboard.dts +++ b/arch/arm/dts/imx6dl-wandboard.dts @@ -11,10 +11,10 @@ device-path = &environment_usdhc3; }; }; +}; - memory { - reg = <0x0 0x0>; - }; +&{/memory@10000000} { + reg = <0x10000000 0x0>; }; &ocotp { diff --git a/arch/arm/dts/imx6q-guf-santaro.dts b/arch/arm/dts/imx6q-guf-santaro.dts index 0fb05d05dc..e72aacc59b 100644 --- a/arch/arm/dts/imx6q-guf-santaro.dts +++ b/arch/arm/dts/imx6q-guf-santaro.dts @@ -20,7 +20,8 @@ model = "Garz+Fricke i.MX6q Santaro"; compatible = "guf,imx6q-santaro", "fsl,imx6q"; - memory { + memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; @@ -46,7 +47,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; power-supply = <®_backlight>; diff --git a/arch/arm/dts/imx6q-mba6x.dts b/arch/arm/dts/imx6q-mba6x.dts index 9391c1d6fe..64635b9582 100644 --- a/arch/arm/dts/imx6q-mba6x.dts +++ b/arch/arm/dts/imx6q-mba6x.dts @@ -21,7 +21,8 @@ stdout-path = &uart2; }; - memory { + memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; }; diff --git a/arch/arm/dts/imx6q-phytec-phycard.dts b/arch/arm/dts/imx6q-phytec-phycard.dts index c06461c2c7..b0e47e9b62 100644 --- a/arch/arm/dts/imx6q-phytec-phycard.dts +++ b/arch/arm/dts/imx6q-phytec-phycard.dts @@ -16,7 +16,7 @@ / { model = "PHYTEC phyCARD-i.MX6 Quad"; - compatible = "phytec,imx6q-pbaa03", "phytec,imx6q-pcaaxl3", "fsl,imx6q"; + compatible = "phytec,imx6q-pcaaxl3", "fsl,imx6q"; chosen { stdout-path = &uart3; diff --git a/arch/arm/dts/imx6q-prti6q.dts b/arch/arm/dts/imx6q-prti6q.dts new file mode 100644 index 0000000000..21e24222a0 --- /dev/null +++ b/arch/arm/dts/imx6q-prti6q.dts @@ -0,0 +1,532 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6q.dtsi> +#include "imx6qdl-prti6q.dtsi" +#include "imx6qdl-prti6q-nor.dtsi" +#include <dt-bindings/leds/common.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + model = "Protonic PRTI6Q board"; + compatible = "prt,prti6q", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <16>; + power-supply = <®_3v3>; + enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + }; + + can3_25m_osc: can3-25m-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-debug1 { + function = LED_FUNCTION_SD; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + + panel { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + enable-active-high; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "regulator-WL12xx"; + startup-delay-us = <70000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + bitclock-master; + frame-master; + }; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; + spdif-out; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux_ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux_pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + status = "okay"; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can3>; + clocks = <&can3_25m_osc>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <5000000>; + }; + + adc@1 { + compatible = "ti,adc128s052"; + reg = <1>; + spi-max-frequency = <2000000>; + vref-supply = <®_3v3>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@4 { + reg = <0>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; +}; + +/* DDC */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* can2_l */ + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can2_h */ + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_l */ + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_h */ + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&sata { + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + +&ssi1 { + #sound-dai-cells = <0>; + fsl,mode = "ac97-slave"; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + pinctrl-0 = <&pinctrl_usbotg &pinctrl_usbotg_id>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + vmmc-supply = <®_wifi>; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + wifi { + compatible = "ti,wl1271"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = "38400000"; + tcxo-clock-frequency = "19200000"; + }; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 + >; + }; + + pinctrl_can3: can3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + pinctrl_ecspi2_cs: ecspi2csgrp { + fsl,pins = < + /* ADC128S022 CS */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + /* NOTE: DDC is done via I2C2, so DON'T + * configure DDC pins for HDMI! + */ + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + /* DDC */ + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg_id: usbotgidgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f058 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + /* WL12xx IRQ */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880 + >; + }; + + pinctrl_wifi_npd: wifinpd { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6q-prtwd2.dts b/arch/arm/dts/imx6q-prtwd2.dts new file mode 100644 index 0000000000..8572917865 --- /dev/null +++ b/arch/arm/dts/imx6q-prtwd2.dts @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2018 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6q.dtsi> +#include "imx6qdl-prti6q.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + model = "Protonic WD2 board"; + compatible = "prt,prtwd2", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; + + /* PRTWD2 rev 1 bitbang I2C for Ethernet Switch */ + i2c@4 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <20>; /* ~10 kHz */ + i2c-gpio,scl-output-only; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&can1 { + pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>; + clock-names = "ipg", "ahb"; + status = "okay"; + + fixed-link { + speed = <100>; + pause; + full-duplex; + }; +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* V in */ + channel@4 { + reg = <4>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* I charge */ + channel@5 { + reg = <5>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* V bus */ + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* nc */ + channel@7 { + reg = <7>; + ti,gain = <1>; + ti,datarate = <3>; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + pm-ignore-notify; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_eth_chg>; + + pinctrl_can1phy: can1phy { + fsl,pins = < + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x130b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1f8b0 + MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f8b0 + >; + }; + + pinctrl_usb_eth_chg: usbethchggrp { + fsl,pins = < + /* USB charging control */ + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x130b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x130b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x130b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_wifi_npd: wifinpd { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; +}; diff --git a/arch/arm/dts/imx6q-var-som.dtsi b/arch/arm/dts/imx6q-var-som.dtsi index 63a17fc660..7dbaa1e3d4 100644 --- a/arch/arm/dts/imx6q-var-som.dtsi +++ b/arch/arm/dts/imx6q-var-som.dtsi @@ -17,7 +17,8 @@ model = "Variscite i.MX6 Quad SOM"; compatible = "variscite,imx6q-som", "fsl,imx6q"; - memory { + memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; }; diff --git a/arch/arm/dts/imx6q-vicut1.dts b/arch/arm/dts/imx6q-vicut1.dts new file mode 100644 index 0000000000..9d1d6fa550 --- /dev/null +++ b/arch/arm/dts/imx6q-vicut1.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6q.dtsi> +#include "imx6qdl-vicut1.dtsi" + +/ { + model = "Kverneland UT1Q Board"; + compatible = "kvg,vicut1q", "fsl,imx6q"; + + memory { + reg = <0x10000000 0xf0000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@4 { + reg = <0>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP_RGMII_MD(0x1b030, 0x10030) */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/dts/imx6q-wandboard.dts b/arch/arm/dts/imx6q-wandboard.dts index d96f057961..d182faf217 100644 --- a/arch/arm/dts/imx6q-wandboard.dts +++ b/arch/arm/dts/imx6q-wandboard.dts @@ -11,10 +11,10 @@ device-path = &environment_usdhc3; }; }; +}; - memory { - reg = <0x0 0x0>; - }; +&{/memory@10000000} { + reg = <0x10000000 0x0>; }; &ocotp { diff --git a/arch/arm/dts/imx6qdl-mba6x.dtsi b/arch/arm/dts/imx6qdl-mba6x.dtsi index 216c3be7e8..9cc31491cc 100644 --- a/arch/arm/dts/imx6qdl-mba6x.dtsi +++ b/arch/arm/dts/imx6qdl-mba6x.dtsi @@ -38,7 +38,7 @@ beeper: beeper@0 { compatible = "pwm-beeper"; - pwms = <&pwm1 2 5000000>; + pwms = <&pwm1 2 5000000 0>; }; disp0: display@0 { diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi index 3cb8b3782a..b83511cb01 100644 --- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi @@ -12,8 +12,6 @@ #include <arm/imx6qdl-phytec-pfla02.dtsi> / { - /delete-node/ memory@10000000; - chosen { environment-nand { compatible = "barebox,environment"; @@ -53,6 +51,8 @@ }; }; +/delete-node/ &{/memory@10000000}; + &ecspi3 { flash: flash@0 { partitions { diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi index e99846c2b6..2fb920945f 100644 --- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi @@ -33,10 +33,10 @@ status = "disabled"; }; }; - - /delete-node/ memory@10000000; }; +/delete-node/ &{/memory@10000000}; + &fec { /delete-property/ phy-supply; phy-reset-duration = <10>; /* in msecs */ diff --git a/arch/arm/dts/imx6qdl-prti6q-nor.dtsi b/arch/arm/dts/imx6qdl-prti6q-nor.dtsi new file mode 100644 index 0000000000..ad718ce421 --- /dev/null +++ b/arch/arm/dts/imx6qdl-prti6q-nor.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +&ecspi1 { + flash@0 { + partition@0 { + label = "barebox"; + reg = <0x0 0x100000>; + }; + }; +}; diff --git a/arch/arm/dts/imx6qdl-prti6q.dtsi b/arch/arm/dts/imx6qdl-prti6q.dtsi new file mode 100644 index 0000000000..bfc059e34f --- /dev/null +++ b/arch/arm/dts/imx6qdl-prti6q.dtsi @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + chosen { + stdout-path = &uart4; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &usdhc3, "partname:barebox-environment"; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Address will be determined by the bootloader */ + ramoops { + compatible = "ramoops"; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Address will be determined by the bootloader */ + ramoops { + compatible = "ramoops"; + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "h1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@100000 { + label = "barebox-environment"; + reg = <0x100000 0x100000>; + }; + + partition@200000 { + label = "state"; + reg = <0x200000 0x100000>; + }; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-udoo.dtsi b/arch/arm/dts/imx6qdl-udoo.dtsi index ebc103858c..bf47297bad 100644 --- a/arch/arm/dts/imx6qdl-udoo.dtsi +++ b/arch/arm/dts/imx6qdl-udoo.dtsi @@ -22,7 +22,8 @@ stdout-path = &uart2; }; - memory { + memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/dts/imx6qdl-vicut1.dtsi b/arch/arm/dts/imx6qdl-vicut1.dtsi new file mode 100644 index 0000000000..dbfcf2527c --- /dev/null +++ b/arch/arm/dts/imx6qdl-vicut1.dtsi @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 Protonic Holland + */ + +#include "imx6qdl-prti6q.dtsi" +#include "imx6qdl-prti6q-nor.dtsi" +#include <dt-bindings/input/input.h> + +/ { + gpio_key_pwr: gpio_keys { + compatible = "gpio-keys"; + autorepeat; + + power { + label = "GPIO Key Power"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + gpio-key,wakeup; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + debug0 { + label = "debug0"; + gpios = <&gpio1 8 0>; + linux,default-trigger = "heartbeat"; + }; + + debug1 { + label = "debug1"; + gpios = <&gpio1 9 0>; + linux,default-trigger = "mmc"; + }; + + power_led { + label = "power_led"; + gpios = <&gpio2 24 0>; + default-state = "on"; + }; + + isb_led { + label = "isb_led"; + gpios = <&gpio4 31 0>; + default-state = "off"; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&i2c3 { + rtc: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&iomuxc { + pinctrl_hog: hoggrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + /* CAN1_SR + CAN2_SR GPIO outputs */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + /* ITU656_nRESET */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + /* CAM1_MIRROR */ + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 + /* CAM2_MIRROR */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 + /* CAM_nDETECT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + /* ISB_IN1 */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 + /* ISB_nIN2 */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + /* WARN_LIGHT */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 + /* ON2_FB */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 + /* YACO_nIRQ */ + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 + /* YACO_BOOT0 */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 + /* YACO_nRESET */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + /* FORCE_ON1 */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + /* AUDIO_nRESET */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 + /* ITU656_nPDN */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + + /* HW revision detect */ + /* REV_ID0 */ + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + /* REV_ID1 = PWM output LED_PWM (SION) */ + /* defined in &pinctrl_pwm3 */ + /* REV_ID2 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 + /* REV_ID3 */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + /* REV_ID4 */ + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 + + /* New in HW revision 1 */ + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 /* ON1_FB */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 /* DIP1_FB */ + + /* New in UTC (UT1 HW revision 1) and TGO */ + /* WHEEL */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x100b0 + /* RADAR */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x100b0 + /* PTO */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x100b0 + /* CPU_ON1_CTRL */ + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 + /* CPU_ON2_CTRL */ + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b0 + /* CPU_HITCH_IN_OUT */ + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x100b0 + /* CPU_LIGHT_ON */ + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b0 + /* CPU_CONTACT_IN */ + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x100b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + /* YaCO AUX Uart */ + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + /* YaCO Touchscreen UART */ + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + /* DEBUG0A */ + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 + /* DEBUG1A */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 + /* DEBUG0 */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + /* DEBUG1 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + /* POWER_LED */ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 + /* ISB_LED */ + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + /* ISB LED (not in TGO or UTC version 1+) */ + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + /* REV_ID1 = PWM output LED_PWM (SION for ID) */ + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x4001b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi index 828be9ce0d..c3e02d2117 100644 --- a/arch/arm/dts/imx6qdl.dtsi +++ b/arch/arm/dts/imx6qdl.dtsi @@ -6,5 +6,26 @@ pwm2 = &pwm3; pwm3 = &pwm4; ipu0 = &ipu1; + gpr.reboot_mode = &reboot_mode_gpr; + }; +}; + +&src { + compatible = "fsl,imx6q-src", "fsl,imx51-src", "syscon", "simple-mfd"; + + reboot_mode_gpr: reboot-mode { + compatible = "barebox,syscon-reboot-mode"; + offset = <0x40>, <0x44>; /* SRC_GPR{9,10} */ + mask = <0xffffffff>, <0x10000000>; + mode-normal = <0>, <0>; + mode-serial = <0x00000010>, <0x10000000>; + mode-spi0-0 = <0x08000030>, <0x10000000>; + mode-spi0-1 = <0x18000030>, <0x10000000>; + mode-spi0-2 = <0x28000030>, <0x10000000>; + mode-spi0-3 = <0x38000030>, <0x10000000>; + mode-mmc0 = <0x00002040>, <0x10000000>; + mode-mmc1 = <0x00002840>, <0x10000000>; + mode-mmc2 = <0x00003040>, <0x10000000>; + mode-mmc3 = <0x00003840>, <0x10000000>; }; }; diff --git a/arch/arm/dts/imx6qp-prtwd3.dts b/arch/arm/dts/imx6qp-prtwd3.dts new file mode 100644 index 0000000000..97b25ee26a --- /dev/null +++ b/arch/arm/dts/imx6qp-prtwd3.dts @@ -0,0 +1,675 @@ +/* + * Copyright (c) 2018 Protonic Holland + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include <arm/imx6qp.dtsi> +#include "imx6qdl-prti6q.dtsi" + +/ { + model = "Protonic WD3 board"; + compatible = "prt,prtwd3", "fsl,imx6qp"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; + + usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; + + clk20m_can: fdcan_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + clk25m_switch: switch_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk25m_phy3: phy3_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk50m_phy: phy_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio0>; + + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpio5 6 GPIO_ACTIVE_HIGH + &gpio5 7 GPIO_ACTIVE_HIGH>; + }; + + display_panel0 { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + + port { + display_panel0_in: endpoint { + remote-endpoint = <&serializer0_out>; + }; + }; + }; + + display_panel1 { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_panel1>; + + port { + display_panel1_in: endpoint { + remote-endpoint = <&serializer1_out>; + }; + }; + }; + + backlight_lcd: backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 1 2 4 6 8 12 16 24 32 48 64 96 128 192 255>; + default-brightness-level = <15>; + power-supply = <®_3v3>; + }; + + backlight_panel1: backlight_panel1 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 5000000 0>; + brightness-levels = <0 1 2 4 6 8 12 16 24 32 48 64 96 128 192 255>; + default-brightness-level = <0>; + power-supply = <®_3v3>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF>; + assigned-clock-rates = <125000000>; + + phy-mode = "rgmii"; + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + /* Microchip KSZ9031 */ + rgmii_phy: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + + interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>; + + /* FIXME: tx/rx clk skew are currently set by imx + * platform driver. Write own walues here to not depend + * fixup of horror. + */ + + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + /* reset assert time is provided by documentation */ + reset-assert-us = <10000>; + /* documented reset deassert time (100us) is not enough + * use test value of 300us. + */ + reset-deassert-us = <1000>; + + clocks = <&clk25m_phy3>; + }; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + sja1105_switch: sja1105@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,sja1105q"; + spi-max-frequency = <4000000>; + spi-cpha; + spi-rx-delay-us = <1>; + spi-tx-delay-us = <1>; + + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + + clocks = <&clk25m_switch>; + #clock-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "usb"; + phy-handle = <&usbeth_phy>; + phy-mode = "rmii"; + }; + + port@1 { + reg = <1>; + label = "t1slave"; + phy-handle = <&tja1102_phy1>; + phy-mode = "rmii"; + }; + + port@2 { + reg = <2>; + label = "t1master"; + phy-handle = <&tja1102_phy0>; + phy-mode = "rmii"; + + }; + + port@3 { + reg = <3>; + label = "rj45"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&fec>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; + +&mdio0 { + usbeth_phy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + + interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <500>; + reset-deassert-us = <1000>; + + /* FIXME: the clock is provided by switch and we should know + * and we should request it only after switch have done clock + * configuration. Since it is currently not implemented, + * use fixed clock. + * WARNING: Using fixed clocks in this case is potential source + * for evil bugs. Switch may reconfigure, stop or change clk + * freq without letting PHY to know about it. + */ + clocks = <&clk50m_phy>; + clock-names = "rmii-ref"; + }; + + tja1102_phy0: ethernet-phy@4 { + compatible = "ethernet-phy-id0180.dc80"; + reg = <0x4>; + + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + /* reset detection time is 20 usec. */ + reset-assert-us = <20>; + /* reset to standby 2 msec. */ + reset-deassert-us = <2000>; + #address-cells = <1>; + #size-cells = <0>; + + tja1102_phy1: ethernet-phy@5 { + reg = <0x5>; + + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&ecspi3 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + can3: can@0 { + compatible = "microchip,mcp2518fd"; + spi-max-frequency = <5000000>; + reg = <0>; + clocks = <&clk20m_can>; + interrupt-parent = <&gpio4>; + interrupts = <25 0x2>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + serializer0: ds90ub927@c { + compatible = "ti,ds90ub927"; + reg = <0x0c>; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + serializer0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + /* port@1 { + reg = <1>; + serializer0_audio_in: endpoint { + remote-endpoint = <&audio_i2s0_out>; + }; + }; */ + port@2 { + reg = <2>; + serializer0_out: endpoint { + remote-endpoint = <&display_panel0_in>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + serializer1: ds90ub927@c { + compatible = "ti,ds90ub927"; + reg = <0x0c>; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + serializer1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + port@2 { + reg = <2>; + serializer1_out: endpoint { + remote-endpoint = <&display_panel1_in>; + }; + }; + }; + + camdeser: ds90ub954@30 { + compatible = "ti,ds90ub954"; + reg = <0x30>; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + camdeser_fpd_link_in: endpoint { + }; + }; + port@1 { + reg = <1>; + camdeser_mipi_out: endpoint { + remote-endpoint = <&mipi_csi_in>; + }; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; /* force 3.3V VIO */ + non-removable; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + pm-ignore-notify; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + channel@5 { + reg = <5>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + channel@7 { + reg = <7>; + ti,gain = <1>; + ti,datarate = <3>; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&serializer0_in>; + }; + }; + }; + + lvds-channel@1 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + remote-endpoint = <&serializer1_in>; + }; + }; + }; +}; + +&mipi_csi { + status = "okay"; + port@0 { + reg = <0>; + + mipi_csi_in: endpoint { + remote-endpoint = <&camdeser_mipi_out>; + }; + }; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + /* Empty, to disable parallel camera from PRTI6Q */ +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Configure clock provider for RGMII ref clock */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 + /* Configure clock consumer for RGMII ref clock */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + + /* SJA1105Q switch reset */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x10030 + + /* phy3/rgmii_phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x10030 + /* phy3/rgmii_phy int */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x40010000 + >; + }; + + pinctrl_mdio0: mdio0grp { + fsl,pins = < + /* phy0/usbeth_phy reset */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x10030 + /* phy0/usbeth_phy int */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + + /* phy12/tja1102_phy0 reset */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x10030 + /* phy12/tja1102_phy0 int */ + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x100b1 + /* phy12/tja1102_phy0 enable. Set 100K pull-up */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1f030 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + + + pinctrl_hog: hoggrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + /* CAN1_SR + CAN2_SR GPIO outputs */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070 + /* CAN1_TERM (not used on WD3) */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + + /* HW revision detect */ + /* REV_ID0 */ + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + /* REV_ID1 */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 + /* REV_ID2 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 + /* REV_ID3 */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + /* REV_ID4 */ + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 + + /* USB charging control */ + /* CHG Control */ + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0 + /* RID0 */ + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x130b0 + /* RID1 */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x130b0 + /* RID2 */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x130b0 + + /* Power VSEL and TG */ + /* VSEL */ + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 + /* TG */ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + + /* Display panel 0 GPIO */ + /* L/R */ + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0 + /* TS_nINT */ + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 + /* EN */ + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0 + /* LVDS0_nINT */ + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x1b0b0 + /* LVDS0_PD */ + MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x1b0b0 + + /* Display panel 1 GPIO */ + /* L/R */ + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 + /* TS_nINT */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + /* EN */ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + /* LVDS1_nINT */ + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x1b0b0 + /* LVDS1_PD */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 + + /* Camera */ + /* CAM_GPIO0 */ + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 + /* CAM_nINT */ + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x1b0b0 + /* CAM_GPIO1 */ + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0 + /* CAM_nPD */ + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x1b0b0 + /* CAM_LOCK */ + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1b0b0 + + /* USB ethernet reset (asix) */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + >; + }; + + pinctrl_wifi_npd: wifinpd { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001f8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_leds: ledsgrp { + /* No leds */ + fsl,pins = <>; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + /* CS */ + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + /* CAN2_nINT */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qp-vicutp.dts b/arch/arm/dts/imx6qp-vicutp.dts new file mode 100644 index 0000000000..44cfe68867 --- /dev/null +++ b/arch/arm/dts/imx6qp-vicutp.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6qp.dtsi> +#include "imx6qdl-vicut1.dtsi" + +/ { + model = "Kverneland UT1P Board"; + compatible = "kvg,vicutp", "fsl,imx6qp"; + + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + /* phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; */ + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP_RGMII_MD(0x1b030, 0x10030) */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/dts/imx6ul-litesom.dtsi b/arch/arm/dts/imx6ul-litesom.dtsi index 8b73bfdd6f..3776d160ca 100644 --- a/arch/arm/dts/imx6ul-litesom.dtsi +++ b/arch/arm/dts/imx6ul-litesom.dtsi @@ -3,6 +3,4 @@ * to dynamic memory size detection based on DDR controller settings */ -/ { - /delete-node/ memory@80000000; -}; +/delete-node/ &{/memory@80000000}; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6ul-phytec-phycore-som-emmc.dts new file mode 100644 index 0000000000..50ce75f12b --- /dev/null +++ b/arch/arm/dts/imx6ul-phytec-phycore-som-emmc.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Author: Yunus Bas <y.bas@phytec.de> + */ + +/dts-v1/; +#ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY +#include CONFIG_BOOTM_FITIMAGE_PUBKEY +#endif +#include <arm/imx6ul.dtsi> +#include "imx6ul-phytec-phycore-som.dtsi" +#include "imx6ul-phytec-state.dtsi" + +/ { + model = "PHYTEC phyCORE-i.MX6 Ultra Light SOM with eMMC"; + compatible = "phytec,imx6ul-pcl063-emmc", "fsl,imx6ul"; +}; + +&fec1 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&state { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ul-pico-hobbit.dts b/arch/arm/dts/imx6ul-pico-hobbit.dts index 2f37b724b6..0c543de8c9 100644 --- a/arch/arm/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/dts/imx6ul-pico-hobbit.dts @@ -9,10 +9,6 @@ device-path = &environment_usdhc1; }; }; - - memory { - /delete-property/ device_type; - }; }; &usdhc1 { diff --git a/arch/arm/dts/imx6ul-prti6g.dts b/arch/arm/dts/imx6ul-prti6g.dts new file mode 100644 index 0000000000..e65198bab2 --- /dev/null +++ b/arch/arm/dts/imx6ul-prti6g.dts @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2016 Protonic Holland + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "imx6ul-prti6g.dtsi" + +/ { + model = "Protonic PRTI6G Board"; + compatible = "prt,prti6g", "fsl,imx6ul"; +}; + +&pinctrl_hog { + fsl,pins = < + /* HW revision detect */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 /* REV_ID0 */ + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 /* REV_ID1 */ + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 /* REV_ID2 */ + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 /* REV_ID3 */ + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BOARD_ID0 */ + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 /* BOARD_ID1 */ + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* BOARD_ID2 */ + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 /* BOARD_ID3 */ + + /* Safety controller IO */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WAKE_SC */ + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* PROGRAM_SC */ + >; +}; + +&ecspi2 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&i2c2 { + can_adc: ads1015@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; +}; diff --git a/arch/arm/dts/imx6ul-prti6g.dtsi b/arch/arm/dts/imx6ul-prti6g.dtsi new file mode 100644 index 0000000000..c20bbd5bc2 --- /dev/null +++ b/arch/arm/dts/imx6ul-prti6g.dtsi @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2016 Protonic Holland + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arm/imx6ul.dtsi> +#include <dt-bindings/gpio/gpio.h> + +/ { + chosen { + stdout-path = &uart1; + environment@0 { + compatible = "barebox,environment"; + device-path = &flash, "partname:env"; + }; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p2v: 3p2-regulator { + compatible = "regulator-fixed"; + regulator-name = "regulator-3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + + reg_1p35v: 1p35-regulator { + compatible = "regulator-fixed"; + regulator-name = "regulator-1P35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + debug { + label = "debug0"; + gpios = <&gpio4 16 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p2v>; + wakeup-source; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: w25q64fv@0 { + compatible = "winbond,w25q64", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + m25p,fast-read; + reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x0 0x60000>; /* 384 Kb */ + }; + + partition@60000 { + label = "env"; + reg = <0x60000 0x10000>; /* 64 Kb */ + }; + + partition@70000 { + label = "dtb"; + reg = <0x70000 0x10000>; /* 64 Kb */ + }; + + partition@80000 { + label = "kernel"; + reg = <0x80000 0x780000>; /* 7680 Kb */ + }; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + /* RFID chip */ +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + rtc: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + tmp103: tmp103@70 { + compatible = "ti,tmp103", "tmp103"; + reg = <0x70>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1 &pinctrl_ethphy0_rst>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + phy-reset-duration = <11>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + prti6g { + pinctrl_hog: hoggrp { + fsl,pins = < + /* HW revision detect */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 /* REV_ID0 */ + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 /* REV_ID1 */ + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 /* REV_ID2 */ + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 /* REV_ID3 */ + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BOARD_ID0 */ + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 /* BOARD_ID1 */ + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* BOARD_ID2 */ + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 /* BOARD_ID3 */ + + /* CAN diagnostics (nSMBALERT) */ + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 + MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x170b0 /* SD1 CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x0b0b0 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x000b1 + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x0b0b0 + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0b0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x0b0b0 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000b1 + MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x0b0b0 + MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x0b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x100b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_ethphy0_rst: ethphy-rstgrp-0 { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x00880 /* PHY RESET */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 /* SR */ + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* TERM */ + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 /* nSMBALERT */ + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* SR */ + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6ul-webasto-ccbv2.dts b/arch/arm/dts/imx6ul-webasto-ccbv2.dts new file mode 100644 index 0000000000..93e9445b48 --- /dev/null +++ b/arch/arm/dts/imx6ul-webasto-ccbv2.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2019, Webasto SE + * Author: Johannes Eigner <johannes.eigner@webasto.com> + */ + +/dts-v1/; + +#include "imx6ul-webasto-ccbv2.dtsi" + +/ { + chosen { + environment { + compatible = "barebox,environment"; + device-path = &environment_emmc; + }; + }; + + aliases { + state = &state_emmc; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dt-overlay@84000000 { + reg = <0x84000000 0x100000>; + no-map; + }; + }; + + state_emmc: state { + #address-cells = <1>; + #size-cells = <1>; + compatible = "barebox,state"; + magic = <0x290cf8c6>; + backend-type = "raw"; + backend = <&backend_state_emmc>; + backend-stridesize = <0x200>; + + bootstate { + #address-cells = <1>; + #size-cells = <1>; + + system0 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@0 { + reg = <0x0 0x4>; + type = "uint32"; + default = <3>; + }; + + priority@4 { + reg = <0x4 0x4>; + type = "uint32"; + default = <20>; + }; + }; + + system1 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@8 { + reg = <0x8 0x4>; + type = "uint32"; + default = <3>; + }; + + priority@c { + reg = <0xc 0x4>; + type = "uint32"; + default = <21>; + }; + }; + + last_chosen@10 { + reg = <0x10 0x4>; + type = "uint32"; + }; + }; + }; +}; + +&usdhc2 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x100000>; + }; + + environment_emmc: partition@100000 { + label = "barebox-environment"; + reg = <0x100000 0x100000>; + }; + + backend_state_emmc: partition@200000 { + label = "barebox-state"; + reg = <0x200000 0x100000>; + }; + }; +}; + + +&ocotp { + barebox,provide-mac-address = <&fec1 0x620>; +}; + +/* include the FIT public key for verifying on demand */ +#ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY +#include CONFIG_BOOTM_FITIMAGE_PUBKEY +#endif diff --git a/arch/arm/dts/imx6ul-webasto-ccbv2.dtsi b/arch/arm/dts/imx6ul-webasto-ccbv2.dtsi new file mode 100644 index 0000000000..829485de32 --- /dev/null +++ b/arch/arm/dts/imx6ul-webasto-ccbv2.dtsi @@ -0,0 +1,469 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2019, Webasto SE +// +// Author: Johannes Eigner <johannes.eigner@webasto.com> + +/dts-v1/; + +#include <arm/imx6ul.dtsi> + +/ { + model = "Webasto common communication board version 2"; + compatible = "webasto,imx6ul-ccbv2", "fsl,imx6ul"; + + chosen { + stdout-path = &uart7; + }; + + reg_4v: regulator-4v { + compatible = "regulator-fixed"; + regulator-name = "V_+4V"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_wl18xx_vmmc: regulator-wl18xx { + compatible = "regulator-fixed"; + regulator-name = "wl1837"; + vin-supply = <®_4v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + reg_dp83822_en: regulator-dp83822 { + compatible = "regulator-fixed"; + regulator-name = "dp83822"; + vin-supply = <&vcc_eth>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-supply = <®_dp83822_en>; + phy-handle = <&dp83822i>; + phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + dp83822i: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + pmic: mc34pf3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + regulators { + sw1a_reg: sw1a { + regulator-name = "V_+3V3_SW1A"; + vin-supply = <®_4v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + vdd_soc_in: sw1b { + regulator-name = "V_+1V4_SW1B"; + vin-supply = <®_4v>; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-ramp-delay = <6250>; + regulator-boot-on; + regulator-always-on; + }; + sw2_reg: sw2 { + regulator-name = "V_+3V3_SW2"; + vin-supply = <®_4v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vcc_ddr3: sw3 { + regulator-name = "V_+1V35_SW3"; + vin-supply = <®_4v>; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + swbst_reg: swbst { + regulator-name = "V_+5V0_SWBST"; + vin-supply = <®_4v>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + vdd_snvs: vsnvs { + regulator-name = "V_+3V0_SNVS"; + vin-supply = <®_4v>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + vrefddr: vrefddr { + regulator-name = "V_+0V675_VREFDDR"; + vin-supply = <&vcc_ddr3>; + regulator-boot-on; + regulator-always-on; + }; + /* 3V3 Supply: i.MX6 modules */ + vgen1_reg: vldo1 { + regulator-name = "V_+3V3_LDO1"; + vin-supply = <®_4v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + }; + vdd_high_in: v33 { + regulator-name = "V_+3V3_V33"; + vin-supply = <®_4v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vcc_eth: vldo3 { + regulator-name = "V_+1V8_LDO3"; + vin-supply = <®_4v>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + vgen6_reg: vldo4 { + regulator-name = "V_+1V8_LDO4"; + vin-supply = <®_4v>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + cs-gpios = < + &gpio3 26 GPIO_ACTIVE_LOW + &gpio3 10 GPIO_ACTIVE_LOW + &gpio3 12 GPIO_ACTIVE_LOW + >; + status = "okay"; + + cc2520: spi@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cc2520>; + compatible = "ti,cc2520"; + reg = <0>; + spi-max-frequency = <4000000>; + fifo-gpio = <&gpio3 15 0>; + fifop-gpio = <&gpio3 16 0>; + sfd-gpio = <&gpio3 24 0>; + cca-gpio = <&gpio3 20 0>; + vreg-gpio = <&gpio3 19 0>; + reset-gpio = <&gpio3 23 0>; + vin-supply = <&sw2_reg>; + }; + qca7000: spi@1 { + compatible = "qca,qca7000"; + reg = <1>; + spi-max-frequency = <8000000>; + interrupt-parent = <&gpio4>; + interrupts = <16 0x1>; + spi-cpha; + spi-cpol; + }; + tfr7970: spi@2 { + compatible = "ti,trf7970a"; + reg = <2>; + spi-max-frequency = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_trf7970>; + interrupt-parent = <&gpio3>; + interrupts = <14 0>; + ti,enable-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>, <&gpio3 17 GPIO_ACTIVE_HIGH>; + vin-supply = <®_4v>; + vdd-io-supply = <&sw2_reg>; + autosuspend-delay = <30000>; + clock-frequency = <27120000>; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + uart-has-rtscts; + status = "okay"; + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + vin-supply = <®_4v>; + }; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + vmmc-supply = <®_wl18xx_vmmc>; + non-removable; + keep-power-in-suspend; + cap-power-off-card; + max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio4>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + vmmc-supply = <&sw1a_reg>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + keep-power-in-suspend; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_minipcie>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +®_arm { + vin-supply = <&vdd_soc_in>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&vdd_soc_in>; + regulator-allow-bypass; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x13030 + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x13030 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10000 + >; + }; + + pinctrl_minipcie: minipciegrp { + fsl,pins = < + /* HYS=1, 100k PullDown, 50MHz, R0/6 */ + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x13030 + MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x13030 + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x13030 + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x13030 + MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x13030 + >; + }; + + pinctrl_spi1: spi1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x1b0b0 + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x1b0b0 + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x1b0b0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x17030 + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x17030 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x17030 + MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x10030 + >; + }; + + pinctrl_cc2520: cc2520grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x13030 + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x13030 + MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x13030 + MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x13030 + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x13030 + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x13030 + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x17030 + + >; + }; + + pinctrl_trf7970: trf7970grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x17030 + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x10030 + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x10030 + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x17000 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x1b0b0 + MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x1b0b0 + MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x1b0b0 + MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x1b0b0 + MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x13030 + MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x13030 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b0 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b0 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b0 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b0 + MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b0 + MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x10030 + MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x00010 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b0 + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x10059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x10059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x10059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x10059 + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x17000 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10030 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100e9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x100e9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x100e9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x100e9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x100e9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x100e9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x100e9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x100e9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x100e9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x100e9 + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10030 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x00b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts index 2201b4c1b2..afd99a3fd9 100644 --- a/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts @@ -10,6 +10,7 @@ #endif #include <arm/imx6ull.dtsi> #include "imx6ul-phytec-phycore-som.dtsi" +#include "imx6ul-phytec-state.dtsi" / { model = "PHYTEC phyCORE-i.MX6 ULL SOM with eMMC"; @@ -24,6 +25,10 @@ status = "okay"; }; +&state { + status = "okay"; +}; + &uart1 { status = "okay"; }; diff --git a/arch/arm/dts/imx7d-ac-sxb.dtsi b/arch/arm/dts/imx7d-ac-sxb.dtsi new file mode 100644 index 0000000000..00b0fd11c6 --- /dev/null +++ b/arch/arm/dts/imx7d-ac-sxb.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright (C) 2017 Atlas Copco Industrial Technique + */ + +/dts-v1/; + +#include <arm/imx7d.dtsi> + +/ { + model = "Atlas Copco SXB Board"; + compatible = "ac,imx7d-sxb", "fsl,imx7d"; + + reg_sd1_vmmc: regulator-reg-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + tuning-step = <2>; + vmmc-supply = <®_sd1_vmmc>; + enable-sdio-wakeup; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; + + usdhc1_sdcard: state@4100000 { + reg = <0x4100000 0xffffff>; + label = "state-sdcard"; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + status = "okay"; + + usdhc3_emmc: usdhc3_emmc@1e800000 { + reg = <0x1e800000 0xffffff>; + label = "state-emmc"; + }; + +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx7d-sxb { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19 + >; + }; + }; +}; + +&iomuxc_lpsr { + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x75 + >; + }; +}; diff --git a/arch/arm/dts/imx7d-pba-c-09.dtsi b/arch/arm/dts/imx7d-pba-c-09.dtsi index 7106d6bfd7..ffe1239801 100644 --- a/arch/arm/dts/imx7d-pba-c-09.dtsi +++ b/arch/arm/dts/imx7d-pba-c-09.dtsi @@ -36,7 +36,6 @@ }; /* Enable if R9 is populated. Conflicts with userbtn2 on PEB-EVAL-02 */ - /* reg_can1_3v3: regulator@2 { compatible = "regulator-fixed"; reg = <2>; @@ -45,8 +44,8 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; enable-active-high; + status = "disabled"; }; - */ }; }; @@ -266,7 +265,7 @@ }; &backlight { - pwms = <&pwm3 0 5000000>; + pwms = <&pwm3 0 5000000 0>; enable-gpios = <&gpio1 1 0>; status = "disabled"; }; diff --git a/arch/arm/dts/imx7d-phyboard-zeta.dts b/arch/arm/dts/imx7d-phyboard-zeta.dts index fbd0da2383..a34f12f616 100644 --- a/arch/arm/dts/imx7d-phyboard-zeta.dts +++ b/arch/arm/dts/imx7d-phyboard-zeta.dts @@ -21,7 +21,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; }; @@ -139,4 +139,4 @@ &uart2 { status = "okay"; -};
\ No newline at end of file +}; diff --git a/arch/arm/dts/imx7d-phycore-som.dtsi b/arch/arm/dts/imx7d-phycore-som.dtsi index 622261bd1e..e892a54bdd 100644 --- a/arch/arm/dts/imx7d-phycore-som.dtsi +++ b/arch/arm/dts/imx7d-phycore-som.dtsi @@ -13,7 +13,8 @@ model = "Phytec i.MX7D phyCORE"; compatible = "phytec,imx7d-phycore-som", "fsl,imx7d"; - memory { + memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x80000000>; }; }; @@ -269,4 +270,4 @@ tuning-step = <2>; non-removable; status = "disabled"; -};
\ No newline at end of file +}; diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index 16bfabe9b3..7beb065920 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -14,7 +14,7 @@ stdout-path = &uart1; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/dts/imx7s-warp.dts b/arch/arm/dts/imx7s-warp.dts index c901477783..8e645999cf 100644 --- a/arch/arm/dts/imx7s-warp.dts +++ b/arch/arm/dts/imx7s-warp.dts @@ -18,11 +18,6 @@ device-path = &bareboxenv; }; }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; }; &usdhc3 { diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts new file mode 100644 index 0000000000..3264ade4b8 --- /dev/null +++ b/arch/arm/dts/imx8mp-evk.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright (C) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> + */ + +/dts-v1/; + +#include <arm64/freescale/imx8mp-evk.dts> +#include "imx8mp.dtsi" + +/ { + chosen { + environment-sd { + compatible = "barebox,environment"; + device-path = &usdhc2, "partname:barebox-environment"; + status = "disabled"; + }; + environment-emmc { + compatible = "barebox,environment"; + device-path = &usdhc3, "partname:barebox-environment"; + status = "disabled"; + }; + }; + + gpio-leds { + status { + barebox,default-trigger = "heartbeat"; + }; + }; +}; + +ðphy1 { + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&ocotp { + barebox,provide-mac-address = <&fec 0x640>; +}; diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi new file mode 100644 index 0000000000..b251ebeada --- /dev/null +++ b/arch/arm/dts/imx8mp.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/ { + remoteproc_cm7: remoteproc-cm7 { + compatible = "fsl,imx8mp-cm7"; + clocks = <&clk IMX8MP_CLK_M7_CORE>; + syscon = <&src>; + }; +}; diff --git a/arch/arm/dts/imx8mq-ddrc.dtsi b/arch/arm/dts/imx8mq-ddrc.dtsi index 64826b0373..1df39151a1 100644 --- a/arch/arm/dts/imx8mq-ddrc.dtsi +++ b/arch/arm/dts/imx8mq-ddrc.dtsi @@ -6,12 +6,5 @@ / { /delete-node/ memory@40000000; - - soc@0 { - ddrc@3d400000 { - compatible = "fsl,imx8mq-ddrc"; - reg = <0x3d400000 0x400000>; - }; - }; }; diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index 44a86c715a..ec8347f38f 100644 --- a/arch/arm/dts/imx8mq.dtsi +++ b/arch/arm/dts/imx8mq.dtsi @@ -5,9 +5,10 @@ */ / { - aliases { - mmc0 = &usdhc1; - mmc1 = &usdhc2; + remoteproc_cm4: remoteproc-cm4 { + compatible = "fsl,imx8mq-cm4"; + clocks = <&clk IMX8MQ_CLK_M4_CORE>; + syscon = <&src>; }; }; diff --git a/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts b/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts index aba7c06160..1be03a7ac0 100644 --- a/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts +++ b/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts @@ -5,10 +5,6 @@ #include "arm/kirkwood-guruplug-server-plus.dts" -/ { - gpio-leds { - health-r { - barebox,default-trigger = "heartbeat"; - }; - }; +&{/gpio-leds/health-r} { + barebox,default-trigger = "heartbeat"; }; diff --git a/arch/arm/dts/kirkwood-openblocks_a6-bb.dts b/arch/arm/dts/kirkwood-openblocks_a6-bb.dts index 42bfb07c94..b13ab2ab93 100644 --- a/arch/arm/dts/kirkwood-openblocks_a6-bb.dts +++ b/arch/arm/dts/kirkwood-openblocks_a6-bb.dts @@ -4,10 +4,6 @@ #include "arm/kirkwood-openblocks_a6.dts" -/ { - gpio-leds { - led-green { - barebox,default-trigger = "heartbeat"; - }; - }; +&{/gpio-leds/led-green} { + barebox,default-trigger = "heartbeat"; }; diff --git a/arch/arm/dts/kirkwood-topkick-bb.dts b/arch/arm/dts/kirkwood-topkick-bb.dts index 20b74b111d..c70d654c52 100644 --- a/arch/arm/dts/kirkwood-topkick-bb.dts +++ b/arch/arm/dts/kirkwood-topkick-bb.dts @@ -5,10 +5,6 @@ #include "arm/kirkwood-topkick.dts" -/ { - gpio-leds { - system { - barebox,default-trigger = "heartbeat"; - }; - }; +&{/gpio-leds/system} { + barebox,default-trigger = "heartbeat"; }; diff --git a/arch/arm/dts/module-mb7707.dts b/arch/arm/dts/module-mb7707.dts index 94a3373fc1..9a0f74997d 100644 --- a/arch/arm/dts/module-mb7707.dts +++ b/arch/arm/dts/module-mb7707.dts @@ -6,7 +6,8 @@ model = "Module MB 77.07"; compatible = "module,mb7707"; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x8000000>; }; }; diff --git a/arch/arm/dts/rk3288-phycore-som.dts b/arch/arm/dts/rk3288-phycore-som.dts index 65c53895c4..67073b2d83 100644 --- a/arch/arm/dts/rk3288-phycore-som.dts +++ b/arch/arm/dts/rk3288-phycore-som.dts @@ -20,7 +20,8 @@ model = "phycore-rk3288"; compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288"; - memory { + memory@0 { + device_type = "memory"; reg = <0x0 0x0 0x0 0x40000000>; }; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 51e964fc0f..15682f9d27 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -6,3 +6,13 @@ mmc1 = &sdmmc1; }; }; + +/delete-node/ &{/memory@20000000}; + +&sdmmc0 { + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; +}; + +&sdmmc1 { + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; +}; diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts b/arch/arm/dts/socfpga_arria10_achilles.dts index 4c6460fb60..6071dbfb49 100644 --- a/arch/arm/dts/socfpga_arria10_achilles.dts +++ b/arch/arm/dts/socfpga_arria10_achilles.dts @@ -106,44 +106,22 @@ }; }; }; +}; - bootstate: bootstate { - compatible = "barebox,bootstate"; - backend-type = "state"; // or "nv", or "efivar" - backend = <&state>; - - system0 { - default_attempts = <3>; - }; - - system1 { - default_attempts = <3>; - }; +&{/soc/clkmgr@ffd04000/clocks/osc1} { + clock-frequency = <25000000>; +}; - factory { - default_attempts = <3>; - }; - }; +&{/soc/clkmgr@ffd04000/clocks/cb_intosc_hs_div2_clk} { + clock-frequency = <0>; +}; - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; +&{/soc/clkmgr@ffd04000/clocks/cb_intosc_ls_clk} { + clock-frequency = <60000000>; +}; - cb_intosc_hs_div2_clk { - clock-frequency = <0>; - }; - cb_intosc_ls_clk { - clock-frequency = <60000000>; - }; - f2s_free_clk { - clock-frequency = <200000000>; - }; - }; - }; - }; +&{/soc/clkmgr@ffd04000/clocks/f2s_free_clk} { + clock-frequency = <200000000>; }; &gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts index 40a7a9c488..427f150fb4 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -31,10 +31,4 @@ file-path = "barebox.env"; }; }; - - leds: gpio-leds { - }; - - buttons: gpio-keys { - }; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index a647694405..ca11492de5 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1,10 +1,5 @@ / { - clocks { - /* Needed to let barebox find the clock nodes */ - compatible = "simple-bus"; - }; - aliases { gpio0 = &gpioa; gpio1 = &gpiob; @@ -33,16 +28,33 @@ pwm15 = &{/soc/timer@44006000/pwm}; pwm16 = &{/soc/timer@44007000/pwm}; pwm17 = &{/soc/timer@44008000/pwm}; + tamp.reboot_mode = &reboot_mode_tamp; }; - psci { - compatible = "arm,psci-0.2"; +}; + +&{/clocks} { + /* Needed to let barebox find the clock nodes */ + compatible = "simple-bus"; +}; + +&{/soc} { + memory-controller@5a003000 { + compatible = "st,stm32mp1-ddr"; + reg = <0x5a003000 0x1000>; }; - soc { - memory-controller@5a003000 { - compatible = "st,stm32mp1-ddr"; - reg = <0x5a003000 0x1000>; + tamp@5c00a000 { + compatible = "simple-bus", "syscon", "simple-mfd"; + reg = <0x5c00a000 0x400>; + + reboot_mode_tamp: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x150>; /* reg20 */ + mask = <0xff>; + mode-normal = <0>; + mode-loader = <0xBB>; + mode-recovery = <0xBC>; }; }; }; diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index f2cafae66b..7a907cc314 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -5,4 +5,4 @@ */ #include <arm/stm32mp157a-dk1.dts> -#include "stm32mp157a-dk1.dtsi" +#include "stm32mp15xx-dkx.dtsi" diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 6e73162ea4..98525abd71 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -5,4 +5,4 @@ */ #include <arm/stm32mp157c-dk2.dts> -#include "stm32mp157a-dk1.dtsi" +#include "stm32mp15xx-dkx.dtsi" diff --git a/arch/arm/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/dts/stm32mp157c-lxa-mc1.dts index 57baaf4005..f89c085280 100644 --- a/arch/arm/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/dts/stm32mp157c-lxa-mc1.dts @@ -3,7 +3,7 @@ * Copyright (C) 2020 Ahmad Fatoum, Pengutronix */ -#include "stm32mp157c-lxa-mc1.dtsi" +#include <arm/stm32mp157c-lxa-mc1.dts> #include "stm32mp151.dtsi" / { diff --git a/arch/arm/dts/stm32mp157c-lxa-mc1.dtsi b/arch/arm/dts/stm32mp157c-lxa-mc1.dtsi deleted file mode 100644 index 6603cf280e..0000000000 --- a/arch/arm/dts/stm32mp157c-lxa-mc1.dtsi +++ /dev/null @@ -1,362 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ -/* - * Copyright (C) 2020 STMicroelectronics - All Rights Reserved - * Copyright (C) 2020 Ahmad Fatoum, Pengutronix - */ - -/dts-v1/; - -#include <arm/stm32mp157.dtsi> -#include "stm32mp15xx-osd32.dtsi" -#include <arm/stm32mp15xxac-pinctrl.dtsi> - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pwm/pwm.h> - -/ { - model = "Linux Automation MC-1 board"; - compatible = "lxa,stm32mp157c-mc1", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - mmc0 = &sdmmc1; - mmc1 = &sdmmc2; - serial0 = &uart4; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&backlight_pwm 1 100000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 31 63 95 127 159 191 223 255>; - default-brightness-level = <7>; - power-supply = <®_5v2>; /* 3V3_BACKLIGHT */ - }; - - chosen { - stdout-path = &uart4; - }; - - led-act { - compatible = "gpio-leds"; - - led-green { - label = "mc1:green:act"; - gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - led-rgb { - compatible = "pwm-leds"; - - led-red { - label = "mc1:red:rgb"; - pwms = <&leds_pwm 1 1000000 0>; - max-brightness = <255>; - active-low; - }; - - led-green { - label = "mc1:green:rgb"; - pwms = <&leds_pwm 2 1000000 0>; - max-brightness = <255>; - active-low; - }; - - led-blue { - label = "mc1:blue:rgb"; - pwms = <&leds_pwm 3 1000000 0>; - max-brightness = <255>; - active-low; - }; - }; - - panel: panel { - compatible = "edt,etm0700g0edh6", "simple-panel"; - backlight = <&backlight>; - enable-gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - - port { - panel_input: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - }; - - reg_3v3: regulator_3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&v3v3>; - }; - - /* supplied by either debug board or PoE */ - reg_5v2: regulator_5v2 { - compatible = "regulator-fixed"; - regulator-name = "5V2"; - regulator-min-microvolt = <5200000>; - regulator-max-microvolt = <5200000>; - regulator-always-on; - }; -}; - -ðernet0 { - pinctrl-names = "default"; - pinctrl-0 = <ðernet0_rgmii_mc1pins_b>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy>; - status = "okay"; - - mdio0 { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@3 { /* KSZ9031RN */ - reg = <3>; - reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ - interrupt-parent = <&gpioa>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */ - rxc-skew-ps = <1860>; - txc-skew-ps = <1860>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - micrel,force-master; - }; - }; -}; - -&gpioz { - gpio-line-names = "HWID0", "HWID1", "HWID2", "HWID3", "", "", - "HWID4", "HWID5"; -}; - -&gpu { - status = "okay"; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_mc1pins_b>; - clock-frequency = <400000>; - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - interrupt-parent = <&gpiod>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; /* TOUCH_INT# */ - vcc-supply = <®_3v3>; - reg = <0x38>; - reset-gpios = <&gpiof 8 GPIO_ACTIVE_LOW>; /* TOUCH_RESET# */ - touchscreen-size-x = <1792>; - touchscreen-size-y = <1024>; - wakeup-source; - }; -}; - -<dc { - pinctrl-names = "default"; - pinctrl-0 = <<dc_mc1pins_c>; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - ltdc_ep0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; -}; - -&pmic { - regulators { - buck4-supply = <®_5v2>; /* VIN */ - ldo2-supply = <®_5v2>; /* PMIC_LDO25IN */ - ldo5-supply = <®_5v2>; /* PMIC_LDO25IN */ - boost-supply = <®_5v2>; /* PMIC_BSTIN */ - pwr_sw2-supply = <&bst_out>; /* PMIC_SWIN */ - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - bus-width = <4>; - cd-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; - disable-wp; - no-1-8-v; - st,neg-edge; - vmmc-supply = <®_3v3>; - status = "okay"; -}; - -&sdmmc1_b4_pins_a { - /* - * board lacks external pull-ups on SDMMC lines. Class 10 SD refuses to - * work, thus enable internal pull-ups. - */ - pins1 { - /delete-property/ bias-disable; - bias-pull-up; - }; - pins2 { - /delete-property/ bias-disable; - bias-pull-up; - }; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_mc1pins_b>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_mc1pins_b>; - bus-width = <8>; - no-1-8-v; - no-sd; - no-sdio; - non-removable; - st,neg-edge; - vmmc-supply = <®_3v3>; - status = "okay"; -}; - -&timers3 { - status = "okay"; - - backlight_pwm: pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_mc1pins_b>; - status = "okay"; - }; -}; - -&timers5 { - status = "okay"; - - leds_pwm: pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm5_mc1pins_b>; - status = "okay"; - }; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; - status = "okay"; -}; - -&pinctrl { - ethernet0_rgmii_mc1pins_b: mc1-rgmii-1 { - pins1 { - pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ - <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ - <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ - bias-disable; - }; - }; - - i2c5_mc1pins_b: mc1-i2c5-1 { - pins { - pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */ - <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - ltdc_mc1pins_c: mc1-ltdc-2 { - pins1 { - pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */ - <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */ - <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */ - <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */ - <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */ - <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */ - <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */ - <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */ - <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */ - <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */ - <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */ - <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */ - <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */ - <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */ - <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */ - <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */ - <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */ - <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */ - <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */ - <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */ - <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - pwm3_mc1pins_b: mc1-pwm3-1 { - pins { - pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm5_mc1pins_b: mc1-pwm5-1 { - pins { - pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */ - <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */ - <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - }; - - sdmmc2_d47_mc1pins_b: mc1-sdmmc2-d47-1 { - pins { - pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ - <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ - <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - }; - -}; diff --git a/arch/arm/dts/stm32mp15xx-osd32.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi index 8750835033..1e5bd8bccb 100644 --- a/arch/arm/dts/stm32mp15xx-osd32.dtsi +++ b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi @@ -1,14 +1,27 @@ -/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) 2020 STMicroelectronics - All Rights Reserved - * Copyright (C) 2020 Ahmad Fatoum, Pengutronix + * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>. */ -#include <arm/stm32mp15-pinctrl.dtsi> +/dts-v1/; +#include <arm/stm32mp157.dtsi> +#include <arm/stm32mp15xc.dtsi> +#include <arm/stm32mp15-pinctrl.dtsi> +#include <arm/stm32mp15xxac-pinctrl.dtsi> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/mfd/st,stpmic1.h> / { + model = "Seeed Studio Odyssey-STM32MP157C SOM"; + compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + reserved-memory { #address-cells = <1>; #size-cells = <1>; @@ -49,22 +62,38 @@ reg = <0x38000000 0x10000>; no-map; }; + + gpu_reserved: gpu@d4000000 { + reg = <0xd4000000 0x4000000>; + no-map; + }; }; - reg_sip_eeprom: regulator_eeprom { - compatible = "regulator-fixed"; - regulator-name = "sip_eeprom"; - regulator-always-on; + led { + compatible = "gpio-leds"; + led-blue { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; }; }; -&i2c4 { +&gpu { + contiguous-area = <&gpu_reserved>; + status = "okay"; +}; + +&i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - clock-frequency = <400000>; + pinctrl-0 = <&i2c2_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; pmic: stpmic@33 { compatible = "st,stpmic1"; @@ -75,14 +104,15 @@ regulators { compatible = "st,stpmic1-regulators"; - ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; ldo6-supply = <&v3v3>; pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; vddcore: buck1 { regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; @@ -123,7 +153,6 @@ regulator-max-microvolt = <1800000>; regulator-always-on; interrupts = <IT_CURLIM_LDO1 0>; - }; v3v3_hdmi: ldo2 { @@ -132,7 +161,6 @@ regulator-max-microvolt = <3300000>; regulator-always-on; interrupts = <IT_CURLIM_LDO2 0>; - }; vtt_ddr: ldo3 { @@ -164,7 +192,6 @@ regulator-max-microvolt = <1200000>; regulator-always-on; interrupts = <IT_CURLIM_LDO6 0>; - }; vref_ddr: vref_ddr { @@ -173,47 +200,46 @@ regulator-over-current-protection; }; - bst_out: boost { + bst_out: boost { regulator-name = "bst_out"; interrupts = <IT_OCP_BOOST 0>; - }; + }; vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = <IT_OCP_OTG 0>; - regulator-active-discharge; - }; + }; - vbus_sw: pwr_sw2 { + vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = <IT_OCP_SWOUT 0>; regulator-active-discharge; - }; + }; }; onkey { compatible = "st,stpmic1-onkey"; - interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; }; - pmic_watchdog: watchdog { + watchdog { compatible = "st,stpmic1-wdt"; status = "disabled"; }; }; - - sip_eeprom: eeprom@50 { - compatible = "atmel,24c32"; - vcc-supply = <®_sip_eeprom>; - reg = <0x50>; - }; }; &ipcc { status = "okay"; }; +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + &m4_rproc { memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>; @@ -227,3 +253,42 @@ &rng1 { status = "okay"; }; + +&rtc { + status = "okay"; +}; + +&sdmmc2_d47_pins_a { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + }; +}; + +&sdmmc2_d47_sleep_pins_a { + pins { + pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ + }; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts new file mode 100644 index 0000000000..0e395bdec9 --- /dev/null +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Ahmad Fatoum, Pengutronix + */ + +#include "stm32mp157c-odyssey.dtsi" +#include "stm32mp151.dtsi" + +/ { + chosen { + environment-sd { + compatible = "barebox,environment"; + device-path = &sdmmc1, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &sdmmc2, "partname:barebox-environment"; + status = "disabled"; + }; + }; +}; + +&phy0 { + reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/stm32mp157c-odyssey.dtsi b/arch/arm/dts/stm32mp157c-odyssey.dtsi new file mode 100644 index 0000000000..85a4f313ae --- /dev/null +++ b/arch/arm/dts/stm32mp157c-odyssey.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>. + */ + +/dts-v1/; + +#include "stm32mp157c-odyssey-som.dtsi" + +/ { + model = "Seeed Studio Odyssey-STM32MP157C Board"; + compatible = "seeed,stm32mp157c-odyssey", + "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@7 { /* KSZ9031RN */ + reg = <7>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp157a-dk1.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index baaf60b18f..173e64e04c 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -14,17 +14,17 @@ device-path = &sdmmc1, "partname:barebox-environment"; }; }; +}; - led { - red { - label = "error"; - gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - status = "okay"; - }; - - blue { - default-state = "on"; - }; +&{/led} { + led-red { + label = "error"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + status = "okay"; }; }; + +&{/led/led-blue} { + default-state = "on"; +}; diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts index 00eef6cacd..027c2e5905 100644 --- a/arch/arm/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/dts/tegra124-jetson-tk1.dts @@ -7,11 +7,7 @@ environment { compatible = "barebox,environment"; - device-path = &emmc, "partname:boot1"; + device-path = &{/mmc@700b0600}, "partname:boot1"; /* eMMC */ }; }; - - /* eMMC */ - emmc: sdhci@700b0600 { - }; }; diff --git a/arch/arm/dts/tegra20-colibri-iris.dts b/arch/arm/dts/tegra20-colibri-iris.dts index 9c615816ca..da5ef7a7e7 100644 --- a/arch/arm/dts/tegra20-colibri-iris.dts +++ b/arch/arm/dts/tegra20-colibri-iris.dts @@ -75,26 +75,22 @@ vqmmc-supply = <&vcc_sd_reg>; }; - regulators { - regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_host_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - }; + regulator_usb_host_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + }; - vcc_sd_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; + vcc_sd_reg: regulator_vcc_sd { + compatible = "regulator-fixed"; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; }; }; diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts index acbdd318b1..7a9ced6cef 100644 --- a/arch/arm/dts/tegra30-beaver.dts +++ b/arch/arm/dts/tegra30-beaver.dts @@ -22,10 +22,6 @@ }; }; - memory { - reg = <0x80000000 0x7ff00000>; - }; - pcie-controller@00003000 { status = "okay"; pex-clk-supply = <&sys_3v3_pexs_reg>; @@ -936,3 +932,7 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; + +&{/memory@80000000} { + reg = <0x80000000 0x7ff00000>; +}; diff --git a/arch/arm/dts/tps65217.dtsi b/arch/arm/dts/tps65217.dtsi deleted file mode 100644 index a63272422d..0000000000 --- a/arch/arm/dts/tps65217.dtsi +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/tps65217.pdf - */ - -&tps { - compatible = "ti,tps65217"; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - dcdc1_reg: regulator@0 { - reg = <0>; - regulator-compatible = "dcdc1"; - }; - - dcdc2_reg: regulator@1 { - reg = <1>; - regulator-compatible = "dcdc2"; - }; - - dcdc3_reg: regulator@2 { - reg = <2>; - regulator-compatible = "dcdc3"; - }; - - ldo1_reg: regulator@3 { - reg = <3>; - regulator-compatible = "ldo1"; - }; - - ldo2_reg: regulator@4 { - reg = <4>; - regulator-compatible = "ldo2"; - }; - - ldo3_reg: regulator@5 { - reg = <5>; - regulator-compatible = "ldo3"; - }; - - ldo4_reg: regulator@6 { - reg = <6>; - regulator-compatible = "ldo4"; - }; - }; -}; diff --git a/arch/arm/dts/versatile-pb.dts b/arch/arm/dts/versatile-pb.dts index 8c80f8c293..d374f54291 100644 --- a/arch/arm/dts/versatile-pb.dts +++ b/arch/arm/dts/versatile-pb.dts @@ -3,8 +3,8 @@ / { model = "ARM Versatile PB"; compatible = "arm,versatile-pb"; +}; - memory { - reg = <0x0 0x04000000>; - }; +&{/memory} { + reg = <0x0 0x04000000>; }; diff --git a/arch/arm/dts/vexpress-v2p-ca15.dts b/arch/arm/dts/vexpress-v2p-ca15.dts index 211eaccb62..78d0025909 100644 --- a/arch/arm/dts/vexpress-v2p-ca15.dts +++ b/arch/arm/dts/vexpress-v2p-ca15.dts @@ -6,22 +6,25 @@ device-path = &barebox_env; }; - smb@8000000 { - motherboard { - flash@0,00000000 { - #address-cells = <1>; - #size-cells = <1>; + chosen { + stdout-path = &v2m_serial0; + }; +}; - partition@0 { - label = "barebox"; - reg = <0x0 0x80000>; - }; +&nor_flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; - barebox_env: partition@80000 { - label = "barebox-environment"; - reg = <0x80000 0x80000>; - }; - }; + barebox_env: partition@80000 { + label = "barebox-environment"; + reg = <0x80000 0x80000>; }; }; }; diff --git a/arch/arm/dts/vexpress-v2p-ca9.dts b/arch/arm/dts/vexpress-v2p-ca9.dts index b13c114f0c..8be04b174b 100644 --- a/arch/arm/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/dts/vexpress-v2p-ca9.dts @@ -10,32 +10,8 @@ state = &state; }; - smb@4000000 { - motherboard { - flash@0,00000000 { - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - - partition@0 { - label = "barebox"; - reg = <0x0 0x80000>; - }; - - barebox_env: partition@80000 { - label = "barebox-environment"; - reg = <0x80000 0x80000>; - }; - - state_storage: partition@100000 { - label = "barebox-state"; - reg = <0x100000 0x100000>; - }; - }; - }; - }; + chosen { + stdout-path = &v2m_serial0; }; /* State: mutable part */ @@ -92,3 +68,26 @@ }; }; }; + +&{/bus@4000000/motherboard/flash@0,00000000} { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + + barebox_env: partition@80000 { + label = "barebox-environment"; + reg = <0x80000 0x80000>; + }; + + state_storage: partition@100000 { + label = "barebox-state"; + reg = <0x100000 0x100000>; + }; + }; +}; diff --git a/arch/arm/dts/vf610-zii-cfu1.dts b/arch/arm/dts/vf610-zii-cfu1.dts index 70cd9d1ba9..9226930612 100644 --- a/arch/arm/dts/vf610-zii-cfu1.dts +++ b/arch/arm/dts/vf610-zii-cfu1.dts @@ -26,6 +26,10 @@ }; }; +&{/gpio-leds/led-status} { + linux,default-trigger = "heartbeat"; +}; + &i2c0 { fiber_eeprom0: eeprom@50 { compatible = "atmel,24c04"; diff --git a/arch/arm/dts/vf610-zii-dev-rev-b.dts b/arch/arm/dts/vf610-zii-dev-rev-b.dts index abc5237080..2949042bc3 100644 --- a/arch/arm/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/dts/vf610-zii-dev-rev-b.dts @@ -8,16 +8,12 @@ #include "vf610-zii-dev.dtsi" -/ { - spi0 { - flash@0 { - #address-cells = <1>; - #size-cells = <0>; +&{/spi0/flash@0} { + #address-cells = <1>; + #size-cells = <0>; - partition@0 { - label = "bootloader"; - reg = <0x0 0x100000>; - }; - }; + partition@0 { + label = "bootloader"; + reg = <0x0 0x100000>; }; }; diff --git a/arch/arm/dts/vf610-zii-dev-rev-c.dts b/arch/arm/dts/vf610-zii-dev-rev-c.dts index 62c70c8905..c1b3bc86dc 100644 --- a/arch/arm/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/dts/vf610-zii-dev-rev-c.dts @@ -17,6 +17,8 @@ */ switch0-eeprom = &switch0; switch1-eeprom = &switch1; + fiber-eeprom0 = &fiber_eeprom0; + fiber-eeprom1 = &fiber_eeprom1; }; }; @@ -31,3 +33,19 @@ }; }; }; + +&sff2_i2c { + fiber_eeprom0: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber0"; + }; +}; + +&sff3_i2c { + fiber_eeprom1: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber1"; + }; +}; diff --git a/arch/arm/dts/virt2real.dts b/arch/arm/dts/virt2real.dts index 8f8c65ba7a..3b543b6e93 100644 --- a/arch/arm/dts/virt2real.dts +++ b/arch/arm/dts/virt2real.dts @@ -5,7 +5,7 @@ / { model = "virt2real"; - memory { + memory@82000000 { device_type = "memory"; reg = <0x82000000 0x01000000>; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index c03112d7a0..8b8dd84c1d 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -8,5 +8,4 @@ */ #include <arm64/xilinx/zynqmp-zcu104-revA.dts> -#include "zynqmp.dtsi" #include "zynqmp-clk.dtsi" diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi deleted file mode 100644 index 59984ee758..0000000000 --- a/arch/arm/dts/zynqmp.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP - * - * (C) Copyright 2014 - 2015, Xilinx, Inc. - * - * Michal Simek <michal.simek@xilinx.com> - */ - -/ { - firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - method = "smc"; - }; - }; -}; diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 6116e4893c..95c6768de8 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -1,12 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 1996-2000 Russell King */ + /* * arch/arm/include/asm/assembler.h * - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * This file contains arm architecture specific defines * for the different processors. * diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index 9b79506b59..cfc359a5ce 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -1,111 +1,9 @@ -/* - * linux/include/asm-arm/atomic.h - * - * Copyright (c) 1996 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 27-06-1996 RMK Created - * 13-04-1997 RMK Made functions atomic! - * 07-12-1997 RMK Upgraded for v2.1. - * 26-08-1998 PJB Added #ifdef __KERNEL__ - */ +// SPDX-License-Identifier: GPL-2.0-only + #ifndef __ASM_ARM_ATOMIC_H #define __ASM_ARM_ATOMIC_H -#ifdef CONFIG_SMP -#error SMP not supported -#endif - -typedef struct { volatile int counter; } atomic_t; - -#define ATOMIC_INIT(i) { (i) } - -#ifdef __KERNEL__ #include <asm/proc-armv/system.h> +#include <asm-generic/atomic.h> -#define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) - -static inline void atomic_add(int i, volatile atomic_t *v) -{ - unsigned long flags = 0; - - local_irq_save(flags); - v->counter += i; - local_irq_restore(flags); -} - -static inline void atomic_sub(int i, volatile atomic_t *v) -{ - unsigned long flags = 0; - - local_irq_save(flags); - v->counter -= i; - local_irq_restore(flags); -} - -static inline void atomic_inc(volatile atomic_t *v) -{ - unsigned long flags = 0; - - local_irq_save(flags); - v->counter += 1; - local_irq_restore(flags); -} - -static inline void atomic_dec(volatile atomic_t *v) -{ - unsigned long flags = 0; - - local_irq_save(flags); - v->counter -= 1; - local_irq_restore(flags); -} - -static inline int atomic_dec_and_test(volatile atomic_t *v) -{ - unsigned long flags = 0; - int val; - - local_irq_save(flags); - val = v->counter; - v->counter = val -= 1; - local_irq_restore(flags); - - return val == 0; -} - -static inline int atomic_add_negative(int i, volatile atomic_t *v) -{ - unsigned long flags = 0; - int val; - - local_irq_save(flags); - val = v->counter; - v->counter = val += i; - local_irq_restore(flags); - - return val < 0; -} - -static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) -{ - unsigned long flags = 0; - - local_irq_save(flags); - *addr &= ~mask; - local_irq_restore(flags); -} - -/* Atomic operations are already serializing on ARM */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - -#endif #endif diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h index 9277b84a19..f81257f896 100644 --- a/arch/arm/include/asm/barebox-arm.h +++ b/arch/arm/include/asm/barebox-arm.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> @@ -6,17 +7,6 @@ * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Alex Zuepke <azu@sysgo.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #ifndef _BAREBOX_ARM_H_ diff --git a/arch/arm/include/asm/cache-l2x0.h b/arch/arm/include/asm/cache-l2x0.h index 9bb245b0be..e325bbbff6 100644 --- a/arch/arm/include/asm/cache-l2x0.h +++ b/arch/arm/include/asm/cache-l2x0.h @@ -1,18 +1,7 @@ -/* - * arch/arm/include/asm/hardware/cache-l2x0.h - * - * Copyright (C) 2007 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2007 ARM Limited */ + +/* arch/arm/include/asm/hardware/cache-l2x0.h */ #ifndef __ASM_ARM_HARDWARE_L2X0_H #define __ASM_ARM_HARDWARE_L2X0_H diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h index 15999a524d..08a9fc43b7 100644 --- a/arch/arm/include/asm/dma.h +++ b/arch/arm/include/asm/dma.h @@ -1,9 +1,5 @@ -/* - * Copyright (C) 2012 by Marc Kleine-Budde <mkl@pengutronix.de> - * - * This file is released under the GPLv2 - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2012 Marc Kleine-Budde <mkl@pengutronix.de> */ #include <common.h> diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index b98b3e52a4..3def567699 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -30,6 +30,9 @@ typedef struct user_fp elf_fpregset_t; #define R_ARM_CALL 28 #define R_ARM_JUMP24 29 +#define R_ARM_THM_CALL 10 +#define R_ARM_THM_JUMP24 30 + /* * These are used to set parameters in the core dumps. */ diff --git a/arch/arm/include/asm/errata.h b/arch/arm/include/asm/errata.h index f020369916..9bb0e650c7 100644 --- a/arch/arm/include/asm/errata.h +++ b/arch/arm/include/asm/errata.h @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2014 Lucas Stach, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2014 Lucas Stach, Pengutronix */ static inline void enable_arm_errata_709718_war(void) { diff --git a/arch/arm/include/asm/esr.h b/arch/arm/include/asm/esr.h index 77eeb2cc64..52347b6862 100644 --- a/arch/arm/include/asm/esr.h +++ b/arch/arm/include/asm/esr.h @@ -1,19 +1,7 @@ -/* - * Copyright (C) 2013 - ARM Ltd - * Author: Marc Zyngier <marc.zyngier@arm.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2013 ARM Ltd */ + +/* Author: Marc Zyngier */ #ifndef __ASM_ESR_H #define __ASM_ESR_H diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h index 3e3996a99e..ab6911f914 100644 --- a/arch/arm/include/asm/hardware/sp810.h +++ b/arch/arm/include/asm/hardware/sp810.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + /* * arch/arm/include/asm/hardware/sp810.h * @@ -5,10 +7,6 @@ * * Copyright (C) 2009 ST Microelectronics * Viresh Kumar <viresh.linux@gmail.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #ifndef __ASM_ARM_SP810_H diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 56db546341..072b47317c 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -4,6 +4,7 @@ #define IO_SPACE_LIMIT 0 #include <asm-generic/io.h> +#include <asm-generic/bitio.h> /* * String version of IO memory access ops: @@ -12,63 +13,6 @@ extern void memcpy_fromio(void *, const volatile void __iomem *, size_t); extern void memcpy_toio(volatile void __iomem *, const void *, size_t); extern void memset_io(volatile void __iomem *, int, size_t); -/* - * Clear and set bits in one shot. These macros can be used to clear and - * set multiple bits in a register using a single call. These macros can - * also be used to set a multiple-bit bit pattern using a mask, by - * specifying the mask in the 'clear' parameter and the new bit pattern - * in the 'set' parameter. - */ - -#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) -#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a)) - -#define out_le64(a,v) out_arch(q,le64,a,v) -#define out_le32(a,v) out_arch(l,le32,a,v) -#define out_le16(a,v) out_arch(w,le16,a,v) - -#define in_le64(a) in_arch(q,le64,a) -#define in_le32(a) in_arch(l,le32,a) -#define in_le16(a) in_arch(w,le16,a) - -#define out_be32(a,v) out_arch(l,be32,a,v) -#define out_be16(a,v) out_arch(w,be16,a,v) - -#define in_be32(a) in_arch(l,be32,a) -#define in_be16(a) in_arch(w,be16,a) - -#define out_8(a,v) __raw_writeb(v,a) -#define in_8(a) __raw_readb(a) - -#define clrbits(type, addr, clear) \ - out_##type((addr), in_##type(addr) & ~(clear)) - -#define setbits(type, addr, set) \ - out_##type((addr), in_##type(addr) | (set)) - -#define clrsetbits(type, addr, clear, set) \ - out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) - -#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) -#define setbits_be32(addr, set) setbits(be32, addr, set) -#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) - -#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) -#define setbits_le32(addr, set) setbits(le32, addr, set) -#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) - -#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) -#define setbits_be16(addr, set) setbits(be16, addr, set) -#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) - -#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) -#define setbits_le16(addr, set) setbits(le16, addr, set) -#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) - -#define clrbits_8(addr, clear) clrbits(8, addr, clear) -#define setbits_8(addr, set) setbits(8, addr, set) -#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) - static inline void *phys_to_virt(unsigned long phys) { return (void *)phys; diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h index 5b4d1a3f36..3ce39bf82b 100644 --- a/arch/arm/include/asm/module.h +++ b/arch/arm/include/asm/module.h @@ -1,13 +1,34 @@ #ifndef _ASM_ARM_MODULE_H #define _ASM_ARM_MODULE_H -struct mod_arch_specific -{ - int foo; +#include <asm-generic/module.h> + +struct unwind_table; + +#ifdef CONFIG_ARM_UNWIND +enum { + ARM_SEC_INIT, + ARM_SEC_DEVINIT, + ARM_SEC_CORE, + ARM_SEC_EXIT, + ARM_SEC_DEVEXIT, + ARM_SEC_HOT, + ARM_SEC_UNLIKELY, + ARM_SEC_MAX, +}; +#endif + +struct mod_arch_specific { +#ifdef CONFIG_ARM_UNWIND + struct unwind_table *unwind[ARM_SEC_MAX]; +#endif +#ifdef CONFIG_ARM_MODULE_PLTS + struct elf32_shdr *plt; + int plt_count; +#endif }; -#define Elf_Shdr Elf32_Shdr -#define Elf_Sym Elf32_Sym -#define Elf_Ehdr Elf32_Ehdr +struct module; +u32 get_module_plt(struct module *mod, unsigned long loc, Elf32_Addr val); #endif /* _ASM_ARM_MODULE_H */ diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h index efcfdf92d9..3d98a0b566 100644 --- a/arch/arm/include/asm/opcodes-virt.h +++ b/arch/arm/include/asm/opcodes-virt.h @@ -1,21 +1,8 @@ -/* - * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions - * Copyright (C) 2012 Linaro Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2012 Linaro Limited */ + +/* opcodes-virt.h: Opcode definitions for the ARM virtualization extensions */ + #ifndef __ASM_ARM_OPCODES_VIRT_H #define __ASM_ARM_OPCODES_VIRT_H diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h index a78bf5d2c5..64e171a818 100644 --- a/arch/arm/include/asm/opcodes.h +++ b/arch/arm/include/asm/opcodes.h @@ -1,10 +1,6 @@ -/* - * arch/arm/include/asm/opcodes.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* arch/arm/include/asm/opcodes.h */ #ifndef __ASM_ARM_OPCODES_H #define __ASM_ARM_OPCODES_H diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index fd1521d5cb..5d6a68c0a6 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -1,12 +1,8 @@ -/* - * arch/arm/include/asm/pgtable-hwdef.h - * - * Copyright (C) 1995-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 1995-2002 Russell King */ + +/* arch/arm/include/asm/pgtable-hwdef.h */ + #ifndef _ASMARM_PGTABLE_HWDEF_H #define _ASMARM_PGTABLE_HWDEF_H diff --git a/arch/arm/include/asm/pgtable64.h b/arch/arm/include/asm/pgtable64.h index d142612d0d..dbec61753b 100644 --- a/arch/arm/include/asm/pgtable64.h +++ b/arch/arm/include/asm/pgtable64.h @@ -1,18 +1,6 @@ -/* - * Copyright (C) 2012 ARM Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2012 ARM Ltd. */ + #ifndef __ASM_PGTABLE64_H #define __ASM_PGTABLE64_H diff --git a/arch/arm/include/asm/proc-armv/system.h b/arch/arm/include/asm/proc-armv/system.h index c61374e9f2..75ab503d9d 100644 --- a/arch/arm/include/asm/proc-armv/system.h +++ b/arch/arm/include/asm/proc-armv/system.h @@ -1,12 +1,8 @@ -/* - * linux/include/asm-arm/proc-armv/system.h - * - * Copyright (C) 1996 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText 1996 Russell King */ + +/* linux/include/asm-arm/proc-armv/system.h */ + #ifndef __ASM_PROC_SYSTEM_H #define __ASM_PROC_SYSTEM_H diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index b616e4b20e..3c1d046eb9 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -1,19 +1,7 @@ -/* - * Copyright (C) 2013 - ARM Ltd - * Author: Marc Zyngier <marc.zyngier@arm.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2013 ARM Ltd */ + +/* Author: Marc Zyngier */ #ifndef __ARM_PSCI_H__ #define __ARM_PSCI_H__ diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 042e0cef70..e0304501cc 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -1,12 +1,8 @@ -/* - * arch/arm/include/asm/ptrace.h - * - * Copyright (C) 1996-2003 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 1996-2003 Russell King */ + +/* arch/arm/include/asm/ptrace.h */ + #ifndef __ASM_ARM_PTRACE_H #define __ASM_ARM_PTRACE_H diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index 6ce35fb8d3..954b777721 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -1,10 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 1997-1999 Russell King */ + /* - * Copyright (C) 1997-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Structure passed to kernel to tell it about the * hardware it's running on. See linux/Documentation/arm/Setup * for more info. diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h index 435647abda..cd79f63402 100644 --- a/arch/arm/include/asm/string.h +++ b/arch/arm/include/asm/string.h @@ -10,4 +10,7 @@ extern void *memset(void *, int, __kernel_size_t); #endif +extern void *__memcpy(void *, const void *, __kernel_size_t); +extern void *__memset(void *, int, __kernel_size_t); + #endif diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h index 9c21066882..22b9642655 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -1,52 +1,6 @@ #ifndef __ASM_ARM_TYPES_H #define __ASM_ARM_TYPES_H -#ifndef __ASSEMBLY__ - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#include <asm/bitsperlong.h> - -#ifndef __ASSEMBLY__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ +#include <asm-generic/int-ll64.h> #endif diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h index 13a2bfffa7..5501d7f703 100644 --- a/arch/arm/include/asm/unified.h +++ b/arch/arm/include/asm/unified.h @@ -1,18 +1,7 @@ -/* - * include/asm-arm/unified.h - Unified Assembler Syntax helper macros - * - * Copyright (C) 2008 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2008 ARM Limited */ + +/* Unified Assembler Syntax helper macros */ #ifndef __ASM_UNIFIED_H #define __ASM_UNIFIED_H diff --git a/arch/arm/include/asm/unwind.h b/arch/arm/include/asm/unwind.h index a6f3a91743..319527ec9b 100644 --- a/arch/arm/include/asm/unwind.h +++ b/arch/arm/include/asm/unwind.h @@ -1,18 +1,7 @@ -/* - * arch/arm/include/asm/unwind.h - * - * Copyright (C) 2008 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2008 ARM Limited */ + +/* arch/arm/include/asm/unwind.h */ #ifndef __ASM_UNWIND_H #define __ASM_UNWIND_H diff --git a/arch/arm/lib32/Makefile b/arch/arm/lib32/Makefile index 597bc07905..ec6a3aea67 100644 --- a/arch/arm/lib32/Makefile +++ b/arch/arm/lib32/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memset.o obj-$(CONFIG_ARM_UNWIND) += unwind.o obj-$(CONFIG_ARM_SEMIHOSTING) += semihosting-trap.o semihosting.o obj-$(CONFIG_MODULES) += module.o +obj-$(CONFIG_ARM_MODULE_PLTS) += module-plts.o extra-y += barebox.lds pbl-y += lib1funcs.o diff --git a/arch/arm/lib32/barebox.lds.S b/arch/arm/lib32/barebox.lds.S index ed279279a2..54d9b3e381 100644 --- a/arch/arm/lib32/barebox.lds.S +++ b/arch/arm/lib32/barebox.lds.S @@ -77,7 +77,9 @@ SECTIONS _sdata = .; . = ALIGN(4); - .data : { *(.data*) } + .data : { *(.data*) + CONSTRUCTORS + } .barebox_imd : { BAREBOX_IMD } diff --git a/arch/arm/lib32/bootm.c b/arch/arm/lib32/bootm.c index 971ebee8ac..28a645a9d0 100644 --- a/arch/arm/lib32/bootm.c +++ b/arch/arm/lib32/bootm.c @@ -20,7 +20,7 @@ #include <restart.h> #include <globalvar.h> #include <tee/optee.h> - +#include <image-fit.h> #include <asm/byteorder.h> #include <asm/setup.h> #include <asm/barebox-arm.h> @@ -114,10 +114,11 @@ static int get_kernel_addresses(size_t image_size, kaddr = mem_start + image_decomp_size; /* - * Make sure we do not place the image past the end of the + * Make sure we do not place the image outside of the * available memory. */ - if (kaddr + image_size + spacing >= mem_end) + if (((kaddr + image_size + spacing) > mem_end) && + ((mem_end - image_size - spacing) >= mem_start)) kaddr = mem_end - image_size - spacing; *load_address = PAGE_ALIGN_DOWN(kaddr); @@ -166,6 +167,34 @@ static int optee_verify_header_request_region(struct image_data *data, struct op return ret; } +static int bootm_load_tee_from_fit(struct image_data *data) +{ + int ret = 0; + struct optee_header hdr; + + if (data->os_fit && + fit_has_image(data->os_fit, data->fit_config, "tee")) { + const void *tee; + unsigned long tee_size; + + ret = fit_open_image(data->os_fit, data->fit_config, "tee", + &tee, &tee_size); + if (ret) { + pr_err("Error opening tee fit image: %s\n", strerror(-ret)); + return ret; + } + memcpy(&hdr, tee, sizeof(hdr)); + if (optee_verify_header_request_region(data, &hdr) < 0) { + pr_err("%s", strerror(errno)); + ret = -errno; + goto out; + } + memcpy((void *)data->tee_res->start, tee + sizeof(hdr), hdr.init_size); + printf("Read optee image to %pa, size 0x%08x\n", (void *)data->tee_res->start, hdr.init_size); + } +out: + return ret; +} static int bootm_load_tee_from_file(struct image_data *data) { int fd, ret; @@ -262,10 +291,16 @@ static int __do_bootm_linux(struct image_data *data, unsigned long free_mem, return ret; } - if (IS_ENABLED(CONFIG_BOOTM_OPTEE) && data->tee_file) { - ret = bootm_load_tee_from_file(data); - if (ret) - return ret; + if (IS_ENABLED(CONFIG_BOOTM_OPTEE)) { + if (data->tee_file && !IS_ENABLED(CONFIG_BOOTM_FORCE_SIGNED_IMAGES)) { + ret = bootm_load_tee_from_file(data); + if (ret) + return ret; + } else if (IS_ENABLED(CONFIG_FITIMAGE)) { + ret = bootm_load_tee_from_fit(data); + if (ret) + return ret; + } } @@ -711,8 +746,8 @@ static struct binfmt_hook binfmt_barebox_hook = { .exec = "bootm", }; -BAREBOX_MAGICVAR_NAMED(global_bootm_boot_atag, global.bootm.boot_atag, - "If true, ignore device tree and boot using ATAGs"); +BAREBOX_MAGICVAR(global.bootm.boot_atag, + "If true, ignore device tree and boot using ATAGs"); static int armlinux_register_image_handler(void) { diff --git a/arch/arm/lib32/memcpy.S b/arch/arm/lib32/memcpy.S index 5123691ca9..0fcdaa88e6 100644 --- a/arch/arm/lib32/memcpy.S +++ b/arch/arm/lib32/memcpy.S @@ -56,9 +56,12 @@ /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ +.weak memcpy ENTRY(memcpy) +ENTRY(__memcpy) #include "copy_template.S" +ENDPROC(__memcpy) ENDPROC(memcpy) diff --git a/arch/arm/lib32/memset.S b/arch/arm/lib32/memset.S index c4d2672038..6079dd89f6 100644 --- a/arch/arm/lib32/memset.S +++ b/arch/arm/lib32/memset.S @@ -15,6 +15,8 @@ .text .align 5 +.weak memset +ENTRY(__memset) ENTRY(memset) ands r3, r0, #3 @ 1 unaligned? mov ip, r0 @ preserve r0 as return value @@ -121,4 +123,4 @@ ENTRY(memset) add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) b 1b ENDPROC(memset) - +ENDPROC(__memset) diff --git a/arch/arm/lib32/module-plts.c b/arch/arm/lib32/module-plts.c new file mode 100644 index 0000000000..53cf6b11c7 --- /dev/null +++ b/arch/arm/lib32/module-plts.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014-2017 Linaro Ltd. <ard.biesheuvel@linaro.org> + */ + +#include <common.h> +#include <elf.h> +#include <module.h> +#include <qsort.h> + +#include <asm/opcodes.h> + +#define PLT_ENT_STRIDE 32 +#define PLT_ENT_COUNT (PLT_ENT_STRIDE / sizeof(u32)) +#define PLT_ENT_SIZE (sizeof(struct plt_entries) / PLT_ENT_COUNT) + +#ifdef CONFIG_THUMB2_BAREBOX +#define PLT_ENT_LDR __opcode_to_mem_thumb32(0xf8dff000 | \ + (PLT_ENT_STRIDE - 4)) +#else +#define PLT_ENT_LDR __opcode_to_mem_arm(0xe59ff000 | \ + (PLT_ENT_STRIDE - 8)) +#endif + +struct plt_entries { + u32 ldr[PLT_ENT_COUNT]; + u32 lit[PLT_ENT_COUNT]; +}; + +u32 get_module_plt(struct module *mod, unsigned long loc, Elf32_Addr val) +{ + struct plt_entries *plt = (struct plt_entries *)mod->arch.plt->sh_addr; + int idx = 0; + + /* + * Look for an existing entry pointing to 'val'. Given that the + * relocations are sorted, this will be the last entry we allocated. + * (if one exists). + */ + if (mod->arch.plt_count > 0) { + plt += (mod->arch.plt_count - 1) / PLT_ENT_COUNT; + idx = (mod->arch.plt_count - 1) % PLT_ENT_COUNT; + + if (plt->lit[idx] == val) + return (u32)&plt->ldr[idx]; + + idx = (idx + 1) % PLT_ENT_COUNT; + if (!idx) + plt++; + } + + mod->arch.plt_count++; + BUG_ON(mod->arch.plt_count * PLT_ENT_SIZE > mod->arch.plt->sh_size); + + if (!idx) + /* Populate a new set of entries */ + *plt = (struct plt_entries){ + { [0 ... PLT_ENT_COUNT - 1] = PLT_ENT_LDR, }, + { val, } + }; + else + plt->lit[idx] = val; + + return (u32)&plt->ldr[idx]; +} + +#define cmp_3way(a,b) ((a) < (b) ? -1 : (a) > (b)) + +static int cmp_rel(const void *a, const void *b) +{ + const Elf32_Rel *x = a, *y = b; + int i; + + /* sort by type and symbol index */ + i = cmp_3way(ELF32_R_TYPE(x->r_info), ELF32_R_TYPE(y->r_info)); + if (i == 0) + i = cmp_3way(ELF32_R_SYM(x->r_info), ELF32_R_SYM(y->r_info)); + return i; +} + +static bool is_zero_addend_relocation(Elf32_Addr base, const Elf32_Rel *rel) +{ + u32 *tval = (u32 *)(base + rel->r_offset); + + /* + * Do a bitwise compare on the raw addend rather than fully decoding + * the offset and doing an arithmetic comparison. + * Note that a zero-addend jump/call relocation is encoded taking the + * PC bias into account, i.e., -8 for ARM and -4 for Thumb2. + */ + switch (ELF32_R_TYPE(rel->r_info)) { + u16 upper, lower; + + case R_ARM_THM_CALL: + case R_ARM_THM_JUMP24: + upper = __mem_to_opcode_thumb16(((u16 *)tval)[0]); + lower = __mem_to_opcode_thumb16(((u16 *)tval)[1]); + + return (upper & 0x7ff) == 0x7ff && (lower & 0x2fff) == 0x2ffe; + + case R_ARM_CALL: + case R_ARM_PC24: + case R_ARM_JUMP24: + return (__mem_to_opcode_arm(*tval) & 0xffffff) == 0xfffffe; + } + BUG(); +} + +static bool duplicate_rel(Elf32_Addr base, const Elf32_Rel *rel, int num) +{ + const Elf32_Rel *prev; + + /* + * Entries are sorted by type and symbol index. That means that, + * if a duplicate entry exists, it must be in the preceding + * slot. + */ + if (!num) + return false; + + prev = rel + num - 1; + return cmp_rel(rel + num, prev) == 0 && + is_zero_addend_relocation(base, prev); +} + +/* Count how many PLT entries we may need */ +static unsigned int count_plts(const Elf32_Sym *syms, Elf32_Addr base, + const Elf32_Rel *rel, int num, Elf32_Word dstidx) +{ + unsigned int ret = 0; + const Elf32_Sym *s; + int i; + + for (i = 0; i < num; i++) { + switch (ELF32_R_TYPE(rel[i].r_info)) { + case R_ARM_CALL: + case R_ARM_PC24: + case R_ARM_JUMP24: + case R_ARM_THM_CALL: + case R_ARM_THM_JUMP24: + /* + * We only have to consider branch targets that resolve + * to symbols that are defined in a different section. + * This is not simply a heuristic, it is a fundamental + * limitation, since there is no guaranteed way to emit + * PLT entries sufficiently close to the branch if the + * section size exceeds the range of a branch + * instruction. So ignore relocations against defined + * symbols if they live in the same section as the + * relocation target. + */ + s = syms + ELF32_R_SYM(rel[i].r_info); + if (s->st_shndx == dstidx) + break; + + /* + * Jump relocations with non-zero addends against + * undefined symbols are supported by the ELF spec, but + * do not occur in practice (e.g., 'jump n bytes past + * the entry point of undefined function symbol f'). + * So we need to support them, but there is no need to + * take them into consideration when trying to optimize + * this code. So let's only check for duplicates when + * the addend is zero. + */ + if (!is_zero_addend_relocation(base, rel + i) || + !duplicate_rel(base, rel, i)) + ret++; + } + } + return ret; +} + +int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs, + char *secstrings, struct module *mod) +{ + unsigned long plts = 0; + Elf32_Shdr *s, *sechdrs_end = sechdrs + ehdr->e_shnum; + Elf32_Sym *syms = NULL; + + /* + * To store the PLTs, we expand the .text section for core module code + * and for initialization code. + */ + for (s = sechdrs; s < sechdrs_end; ++s) { + if (strcmp(".plt", secstrings + s->sh_name) == 0) + mod->arch.plt = s; + else if (s->sh_type == SHT_SYMTAB) + syms = (Elf32_Sym *)s->sh_addr; + } + + if (!mod->arch.plt) { + pr_err("%s: module PLT section missing\n", mod->name); + return -ENOEXEC; + } + if (!syms) { + pr_err("%s: module symtab section missing\n", mod->name); + return -ENOEXEC; + } + + for (s = sechdrs + 1; s < sechdrs_end; ++s) { + Elf32_Rel *rels = (void *)ehdr + s->sh_offset; + int numrels = s->sh_size / sizeof(Elf32_Rel); + Elf32_Shdr *dstsec = sechdrs + s->sh_info; + + if (s->sh_type != SHT_REL) + continue; + + /* ignore relocations that operate on non-exec sections */ + if (!(dstsec->sh_flags & SHF_EXECINSTR)) + continue; + + /* sort by type and symbol index */ + /* n.b. Barebox qsort instead of Linux sort */ + qsort(rels, numrels, sizeof(Elf32_Rel), cmp_rel); + + plts += count_plts(syms, dstsec->sh_addr, rels, numrels, s->sh_info); + } + + mod->arch.plt->sh_type = SHT_NOBITS; + mod->arch.plt->sh_flags = SHF_EXECINSTR | SHF_ALLOC; + mod->arch.plt->sh_addralign = PLT_ENT_STRIDE; + mod->arch.plt->sh_size = round_up(plts * PLT_ENT_SIZE, + sizeof(struct plt_entries)); + mod->arch.plt_count = 0; + + pr_debug("%s: plt=%x\n", __func__, mod->arch.plt->sh_size); + return 0; +} diff --git a/arch/arm/lib32/module.c b/arch/arm/lib32/module.c index be7965d59c..3ded9896b7 100644 --- a/arch/arm/lib32/module.c +++ b/arch/arm/lib32/module.c @@ -64,6 +64,20 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, offset -= 0x04000000; offset += sym->st_value - loc; + + /* + * Route through a PLT entry if 'offset' exceeds the + * supported range. Note that 'offset + loc + 8' + * contains the absolute jump target, i.e., + * @sym + addend, corrected for the +8 PC bias. + */ + if (IS_ENABLED(CONFIG_ARM_MODULE_PLTS) && + (offset <= (s32)0xfe000000 || + offset >= (s32)0x02000000)) + offset = get_module_plt(module, loc, + offset + loc + 8) + - loc - 8; + if (offset & 3 || offset <= (s32)0xfe000000 || offset >= (s32)0x02000000) { diff --git a/arch/arm/lib32/module.lds b/arch/arm/lib32/module.lds new file mode 100644 index 0000000000..0dd204608c --- /dev/null +++ b/arch/arm/lib32/module.lds @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +SECTIONS { + .plt : { BYTE(0) } +} diff --git a/arch/arm/lib64/armlinux.c b/arch/arm/lib64/armlinux.c index bcff770793..a5f122edcd 100644 --- a/arch/arm/lib64/armlinux.c +++ b/arch/arm/lib64/armlinux.c @@ -1,15 +1,5 @@ -/* - * Copyright (C) 2018 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2018 Sascha Hauer <s.hauer@pengutronix.de> #include <boot.h> #include <common.h> diff --git a/arch/arm/lib64/barebox.lds.S b/arch/arm/lib64/barebox.lds.S index 8ae7bfb71c..2ebaabef0f 100644 --- a/arch/arm/lib64/barebox.lds.S +++ b/arch/arm/lib64/barebox.lds.S @@ -1,19 +1,5 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2000-2004 Wolfgang Denk <wd@denx.de>, DENX Software Engineering */ #include <asm-generic/barebox.lds.h> diff --git a/arch/arm/lib64/copy_template.S b/arch/arm/lib64/copy_template.S index cc9a84260d..8e4ff059d1 100644 --- a/arch/arm/lib64/copy_template.S +++ b/arch/arm/lib64/copy_template.S @@ -1,28 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2013 ARM Ltd. */ +/* SPDX-FileCopyrightText: 2013 Linaro */ + /* - * Copyright (C) 2013 ARM Ltd. - * Copyright (C) 2013 Linaro. - * * This code is based on glibc cortex strings work originally authored by Linaro * and re-licensed under GPLv2 for the Linux kernel. The original code can * be found @ * * http://bazaar.launchpad.net/~linaro-toolchain-dev/cortex-strings/trunk/ * files/head:/src/aarch64/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ - /* * Copy a buffer from src to dest (alignment handled by the hardware) * diff --git a/arch/arm/lib64/div0.c b/arch/arm/lib64/div0.c index 46f6452419..56ecba750c 100644 --- a/arch/arm/lib64/div0.c +++ b/arch/arm/lib64/div0.c @@ -1,18 +1,6 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2002 Wolfgang Denk <wd@denx.de>, DENX Software Engineering + #include <common.h> extern void __div0(void); diff --git a/arch/arm/lib64/memcpy.S b/arch/arm/lib64/memcpy.S index a70e96ca29..92845b25a6 100644 --- a/arch/arm/lib64/memcpy.S +++ b/arch/arm/lib64/memcpy.S @@ -1,25 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2013 ARM Ltd. */ +/* SPDX-FileCopyrightText: 2013 Linaro */ + /* - * Copyright (C) 2013 ARM Ltd. - * Copyright (C) 2013 Linaro. - * * This code is based on glibc cortex strings work originally authored by Linaro * and re-licensed under GPLv2 for the Linux kernel. The original code can * be found @ * * http://bazaar.launchpad.net/~linaro-toolchain-dev/cortex-strings/trunk/ * files/head:/src/aarch64/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <linux/linkage.h> diff --git a/arch/arm/lib64/memset.S b/arch/arm/lib64/memset.S index d17bcc6125..ff201750f1 100644 --- a/arch/arm/lib64/memset.S +++ b/arch/arm/lib64/memset.S @@ -1,25 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2013 ARM Ltd. */ +/* SPDX-FileCopyrightText: 2013 Linaro */ + /* - * Copyright (C) 2013 ARM Ltd. - * Copyright (C) 2013 Linaro. - * * This code is based on glibc cortex strings work originally authored by Linaro * and re-licensed under GPLv2 for the Linux kernel. The original code can * be found @ * * http://bazaar.launchpad.net/~linaro-toolchain-dev/cortex-strings/trunk/ * files/head:/src/aarch64/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <linux/linkage.h> diff --git a/arch/arm/lib64/setjmp.S b/arch/arm/lib64/setjmp.S index a7f6d05417..0910e2f5a6 100644 --- a/arch/arm/lib64/setjmp.S +++ b/arch/arm/lib64/setjmp.S @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) 2017 Theobroma Systems Design und Consulting GmbH - */ +/* SPDX-FileCopyrightText: 2017 Theobroma Systems Design und Consulting GmbH */ #include <config.h> #include <linux/linkage.h> diff --git a/arch/arm/lib64/stacktrace.c b/arch/arm/lib64/stacktrace.c index 4391188446..db5691a609 100644 --- a/arch/arm/lib64/stacktrace.c +++ b/arch/arm/lib64/stacktrace.c @@ -1,13 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only #include <common.h> #include <asm/stacktrace.h> diff --git a/arch/arm/lib64/string.c b/arch/arm/lib64/string.c index cb26331527..a2cf09e58e 100644 --- a/arch/arm/lib64/string.c +++ b/arch/arm/lib64/string.c @@ -5,18 +5,34 @@ void *__arch_memset(void *dst, int c, __kernel_size_t size); void *__arch_memcpy(void * dest, const void *src, size_t count); -void *memset(void *dst, int c, __kernel_size_t size) +static void *_memset(void *dst, int c, __kernel_size_t size) { if (likely(get_cr() & CR_M)) return __arch_memset(dst, c, size); - return __default_memset(dst, c, size); + return __nokasan_default_memset(dst, c, size); } -void *memcpy(void * dest, const void *src, size_t count) +void __weak *memset(void *dst, int c, __kernel_size_t size) +{ + return _memset(dst, c, size); +} + +void *__memset(void *dst, int c, __kernel_size_t size) + __alias(_memset); + +static void *_memcpy(void * dest, const void *src, size_t count) { if (likely(get_cr() & CR_M)) return __arch_memcpy(dest, src, count); - return __default_memcpy(dest, src, count); -}
\ No newline at end of file + return __nokasan_default_memcpy(dest, src, count); +} + +void __weak *memcpy(void * dest, const void *src, size_t count) +{ + return _memcpy(dest, src, count); +} + +void *__memcpy(void * dest, const void *src, size_t count) + __alias(_memcpy); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 54fa9b8aa2..52eefc7361 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -40,6 +40,14 @@ config HAVE_AT91_I2S_MUX_CLK config HAVE_AT91_SAM9X60_PLL bool +config HAVE_AT91_DDRAMC + bool + +config AT91_MCI_PBL + bool + depends on MCI_ATMEL_SDHCI_PBL + default y + # Select if board uses the common at91sam926x_board_init config AT91SAM926X_BOARD_INIT bool @@ -82,6 +90,7 @@ config SOC_SAMA5D2 select PINCTRL_AT91PIO4 select HAS_MACB select HAVE_MACH_ARM_HEAD + select HAVE_AT91_DDRAMC config SOC_SAMA5D3 bool @@ -598,7 +607,9 @@ config MACH_SAMA5D27_SOM1 bool "Microchip SAMA5D27 SoM-1 Evaluation Kit" select SOC_SAMA5D2 select OFDEVICE + select MCI_ATMEL_SDHCI_PBL select COMMON_CLK_OF_PROVIDER + select FS_FAT_WRITE if MCI_ATMEL_SDHCI && FS_FAT && ENV_HANDLING help Select this if you are using Microchip's sama5d27 SoM evaluation kit diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 89aff54b8a..9cfba28fa0 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -1,5 +1,6 @@ -obj-y += setup.o -lwl-y += at91_pmc_ll.o +obj-y += setup.o aic.o +lwl-y += at91_pmc_ll.o ddramc_ll.o matrix.o +lwl-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += early_udelay.o ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),) obj-y += clock.o @@ -8,9 +9,12 @@ endif obj-$(CONFIG_CMD_AT91_BOOT_TEST) += boot_test_cmd.o obj-$(CONFIG_AT91_BOOTSTRAP) += bootstrap.o +obj-$(CONFIG_BOOTM) += bootm-barebox.o obj-y += at91sam9_reset.o obj-y += at91sam9g45_reset.o +obj-pbl-$(CONFIG_HAVE_AT91_DDRAMC) += ddramc.o +pbl-$(CONFIG_AT91_MCI_PBL) += xload-mmc.o obj-$(CONFIG_AT91SAM9_SMC) += sam9_smc.o obj-$(CONFIG_HAVE_AT91SAM9_RST) += at91sam9_rst.o @@ -24,6 +28,8 @@ ifeq ($(CONFIG_OFDEVICE),) obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o sama5d3_devices.o endif +lwl-$(CONFIG_SOC_SAMA5D2) += sama5d2_ll.o +obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o obj-$(CONFIG_SOC_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o at91sam9x5_devices.o diff --git a/arch/arm/mach-at91/aic.c b/arch/arm/mach-at91/aic.c new file mode 100644 index 0000000000..b40f1d214b --- /dev/null +++ b/arch/arm/mach-at91/aic.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-1-Clause +/* + * Copyright (c) 2015, Atmel Corporation + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + */ + +#include <mach/aic.h> +#include <io.h> + +#define SFR_AICREDIR 0x54 +#define SFR_SN1 0x50 /* Serial Number 1 Register */ + +void at91_aic_redir(void __iomem *sfr, u32 key) +{ + u32 key32; + + if (readl(sfr + SFR_AICREDIR) & 0x01) + return; + + key32 = readl(sfr + SFR_SN1) ^ key; + writel(key32 | 0x01, sfr + SFR_AICREDIR); + /* bits[31:1] = key */ + /* bit[0] = 1 => all interrupts redirected to AIC */ + /* bit[0] = 0 => secure interrupts directed to SAIC, + others to AIC (default) */ +} diff --git a/arch/arm/mach-at91/at91_pmc_ll.c b/arch/arm/mach-at91/at91_pmc_ll.c index 4d39f57909..e561f20755 100644 --- a/arch/arm/mach-at91/at91_pmc_ll.c +++ b/arch/arm/mach-at91/at91_pmc_ll.c @@ -1,17 +1,51 @@ // SPDX-License-Identifier: BSD-1-Clause /* * Copyright (c) 2006, Atmel Corporation + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries * - * Atmel's name may not be used to endorse or promote products + * Atmel/Microchip's name may not be used to endorse or promote products * derived from this software without specific prior written permission. */ +#define pr_fmt(fmt) "at91pmc: " fmt + #include <common.h> +#include <mach/hardware.h> +#include <mach/at91_pmc.h> #include <mach/at91_pmc_ll.h> +#include <mach/early_udelay.h> + +#define SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */ +#define AT91_UTMICKTRIM_FREQ 0x03 + +#define PMC_GCSR0 0xC0 /* PMCv2 Generic Clock Status Register 0 */ +#define PMC_GCSR1 0xC4 /* PMCv2 Generic Clock Status Register 1 */ #define at91_pmc_write(off, val) writel(val, pmc_base + off) #define at91_pmc_read(off) readl(pmc_base + off) +#define MHZ (1000 * 1000UL) + +static unsigned long at91_pmc_get_main_xtal(void __iomem *pmc_base) +{ + u32 tmp; + + /* Enable a measurement of the Main Crystal Oscillator */ + tmp = at91_pmc_read(AT91_CKGR_MCFR); + tmp |= AT91_PMC_CCSS_XTAL_OSC; + tmp |= AT91_PMC_RCMEAS; + at91_pmc_write(AT91_CKGR_MCFR, tmp); + + do { + tmp = at91_pmc_read(AT91_CKGR_MCFR); + } while (!(tmp & AT91_PMC_MAINRDY)); + + /* read once more like the datasheet says */ + tmp = at91_pmc_read(AT91_CKGR_MCFR) & AT91_PMC_MAINF; + + return tmp * (AT91_SLOW_CLOCK / 16); +} + void at91_pmc_init(void __iomem *pmc_base, unsigned int flags) { u32 tmp; @@ -46,22 +80,16 @@ void at91_pmc_init(void __iomem *pmc_base, unsigned int flags) while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MOSCS)) ; - if (flags & AT91_PMC_LL_FLAG_MEASURE_XTAL) { - /* Enable a measurement of the Main Crystal Oscillator */ - tmp = at91_pmc_read(AT91_CKGR_MCFR); - tmp |= AT91_PMC_CCSS_XTAL_OSC; - tmp |= AT91_PMC_RCMEAS; - at91_pmc_write(AT91_CKGR_MCFR, tmp); - - while (!(at91_pmc_read(AT91_CKGR_MCFR) & AT91_PMC_MAINRDY)) - ; - } + if (flags & AT91_PMC_LL_FLAG_MEASURE_XTAL) + (void)at91_pmc_get_main_xtal(pmc_base); /* Switch from internal 12MHz RC to the Main Crystal Oscillator */ tmp = at91_pmc_read(AT91_CKGR_MOR); tmp &= ~AT91_PMC_OSCBYPASS; tmp &= ~AT91_PMC_KEY_MASK; tmp |= AT91_PMC_KEY; + if (flags & AT91_PMC_LL_FLAG_MCK_BYPASS) + tmp |= AT91_PMC_OSCBYPASS; at91_pmc_write(AT91_CKGR_MOR, tmp); tmp = at91_pmc_read(AT91_CKGR_MOR); @@ -184,3 +212,124 @@ void at91_pmc_cfg_mck(void __iomem *pmc_base, u32 pmc_mckr, unsigned int flags) while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MCKRDY)) ; } + +static void pmc_configure_utmi_ref_clk(void __iomem *pmc_base, + void __iomem *sfr_base, + unsigned long main_xtal) +{ + unsigned int utmi_ref_clk_freq = 0, tmp; + + /* + * If mainck rate is different from 12 MHz, we have to configure + * the FREQ field of the SFR_UTMICKTRIM register to generate properly + * the utmi clock. + */ + if (main_xtal < (16 + 4) * MHZ) + utmi_ref_clk_freq++; + if (main_xtal < (24 + 10) * MHZ) + utmi_ref_clk_freq++; + if (main_xtal < (48 + 10) * MHZ) + utmi_ref_clk_freq++; + + /* + * Not supported on SAMA5D2 but it's not an issue since MAINCK + * maximum value is 24 MHz. + */ + tmp = readl(sfr_base + SFR_UTMICKTRIM); + tmp &= ~AT91_UTMICKTRIM_FREQ; + tmp |= utmi_ref_clk_freq; + writel(tmp, sfr_base + SFR_UTMICKTRIM); +} + +static void pmc_uckr_clk(void __iomem *pmc_base, + void __iomem *sfr_base, + unsigned long main_xtal) +{ + unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR); + unsigned int sr; + + if (main_xtal) { + pmc_configure_utmi_ref_clk(pmc_base, sfr_base, + main_xtal); + uckr |= (AT91_PMC_UPLLCOUNT_DEFAULT | + AT91_PMC_UPLLEN | AT91_PMC_BIASEN); + sr = AT91_PMC_LOCKU; + } else { + uckr &= ~(AT91_PMC_UPLLEN | AT91_PMC_BIASEN); + sr = 0; + } + + at91_pmc_write(AT91_CKGR_UCKR, uckr); + + do { + early_udelay(1); + } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != sr); +} + +static inline unsigned gck_status(unsigned periph_id, + unsigned flags) +{ + if (flags & AT91_PMC_LL_FLAG_GCSR) + return periph_id < 32 ? PMC_GCSR0 : PMC_GCSR1; + + return AT91_PMC_SR; +} + +static inline unsigned gck_ready(unsigned status, + unsigned periph_id, + unsigned flags) +{ + unsigned mask; + + if (flags & AT91_PMC_LL_FLAG_GCSR) + mask = 1 << (periph_id & 0x1f); + else + mask = AT91_PMC_GCKRDY; + + return status & mask; +} + +int at91_pmc_enable_generic_clock(void __iomem *pmc_base, + void __iomem *sfr_base, + unsigned int periph_id, + unsigned int clk_source, unsigned int div, + unsigned int flags) +{ + unsigned long main_xtal; + unsigned int regval, status; + unsigned int timeout = 1000; + + if (periph_id > 0x7f) + return -EINVAL; + + if (div > 0xff) + return -EINVAL; + + main_xtal = at91_pmc_get_main_xtal(pmc_base); + + if ((flags & AT91_PMC_LL_FLAG_PMC_UTMI) && + !(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU)) + pmc_uckr_clk(pmc_base, sfr_base, main_xtal); + + at91_pmc_write(AT91_PMC_PCR, periph_id); + regval = at91_pmc_read(AT91_PMC_PCR); + regval &= ~AT91_PMC_GCKCSS; + regval &= ~AT91_PMC_GCKDIV; + + regval |= clk_source; + regval |= AT91_PMC_PCR_CMD | AT91_PMC_GCKDIV_(div) | AT91_PMC_GCK_EN; + + at91_pmc_write(AT91_PMC_PCR, regval); + + for (timeout = 1000; timeout; timeout--) { + early_udelay(1); + + status = at91_pmc_read(gck_status(periph_id, flags)); + if (gck_ready(status, periph_id, flags)) + return 0; + } + + pr_warn("Timeout waiting for GCK ready!\n"); + + return 0; +} diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index 975cd956c9..f89983fe63 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -88,7 +88,7 @@ static void __noreturn at91rm9200_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(at91rm9200_restart_soc); + restart_handler_register_fn("soc-wdt", at91rm9200_restart_soc); return 0; } diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 56327a2c47..fdd8ea014e 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -243,7 +243,7 @@ static void at91sam9260_initialize(void) at91_add_pit(AT91SAM9260_BASE_PIT); at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9260_BASE_SMC, 0x200); - restart_handler_register_fn(at91sam9260_restart); + restart_handler_register_fn("soc", at91sam9260_restart); } static int at91sam9260_setup(void) diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 4abc556354..0465ed9524 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -235,7 +235,7 @@ static void at91sam9261_initialize(void) at91_add_pit(AT91SAM9261_BASE_PIT); at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9261_BASE_SMC, 0x200); - restart_handler_register_fn(at91sam9261_restart); + restart_handler_register_fn("soc", at91sam9261_restart); } static int at91sam9261_setup(void) diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 690f8e06bb..dc5dddfb64 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -256,7 +256,7 @@ static void at91sam9263_initialize(void) at91_add_sam9_smc(0, AT91SAM9263_BASE_SMC0, 0x200); at91_add_sam9_smc(1, AT91SAM9263_BASE_SMC1, 0x200); - restart_handler_register_fn(at91sam9263_restart); + restart_handler_register_fn("soc", at91sam9263_restart); } static int at91sam9263_setup(void) diff --git a/arch/arm/mach-at91/at91sam9_reset.S b/arch/arm/mach-at91/at91sam9_reset.S index 65e22f4fe7..ba3f768331 100644 --- a/arch/arm/mach-at91/at91sam9_reset.S +++ b/arch/arm/mach-at91/at91sam9_reset.S @@ -14,7 +14,6 @@ */ #include <linux/linkage.h> -#include <mach/hardware.h> #include <mach/at91sam9_sdramc.h> #include <mach/at91_rstc.h> diff --git a/arch/arm/mach-at91/at91sam9_rst.c b/arch/arm/mach-at91/at91sam9_rst.c index 8f03576e69..a61a26936f 100644 --- a/arch/arm/mach-at91/at91sam9_rst.c +++ b/arch/arm/mach-at91/at91sam9_rst.c @@ -7,14 +7,42 @@ #include <init.h> #include <io.h> #include <restart.h> +#include <linux/bitfield.h> #include <linux/clk.h> #include <mach/at91_rstc.h> +#include <reset_source.h> struct at91sam9x_rst { struct restart_handler restart; void __iomem *base; }; +static int reasons[] = { + RESET_POR, /* GENERAL Both VDDCORE and VDDBU rising */ + RESET_WKE, /* WAKEUP VDDCORE rising */ + RESET_WDG, /* WATCHDOG Watchdog fault occurred */ + RESET_RST, /* SOFTWARE Reset required by the software */ + RESET_EXT, /* USER NRST pin detected low */ +}; + +static void at91sam9x_set_reset_reason(struct device_d *dev, + void __iomem *base) +{ + enum reset_src_type type = RESET_UKWN; + u32 sr, rsttyp; + + sr = readl(base + AT91_RSTC_SR); + rsttyp = FIELD_GET(AT91_RSTC_RSTTYP, sr); + + if (rsttyp < ARRAY_SIZE(reasons)) + type = reasons[rsttyp]; + + dev_info(dev, "reset reason %s (RSTC_SR: 0x%05x)\n", + reset_source_to_string(type), sr); + + reset_source_set(type); +} + static void __noreturn at91sam9x_restart_soc(struct restart_handler *rst) { struct at91sam9x_rst *priv = container_of(rst, struct at91sam9x_rst, restart); @@ -52,6 +80,8 @@ static int at91sam9x_rst_probe(struct device_d *dev) clk_enable(clk); + at91sam9x_set_reset_reason(dev, priv->base); + priv->restart.name = "at91sam9x-rst"; priv->restart.restart = at91sam9x_restart_soc; diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 569aa274fc..affc624b1d 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -270,7 +270,7 @@ static void at91sam9g45_initialize(void) at91_add_pit(AT91SAM9G45_BASE_PIT); at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9G45_BASE_SMC, 0x200); - restart_handler_register_fn(at91sam9g45_restart); + restart_handler_register_fn("soc", at91sam9g45_restart); } static int at91sam9g45_setup(void) diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 43d8d5fbd6..389d88c17d 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -17,7 +17,7 @@ #include <mach/hardware.h> #include <mach/at91_pmc.h> #include <mach/at91sam9g45_matrix.h> -#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_ddrsdrc.h> #include <mach/at91_rtt.h> #include <mach/board.h> #include <mach/iomux.h> diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S index 6a58de618c..67517bf591 100644 --- a/arch/arm/mach-at91/at91sam9g45_reset.S +++ b/arch/arm/mach-at91/at91sam9g45_reset.S @@ -11,8 +11,7 @@ */ #include <linux/linkage.h> -#include <mach/hardware.h> -#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_ddrsdrc.h> #include <mach/at91_rstc.h> .arm @@ -20,13 +19,13 @@ .globl at91sam9g45_reset at91sam9g45_reset: mov r2, #1 - mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN + mov r3, #AT91_DDRC2_LPCB_POWERDOWN ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST .balign 32 @ align to cache line - str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access - str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0 + str r2, [r0, #AT91_HDDRSDRC2_RTR] @ disable DDR0 access + str r3, [r0, #AT91_HDDRSDRC2_LPR] @ power down DDR0 str r4, [r1] @ reset processor b . diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index 365bded56e..850d34604a 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c @@ -226,7 +226,7 @@ static void at91sam9n12_initialize(void) at91_add_pit(AT91SAM9N12_BASE_PIT); at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9N12_BASE_SMC, 0x200); - restart_handler_register_fn(at91sam9n12_restart); + restart_handler_register_fn("soc", at91sam9n12_restart); } static int at91sam9n12_setup(void) diff --git a/arch/arm/mach-at91/at91sam9n12_devices.c b/arch/arm/mach-at91/at91sam9n12_devices.c index 43cbb79af4..91b3e9b2fb 100644 --- a/arch/arm/mach-at91/at91sam9n12_devices.c +++ b/arch/arm/mach-at91/at91sam9n12_devices.c @@ -18,7 +18,7 @@ #include <mach/board.h> #include <mach/at91_pmc.h> #include <mach/at91sam9n12_matrix.h> -#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_ddrsdrc.h> #include <mach/iomux.h> #include <mach/cpu.h> #include <i2c/i2c-gpio.h> diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index 40ba9ed56e..086e27a79f 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c @@ -13,7 +13,7 @@ static void at91sam9x5_restart(struct restart_handler *rst) static int at91sam9x5_initialize(void) { - restart_handler_register_fn(at91sam9x5_restart); + restart_handler_register_fn("soc", at91sam9x5_restart); return 0; } diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c index ab506a1f42..022e4fb59a 100644 --- a/arch/arm/mach-at91/at91sam9x5_devices.c +++ b/arch/arm/mach-at91/at91sam9x5_devices.c @@ -17,7 +17,7 @@ #include <mach/board.h> #include <mach/at91_pmc.h> #include <mach/at91sam9x5_matrix.h> -#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_ddrsdrc.h> #include <mach/iomux.h> #include <mach/cpu.h> #include <i2c/i2c-gpio.h> diff --git a/arch/arm/mach-at91/bootm-barebox.c b/arch/arm/mach-at91/bootm-barebox.c new file mode 100644 index 0000000000..1dccdb86a9 --- /dev/null +++ b/arch/arm/mach-at91/bootm-barebox.c @@ -0,0 +1,46 @@ +#define pr_fmt(fmt) "at91-bootm-barebox: " fmt + +#include <bootm.h> +#include <common.h> +#include <init.h> +#include <memory.h> +#include <mach/cpu.h> +#include <mach/sama5_bootsource.h> + +static int do_bootm_at91_barebox_image(struct image_data *data) +{ + resource_size_t start, end; + int ret; + + ret = memory_bank_first_find_space(&start, &end); + if (ret) + return ret; + + ret = bootm_load_os(data, start); + if (ret) + return ret; + + if (data->verbose) + printf("Loaded barebox image to 0x%08zx\n", start); + + shutdown_barebox(); + + sama5_boot_xload((void *)start, at91_bootsource); + + return -EIO; +} + +static struct image_handler image_handler_at91_barebox_image = { + .name = "AT91 barebox image", + .bootm = do_bootm_at91_barebox_image, + .filetype = filetype_arm_barebox, +}; + +static int at91_register_barebox_image_handler(void) +{ + if (!of_machine_is_compatible("atmel,sama5d2")) + return 0; + + return register_image_handler(&image_handler_at91_barebox_image); +} +late_initcall(at91_register_barebox_image_handler); diff --git a/arch/arm/mach-at91/ddramc.c b/arch/arm/mach-at91/ddramc.c new file mode 100644 index 0000000000..c3ef6b0090 --- /dev/null +++ b/arch/arm/mach-at91/ddramc.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 Ahmad Fatoum <a.fatoum@pengutronix.de> + */ + +#include <common.h> +#include <init.h> +#include <mach/ddramc.h> +#include <mach/hardware.h> +#include <asm/barebox-arm.h> +#include <mach/at91_ddrsdrc.h> +#include <mach/sama5_bootsource.h> +#include <asm/memory.h> +#include <pbl.h> +#include <io.h> + +static unsigned sama5_ramsize(void __iomem *base) +{ + return at91_get_ddram_size(base, true); +} + +void __noreturn sama5d2_barebox_entry(unsigned int r4, void *boarddata) +{ + __sama5d2_stashed_bootrom_r4 = r4; + barebox_arm_entry(SAMA5_DDRCS, sama5_ramsize(SAMA5D2_BASE_MPDDRC), + boarddata); +} + +static int sama5_ddr_probe(struct device_d *dev) +{ + struct resource *iores; + void __iomem *base; + + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); + + arm_add_mem_device("ram0", SAMA5_DDRCS, sama5_ramsize(base)); + + return 0; +} + +static struct of_device_id sama5_ddr_dt_ids[] = { + { .compatible = "atmel,sama5d3-ddramc" }, + { /* sentinel */ } +}; + +static struct driver_d sama5_ddr_driver = { + .name = "sama5-ddramc", + .probe = sama5_ddr_probe, + .of_compatible = sama5_ddr_dt_ids, +}; + +mem_platform_driver(sama5_ddr_driver); diff --git a/arch/arm/mach-at91/ddramc_ll.c b/arch/arm/mach-at91/ddramc_ll.c new file mode 100644 index 0000000000..4768fdcd62 --- /dev/null +++ b/arch/arm/mach-at91/ddramc_ll.c @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: BSD-1-Clause +/* + * Copyright (c) 2007, Stelian Pop <stelian.pop@leadtechdesign.com> + * Copyright (c) 2007 Lead Tech Design <www.leadtechdesign.com> + */ + +#include <linux/kconfig.h> +#include <asm/system.h> +#include <mach/at91_ddrsdrc.h> +#include <mach/ddramc.h> +#include <mach/early_udelay.h> + +void at91_ddram_initialize(void __iomem *base_address, + void __iomem *ram_address, + struct at91_ddramc_register *ddramc_config) +{ + unsigned long ba_offset; + unsigned long cr = 0; + + /* compute BA[] offset according to CR configuration */ + ba_offset = (ddramc_config->cr & AT91_DDRC2_NC) + 9; + if ((ddramc_config->cr & AT91_DDRC2_DECOD) == AT91_DDRC2_DECOD_SEQUENTIAL) + ba_offset += ((ddramc_config->cr & AT91_DDRC2_NR) >> 2) + 11; + + ba_offset += (ddramc_config->mdr & AT91_DDRC2_DBW) ? 1 : 2; + + /* + * Step 1: Program the memory device type into the Memory Device Register + */ + writel(ddramc_config->mdr, base_address + AT91_HDDRSDRC2_MDR); + + /* + * Step 2: Program the feature of DDR2-SDRAM device into + * the Timing Register, and into the Configuration Register + */ + writel(ddramc_config->cr, base_address + AT91_HDDRSDRC2_CR); + + writel(ddramc_config->t0pr, base_address + AT91_HDDRSDRC2_T0PR); + writel(ddramc_config->t1pr, base_address + AT91_HDDRSDRC2_T1PR); + writel(ddramc_config->t2pr, base_address + AT91_HDDRSDRC2_T2PR); + + /* + * Step 3: An NOP command is issued to the DDR2-SDRAM + */ + writel(AT91_DDRC2_MODE_NOP_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + /* Now, clocks which drive the DDR2-SDRAM device are enabled */ + + /* A minimum pause wait 200 us is provided to precede any signal toggle. + (6 core cycles per iteration, core is at 396MHz: min 13340 loops) */ + early_udelay(200); + + /* + * Step 4: An NOP command is issued to the DDR2-SDRAM + */ + writel(AT91_DDRC2_MODE_NOP_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + /* Now, CKE is driven high */ + /* wait 400 ns min */ + early_udelay(1); + + /* + * Step 5: An all banks precharge command is issued to the DDR2-SDRAM. + */ + writel(AT91_DDRC2_MODE_PRCGALL_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 6: An Extended Mode Register set(EMRS2) cycle is issued to chose between commercial or high + * temperature operations. + * Perform a write access to DDR2-SDRAM to acknowledge this command. + * The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. + */ + writel(AT91_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x2 << ba_offset)); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 7: An Extended Mode Register set(EMRS3) cycle is issued + * to set the Extended Mode Register to "0". + * Perform a write access to DDR2-SDRAM to acknowledge this command. + * The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 1. + */ + writel(AT91_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x3 << ba_offset)); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 8: An Extened Mode Register set(EMRS1) cycle is issued to enable DLL, + * and to program D.I.C(Output Driver Impedance Control) + * Perform a write access to DDR2-SDRAM to acknowledge this command. + * The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. + */ + writel(AT91_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x1 << ba_offset)); + + /* An additional 200 cycles of clock are required for locking DLL */ + early_udelay(1); + + /* + * Step 9: Program DLL field into the Configuration Register to high(Enable DLL reset) + */ + cr = readl(base_address + AT91_HDDRSDRC2_CR); + writel(cr | AT91_DDRC2_ENABLE_RESET_DLL, base_address + AT91_HDDRSDRC2_CR); + + /* + * Step 10: A Mode Register set(MRS) cycle is issied to reset DLL. + * Perform a write access to DDR2-SDRAM to acknowledge this command. + * The write address must be chosen so that BA[1:0] bits are set to 0. + */ + writel(AT91_DDRC2_MODE_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x0 << ba_offset)); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 11: An all banks precharge command is issued to the DDR2-SDRAM. + */ + writel(AT91_DDRC2_MODE_PRCGALL_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* wait 400 ns min (not needed on certain DDR2 devices) */ + early_udelay(1); + + /* + * Step 12: Two auto-refresh (CBR) cycles are provided. + * Program the auto refresh command (CBR) into the Mode Register. + */ + writel(AT91_DDRC2_MODE_RFSH_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* wait TRFC cycles min (135 ns min) extended to 400 ns */ + early_udelay(1); + + /* Set 2nd CBR */ + writel(AT91_DDRC2_MODE_RFSH_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* wait TRFC cycles min (135 ns min) extended to 400 ns */ + early_udelay(1); + + /* + * Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset). + */ + cr = readl(base_address + AT91_HDDRSDRC2_CR); + writel(cr & ~AT91_DDRC2_ENABLE_RESET_DLL, base_address + AT91_HDDRSDRC2_CR); + + /* + * Step 14: A Mode Register set (MRS) cycle is issued to program + * the parameters of the DDR2-SDRAM devices, in particular CAS latency, + * burst length and to disable DDL reset. + * Perform a write access to DDR2-SDRAM to acknowledge this command. + * The write address must be chosen so that BA[1:0] bits are set to 0. + */ + writel(AT91_DDRC2_MODE_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x0 << ba_offset)); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 15: Program OCD field into the Configuration Register + * to high (OCD calibration default). + */ + cr = readl(base_address + AT91_HDDRSDRC2_CR); + writel(cr | AT91_DDRC2_OCD_DEFAULT, base_address + AT91_HDDRSDRC2_CR); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. + * Perform a write access to DDR2-SDRAM to acknowledge this command. + * The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. + */ + writel(AT91_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x1 << ba_offset)); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 17: Program OCD field into the Configuration Register + * to low (OCD calibration mode exit). + */ + cr = readl(base_address + AT91_HDDRSDRC2_CR); + writel(cr & ~AT91_DDRC2_OCD_DEFAULT, base_address + AT91_HDDRSDRC2_CR); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit. + * Perform a write access to DDR2-SDRAM to acknowledge this command. + * The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. + */ + writel(AT91_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x1 << ba_offset)); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 19: A Nornal mode command is provided. + */ + writel(AT91_DDRC2_MODE_NORMAL_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* + * Step 20: Perform a write access to any DDR2-SDRAM address + */ + writel(0, ram_address); + + /* + * Step 21: Write the refresh rate into the count field in the Refresh Timer register. + */ + writel(ddramc_config->rtr, base_address + AT91_HDDRSDRC2_RTR); + + /* + * Now we are ready to work on the DDRSDR + * wait for end of calibration + */ + early_udelay(10); +} + +/* This initialization sequence is sama5d3 and sama5d4 LP-DDR2 specific */ + +void at91_lpddr2_sdram_initialize(void __iomem *base_address, + void __iomem *ram_address, + struct at91_ddramc_register *ddramc_config) +{ + unsigned long reg; + + writel(ddramc_config->lpddr2_lpr, base_address + AT91_MPDDRC_LPDDR2_LPR); + + writel(ddramc_config->tim_calr, base_address + AT91_MPDDRC_LPDDR2_TIM_CAL); + + /* + * Step 1: Program the memory device type. + */ + writel(ddramc_config->mdr, base_address + AT91_HDDRSDRC2_MDR); + + /* + * Step 2: Program the feature of the low-power DDR2-SDRAM device. + */ + writel(ddramc_config->cr, base_address + AT91_HDDRSDRC2_CR); + + writel(ddramc_config->t0pr, base_address + AT91_HDDRSDRC2_T0PR); + writel(ddramc_config->t1pr, base_address + AT91_HDDRSDRC2_T1PR); + writel(ddramc_config->t2pr, base_address + AT91_HDDRSDRC2_T2PR); + + /* + * Step 3: A NOP command is issued to the low-power DDR2-SDRAM. + */ + writel(AT91_DDRC2_MODE_NOP_CMD, base_address + AT91_HDDRSDRC2_MR); + + /* + * Step 3bis: Add memory barrier then Perform a write access to + * any low-power DDR2-SDRAM address to acknowledge the command. + */ + dmb(); + writel(0, ram_address); + + /* + * Step 4: A pause of at least 100 ns must be observed before + * a single toggle. + */ + early_udelay(1); + + /* + * Step 5: A NOP command is issued to the low-power DDR2-SDRAM. + */ + writel(AT91_DDRC2_MODE_NOP_CMD, base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 6: A pause of at least 200 us must be observed before a Reset + * Command. + */ + early_udelay(200); + + /* + * Step 7: A Reset command is issued to the low-power DDR2-SDRAM. + */ + writel(AT91_DDRC2_MRS(63) | AT91_DDRC2_MODE_LPDDR2_CMD, + base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 8: A pause of at least tINIT5 must be observed before issuing + * any commands. + */ + early_udelay(1); + + /* + * Step 9: A Calibration command is issued to the low-power DDR2-SDRAM. + */ + reg = readl(base_address + AT91_HDDRSDRC2_CR); + reg &= ~AT91_DDRC2_ZQ; + reg |= AT91_DDRC2_ZQ_RESET; + writel(reg, base_address + AT91_HDDRSDRC2_CR); + + writel(AT91_DDRC2_MRS(10) | AT91_DDRC2_MODE_LPDDR2_CMD, + base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 9bis: The ZQ Calibration command is now issued. + * Program the type of calibration in the MPDDRC_CR: set the + * ZQ field to the SHORT value. + */ + reg = readl(base_address + AT91_HDDRSDRC2_CR); + reg &= ~AT91_DDRC2_ZQ; + reg |= AT91_DDRC2_ZQ_SHORT; + writel(reg, base_address + AT91_HDDRSDRC2_CR); + + /* + * Step 10: A Mode Register Write command with 1 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + writel(AT91_DDRC2_MRS(1) | AT91_DDRC2_MODE_LPDDR2_CMD, + base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 11: A Mode Register Write command with 2 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + writel(AT91_DDRC2_MRS(2) | AT91_DDRC2_MODE_LPDDR2_CMD, + base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 12: A Mode Register Write command with 3 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + writel(AT91_DDRC2_MRS(3) | AT91_DDRC2_MODE_LPDDR2_CMD, + base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 13: A Mode Register Write command with 16 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + writel(AT91_DDRC2_MRS(16) | AT91_DDRC2_MODE_LPDDR2_CMD, + base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 14: A Normal Mode command is provided. + */ + writel(AT91_DDRC2_MODE_NORMAL_CMD, base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 15: close the input buffers: error in documentation: no need. + */ + + /* + * Step 16: Write the refresh rate into the COUNT field in the MPDDRC + * Refresh Timer Register. + */ + writel(ddramc_config->rtr, base_address + AT91_HDDRSDRC2_RTR); + + /* + * Now configure the CAL MR4 register. + */ + writel(ddramc_config->cal_mr4r, base_address + AT91_MPDDRC_LPDDR2_CAL_MR4); +} + +void at91_lpddr1_sdram_initialize(void __iomem *base_address, + void __iomem *ram_address, + struct at91_ddramc_register *ddramc_config) +{ + unsigned long ba_offset; + + /* Compute BA[] offset according to CR configuration */ + ba_offset = (ddramc_config->cr & AT91_DDRC2_NC) + 8; + if (!(ddramc_config->cr & AT91_DDRC2_DECOD_INTERLEAVED)) + ba_offset += ((ddramc_config->cr & AT91_DDRC2_NR) >> 2) + 11; + + ba_offset += (ddramc_config->mdr & AT91_DDRC2_DBW) ? 1 : 2; + + /* + * Step 1: Program the memory device type in the MPDDRC Memory Device Register + */ + writel(ddramc_config->mdr, base_address + AT91_HDDRSDRC2_MDR); + + /* + * Step 2: Program the features of the low-power DDR1-SDRAM device + * in the MPDDRC Configuration Register and in the MPDDRC Timing + * Parameter 0 Register/MPDDRC Timing Parameter 1 Register. + */ + writel(ddramc_config->cr, base_address + AT91_HDDRSDRC2_CR); + + writel(ddramc_config->t0pr, base_address + AT91_HDDRSDRC2_T0PR); + writel(ddramc_config->t1pr, base_address + AT91_HDDRSDRC2_T1PR); + writel(ddramc_config->t2pr, base_address + AT91_HDDRSDRC2_T2PR); + + /* + * Step 3: Program Temperature Compensated Self-refresh (TCR), + * Partial Array Self-refresh (PASR) and Drive Strength (DS) parameters + * in the MPDDRC Low-power Register. + */ + writel(ddramc_config->lpr, base_address + AT91_HDDRSDRC2_LPR); + + /* + * Step 4: A NOP command is issued to the low-power DDR1-SDRAM. + * Program the NOP command in the MPDDRC Mode Register (MPDDRC_MR). + * The clocks which drive the low-power DDR1-SDRAM device + * are now enabled. + */ + writel(AT91_DDRC2_MODE_NOP_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* + * Step 5: A pause of at least 200 us must be observed before + * a signal toggle. + */ + early_udelay(200); + + /* + * Step 6: A NOP command is issued to the low-power DDR1-SDRAM. + * Program the NOP command in the MPDDRC_MR. calibration request is + * now made to the I/O pad. + */ + writel(AT91_DDRC2_MODE_NOP_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* + * Step 7: An All Banks Precharge command is issued + * to the low-power DDR1-SDRAM. + * Program All Banks Precharge command in the MPDDRC_MR. + */ + writel(AT91_DDRC2_MODE_PRCGALL_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* + * Step 8: Two auto-refresh (CBR) cycles are provided. + * Program the Auto Refresh command (CBR) in the MPDDRC_MR. + * The application must write a four to the MODE field + * in the MPDDRC_MR. Perform a write access to any low-power + * DDR1-SDRAM location twice to acknowledge these commands. + */ + writel(AT91_DDRC2_MODE_RFSH_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + writel(AT91_DDRC2_MODE_RFSH_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* + * Step 9: An Extended Mode Register Set (EMRS) cycle is issued to + * program the low-power DDR1-SDRAM parameters (TCSR, PASR, DS). + * The application must write a five to the MODE field in the MPDDRC_MR + * and perform a write access to the SDRAM to acknowledge this command. + * The write address must be chosen so that signal BA[1] is set to 1 + * and BA[0] is set to 0. + */ + writel(AT91_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x2 << ba_offset)); + + /* + * Step 10: A Mode Register Set (MRS) cycle is issued to program + * parameters of the low-power DDR1-SDRAM devices, in particular + * CAS latency. + * The application must write a three to the MODE field in the MPDDRC_MR + * and perform a write access to the SDRAM to acknowledge this command. + * The write address must be chosen so that signals BA[1:0] are set to 0. + */ + writel(AT91_DDRC2_MODE_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x0 << ba_offset)); + + /* + * Step 11: The application must enter Normal mode, write a zero + * to the MODE field in the MPDDRC_MR and perform a write access + * at any location in the SDRAM to acknowledge this command. + */ + writel(AT91_DDRC2_MODE_NORMAL_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* + * Step 12: Perform a write access to any low-power DDR1-SDRAM address. + */ + writel(0, ram_address); + + /* + * Step 14: Write the refresh rate into the COUNT field in the MPDDRC + * Refresh Timer Register (MPDDRC_RTR): + */ + writel(ddramc_config->rtr, base_address + AT91_HDDRSDRC2_RTR); +} diff --git a/arch/arm/mach-at91/early_udelay.c b/arch/arm/mach-at91/early_udelay.c new file mode 100644 index 0000000000..632e797beb --- /dev/null +++ b/arch/arm/mach-at91/early_udelay.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: BSD-1-Clause +/* + * Copyright (c) 2012, Atmel Corporation + */ + +#include <mach/hardware.h> +#include <asm/io.h> +#include <mach/at91_pmc_ll.h> +#include <mach/at91_pit.h> +#include <mach/early_udelay.h> + +static unsigned int master_clock; +static void __iomem *pmc, *pit; +static bool has_h32mxdiv; + +/* Because the below statement is used in the function: + * ((MASTER_CLOCK >> 10) * usec) is used, + * to our 32-bit system. the argu "usec" maximum value is: + * supposed "MASTER_CLOCK" is 132M. + * 132000000 / 1024 = 128906 + * (0xffffffff) / 128906 = 33318. + * So the maximum delay time is 33318 us. + */ +/* requires PIT to be initialized, but not the clocksource framework */ +void early_udelay(unsigned int usec) +{ + unsigned int delay; + unsigned int current; + unsigned int base = readl(pit + AT91_PIT_PIIR); + + if (has_h32mxdiv) + master_clock /= 2; + + delay = ((master_clock >> 10) * usec) >> 14; + + do { + current = readl(pit + AT91_PIT_PIIR); + current -= base; + } while (current < delay); +} + +void early_udelay_init(void __iomem *pmc_base, + void __iomem *pit_base, + unsigned int clock, + unsigned int master_clock_rate, + unsigned int flags) +{ + master_clock = master_clock_rate; + pmc = pmc_base; + pit = pit_base; + has_h32mxdiv = at91_pmc_check_mck_h32mxdiv(pmc, flags); + + writel(AT91_PIT_PIV | AT91_PIT_PITEN, pit + AT91_PIT_MR); + + at91_pmc_enable_periph_clock(pmc_base, clock); +} diff --git a/arch/arm/mach-at91/include/mach/aic.h b/arch/arm/mach-at91/include/mach/aic.h new file mode 100644 index 0000000000..c1f026b60c --- /dev/null +++ b/arch/arm/mach-at91/include/mach/aic.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: BSD-1-Clause */ +#ifndef __AT91_AIC_H_ +#define __AT91_AIC_H_ + +#include <linux/compiler.h> + +void at91_aic_redir(void __iomem *sfr, u32 key); + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h index 0ba9cdae10..29aaa2dfe1 100644 --- a/arch/arm/mach-at91/include/mach/at91_dbgu.h +++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h @@ -94,30 +94,28 @@ static inline void at91_dbgu_setup_ll(void __iomem *dbgu_base, unsigned mck, unsigned baudrate) { - if (IS_ENABLED(CONFIG_DEBUG_LL)) { - u32 brgr = mck / (baudrate * 16); + u32 brgr = mck / (baudrate * 16); - if ((mck / (baudrate * 16)) % 10 >= 5) - brgr++; + if ((mck / (baudrate * 16)) % 10 >= 5) + brgr++; - writel(~0, dbgu_base + AT91_DBGU_IDR); + writel(~0, dbgu_base + AT91_DBGU_IDR); - writel(AT91_DBGU_RSTRX - | AT91_DBGU_RSTTX - | AT91_DBGU_RXDIS - | AT91_DBGU_TXDIS, - dbgu_base + AT91_DBGU_CR); + writel(AT91_DBGU_RSTRX + | AT91_DBGU_RSTTX + | AT91_DBGU_RXDIS + | AT91_DBGU_TXDIS, + dbgu_base + AT91_DBGU_CR); - writel(brgr, dbgu_base + AT91_DBGU_BRGR); + writel(brgr, dbgu_base + AT91_DBGU_BRGR); - writel(AT91_DBGU_PAR_NONE - | AT91_DBGU_CHMODE_NORMAL - | AT91_DBGU_CHRL_8BIT - | AT91_DBGU_NBSTOP_1BIT, - dbgu_base + AT91_DBGU_MR); + writel(AT91_DBGU_PAR_NONE + | AT91_DBGU_CHMODE_NORMAL + | AT91_DBGU_CHRL_8BIT + | AT91_DBGU_NBSTOP_1BIT, + dbgu_base + AT91_DBGU_MR); - writel(AT91_DBGU_RXEN | AT91_DBGU_TXEN, dbgu_base + AT91_DBGU_CR); - } + writel(AT91_DBGU_RXEN | AT91_DBGU_TXEN, dbgu_base + AT91_DBGU_CR); } #endif diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h new file mode 100644 index 0000000000..7d70fe4cb4 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h @@ -0,0 +1,373 @@ +/* SPDX-License-Identifier: BSD-1-Clause */ +/* + * Copyright (c) 2006, Atmel Corporation + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + */ +#ifndef __AT91_DDRSDRC_H__ +#define __AT91_DDRSDRC_H__ + +/**** Register offset in AT91S_HDDRSDRC2 structure ***/ +#define AT91_HDDRSDRC2_MR 0x00 /* Mode Register */ +#define AT91_HDDRSDRC2_RTR 0x04 /* Refresh Timer Register */ +#define AT91_HDDRSDRC2_CR 0x08 /* Configuration Register */ +#define AT91_HDDRSDRC2_T0PR 0x0C /* Timing Parameter 0 Register */ +#define AT91_HDDRSDRC2_T1PR 0x10 /* Timing Parameter 1 Register */ +#define AT91_HDDRSDRC2_T2PR 0x14 /* Timing Parameter 2 Register */ +#define AT91_HDDRSDRC2_T3PR 0x18 /* Timing Parameter 3 Register */ +#define AT91_HDDRSDRC2_LPR 0x1C /* Low-power Register */ +#define AT91_HDDRSDRC2_MDR 0x20 /* Memory Device Register */ +#define AT91_HDDRSDRC2_DLL 0x24 /* DLL Information Register */ +#define AT91_HDDRSDRC2_HS 0x2C /* High Speed Register */ + +/* below items defined for sama5d3x */ +#define AT91_MPDDRC_LPDDR2_HS 0x24 /* MPDDRC LPDDR2 High Speed Register */ +#define AT91_MPDDRC_LPDDR2_LPR 0x28 /* MPDDRC LPDDR2 Low-power Register */ +#define AT91_MPDDRC_LPDDR2_CAL_MR4 0x2C /* MPDDRC LPDDR2 Calibration and MR4 Register */ +#define AT91_MPDDRC_LPDDR2_TIM_CAL 0x30 /* MPDDRC LPDDR2 Timing Calibration Register */ +#define AT91_MPDDRC_IO_CALIBR 0x34 /* MPDDRC IO Calibration */ +#define AT91_MPDDRC_OCMS 0x38 /* MPDDRC OCMS Register */ +#define AT91_MPDDRC_OCMS_KEY1 0x3C /* MPDDRC OCMS KEY1 Register */ +#define AT91_MPDDRC_OCMS_KEY2 0x40 /* MPDDRC OCMS KEY2 Register */ +/* 0x54 ~ 0x70 Reserved */ +#define AT91_MPDDRC_DLL_MOR 0x74 /* MPDDRC DLL Master Offset Register */ +#define AT91_MPDDRC_DLL_SOR 0x78 /* MPDDRC DLL Slave Offset Register */ +#define AT91_MPDDRC_DLL_MSR 0x7C /* MPDDRC DLL Master Status Register */ +#define AT91_MPDDRC_DLL_S0SR 0x80 /* MPDDRC DLL Slave 0 Status Register */ +#define AT91_MPDDRC_DLL_S1SR 0x84 /* MPDDRC DLL Slave 1 Status Register */ + +#define AT91_MPDDRC_RD_DATA_PATH 0x5C /* MPDDRC Read Data Path */ + +/* 0x94 ~ 0xE0 Reserved */ +#define AT91_HDDRSDRC2_WPCR 0xE4 /* Write Protect Mode Register */ +#define AT91_HDDRSDRC2_WPSR 0xE8 /* Write Protect Status Register */ + +/* -------- HDDRSDRC2_MR : (HDDRSDRC2 Offset: 0x0) Mode Register --------*/ +#define AT91_DDRC2_MODE (0x7UL << 0) +#define AT91_DDRC2_MODE_NORMAL_CMD (0x0UL) +#define AT91_DDRC2_MODE_NOP_CMD (0x1UL) +#define AT91_DDRC2_MODE_PRCGALL_CMD (0x2UL) +#define AT91_DDRC2_MODE_LMR_CMD (0x3UL) +#define AT91_DDRC2_MODE_RFSH_CMD (0x4UL) +#define AT91_DDRC2_MODE_EXT_LMR_CMD (0x5UL) +#define AT91_DDRC2_MODE_DEEP_CMD (0x6UL) +#define AT91_DDRC2_MODE_LPDDR2_CMD (0x7UL) +#define AT91_DDRC2_MRS(value) (value << 8) + +/* -------- HDDRSDRC2_RTR : (HDDRSDRC2 Offset: 0x4) Refresh Timer Register -------- */ +#define AT91_DDRC2_COUNT (0xFFFUL << 0) +#define AT91_DDRC2_ADJ_REF (0x1UL << 16) +#define AT91_DDRC2_DISABLE_ADJ_REF (0x0UL << 16) +#define AT91_DDRC2_ENABLE_ADJ_REF (0x1UL << 16) + +/* -------- HDDRSDRC2_CR : (HDDRSDRC2 Offset: 0x8) Configuration Register --------*/ +#define AT91_DDRC2_NC (0x3UL << 0) +#define AT91_DDRC2_NC_DDR9_SDR8 (0x0UL) +#define AT91_DDRC2_NC_DDR10_SDR9 (0x1UL) +#define AT91_DDRC2_NC_DDR11_SDR10 (0x2UL) +#define AT91_DDRC2_NC_DDR12_SDR11 (0x3UL) +#define AT91_DDRC2_NR (0x3UL << 2) +#define AT91_DDRC2_NR_11 (0x0UL << 2) +#define AT91_DDRC2_NR_12 (0x1UL << 2) +#define AT91_DDRC2_NR_13 (0x2UL << 2) +#define AT91_DDRC2_NR_14 (0x3UL << 2) +#define AT91_DDRC2_CAS (0x7UL << 4) +#define AT91_DDRC2_CAS_2 (0x2UL << 4) +#define AT91_DDRC2_CAS_3 (0x3UL << 4) +#define AT91_DDRC2_CAS_4 (0x4UL << 4) +#define AT91_DDRC2_CAS_5 (0x5UL << 4) +#define AT91_DDRC2_CAS_6 (0x6UL << 4) +#define AT91_DDRC2_RESET_DLL (0x1UL << 7) +#define AT91_DDRC2_DISABLE_RESET_DLL (0x0UL << 7) +#define AT91_DDRC2_ENABLE_RESET_DLL (0x1UL << 7) +#define AT91_DDRC2_DIC_DS (0x1UL << 8) +#define AT91_DDRC2_NORMAL_STRENGTH_RZQ6 (0x0UL << 8) +#define AT91_DDRC2_WEAK_STRENGTH_RZQ7 (0x1UL << 8) +#define AT91_DDRC2_DLL (0x1UL << 9) +#define AT91_DDRC2_ENABLE_DLL (0x0UL << 9) +#define AT91_DDRC2_DISABLE_DLL (0x1UL << 9) +#define AT91_DDRC2_ZQ (0x03 << 10) +#define AT91_DDRC2_ZQ_INIT (0x0 << 10) +#define AT91_DDRC2_ZQ_LONG (0x1 << 10) +#define AT91_DDRC2_ZQ_SHORT (0x2 << 10) +#define AT91_DDRC2_ZQ_RESET (0x3 << 10) +#define AT91_DDRC2_OCD (0x7UL << 12) +#define AT91_DDRC2_OCD_EXIT (0x0UL << 12) +#define AT91_DDRC2_OCD_DEFAULT (0x7UL << 12) +#define AT91_DDRC2_EBISHARE (0x1UL << 16) +#define AT91_DDRC2_DQMS (0x1UL << 16) +#define AT91_DDRC2_DQMS_NOT_SHARED (0x0UL << 16) +#define AT91_DDRC2_DQMS_SHARED (0x1UL << 16) +#define AT91_DDRC2_ENRDM (0x1UL << 17) +#define AT91_DDRC2_ENRDM_DISABLE (0x0UL << 17) +#define AT91_DDRC2_ENRDM_ENABLE (0x1UL << 17) +#define AT91_DDRC2_ACTBST (0x1UL << 18) +#define AT91_DDRC2_NB_BANKS (0x1UL << 20) +#define AT91_DDRC2_NB_BANKS_4 (0x0UL << 20) +#define AT91_DDRC2_NB_BANKS_8 (0x1UL << 20) +#define AT91_DDRC2_NDQS (0x1UL << 21) /* Not DQS(sama5d3x only) */ +#define AT91_DDRC2_NDQS_ENABLED (0x0UL << 21) +#define AT91_DDRC2_NDQS_DISABLED (0x1UL << 21) +#define AT91_DDRC2_DECOD (0x1UL << 22) +#define AT91_DDRC2_DECOD_SEQUENTIAL (0x0UL << 22) +#define AT91_DDRC2_DECOD_INTERLEAVED (0x1UL << 22) +#define AT91_DDRC2_UNAL (0x1UL << 23) /* Support Unaligned Access(sama5d3x only) */ +#define AT91_DDRC2_UNAL_UNSUPPORTED (0x0UL << 23) +#define AT91_DDRC2_UNAL_SUPPORTED (0x1UL << 23) + +/* -------- HDDRSDRC2_T0PR : (HDDRSDRC2 Offset: 0xc) Timing0 Register --------*/ +#define AT91_DDRC2_TRAS (0xFUL << 0) +#define AT91_DDRC2_TRAS_(x) (x & 0x0f) +#define AT91_DDRC2_TRCD (0xFUL << 4) +#define AT91_DDRC2_TRCD_(x) ((x & 0x0f) << 4) +#define AT91_DDRC2_TWR (0xFUL << 8) +#define AT91_DDRC2_TWR_(x) ((x & 0x0f) << 8) +#define AT91_DDRC2_TRC (0xFUL << 12) +#define AT91_DDRC2_TRC_(x) ((x & 0x0f) << 12) +#define AT91_DDRC2_TRP (0xFUL << 16) +#define AT91_DDRC2_TRP_(x) ((x & 0x0f) << 16) +#define AT91_DDRC2_TRRD (0xFUL << 20) +#define AT91_DDRC2_TRRD_(x) ((x & 0x0f) << 20) +#define AT91_DDRC2_TWTR (0xFUL << 24) +#define AT91_DDRC2_TWTR_(x) ((x & 0x0f) << 24) +#define AT91_DDRC2_TMRD (0xFUL << 28) +#define AT91_DDRC2_TMRD_(x) ((x & 0x0f) << 28) + +/* -------- HDDRSDRC2_T1PR : (HDDRSDRC2 Offset: 0x10) Timing1 Register -------- */ +#define AT91_DDRC2_TRFC (0x7FUL << 0) +#define AT91_DDRC2_TRFC_(x) (x & 0x7f) +#define AT91_DDRC2_TXSNR (0xFFUL << 8) +#define AT91_DDRC2_TXSNR_(x) ((x & 0xff) << 8) +#define AT91_DDRC2_TXSRD (0xFFUL << 16) +#define AT91_DDRC2_TXSRD_(x) ((x & 0xff) << 16) +#define AT91_DDRC2_TXP (0xFUL << 24) +#define AT91_DDRC2_TXP_(x) ((x & 0x0f) << 24) + +/* -------- HDDRSDRC2_T2PR : (HDDRSDRC2 Offset: 0x14) Timing2 Register --------*/ +#define AT91_DDRC2_TXARD (0xFUL << 0) +#define AT91_DDRC2_TXARD_(x) (x & 0x0f) +#define AT91_DDRC2_TXARDS (0xFUL << 4) +#define AT91_DDRC2_TXARDS_(x) ((x & 0x0f) << 4) +#define AT91_DDRC2_TRPA (0xFUL << 8) +#define AT91_DDRC2_TRPA_(x) ((x & 0x0f) << 8) +#define AT91_DDRC2_TRT (0xFUL << 12) +#define AT91_DDRC2_TRTP_(x) ((x & 0x0f) << 12) +#define AT91_DDRC2_TFA (0xFUL << 16) +#define AT91_DDRC2_TFAW_(x) ((x & 0x0f) << 16) + +/* -------- HDDRSDRC2_LPR : (HDDRSDRC2 Offset: 0x1c) --------*/ +#define AT91_DDRC2_LPCB (0x3UL << 0) +#define AT91_DDRC2_LPCB_DISABLED (0x0UL) +#define AT91_DDRC2_LPCB_SELFREFRESH (0x1UL) +#define AT91_DDRC2_LPCB_POWERDOWN (0x2UL) +#define AT91_DDRC2_LPCB_DEEP_PWD (0x3UL) +#define AT91_DDRC2_CLK_FR (0x1UL << 2) +#define AT91_DDRC2_PASR (0x7UL << 4) +#define AT91_DDRC2_PASR_(x) ((x & 0x7) << 4) +#define AT91_DDRC2_DS (0x7UL << 8) +#define AT91_DDRC2_DS_(x) ((x & 0x7) << 8) +#define AT91_DDRC2_TIMEOUT (0x3UL << 12) +#define AT91_DDRC2_TIMEOUT_0 (0x0UL << 12) +#define AT91_DDRC2_TIMEOUT_64 (0x1UL << 12) +#define AT91_DDRC2_TIMEOUT_128 (0x2UL << 12) +#define AT91_DDRC2_TIMEOUT_Reserved (0x3UL << 12) +#define AT91_DDRC2_ADPE (0x1UL << 16) +#define AT91_DDRC2_ADPE_FAST (0x0UL << 16) +#define AT91_DDRC2_ADPE_SLOW (0x1UL << 16) +#define AT91_DDRC2_UPD_MR (0x3UL << 20) +#define AT91_DDRC2_UPD_MR_NO_UPDATE (0x0UL << 20) +#define AT91_DDRC2_UPD_MR_SHARED_BUS (0x1UL << 20) +#define AT91_DDRC2_UPD_MR_NO_SHARED_BUS (0x2UL << 20) +#define AT91_DDRC2_SELF_DONE (0x1UL << 25) + +/* -------- HDDRSDRC2_MDR : (HDDRSDRC2 Offset: 0x20) Memory Device Register -------- */ +#define AT91_DDRC2_MD (0x7UL << 0) +#define AT91_DDRC2_MD_SDR_SDRAM (0x0UL) +#define AT91_DDRC2_MD_LP_SDR_SDRAM (0x1UL) +#define AT91_DDRC2_MD_DDR_SDRAM (0x2UL) +#define AT91_DDRC2_MD_LP_DDR_SDRAM (0x3UL) +#define AT91_DDRC2_MD_DDR3_SDRAM (0x4UL) +#define AT91_DDRC2_MD_LPDDR3_SDRAM (0x5UL) +#define AT91_DDRC2_MD_DDR2_SDRAM (0x6UL) +#define AT91_DDRC2_MD_LPDDR2_SDRAM (0x7UL) +#define AT91_DDRC2_DBW (0x1UL << 4) +#define AT91_DDRC2_DBW_32_BITS (0x0UL << 4) +#define AT91_DDRC2_DBW_16_BITS (0x1UL << 4) + +/* -------- HDDRSDRC2_DLL : (HDDRSDRC2 Offset: 0x24) DLL Information Register --------*/ +#define AT91_DDRC2_MDINC (0x1UL << 0) +#define AT91_DDRC2_MDDEC (0x1UL << 1) +#define AT91_DDRC2_MDOVF (0x1UL << 2) +#define AT91_DDRC2_MDVAL (0xFFUL << 8) + +/* ------- MPDDRC_LPDDR2_LPR (offset: 0x28) */ +#define AT91_LPDDRC2_BK_MASK_PASR(value) (value << 0) +#define AT91_LPDDRC2_SEG_MASK(value) (value << 8) +#define AT91_LPDDRC2_DS(value) (value << 24) + +/* -------- HDDRSDRC2_HS : (HDDRSDRC2 Offset: 0x2c) High Speed Register --------*/ +#define AT91_DDRC2_NO_ANT (0x1UL << 2) + +/* -------- MPDDRC_LPDDR2_CAL_MR4: (MPDDRC Offset: 0x2c) Calibration and MR4 Register --------*/ +#define AT91_DDRC2_COUNT_CAL_MASK (0xFFFFUL) +#define AT91_DDRC2_COUNT_CAL(value) (((value) & AT91_DDRC2_COUNT_CAL_MASK) << 0) +#define AT91_DDRC2_MR4R(value) (((value) & 0xFFFFUL) << 16) + +/* -------- MPDDRC_LPDDR2_TIM_CAL : (MPDDRC Offset: 0x30) */ +#define AT91_DDRC2_ZQCS(value) (value << 0) + +/* -------- MPDDRC_IO_CALIBR : (MPDDRC Offset: 0x34) IO Calibration --------*/ +#define AT91_MPDDRC_RDIV (0x7UL << 0) +#define AT91_MPDDRC_RDIV_LPDDR2_RZQ_34 (0x1UL << 0) +#define AT91_MPDDRC_RDIV_LPDDR2_RZQ_48 (0x3UL << 0) +#define AT91_MPDDRC_RDIV_LPDDR2_RZQ_60 (0x4UL << 0) +#define AT91_MPDDRC_RDIV_LPDDR2_RZQ_120 (0x7UL << 0) + +#define AT91_MPDDRC_RDIV_DDR2_RZQ_33_3 (0x2UL << 0) +#define AT91_MPDDRC_RDIV_DDR2_RZQ_50 (0x4UL << 0) +#define AT91_MPDDRC_RDIV_DDR2_RZQ_66_7 (0x6UL << 0) +#define AT91_MPDDRC_RDIV_DDR2_RZQ_100 (0x7UL << 0) + +#define AT91_MPDDRC_RDIV_LPDDR3_RZQ_38 (0x02UL << 0) +#define AT91_MPDDRC_RDIV_LPDDR3_RZQ_46 (0x03UL << 0) +#define AT91_MPDDRC_RDIV_LPDDR3_RZQ_57 (0x04UL << 0) +#define AT91_MPDDRC_RDIV_LPDDR3_RZQ_77 (0x06UL << 0) +#define AT91_MPDDRC_RDIV_LPDDR3_RZQ_115 (0x07UL << 0) + +#define AT91_MPDDRC_ENABLE_CALIB (0x01 << 4) +#define AT91_MPDDRC_DISABLE_CALIB (0x00 << 4) +#define AT91_MPDDRC_EN_CALIB (0x01 << 4) + +#define AT91_MPDDRC_TZQIO (0x7FUL << 8) +#define AT91_MPDDRC_TZQIO_(x) ((x) << 8) +#define AT91_MPDDRC_TZQIO_0 (0x0UL << 8) +#define AT91_MPDDRC_TZQIO_1 (0x1UL << 8) +#define AT91_MPDDRC_TZQIO_3 (0x3UL << 8) +#define AT91_MPDDRC_TZQIO_4 (0x4UL << 8) +#define AT91_MPDDRC_TZQIO_5 (0x5UL << 8) +#define AT91_MPDDRC_TZQIO_31 (0x1FUL << 8) + +#define AT91_MPDDRC_CALCODEP (0xFUL << 16) +#define AT91_MPDDRC_CALCODEP_(x) ((x) << 16) + +#define AT91_MPDDRC_CALCODEN (0xFUL << 20) +#define AT91_MPDDRC_CALCODEN_(x) ((x) << 20) + +/* ---- MPDDRC_RD_DATA_PATH : (MPDDRC Offset: 0x5c) MPDDRC Read Data Path */ +#define AT91_MPDDRC_SHIFT_SAMPLING (0x03 << 0) +#define AT91_MPDDRC_RD_DATA_PATH_NO_SHIFT (0x00 << 0) +#define AT91_MPDDRC_RD_DATA_PATH_ONE_CYCLES (0x01 << 0) +#define AT91_MPDDRC_RD_DATA_PATH_TWO_CYCLES (0x02 << 0) +#define AT91_MPDDRC_RD_DATA_PATH_THREE_CYCLES (0x03 << 0) + +/* -------- MPDDRC_DLL_MOR : (MPDDRC Offset: 0x74) DLL Master Offset Register --------*/ +#define AT91_MPDDRC_MOFF(value) (value << 0) +#define AT91_MPDDRC_MOFF_1 (0x1UL << 0) +#define AT91_MPDDRC_MOFF_7 (0x7UL << 0) +#define AT91_MPDDRC_CLK90OFF(value) (value << 8) +#define AT91_MPDDRC_CLK90OFF_1 (0x1UL << 8) +#define AT91_MPDDRC_CLK90OFF_31 (0x1FUL << 8) +#define AT91_MPDDRC_SELOFF (0x1UL << 16) +#define AT91_MPDDRC_SELOFF_DISABLED (0x0UL << 16) +#define AT91_MPDDRC_SELOFF_ENABLED (0x1UL << 16) +#define AT91_MPDDRC_KEY (0xC5UL << 24) + +/* -------- MPDDRC_DLL_SOR : (MPDDRC Offset: 0x78) DLL Slave Offset Register --------*/ +#define AT91_MPDDRC_S0OFF_1 (0x1UL << 0) +#define AT91_MPDDRC_S1OFF_1 (0x1UL << 8) +#define AT91_MPDDRC_S2OFF_1 (0x1UL << 16) +#define AT91_MPDDRC_S3OFF_1 (0x1UL << 24) + +#define AT91_MPDDRC_S0OFF(value) (value << 0) +#define AT91_MPDDRC_S1OFF(value) (value << 8) +#define AT91_MPDDRC_S2OFF(value) (value << 16) +#define AT91_MPDDRC_S3OFF(value) (value << 24) + +/* -------- HDDRSDRC2_WPCR : (HDDRSDRC2 Offset: 0xe4) Write Protect Control Register --------*/ +#define AT91_DDRC2_WPEN (0x1UL << 0) +#define AT91_DDRC2_WPKEY (0xFFFFFFUL << 8) + +/* -------- HDDRSDRC2_WPSR : (HDDRSDRC2 Offset: 0xe8) Write Protect Status Register --------*/ +#define AT91_DDRC2_WPVS (0x1UL << 0) +#define AT91_DDRC2_WPSRC (0xFFFFUL << 8) + +#ifndef __ASSEMBLY__ +#include <common.h> +#include <io.h> +#include <mach/hardware.h> + +static inline u32 at91_get_ddram_size(void __iomem *base, bool is_nb) +{ + u32 cr; + u32 mdr; + u32 size; + bool is_sdram; + + cr = readl(base + AT91_HDDRSDRC2_CR); + mdr = readl(base + AT91_HDDRSDRC2_MDR); + + /* will always be false for sama5d2, sama5d3 or sama5d4 */ + is_sdram = (mdr & AT91_DDRC2_MD) <= AT91_DDRC2_MD_LP_SDR_SDRAM; + + /* Formula: + * size = bank << (col + row + 1); + * if (bandwidth == 32 bits) + * size <<= 1; + */ + size = 1; + /* COL */ + size += (cr & AT91_DDRC2_NC) + 8; + if (!is_sdram) + size ++; + /* ROW */ + size += ((cr & AT91_DDRC2_NR) >> 2) + 11; + /* BANK */ + if (is_nb) + size = ((cr & AT91_DDRC2_NB_BANKS) ? 8 : 4) << size; + else + size = 4 << size; + + /* bandwidth */ + if (!(mdr & AT91_DDRC2_DBW)) + size <<= 1; + + return size; +} + +static inline u32 at91sam9g45_get_ddram_size(int bank) +{ + switch (bank) { + case 0: + return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC0), false); + case 1: + return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC1), false); + default: + return 0; + } +} + +static inline u32 at91sam9x5_get_ddram_size(void) +{ + return at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0), true); +} + +static inline u32 at91sam9n12_get_ddram_size(void) +{ + return at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0), true); +} + +static inline u32 at91sama5d3_get_ddram_size(void) +{ + return at91_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC), true); +} + +static inline u32 at91sama5d4_get_ddram_size(void) +{ + return at91_get_ddram_size(IOMEM(SAMA5D4_BASE_MPDDRC), true); +} + + +#endif /* __ASSEMBLY__ */ + +#endif /* #ifndef __AT91_DDRSDRC_H__ */ diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 4d60becefb..66b4e49286 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -42,6 +42,7 @@ #define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */ #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ +#define AT91_PMC_UPLLCOUNT_DEFAULT (0x1UL << 20) #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ @@ -66,9 +67,17 @@ #define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ #define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ #define AT91_PMC_DIV (0xff << 0) /* Divider */ +#define AT91_PMC_DIV_BYPASS (1 << 0) /* Divider bypass */ #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ +#define AT91_PMC_OUT_0 (0 << 14) +#define AT91_PMC_OUT_1 (1 << 14) +#define AT91_PMC_OUT_2 (2 << 14) +#define AT91_PMC_OUT_3 (3 << 14) #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ +#define AT91_PMC_MUL_(n) (((n) << 16) & AT91_PMC_MUL) +#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only]*/ +#define AT91_PMC3_MUL_(n) (((n) << 18) & AT91_PMC3_MUL) #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ #define AT91_PMC_USBDIV_1 (0 << 28) #define AT91_PMC_USBDIV_2 (1 << 28) @@ -153,6 +162,7 @@ #define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ +#define AT91_PMC_GCKRDY (1 << 24) #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ #define AT91_PMC_ICPPLLA (0xf << 0) @@ -179,6 +189,13 @@ #define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */ #define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ +#define AT91_PMC_GCKCSS (0x7 << 8) +#define AT91_PMC_GCKCSS_SLOW_CLK (0x0 << 8) +#define AT91_PMC_GCKCSS_MAIN_CLK (0x1 << 8) +#define AT91_PMC_GCKCSS_PLLA_CLK (0x2 << 8) +#define AT91_PMC_GCKCSS_UPLL_CLK (0x3 << 8) +#define AT91_PMC_GCKCSS_MCK_CLK (0x4 << 8) +#define AT91_PMC_GCKCSS_AUDIO_CLK (0x5 << 8) #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */ #define AT91_PMC_PCR_DIV_MASK (0x3 << 16) #define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor value */ @@ -186,7 +203,12 @@ #define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */ #define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */ #define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */ +#define AT91_PMC_GCKDIV (0xff << 20) +#define AT91_PMC_GCKDIV_MSK 0xff +#define AT91_PMC_GCKDIV_OFFSET 20 +#define AT91_PMC_GCKDIV_(x) (((x) & AT91_PMC_GCKDIV_MSK) << AT91_PMC_GCKDIV_OFFSET) #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ +#define AT91_PMC_GCK_EN (0x1 << 29) #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 */ #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Disable Register 1 */ diff --git a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h index eda40e8e12..85896a01d5 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h @@ -13,26 +13,44 @@ #define AT91_PMC_LL_FLAG_SAM9X5_PMC (1 << 0) #define AT91_PMC_LL_FLAG_MEASURE_XTAL (1 << 1) #define AT91_PMC_LL_FLAG_DISABLE_RC (1 << 2) +#define AT91_PMC_LL_FLAG_H32MXDIV (1 << 3) +#define AT91_PMC_LL_FLAG_PMC_UTMI (1 << 4) +#define AT91_PMC_LL_FLAG_GCSR (1 << 5) +#define AT91_PMC_LL_FLAG_MCK_BYPASS (1 << 6) #define AT91_PMC_LL_AT91RM9200 (0) #define AT91_PMC_LL_AT91SAM9260 (0) #define AT91_PMC_LL_AT91SAM9261 (0) #define AT91_PMC_LL_AT91SAM9263 (0) -#define AT91_PMC_LL_AT91SAM9G45 (0) +#define AT91_PMC_LL_AT91SAM9G45 (AT91_PMC_LL_FLAG_PMC_UTMI) #define AT91_PMC_LL_AT91SAM9X5 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ - AT91_PMC_LL_FLAG_DISABLE_RC) + AT91_PMC_LL_FLAG_DISABLE_RC | \ + AT91_PMC_LL_FLAG_PMC_UTMI) #define AT91_PMC_LL_AT91SAM9N12 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ AT91_PMC_LL_FLAG_DISABLE_RC) #define AT91_PMC_LL_SAMA5D2 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ - AT91_PMC_LL_FLAG_MEASURE_XTAL) + AT91_PMC_LL_FLAG_MEASURE_XTAL | \ + AT91_PMC_LL_FLAG_PMC_UTMI) +/* This assumes a crystal on both XIN and XOUT. If your board + * instead has an extenal oscillator on XIN only, + * AT91_PMC_LL_FLAG_MCK_BYPASS needs to be OR`ed in as well + */ #define AT91_PMC_LL_SAMA5D3 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ - AT91_PMC_LL_FLAG_DISABLE_RC) -#define AT91_PMC_LL_SAMA5D4 (AT91_PMC_LL_FLAG_SAM9X5_PMC) + AT91_PMC_LL_FLAG_DISABLE_RC | \ + AT91_PMC_LL_FLAG_PMC_UTMI) +#define AT91_PMC_LL_SAMA5D4 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ + AT91_PMC_LL_FLAG_H32MXDIV | \ + AT91_PMC_LL_FLAG_PMC_UTMI) void at91_pmc_init(void __iomem *pmc_base, unsigned int flags); void at91_pmc_cfg_mck(void __iomem *pmc_base, u32 pmc_mckr, unsigned int flags); void at91_pmc_cfg_plla(void __iomem *pmc_base, u32 pmc_pllar, unsigned int flags); +int at91_pmc_enable_generic_clock(void __iomem *pmc_base, void __iomem *sfr_base, + unsigned int periph_id, + unsigned int clk_source, unsigned int div, + unsigned int flags); + static inline void at91_pmc_init_pll(void __iomem *pmc_base, u32 pmc_pllicpr) { writel(pmc_pllicpr, pmc_base + AT91_PMC_PLLICPR); @@ -75,4 +93,13 @@ static inline int at91_pmc_sam9x5_enable_periph_clock(void __iomem *pmc_base, return 0; } +static inline bool at91_pmc_check_mck_h32mxdiv(void __iomem *pmc_base, + unsigned flags) +{ + if (flags & AT91_PMC_LL_FLAG_H32MXDIV) + return readl(pmc_base + AT91_PMC_MCKR) & AT91_PMC_H32MXDIV; + + return false; +} + #endif diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h index 36d37b9d2d..04924742a5 100644 --- a/arch/arm/mach-at91/include/mach/at91_wdt.h +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h @@ -35,4 +35,20 @@ #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ +#ifndef __ASSEMBLY__ +// SPDX-License-Identifier: BSD-1-Clause +/* + * Copyright (c) 2006, Atmel Corporation + */ + +#include <asm/io.h> + +static inline void at91_wdt_disable(void __iomem *wdt_base) +{ + u32 reg = readl(wdt_base + AT91_WDT_MR); + reg |= AT91_WDT_WDDIS; + writel(reg, wdt_base + AT91_WDT_MR); +} + +#endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h deleted file mode 100644 index 496cf70701..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Header file for the Atmel DDR/SDR SDRAM Controller - * - * Copyright (C) 2010 Atmel Corporation - * Nicolas Ferre <nicolas.ferre@atmel.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#ifndef AT91SAM9_DDRSDR_H -#define AT91SAM9_DDRSDR_H - -#define AT91_DDRSDRC_MR 0x00 /* Mode Register */ -#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */ -#define AT91_DDRSDRC_MODE_NORMAL 0 -#define AT91_DDRSDRC_MODE_NOP 1 -#define AT91_DDRSDRC_MODE_PRECHARGE 2 -#define AT91_DDRSDRC_MODE_LMR 3 -#define AT91_DDRSDRC_MODE_REFRESH 4 -#define AT91_DDRSDRC_MODE_EXT_LMR 5 -#define AT91_DDRSDRC_MODE_DEEP 6 - -#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */ -#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ - -#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */ -#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ -#define AT91_DDRSDRC_NC_SDR8 (0 << 0) -#define AT91_DDRSDRC_NC_SDR9 (1 << 0) -#define AT91_DDRSDRC_NC_SDR10 (2 << 0) -#define AT91_DDRSDRC_NC_SDR11 (3 << 0) -#define AT91_DDRSDRC_NC_DDR9 (0 << 0) -#define AT91_DDRSDRC_NC_DDR10 (1 << 0) -#define AT91_DDRSDRC_NC_DDR11 (2 << 0) -#define AT91_DDRSDRC_NC_DDR12 (3 << 0) -#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ -#define AT91_DDRSDRC_NR_11 (0 << 2) -#define AT91_DDRSDRC_NR_12 (1 << 2) -#define AT91_DDRSDRC_NR_13 (2 << 2) -#define AT91_DDRSDRC_NR_14 (3 << 2) -#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ -#define AT91_DDRSDRC_CAS_2 (2 << 4) -#define AT91_DDRSDRC_CAS_3 (3 << 4) -#define AT91_DDRSDRC_CAS_25 (6 << 4) -#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */ -#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ -#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */ -#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */ -#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */ -#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */ -#define AT91_DDRSDRC_NB (1 << 20) /* Number of -Banks [not SAM9G45] */ -#define AT91_SDRAMC_NB_4 (0 << 20) -#define AT91_SDRAMC_NB_8 (1 << 20) - -#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ -#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ -#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ -#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ -#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ -#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ -#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ -#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ -#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ -#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ -#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ - -#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ -#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ -#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ -#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ -#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ - -#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */ -#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */ -#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */ -#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */ -#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ - -#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ -#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */ -#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ -#define AT91_DDRSDRC_LPCB_DISABLE 0 -#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 -#define AT91_DDRSDRC_LPCB_POWER_DOWN 2 -#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 -#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ -#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ -#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ -#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ -#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ -#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) -#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) -#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) -#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */ -#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ - -#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ -#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */ -#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ -#define AT91_DDRSDRC_MD_SDR 0 -#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 -#define AT91CAP9_DDRSDRC_MD_DDR 2 -#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 -#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ -#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ -#define AT91_DDRSDRC_DBW_32BITS (0 << 4) -#define AT91_DDRSDRC_DBW_16BITS (1 << 4) - -#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ -#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */ -#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ -#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ -#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ -#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */ -#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */ -#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */ -#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ -#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ -#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ - -#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */ -#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ - -#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */ - -#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */ -#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */ -#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */ -#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */ - -#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */ -#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ -#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ - -#ifndef __ASSEMBLY__ -#include <io.h> -#include <mach/hardware.h> - -static inline u32 at91_get_ddram_size(void __iomem *base, bool is_nb) -{ - u32 cr; - u32 mdr; - u32 size; - bool is_sdram; - - cr = readl(base + AT91_DDRSDRC_CR); - mdr = readl(base + AT91_DDRSDRC_MDR); - - /* will always be false for sama5d2, sama5d3 or sama5d4 */ - is_sdram = (mdr & AT91_DDRSDRC_MD) <= AT91_DDRSDRC_MD_LOW_POWER_SDR; - - /* Formula: - * size = bank << (col + row + 1); - * if (bandwidth == 32 bits) - * size <<= 1; - */ - size = 1; - /* COL */ - size += (cr & AT91_DDRSDRC_NC) + 8; - if (!is_sdram) - size ++; - /* ROW */ - size += ((cr & AT91_DDRSDRC_NR) >> 2) + 11; - /* BANK */ - if (is_nb) - size = ((cr & AT91_DDRSDRC_NB) ? 8 : 4) << size; - else - size = 4 << size; - - /* bandwidth */ - if (!(mdr & AT91_DDRSDRC_DBW)) - size <<= 1; - - return size; -} - -static inline u32 at91sam9g45_get_ddram_size(int bank) -{ - switch (bank) { - case 0: - return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC0), false); - case 1: - return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC1), false); - default: - return 0; - } -} - -static inline u32 at91sam9x5_get_ddram_size(void) -{ - return at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0), true); -} - -static inline u32 at91sam9n12_get_ddram_size(void) -{ - return at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0), true); -} - -static inline u32 at91sama5d3_get_ddram_size(void) -{ - return at91_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC), true); -} - -static inline u32 at91sama5d4_get_ddram_size(void) -{ - return at91_get_ddram_size(IOMEM(SAMA5D4_BASE_MPDDRC), true); -} - -#endif - -#endif diff --git a/arch/arm/mach-at91/include/mach/barebox-arm.h b/arch/arm/mach-at91/include/mach/barebox-arm.h new file mode 100644 index 0000000000..4a65c6f8fa --- /dev/null +++ b/arch/arm/mach-at91/include/mach/barebox-arm.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AT91_BAREBOX_ARM_H_ +#define AT91_BAREBOX_ARM_H_ + +#include <asm/barebox-arm.h> + +#define SAMA5_ENTRY_FUNCTION(name, r4) \ + void name (u32 r0, u32 r1, u32 r2, u32 r3); \ + \ + static void __##name(u32); \ + \ + void NAKED __section(.text_head_entry_##name) name \ + (u32 r0, u32 r1, u32 r2, u32 r3) \ + { \ + register u32 r4 asm("r4"); \ + __barebox_arm_head(); \ + __##name(r4); \ + } \ + static void NAKED noinline __##name \ + (u32 r4) +#endif diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index 6e0f25f325..fa25a4783b 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -167,6 +167,7 @@ struct at91_socinfo { extern struct at91_socinfo at91_soc_initdata; const char *at91_get_soc_type(struct at91_socinfo *c); const char *at91_get_soc_subtype(struct at91_socinfo *c); +extern unsigned long at91_bootsource; static inline int at91_soc_is_detected(void) { diff --git a/arch/arm/mach-at91/include/mach/ddramc.h b/arch/arm/mach-at91/include/mach/ddramc.h new file mode 100644 index 0000000000..b929bf5f58 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/ddramc.h @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: BSD-1-Clause +/* + * Copyright (c) 2006, Atmel Corporation + */ +#ifndef __DDRAMC_H__ +#define __DDRAMC_H__ + +/* Note: reserved bits must always be zeroed */ +struct at91_ddramc_register { + unsigned long mdr; + unsigned long cr; + unsigned long rtr; + unsigned long t0pr; + unsigned long t1pr; + unsigned long t2pr; + unsigned long lpr; + unsigned long lpddr2_lpr; + unsigned long tim_calr; + unsigned long cal_mr4r; +}; + +void at91_ddram_initialize(void __iomem *base_address, + void __iomem *ram_address, + struct at91_ddramc_register *ddramc_config); + +void at91_lpddr2_sdram_initialize(void __iomem *base_address, + void __iomem *ram_address, + struct at91_ddramc_register *ddramc_config); + + +void at91_lpddr1_sdram_initialize(void __iomem *base_address, + void __iomem *ram_address, + struct at91_ddramc_register *ddramc_config); + +void __noreturn sama5d2_barebox_entry(unsigned int r4, void *boarddata); + +#endif /* #ifndef __DDRAMC_H__ */ diff --git a/arch/arm/mach-at91/include/mach/debug_ll.h b/arch/arm/mach-at91/include/mach/debug_ll.h index b713930424..b3cbdbc26f 100644 --- a/arch/arm/mach-at91/include/mach/debug_ll.h +++ b/arch/arm/mach-at91/include/mach/debug_ll.h @@ -9,6 +9,9 @@ #define __MACH_DEBUG_LL_H__ #include <asm/io.h> +#include <mach/gpio.h> +#include <mach/hardware.h> +#include <mach/at91_dbgu.h> #define ATMEL_US_CSR 0x0014 #define ATMEL_US_THR 0x001c @@ -22,13 +25,19 @@ * * This does not append a newline */ -static inline void PUTC_LL(char c) +static inline void at91_dbgu_putc(void __iomem *base, int c) { - while (!(readl(CONFIG_DEBUG_AT91_UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXRDY)) + while (!(readl(base + ATMEL_US_CSR) & ATMEL_US_TXRDY)) barrier(); - writel(c, CONFIG_DEBUG_AT91_UART_BASE + ATMEL_US_THR); + writel(c, base + ATMEL_US_THR); - while (!(readl(CONFIG_DEBUG_AT91_UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) + while (!(readl(base + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) barrier(); } + +static inline void PUTC_LL(char c) +{ + at91_dbgu_putc(IOMEM(CONFIG_DEBUG_AT91_UART_BASE), c); +} + #endif diff --git a/arch/arm/mach-at91/include/mach/early_udelay.h b/arch/arm/mach-at91/include/mach/early_udelay.h new file mode 100644 index 0000000000..1c1b0123fe --- /dev/null +++ b/arch/arm/mach-at91/include/mach/early_udelay.h @@ -0,0 +1,14 @@ +#ifndef __EARLY_UDELAY_H__ +#define __EARLY_UDELAY_H__ + +#include <linux/compiler.h> + +/* requires PIT to be initialized, but not the clocksource framework */ +void early_udelay(unsigned int usec); +void early_udelay_init(void __iomem *pmc_base, + void __iomem *pit_base, + unsigned int clock, + unsigned int master_clock_rate, + unsigned int flags); + +#endif diff --git a/arch/arm/mach-at91/include/mach/matrix.h b/arch/arm/mach-at91/include/mach/matrix.h new file mode 100644 index 0000000000..5dbfcfe414 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/matrix.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: BSD-1-Clause */ +/* + * Copyright (c) 2013, Atmel Corporation + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + */ +#ifndef __MATRIX_H__ +#define __MATRIX_H__ + +#include <linux/compiler.h> + +void at91_matrix_write_protect_enable(void __iomem *matrix_base); +void at91_matrix_write_protect_disable(void __iomem *matrix_base); +void at91_matrix_configure_slave_security(void __iomem *matrix_base, + unsigned int slave, + unsigned int srtop_setting, + unsigned int srsplit_setting, + unsigned int ssr_setting); + +#endif /* #ifndef __MATRIX_H__ */ diff --git a/arch/arm/mach-at91/include/mach/sama5_bootsource.h b/arch/arm/mach-at91/include/mach/sama5_bootsource.h new file mode 100644 index 0000000000..8355c2eeb6 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5_bootsource.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AT91_SAMA5_BOOTSOURCE_H_ +#define AT91_SAMA5_BOOTSOURCE_H_ + +#include <errno.h> +#include <bootsource.h> +#include <linux/bitops.h> +#include <linux/bitfield.h> +#include <mach/hardware.h> + +/* Boot modes stored by BootROM in r4 */ +#define SAMA5_BOOTSOURCE_SPI 0 +#define SAMA5_BOOTSOURCE_MCI 1 +#define SAMA5_BOOTSOURCE_SMC 2 +#define SAMA5_BOOTSOURCE_TWI 3 +#define SAMA5_BOOTSOURCE_QSPI 4 +#define SAMA5_BOOTSOURCE_SAM_BA 7 + +#define SAMA5_BOOTSOURCE GENMASK(3, 0) +#define SAMA5_BOOTSOURCE_INSTANCE GENMASK(7, 4) + +static inline int sama5_bootsource(u32 reg) +{ + u32 dev = FIELD_GET(SAMA5_BOOTSOURCE, reg); + + switch(dev) { + case SAMA5_BOOTSOURCE_MCI: + return BOOTSOURCE_MMC; + case SAMA5_BOOTSOURCE_SPI: + return BOOTSOURCE_SPI_NOR; + case SAMA5_BOOTSOURCE_QSPI: + return BOOTSOURCE_SPI; + case SAMA5_BOOTSOURCE_SMC: + return BOOTSOURCE_NAND; + case SAMA5_BOOTSOURCE_SAM_BA: + return BOOTSOURCE_SERIAL; + } + return BOOTSOURCE_UNKNOWN; +} + +static inline int sama5_bootsource_instance(u32 reg) +{ + return FIELD_GET(SAMA5_BOOTSOURCE_INSTANCE, reg); +} + +#define __sama5d2_stashed_bootrom_r4 \ + (*(volatile u32 *)(SAMA5D2_SRAM_BASE + SAMA5D2_SRAM_SIZE - 0x4)) + +static inline void __noreturn sama5_boot_xload(void __noreturn (*bb)(void), u32 r4) +{ + asm volatile("mov r4, %0" : : "r"(r4) : ); + asm volatile("bx %0" : : "r"(bb) : ); + __builtin_unreachable(); +} + +#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d2-sip-ddramc.h b/arch/arm/mach-at91/include/mach/sama5d2-sip-ddramc.h new file mode 100644 index 0000000000..35c92c43fc --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d2-sip-ddramc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: BSD-1-Clause + * + * Copyright (C) 2014, Atmel Corporation + * + * SAMA5D27 System-in-Package DDRAMC configuration + */ + +#include <mach/at91_ddrsdrc.h> +#include <mach/ddramc.h> +#include <mach/sama5d2_ll.h> + +static inline void sama5d2_d1g_ddrconf(void) /* DDR2 1Gbit SDRAM */ +{ + struct at91_ddramc_register conf = { + .mdr = AT91_DDRC2_DBW_16_BITS | AT91_DDRC2_MD_DDR2_SDRAM, + + .cr = AT91_DDRC2_NC_DDR10_SDR9 | AT91_DDRC2_NR_13 | + AT91_DDRC2_CAS_3 | AT91_DDRC2_DISABLE_RESET_DLL | + AT91_DDRC2_WEAK_STRENGTH_RZQ7 | AT91_DDRC2_ENABLE_DLL | + AT91_DDRC2_NB_BANKS_8 | AT91_DDRC2_NDQS_ENABLED | + AT91_DDRC2_DECOD_INTERLEAVED | AT91_DDRC2_UNAL_SUPPORTED, + + .rtr = 0x511, + + .t0pr = AT91_DDRC2_TRAS_(7) | AT91_DDRC2_TRCD_(3) | + AT91_DDRC2_TWR_(3) | AT91_DDRC2_TRC_(9) | + AT91_DDRC2_TRP_(3) | AT91_DDRC2_TRRD_(2) | + AT91_DDRC2_TWTR_(2) | AT91_DDRC2_TMRD_(2), + + .t1pr = AT91_DDRC2_TRFC_(22) | AT91_DDRC2_TXSNR_(23) | + AT91_DDRC2_TXSRD_(200) | AT91_DDRC2_TXP_(2), + + .t2pr = AT91_DDRC2_TXARD_(2) | AT91_DDRC2_TXARDS_(8) | + AT91_DDRC2_TRPA_(4) | AT91_DDRC2_TRTP_(2) | + AT91_DDRC2_TFAW_(8), + }; + + sama5d2_ddr2_init(&conf); +} diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index 3dad7d9c9c..90b566ffc4 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -14,6 +14,11 @@ #ifndef SAMA5D2_H #define SAMA5D2_H +#include <asm/io.h> +#include <linux/sizes.h> +#include <linux/bitops.h> +#include <linux/bitfield.h> + /* * Peripheral identifiers/interrupts. (Table 18-9) */ @@ -101,100 +106,100 @@ * User Peripheral physical base addresses. */ -#define SAMA5D2_BASE_LCDC 0xf0000000 -#define SAMA5D2_BASE_XDMAC1 0xf0004000 -#define SAMA5D2_BASE_HXISI 0xf0008000 -#define SAMA5D2_BASE_MPDDRC 0xf000c000 -#define SAMA5D2_BASE_XDMAC0 0xf0010000 -#define SAMA5D2_BASE_PMC 0xf0014000 -#define SAMA5D2_BASE_MATRIX64 0xf0018000 /* MATRIX0 */ -#define SAMA5D2_BASE_AESB 0xf001c000 -#define SAMA5D2_BASE_QSPI0 0xf0020000 -#define SAMA5D2_BASE_QSPI1 0xf0024000 -#define SAMA5D2_BASE_SHA 0xf0028000 -#define SAMA5D2_BASE_AES 0xf002c000 +#define SAMA5D2_BASE_LCDC IOMEM(0xf0000000) +#define SAMA5D2_BASE_XDMAC1 IOMEM(0xf0004000) +#define SAMA5D2_BASE_HXISI IOMEM(0xf0008000) +#define SAMA5D2_BASE_MPDDRC IOMEM(0xf000c000) +#define SAMA5D2_BASE_XDMAC0 IOMEM(0xf0010000) +#define SAMA5D2_BASE_PMC IOMEM(0xf0014000) +#define SAMA5D2_BASE_MATRIX64 IOMEM(0xf0018000) /* MATRIX0 */ +#define SAMA5D2_BASE_AESB IOMEM(0xf001c000) +#define SAMA5D2_BASE_QSPI0 IOMEM(0xf0020000) +#define SAMA5D2_BASE_QSPI1 IOMEM(0xf0024000) +#define SAMA5D2_BASE_SHA IOMEM(0xf0028000) +#define SAMA5D2_BASE_AES IOMEM(0xf002c000) -#define SAMA5D2_BASE_SPI0 0xf8000000 -#define SAMA5D2_BASE_SSC0 0xf8004000 -#define SAMA5D2_BASE_GMAC 0xf8008000 -#define SAMA5D2_BASE_TC0 0xf800c000 -#define SAMA5D2_BASE_TC1 0xf8010000 -#define SAMA5D2_BASE_HSMC 0xf8014000 -#define SAMA5D2_BASE_PDMIC 0xf8018000 -#define SAMA5D2_BASE_UART0 0xf801c000 -#define SAMA5D2_BASE_UART1 0xf8020000 -#define SAMA5D2_BASE_UART2 0xf8024000 -#define SAMA5D2_BASE_TWI0 0xf8028000 -#define SAMA5D2_BASE_PWMC 0xf802c000 -#define SAMA5D2_BASE_SFR 0xf8030000 -#define SAMA5D2_BASE_FLEXCOM0 0xf8034000 -#define SAMA5D2_BASE_FLEXCOM1 0xf8038000 -#define SAMA5D2_BASE_SAIC 0xf803c000 -#define SAMA5D2_BASE_ICM 0xf8040000 -#define SAMA5D2_BASE_SECURAM 0xf8044000 -#define SAMA5D2_BASE_SYSC 0xf8048000 -#define SAMA5D2_BASE_ACC 0xf804a000 -#define SAMA5D2_BASE_SFC 0xf804c000 -#define SAMA5D2_BASE_I2SC0 0xf8050000 -#define SAMA5D2_BASE_CAN0 0xf8054000 +#define SAMA5D2_BASE_SPI0 IOMEM(0xf8000000) +#define SAMA5D2_BASE_SSC0 IOMEM(0xf8004000) +#define SAMA5D2_BASE_GMAC IOMEM(0xf8008000) +#define SAMA5D2_BASE_TC0 IOMEM(0xf800c000) +#define SAMA5D2_BASE_TC1 IOMEM(0xf8010000) +#define SAMA5D2_BASE_HSMC IOMEM(0xf8014000) +#define SAMA5D2_BASE_PDMIC IOMEM(0xf8018000) +#define SAMA5D2_BASE_UART0 IOMEM(0xf801c000) +#define SAMA5D2_BASE_UART1 IOMEM(0xf8020000) +#define SAMA5D2_BASE_UART2 IOMEM(0xf8024000) +#define SAMA5D2_BASE_TWI0 IOMEM(0xf8028000) +#define SAMA5D2_BASE_PWMC IOMEM(0xf802c000) +#define SAMA5D2_BASE_SFR IOMEM(0xf8030000) +#define SAMA5D2_BASE_FLEXCOM0 IOMEM(0xf8034000) +#define SAMA5D2_BASE_FLEXCOM1 IOMEM(0xf8038000) +#define SAMA5D2_BASE_SAIC IOMEM(0xf803c000) +#define SAMA5D2_BASE_ICM IOMEM(0xf8040000) +#define SAMA5D2_BASE_SECURAM IOMEM(0xf8044000) +#define SAMA5D2_BASE_SYSC IOMEM(0xf8048000) +#define SAMA5D2_BASE_ACC IOMEM(0xf804a000) +#define SAMA5D2_BASE_SFC IOMEM(0xf804c000) +#define SAMA5D2_BASE_I2SC0 IOMEM(0xf8050000) +#define SAMA5D2_BASE_CAN0 IOMEM(0xf8054000) -#define SAMA5D2_BASE_SPI1 0xfc000000 -#define SAMA5D2_BASE_SSC1 0xfc004000 -#define SAMA5D2_BASE_UART3 0xfc008000 -#define SAMA5D2_BASE_UART4 0xfc00c000 -#define SAMA5D2_BASE_FLEXCOM2 0xfc010000 -#define SAMA5D2_BASE_FLEXCOM3 0xfc014000 -#define SAMA5D2_BASE_FLEXCOM4 0xfc018000 -#define SAMA5D2_BASE_TRNG 0xfc01c000 -#define SAMA5D2_BASE_AIC 0xfc020000 -#define SAMA5D2_BASE_TWI1 0xfc028000 -#define SAMA5D2_BASE_UDPHS 0xfc02c000 -#define SAMA5D2_BASE_ADC 0xfc030000 +#define SAMA5D2_BASE_SPI1 IOMEM(0xfc000000) +#define SAMA5D2_BASE_SSC1 IOMEM(0xfc004000) +#define SAMA5D2_BASE_UART3 IOMEM(0xfc008000) +#define SAMA5D2_BASE_UART4 IOMEM(0xfc00c000) +#define SAMA5D2_BASE_FLEXCOM2 IOMEM(0xfc010000) +#define SAMA5D2_BASE_FLEXCOM3 IOMEM(0xfc014000) +#define SAMA5D2_BASE_FLEXCOM4 IOMEM(0xfc018000) +#define SAMA5D2_BASE_TRNG IOMEM(0xfc01c000) +#define SAMA5D2_BASE_AIC IOMEM(0xfc020000) +#define SAMA5D2_BASE_TWI1 IOMEM(0xfc028000) +#define SAMA5D2_BASE_UDPHS IOMEM(0xfc02c000) +#define SAMA5D2_BASE_ADC IOMEM(0xfc030000) -#define SAMA5D2_BASE_PIOA 0xfc038000 -#define SAMA5D2_BASE_MATRIX32 0xfc03c000 /* MATRIX1 */ -#define SAMA5D2_BASE_SECUMOD 0xfc040000 -#define SAMA5D2_BASE_TDES 0xfc044000 -#define SAMA5D2_BASE_CLASSD 0xfc048000 -#define SAMA5D2_BASE_I2SC1 0xfc04c000 -#define SAMA5D2_BASE_CAN1 0xfc050000 -#define SAMA5D2_BASE_SFRBU 0xfc05c000 -#define SAMA5D2_BASE_CHIPID 0xfc069000 +#define SAMA5D2_BASE_PIOA IOMEM(0xfc038000) +#define SAMA5D2_BASE_MATRIX32 IOMEM(0xfc03c000) /* MATRIX1 */ +#define SAMA5D2_BASE_SECUMOD IOMEM(0xfc040000) +#define SAMA5D2_BASE_TDES IOMEM(0xfc044000) +#define SAMA5D2_BASE_CLASSD IOMEM(0xfc048000) +#define SAMA5D2_BASE_I2SC1 IOMEM(0xfc04c000) +#define SAMA5D2_BASE_CAN1 IOMEM(0xfc050000) +#define SAMA5D2_BASE_SFRBU IOMEM(0xfc05c000) +#define SAMA5D2_BASE_CHIPID IOMEM(0xfc069000) /* * Address Memory Space */ -#define SAMA5D2_BASE_INTERNAL_MEM 0x00000000 -#define SAMA5D2_BASE_CS0 0x10000000 -#define SAMA5D2_BASE_DDRCS 0x20000000 -#define SAMA5D2_BASE_DDRCS_AES 0x40000000 -#define SAMA5D2_BASE_CS1 0x60000000 -#define SAMA5D2_BASE_CS2 0x70000000 -#define SAMA5D2_BASE_CS3 0x80000000 -#define SAMA5D2_BASE_QSPI0_AES_MEM 0x90000000 -#define SAMA5D2_BASE_QSPI1_AES_MEM 0x98000000 -#define SAMA5D2_BASE_SDHC0 0xa0000000 -#define SAMA5D2_BASE_SDHC1 0xb0000000 -#define SAMA5D2_BASE_NFC_CMD_REG 0xc0000000 -#define SAMA5D2_BASE_QSPI0_MEM 0xd0000000 -#define SAMA5D2_BASE_QSPI1_MEM 0xd8000000 -#define SAMA5D2_BASE_PERIPH 0xf0000000 +#define SAMA5D2_BASE_INTERNAL_MEM IOMEM(0x00000000) +#define SAMA5D2_BASE_CS0 IOMEM(0x10000000) +#define SAMA5D2_BASE_DDRCS IOMEM(0x20000000) +#define SAMA5D2_BASE_DDRCS_AES IOMEM(0x40000000) +#define SAMA5D2_BASE_CS1 IOMEM(0x60000000) +#define SAMA5D2_BASE_CS2 IOMEM(0x70000000) +#define SAMA5D2_BASE_CS3 IOMEM(0x80000000) +#define SAMA5D2_BASE_QSPI0_AES_MEM IOMEM(0x90000000) +#define SAMA5D2_BASE_QSPI1_AES_MEM IOMEM(0x98000000) +#define SAMA5D2_BASE_SDHC0 IOMEM(0xa0000000) +#define SAMA5D2_BASE_SDHC1 IOMEM(0xb0000000) +#define SAMA5D2_BASE_NFC_CMD_REG IOMEM(0xc0000000) +#define SAMA5D2_BASE_QSPI0_MEM IOMEM(0xd0000000) +#define SAMA5D2_BASE_QSPI1_MEM IOMEM(0xd8000000) +#define SAMA5D2_BASE_PERIPH IOMEM(0xf0000000) /* * Internal Memories */ -#define SAMA5D2_BASE_ROM 0x00000000 /* ROM */ -#define SAMA5D2_BASE_ECC_ROM 0x00060000 /* ECC ROM */ -#define SAMA5D2_BASE_NFC_SRAM 0x00100000 /* NFC SRAM */ -#define SAMA5D2_BASE_SRAM0 0x00200000 /* SRAM0 */ -#define SAMA5D2_BASE_SRAM1 0x00220000 /* SRAM1 */ -#define SAMA5D2_BASE_UDPHS_SRAM 0x00300000 /* UDPHS RAM */ -#define SAMA5D2_BASE_UHP_OHCI 0x00400000 /* UHP OHCI */ -#define SAMA5D2_BASE_UHP_EHCI 0x00500000 /* UHP EHCI */ -#define SAMA5D2_BASE_AXI_MATRIX 0x00600000 /* AXI Maxtrix */ -#define SAMA5D2_BASE_DAP 0x00700000 /* DAP */ -#define SAMA5D2_BASE_PTC 0x00800000 /* PTC */ -#define SAMA5D2_BASE_L2CC 0x00A00000 /* L2CC */ +#define SAMA5D2_BASE_ROM IOMEM(0x00000000) /* ROM */ +#define SAMA5D2_BASE_ECC_ROM IOMEM(0x00060000) /* ECC ROM */ +#define SAMA5D2_BASE_NFC_SRAM 0x00100000 /* NFC SRAM */ +#define SAMA5D2_BASE_SRAM0 0x00200000 /* SRAM0 */ +#define SAMA5D2_BASE_SRAM1 0x00220000 /* SRAM1 */ +#define SAMA5D2_BASE_UDPHS_SRAM 0x00300000 /* UDPHS RAM */ +#define SAMA5D2_BASE_UHP_OHCI IOMEM(0x00400000) /* UHP OHCI */ +#define SAMA5D2_BASE_UHP_EHCI IOMEM(0x00500000) /* UHP EHCI */ +#define SAMA5D2_BASE_AXI_MATRIX IOMEM(0x00600000) /* AXI Maxtrix */ +#define SAMA5D2_BASE_DAP IOMEM(0x00700000) /* DAP */ +#define SAMA5D2_BASE_PTC IOMEM(0x00800000) /* PTC */ +#define SAMA5D2_BASE_L2CC IOMEM(0x00A00000) /* L2CC */ /* * Other misc defines @@ -258,4 +263,58 @@ #define SAMA5D2_SRAM_BASE SAMA5D2_BASE_SRAM0 #define SAMA5D2_SRAM_SIZE (128 * SZ_1K) +static inline void __iomem *sama5d2_pio_map_bank(int bank, unsigned *id) +{ + switch(bank + 'A') { + case 'A': + *id = SAMA5D2_ID_PIOA; + return SAMA5D2_BASE_PIOA; + case 'B': + *id = SAMA5D2_ID_PIOB; + return SAMA5D2_BASE_PIOB; + case 'C': + *id = SAMA5D2_ID_PIOC; + return SAMA5D2_BASE_PIOC; + case 'D': + *id = SAMA5D2_ID_PIOD; + return SAMA5D2_BASE_PIOD; + } + + return NULL; +} + +#define SAMA5D2_BUREG_INDEX GENMASK(1, 0) +#define SAMA5D2_BUREG_VALID BIT(2) + +#define SAMA5D2_SFC_DR(x) (SAMA5D2_BASE_SFC + 0x20 + 4 * (x)) + +#define SAMA5D2_BOOTCFG_QSPI_0 GENMASK(1, 0) +#define SAMA5D2_BOOTCFG_QSPI_1 GENMASK(3, 2) +#define SAMA5D2_BOOTCFG_SPI_0 GENMASK(5, 4) +#define SAMA5D2_BOOTCFG_SPI_1 GENMASK(7, 6) +#define SAMA5D2_BOOTCFG_NFC GENMASK(9, 8) +#define SAMA5D2_BOOTCFG_SDMMC_0 BIT(10) +#define SAMA5D2_BOOTCFG_SDMMC_1 BIT(11) +#define SAMA5D2_BOOTCFG_UART GENMASK(15, 12) +#define SAMA5D2_BOOTCFG_JTAG GENMASK(17, 16) +#define SAMA5D2_BOOTCFG_EXT_MEM_BOOT_EN BIT(18) +#define SAMA5D2_BOOTCFG_QSPI_XIP BIT(21) +#define SAMA5D2_DISABLE_BSC_CR BIT(22) +#define SAMA5D2_DISABLE_MONITOR BIT(24) +#define SAMA5D2_SECURE_MODE BIT(29) + +static inline u32 sama5d2_bootcfg(void) +{ + u32 __iomem *bureg = SAMA5D2_BASE_SECURAM + 0x1400; + u32 bsc_cr = readl(SAMA5D2_BASE_SYSC + 0x54); + u32 __iomem *bootcfg; + + if (bsc_cr & SAMA5D2_BUREG_VALID) + bootcfg = &bureg[FIELD_GET(SAMA5D2_BUREG_INDEX, bsc_cr)]; + else + bootcfg = SAMA5D2_SFC_DR(512 / 32); + + return readl(bootcfg); +} + #endif diff --git a/arch/arm/mach-at91/include/mach/sama5d2_ll.h b/arch/arm/mach-at91/include/mach/sama5d2_ll.h new file mode 100644 index 0000000000..96f3bc5452 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d2_ll.h @@ -0,0 +1,139 @@ +#ifndef __MACH_SAMA5D2_LL__ +#define __MACH_SAMA5D2_LL__ + +#include <mach/sama5d2.h> +#include <mach/at91_pmc_ll.h> +#include <mach/iomux.h> +#include <mach/debug_ll.h> +#include <mach/early_udelay.h> +#include <mach/ddramc.h> + +#include <common.h> + +void sama5d2_lowlevel_init(void); + +static inline void sama5d2_pmc_enable_periph_clock(int clk) +{ + at91_pmc_sam9x5_enable_periph_clock(SAMA5D2_BASE_PMC, clk); +} + +/* requires relocation */ +static inline void sama5d2_udelay_init(unsigned int msc) +{ + early_udelay_init(SAMA5D2_BASE_PMC, SAMA5D2_BASE_PITC, + SAMA5D2_ID_PIT, msc, AT91_PMC_LL_SAMA5D2); +} + + +void sama5d2_ddr2_init(struct at91_ddramc_register *ddramc_reg_config); + +static inline int sama5d2_pmc_enable_generic_clock(unsigned int periph_id, + unsigned int clk_source, + unsigned int div) +{ + return at91_pmc_enable_generic_clock(SAMA5D2_BASE_PMC, + SAMA5D2_BASE_SFR, + periph_id, clk_source, div, + AT91_PMC_LL_SAMA5D2); +} + +static inline int sama5d2_dbgu_setup_ll(unsigned dbgu_id, + unsigned pin, unsigned periph, + unsigned mck) +{ + unsigned mask, bank, pio_id; + void __iomem *dbgu_base, *pio_base; + + mask = pin_to_mask(pin); + bank = pin_to_bank(pin); + + switch (dbgu_id) { + case SAMA5D2_ID_UART0: + dbgu_base = SAMA5D2_BASE_UART0; + break; + case SAMA5D2_ID_UART1: + dbgu_base = SAMA5D2_BASE_UART1; + break; + case SAMA5D2_ID_UART2: + dbgu_base = SAMA5D2_BASE_UART2; + break; + case SAMA5D2_ID_UART3: + dbgu_base = SAMA5D2_BASE_UART3; + break; + case SAMA5D2_ID_UART4: + dbgu_base = SAMA5D2_BASE_UART4; + break; + default: + return -EINVAL; + } + + pio_base = sama5d2_pio_map_bank(bank, &pio_id); + if (!pio_base) + return -EINVAL; + + sama5d2_pmc_enable_periph_clock(pio_id); + + at91_mux_pio4_set_periph(pio_base, mask, periph); + + sama5d2_pmc_enable_periph_clock(dbgu_id); + + at91_dbgu_setup_ll(dbgu_base, mck / 2, CONFIG_BAUDRATE); + + return 0; +} + +struct sama5d2_uart_pinmux { + void __iomem *base; + u8 id, dtxd, periph; +}; + +#define SAMA5D2_UART(idx, pio, periph) (struct sama5d2_uart_pinmux) { \ + SAMA5D2_BASE_UART##idx, SAMA5D2_ID_UART##idx, \ + AT91_PIN_##pio, AT91_MUX_PERIPH_##periph } + +static inline void __iomem *sama5d2_resetup_uart_console(unsigned mck) +{ + struct sama5d2_uart_pinmux pinmux; + + /* Table 48-2 I/O Lines and 16.4.4 Boot Configuration Word */ + + switch (FIELD_GET(SAMA5D2_BOOTCFG_UART, sama5d2_bootcfg())) { + case 0: /* UART_1_IOSET_1 */ + pinmux = SAMA5D2_UART(1, PD3, A); + break; + case 1: /* UART_0_IOSET_1 */ + pinmux = SAMA5D2_UART(0, PB27, C); + break; + case 2: /* UART_1_IOSET_2 */ + pinmux = SAMA5D2_UART(1, PC8, E); + break; + case 3: /* UART_2_IOSET_1 */ + pinmux = SAMA5D2_UART(2, PD5, B); + break; + case 4: /* UART_2_IOSET_2 */ + pinmux = SAMA5D2_UART(2, PD24, A); + break; + case 5: /* UART_2_IOSET_3 */ + pinmux = SAMA5D2_UART(2, PD20, C); + break; + case 6: /* UART_3_IOSET_1 */ + pinmux = SAMA5D2_UART(3, PC13, D); + break; + case 7: /* UART_3_IOSET_2 */ + pinmux = SAMA5D2_UART(3, PD0, C); + break; + case 8: /* UART_3_IOSET_3 */ + pinmux = SAMA5D2_UART(3, PB12, C); + break; + case 9: /* UART_4_IOSET_1 */ + pinmux = SAMA5D2_UART(4, PB4, A); + break; + default: + return NULL; + } + + sama5d2_dbgu_setup_ll(pinmux.id, pinmux.dtxd, pinmux.periph, mck); + return pinmux.base; +} + +#endif diff --git a/arch/arm/mach-at91/include/mach/tz_matrix.h b/arch/arm/mach-at91/include/mach/tz_matrix.h new file mode 100644 index 0000000000..85589bfa65 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/tz_matrix.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: BSD-1-Clause */ +/* + * Copyright (c) 2013, Atmel Corporation + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + */ +#ifndef __TZ_MATRIX_H__ +#define __TZ_MATRIX_H__ + +#define MATRIX_MCFG(n) (0x0000 + (n) * 4)/* Master Configuration Register */ +#define MATRIX_SCFG(n) (0x0040 + (n) * 4)/* Slave Configuration Register */ +#define MATRIX_PRAS(n) (0x0080 + (n) * 8)/* Priority Register A for Slave */ +#define MATRIX_PRBS(n) (0x0084 + (n) * 8)/* Priority Register B for Slave */ + +#define MATRIX_MRCR 0x0100 /* Master Remap Control Register */ +#define MATRIX_MEIER 0x0150 /* Master Error Interrupt Enable Register */ +#define MATRIX_MEIDR 0x0154 /* Master Error Interrupt Disable Register */ +#define MATRIX_MEIMR 0x0158 /* Master Error Interrupt Mask Register */ +#define MATRIX_MESR 0x015c /* Master Error Statue Register */ + +/* Master n Error Address Register */ +#define MATRIX_MEAR(n) (0x0160 + (n) * 4) + +#define MATRIX_WPMR 0x01E4 /* Write Protect Mode Register */ +#define MATRIX_WPSR 0x01E8 /* Write Protect Status Register */ + +/* Security Slave n Register */ +#define MATRIX_SSR(n) (0x0200 + (n) * 4) +/* Security Area Split Slave n Register */ +#define MATRIX_SASSR(n) (0x0240 + (n) * 4) +/* Security Region Top Slave n Register */ +#define MATRIX_SRTSR(n) (0x0280 + (n) * 4) + +/* Security Peripheral Select n Register */ +#define MATRIX_SPSELR(n) (0x02c0 + (n) * 4) + +/**************************************************************************/ +/* Write Protect Mode Register (MATRIX_WPMR) */ +#define MATRIX_WPMR_WPEN (1 << 0) /* Write Protect Enable */ +#define MATRIX_WPMR_WPEN_DISABLE (0 << 0) +#define MATRIX_WPMR_WPEN_ENABLE (1 << 0) +#define MATRIX_WPMR_WPKEY (PASSWD << 8) /* Write Protect KEY */ +#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154 << 8) + +/* Security Slave Registers (MATRIX_SSRx) */ +#define MATRIX_LANSECH(n, bit) ((bit) << n) +#define MATRIX_LANSECH_S(n) (0x00 << n) +#define MATRIX_LANSECH_NS(n) (0x01 << n) +#define MATRIX_RDNSECH(n, bit) ((bit) << (n + 8)) +#define MATRIX_RDNSECH_S(n) (0x00 << (n + 8)) +#define MATRIX_RDNSECH_NS(n) (0x01 << (n + 8)) +#define MATRIX_WRNSECH(n, bit) ((bit) << (n + 16)) +#define MATRIX_WRNSECH_S(n) (0x00 << (n + 16)) +#define MATRIX_WRNSECH_NS(n) (0x01 << (n + 16)) + +/* Security Areas Split Slave Registers (MATRIX_SASSRx) */ +#define MATRIX_SASPLIT(n, value) ((value) << (4 * n)) +#define MATRIX_SASPLIT_VALUE_4K 0x00 +#define MATRIX_SASPLIT_VALUE_8K 0x01 +#define MATRIX_SASPLIT_VALUE_16K 0x02 +#define MATRIX_SASPLIT_VALUE_32K 0x03 +#define MATRIX_SASPLIT_VALUE_64K 0x04 +#define MATRIX_SASPLIT_VALUE_128K 0x05 +#define MATRIX_SASPLIT_VALUE_256K 0x06 +#define MATRIX_SASPLIT_VALUE_512K 0x07 +#define MATRIX_SASPLIT_VALUE_1M 0x08 +#define MATRIX_SASPLIT_VALUE_2M 0x09 +#define MATRIX_SASPLIT_VALUE_4M 0x0a +#define MATRIX_SASPLIT_VALUE_8M 0x0b +#define MATRIX_SASPLIT_VALUE_16M 0x0c +#define MATRIX_SASPLIT_VALUE_32M 0x0d +#define MATRIX_SASPLIT_VALUE_64M 0x0e +#define MATRIX_SASPLIT_VALUE_128M 0x0f + +/* Security Region Top Slave Registers (MATRIX_SRTSRx) */ +#define MATRIX_SRTOP(n, value) ((value) << (4 * n)) +#define MATRIX_SRTOP_VALUE_4K 0x00 +#define MATRIX_SRTOP_VALUE_8K 0x01 +#define MATRIX_SRTOP_VALUE_16K 0x02 +#define MATRIX_SRTOP_VALUE_32K 0x03 +#define MATRIX_SRTOP_VALUE_64K 0x04 +#define MATRIX_SRTOP_VALUE_128K 0x05 +#define MATRIX_SRTOP_VALUE_256K 0x06 +#define MATRIX_SRTOP_VALUE_512K 0x07 +#define MATRIX_SRTOP_VALUE_1M 0x08 +#define MATRIX_SRTOP_VALUE_2M 0x09 +#define MATRIX_SRTOP_VALUE_4M 0x0a +#define MATRIX_SRTOP_VALUE_8M 0x0b +#define MATRIX_SRTOP_VALUE_16M 0x0c +#define MATRIX_SRTOP_VALUE_32M 0x0d +#define MATRIX_SRTOP_VALUE_64M 0x0e +#define MATRIX_SRTOP_VALUE_128M 0x0f + +#endif /* #ifndef __TZ_MATRIX_H__ */ diff --git a/arch/arm/mach-at91/include/mach/xload.h b/arch/arm/mach-at91/include/mach/xload.h new file mode 100644 index 0000000000..338577c221 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/xload.h @@ -0,0 +1,11 @@ +#ifndef __MACH_XLOAD_H +#define __MACH_XLOAD_H + +#include <linux/compiler.h> +#include <pbl.h> + +void __noreturn sama5d2_sdhci_start_image(u32 r4); + +int at91_sdhci_bio_init(struct pbl_bio *bio, void __iomem *base); + +#endif /* __MACH_XLOAD_H */ diff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c new file mode 100644 index 0000000000..b2e7345ec1 --- /dev/null +++ b/arch/arm/mach-at91/matrix.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: BSD-1-Clause */ +/* + * Copyright (c) 2013, Atmel Corporation + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + */ + +#include <io.h> +#include <mach/tz_matrix.h> +#include <mach/matrix.h> + +static inline void matrix_write(void __iomem *base, + unsigned int offset, + const unsigned int value) +{ + writel(value, base + offset); +} + +static inline unsigned int matrix_read(void __iomem *base, unsigned int offset) +{ + return readl(base + offset); +} + +void at91_matrix_write_protect_enable(void __iomem *matrix_base) +{ + matrix_write(matrix_base, MATRIX_WPMR, + MATRIX_WPMR_WPKEY_PASSWD | MATRIX_WPMR_WPEN_ENABLE); +} + +void at91_matrix_write_protect_disable(void __iomem *matrix_base) +{ + matrix_write(matrix_base, MATRIX_WPMR, MATRIX_WPMR_WPKEY_PASSWD); +} + +void at91_matrix_configure_slave_security(void __iomem *matrix_base, + unsigned int slave, + unsigned int srtop_setting, + unsigned int srsplit_setting, + unsigned int ssr_setting) +{ + matrix_write(matrix_base, MATRIX_SSR(slave), ssr_setting); + matrix_write(matrix_base, MATRIX_SRTSR(slave), srtop_setting); + matrix_write(matrix_base, MATRIX_SASSR(slave), srsplit_setting); +} diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index 05584c0711..813c2a0d94 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c @@ -200,8 +200,4 @@ static struct driver_d at91sam9_smc_driver = { .probe = at91sam9_smc_probe, }; -static int at91sam9_smc_init(void) -{ - return platform_driver_register(&at91sam9_smc_driver); -} -coredevice_initcall(at91sam9_smc_init); +coredevice_platform_driver(at91sam9_smc_driver); diff --git a/arch/arm/mach-at91/sama5d2.c b/arch/arm/mach-at91/sama5d2.c new file mode 100644 index 0000000000..a4aa8a2339 --- /dev/null +++ b/arch/arm/mach-at91/sama5d2.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <common.h> +#include <of.h> +#include <init.h> +#include <mach/aic.h> +#include <mach/sama5d2.h> +#include <asm/cache-l2x0.h> +#include <mach/sama5_bootsource.h> +#include <asm/mmu.h> +#include <mach/cpu.h> + +#define SFR_CAN 0x48 +#define SFR_L2CC_HRAMC 0x58 + +static void sama5d2_can_ram_init(void) +{ + writel(0x00210021, SAMA5D2_BASE_SFR + SFR_CAN); +} + +static void sama5d2_l2x0_init(void) +{ + void __iomem *l2x0_base = SAMA5D2_BASE_L2CC; + u32 cfg; + + writel(0x1, SAMA5D2_BASE_SFR + SFR_L2CC_HRAMC); + + /* Prefetch Control */ + cfg = readl(l2x0_base + L2X0_PREFETCH_CTRL); + /* prefetch offset: TODO find proper values */ + cfg |= 0x1; + cfg |= L2X0_INCR_DOUBLE_LINEFILL_EN | L2X0_PREFETCH_DROP_EN + | L2X0_DOUBLE_LINEFILL_EN; + cfg |= L2X0_DATA_PREFETCH_EN | L2X0_INSTRUCTION_PREFETCH_EN; + writel(cfg, l2x0_base + L2X0_PREFETCH_CTRL); + + /* Power Control */ + cfg = readl(l2x0_base + L2X0_POWER_CTRL); + cfg |= L2X0_STNDBY_MODE_EN | L2X0_DYNAMIC_CLK_GATING_EN; + writel(cfg, l2x0_base + L2X0_POWER_CTRL); + + l2x0_init(l2x0_base, 0x0, ~0UL); +} + +static int sama5d2_init(void) +{ + if (!of_machine_is_compatible("atmel,sama5d2")) + return 0; + + at91_aic_redir(SAMA5D2_BASE_SFR, SAMA5D2_AICREDIR_KEY); + sama5d2_can_ram_init(); + sama5d2_l2x0_init(); + + return 0; +} +postmmu_initcall(sama5d2_init); + +static int sama5d2_bootsource_init(void) +{ + if (!of_machine_is_compatible("atmel,sama5d2")) + return 0; + + at91_bootsource = __sama5d2_stashed_bootrom_r4; + + bootsource_set(sama5_bootsource(at91_bootsource)); + bootsource_set_instance(sama5_bootsource_instance(at91_bootsource)); + + return 0; +} +postcore_initcall(sama5d2_bootsource_init); diff --git a/arch/arm/mach-at91/sama5d2_ll.c b/arch/arm/mach-at91/sama5d2_ll.c new file mode 100644 index 0000000000..c3b5061777 --- /dev/null +++ b/arch/arm/mach-at91/sama5d2_ll.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: BSD-1-Clause +/* + * Copyright (c) 2017, Microchip Corporation + * + * Microchip's name may not be used to endorse or promote products derived + * from this software without specific prior written permission. + */ + +#include <mach/sama5d2_ll.h> +#include <mach/at91_ddrsdrc.h> +#include <mach/ddramc.h> +#include <mach/early_udelay.h> +#include <mach/tz_matrix.h> +#include <mach/matrix.h> +#include <mach/at91_rstc.h> +#include <asm/barebox-arm.h> + +#define sama5d2_pmc_write(off, val) writel(val, SAMA5D2_BASE_PMC + off) +#define sama5d2_pmc_read(off) readl(SAMA5D2_BASE_PMC + off) + +void sama5d2_ddr2_init(struct at91_ddramc_register *ddramc_reg_config) +{ + unsigned int reg; + + /* enable ddr2 clock */ + sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_MPDDRC); + sama5d2_pmc_write(AT91_PMC_SCER, AT91CAP9_PMC_DDR); + + reg = AT91_MPDDRC_RD_DATA_PATH_ONE_CYCLES; + writel(reg, SAMA5D2_BASE_MPDDRC + AT91_MPDDRC_RD_DATA_PATH); + + reg = readl(SAMA5D2_BASE_MPDDRC + AT91_MPDDRC_IO_CALIBR); + reg &= ~AT91_MPDDRC_RDIV; + reg &= ~AT91_MPDDRC_TZQIO; + reg |= AT91_MPDDRC_RDIV_DDR2_RZQ_50; + reg |= AT91_MPDDRC_TZQIO_(101); + writel(reg, SAMA5D2_BASE_MPDDRC + AT91_MPDDRC_IO_CALIBR); + + /* DDRAM2 Controller initialize */ + at91_ddram_initialize(SAMA5D2_BASE_MPDDRC, IOMEM(SAMA5_DDRCS), + ddramc_reg_config); +} + +static void sama5d2_pmc_init(void) +{ + at91_pmc_init(SAMA5D2_BASE_PMC, AT91_PMC_LL_SAMA5D2); + + /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ + sama5d2_pmc_write(AT91_CKGR_PLLAR, AT91_PMC_PLLA_WR_ERRATA); + sama5d2_pmc_write(AT91_CKGR_PLLAR, AT91_PMC_PLLA_WR_ERRATA + | AT91_PMC3_MUL_(40) | AT91_PMC_OUT_0 + | AT91_PMC_PLLCOUNT + | AT91_PMC_DIV_BYPASS); + + while (!(sama5d2_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKA)) + ; + + /* Initialize PLLA charge pump */ + /* No need: we keep what is set in ROM code */ + //sama5d2_pmc_write(AT91_PMC_PLLICPR, AT91_PMC_IPLLA_3); + + /* Switch PCK/MCK on PLLA output */ + at91_pmc_cfg_mck(SAMA5D2_BASE_PMC, + AT91_PMC_H32MXDIV + | AT91_PMC_PLLADIV2_ON + | AT91SAM9_PMC_MDIV_3 + | AT91_PMC_CSS_PLLA, + AT91_PMC_LL_SAMA5D2); +} + +static void matrix_configure_slave(void) +{ + u32 ddr_port; + u32 ssr_setting, sasplit_setting, srtop_setting; + + /* + * Matrix 0 (H64MX) + */ + + /* + * 0: Bridge from H64MX to AXIMX + * (Internal ROM, Crypto Library, PKCC RAM): Always Secured + */ + + /* 1: H64MX Peripheral Bridge */ + + /* 2 ~ 9 DDR2 Port0 ~ 7: Non-Secure */ + srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_128M); + sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_128M); + ssr_setting = MATRIX_LANSECH_NS(0) | + MATRIX_RDNSECH_NS(0) | + MATRIX_WRNSECH_NS(0); + for (ddr_port = 0; ddr_port < 8; ddr_port++) { + at91_matrix_configure_slave_security(SAMA5D2_BASE_MATRIX64, + SAMA5D2_H64MX_SLAVE_DDR2_PORT_0 + ddr_port, + srtop_setting, + sasplit_setting, + ssr_setting); + } + + /* + * 10: Internal SRAM 128K + * TOP0 is set to 128K + * SPLIT0 is set to 64K + * LANSECH0 is set to 0, the low area of region 0 is the Securable one + * RDNSECH0 is set to 0, region 0 Securable area is secured for reads. + * WRNSECH0 is set to 0, region 0 Securable area is secured for writes + */ + srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_128K); + sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_64K); + ssr_setting = MATRIX_LANSECH_S(0) | + MATRIX_RDNSECH_S(0) | + MATRIX_WRNSECH_S(0); + at91_matrix_configure_slave_security(SAMA5D2_BASE_MATRIX64, + SAMA5D2_H64MX_SLAVE_INTERNAL_SRAM, + srtop_setting, + sasplit_setting, + ssr_setting); + + /* 11: Internal SRAM 128K (Cache L2) */ + /* 12: QSPI0 */ + /* 13: QSPI1 */ + /* 14: AESB */ + + /* + * Matrix 1 (H32MX) + */ + + /* 0: Bridge from H32MX to H64MX: Not Secured */ + + /* 1: H32MX Peripheral Bridge 0: Not Secured */ + + /* 2: H32MX Peripheral Bridge 1: Not Secured */ + + /* + * 3: External Bus Interface + * EBI CS0 Memory(256M) ----> Slave Region 0, 1 + * EBI CS1 Memory(256M) ----> Slave Region 2, 3 + * EBI CS2 Memory(256M) ----> Slave Region 4, 5 + * EBI CS3 Memory(128M) ----> Slave Region 6 + * NFC Command Registers(128M) -->Slave Region 7 + * + * NANDFlash(EBI CS3) --> Slave Region 6: Non-Secure + */ + srtop_setting = MATRIX_SRTOP(6, MATRIX_SRTOP_VALUE_128M) | + MATRIX_SRTOP(7, MATRIX_SRTOP_VALUE_128M); + sasplit_setting = MATRIX_SASPLIT(6, MATRIX_SASPLIT_VALUE_128M) | + MATRIX_SASPLIT(7, MATRIX_SASPLIT_VALUE_128M); + ssr_setting = MATRIX_LANSECH_NS(6) | + MATRIX_RDNSECH_NS(6) | + MATRIX_WRNSECH_NS(6) | + MATRIX_LANSECH_NS(7) | + MATRIX_RDNSECH_NS(7) | + MATRIX_WRNSECH_NS(7); + at91_matrix_configure_slave_security(SAMA5D2_BASE_MATRIX32, + SAMA5D2_H32MX_EXTERNAL_EBI, + srtop_setting, + sasplit_setting, + ssr_setting); + + /* 4: NFC SRAM (4K): Non-Secure */ + srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_8K); + sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_8K); + ssr_setting = MATRIX_LANSECH_NS(0) | + MATRIX_RDNSECH_NS(0) | + MATRIX_WRNSECH_NS(0); + at91_matrix_configure_slave_security(SAMA5D2_BASE_MATRIX32, + SAMA5D2_H32MX_NFC_SRAM, + srtop_setting, + sasplit_setting, + ssr_setting); + + /* 5: + * USB Device High Speed Dual Port RAM (DPR): 1M + * USB Host OHCI registers: 1M + * USB Host EHCI registers: 1M + */ + srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_1M) | + MATRIX_SRTOP(1, MATRIX_SRTOP_VALUE_1M) | + MATRIX_SRTOP(2, MATRIX_SRTOP_VALUE_1M); + sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_1M) | + MATRIX_SASPLIT(1, MATRIX_SASPLIT_VALUE_1M) | + MATRIX_SASPLIT(2, MATRIX_SASPLIT_VALUE_1M); + ssr_setting = MATRIX_LANSECH_NS(0) | + MATRIX_LANSECH_NS(1) | + MATRIX_LANSECH_NS(2) | + MATRIX_RDNSECH_NS(0) | + MATRIX_RDNSECH_NS(1) | + MATRIX_RDNSECH_NS(2) | + MATRIX_WRNSECH_NS(0) | + MATRIX_WRNSECH_NS(1) | + MATRIX_WRNSECH_NS(2); + at91_matrix_configure_slave_security(SAMA5D2_BASE_MATRIX32, + SAMA5D2_H32MX_USB, + srtop_setting, + sasplit_setting, + ssr_setting); +} + +static void sama5d2_matrix_init(void) +{ + at91_matrix_write_protect_disable(SAMA5D2_BASE_MATRIX64); + at91_matrix_write_protect_disable(SAMA5D2_BASE_MATRIX32); + + matrix_configure_slave(); +} + +static void sama5d2_rstc_init(void) +{ + writel(AT91_RSTC_KEY | AT91_RSTC_URSTEN, + SAMA5D2_BASE_RSTC + AT91_RSTC_MR); +} + +void sama5d2_lowlevel_init(void) +{ + arm_cpu_lowlevel_init(); + sama5d2_pmc_init(); + sama5d2_matrix_init(); + sama5d2_rstc_init(); +} diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c index a5d464eca0..b1e7b2c565 100644 --- a/arch/arm/mach-at91/sama5d3.c +++ b/arch/arm/mach-at91/sama5d3.c @@ -397,7 +397,7 @@ static void sama5d3_initialize(void) at91_add_pit(SAMA5D3_BASE_PIT); at91_add_sam9_smc(DEVICE_ID_SINGLE, SAMA5D3_BASE_HSMC + 0x600, 0xa0); - restart_handler_register_fn(sama5d3_restart); + restart_handler_register_fn("soc", sama5d3_restart); } static int sama5d3_setup(void) diff --git a/arch/arm/mach-at91/sama5d3_devices.c b/arch/arm/mach-at91/sama5d3_devices.c index bf4a03d404..e29ed2ba97 100644 --- a/arch/arm/mach-at91/sama5d3_devices.c +++ b/arch/arm/mach-at91/sama5d3_devices.c @@ -18,7 +18,7 @@ #include <mach/board.h> #include <mach/at91_pmc.h> #include <mach/at91sam9x5_matrix.h> -#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_ddrsdrc.h> #include <mach/iomux.h> #include <mach/cpu.h> #include <i2c/i2c-gpio.h> diff --git a/arch/arm/mach-at91/sama5d4.c b/arch/arm/mach-at91/sama5d4.c index ca09dfe425..62e466fe51 100644 --- a/arch/arm/mach-at91/sama5d4.c +++ b/arch/arm/mach-at91/sama5d4.c @@ -305,7 +305,7 @@ static void sama5d4_initialize(void) at91_add_pit(SAMA5D4_BASE_PIT); at91_add_sam9_smc(DEVICE_ID_SINGLE, SAMA5D4_BASE_HSMC + 0x600, 0xa0); - restart_handler_register_fn(sama5d4_restart); + restart_handler_register_fn("soc", sama5d4_restart); } static int sama5d4_setup(void) diff --git a/arch/arm/mach-at91/sama5d4_devices.c b/arch/arm/mach-at91/sama5d4_devices.c index 5a1109dc0e..7be9e260d4 100644 --- a/arch/arm/mach-at91/sama5d4_devices.c +++ b/arch/arm/mach-at91/sama5d4_devices.c @@ -19,7 +19,7 @@ #include <mach/board.h> #include <mach/at91_pmc.h> #include <mach/at91sam9x5_matrix.h> -#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_ddrsdrc.h> #include <mach/iomux.h> #include <mach/cpu.h> #include <i2c/i2c-gpio.h> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index b7a66aa0ae..47247dc97c 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -403,3 +403,6 @@ void at91sam_phy_reset(void __iomem *rstc_base) /* Restore NRST value */ writel(AT91_RSTC_KEY | (rstc) | AT91_RSTC_URSTEN, rstc_base + AT91_RSTC_MR); } + +unsigned long at91_bootsource; +EXPORT_SYMBOL(at91_bootsource); diff --git a/arch/arm/mach-at91/xload-mmc.c b/arch/arm/mach-at91/xload-mmc.c new file mode 100644 index 0000000000..e9edeccb7f --- /dev/null +++ b/arch/arm/mach-at91/xload-mmc.c @@ -0,0 +1,84 @@ +#include <common.h> +#include <mach/xload.h> +#include <mach/sama5_bootsource.h> +#include <mach/hardware.h> +#include <mach/sama5d2_ll.h> +#include <mach/gpio.h> +#include <linux/sizes.h> +#include <asm/cache.h> +#include <pbl.h> + +static void at91_fat_start_image(struct pbl_bio *bio, + void *buf, unsigned int len, + u32 r4) +{ + void __noreturn (*bb)(void); + int ret; + + ret = pbl_fat_load(bio, "barebox.bin", buf, len); + if (ret < 0) { + pr_err("pbl_fat_load: error %d\n", ret); + return; + } + + bb = buf; + + sync_caches_for_execution(); + + sama5_boot_xload(bb, r4); +} + +static const struct sdhci_instance { + void __iomem *base; + unsigned id; + u8 periph; + s8 pins[15]; +} sdhci_instances[] = { + [0] = { + .base = SAMA5D2_BASE_SDHC0, .id = SAMA5D2_ID_SDMMC0, .periph = AT91_MUX_PERIPH_A, + .pins = { 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 13, 10, 11, 12, -1 } + }, + [1] = { + .base = SAMA5D2_BASE_SDHC1, .id = SAMA5D2_ID_SDMMC1, .periph = AT91_MUX_PERIPH_E, + .pins = { 18, 19, 20, 21, 22, 28, 30, -1 } + }, +}; + +/** + * sama5d2_sdhci_start_image - Load and start an image from FAT-formatted SDHCI + * @r4: value of r4 passed by BootROM + */ +void __noreturn sama5d2_sdhci_start_image(u32 r4) +{ + void *buf = (void *)SAMA5_DDRCS; + const struct sdhci_instance *instance; + struct pbl_bio bio; + const s8 *pin; + int ret; + + ret = sama5_bootsource_instance(r4); + if (ret > 1) + panic("Couldn't determine boot MCI instance\n"); + + instance = &sdhci_instances[ret]; + + sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_PIOA); + for (pin = instance->pins; *pin >= 0; pin++) { + at91_mux_pio4_set_periph(SAMA5D2_BASE_PIOA, + BIT(*pin), instance->periph); + } + + sama5d2_pmc_enable_periph_clock(instance->id); + sama5d2_pmc_enable_generic_clock(instance->id, AT91_PMC_GCKCSS_UPLL_CLK, 1); + + ret = at91_sdhci_bio_init(&bio, instance->base); + if (ret) + goto out_panic; + + /* TODO: eMMC boot partition handling: they are not FAT-formatted */ + + at91_fat_start_image(&bio, buf, SZ_16M, r4); + +out_panic: + panic("FAT chainloading failed\n"); +} diff --git a/arch/arm/mach-bcm283x/mbox.c b/arch/arm/mach-bcm283x/mbox.c index 22abbb0ca5..9839683d03 100644 --- a/arch/arm/mach-bcm283x/mbox.c +++ b/arch/arm/mach-bcm283x/mbox.c @@ -179,8 +179,4 @@ static struct driver_d bcm2835_mbox_driver = { .probe = bcm2835_mbox_probe, }; -static int __init bcm2835_mbox_init(void) -{ - return platform_driver_register(&bcm2835_mbox_driver); -} -core_initcall(bcm2835_mbox_init); +core_platform_driver(bcm2835_mbox_driver); diff --git a/arch/arm/mach-clps711x/reset.c b/arch/arm/mach-clps711x/reset.c index 03f40b73fa..90ddb8f5d2 100644 --- a/arch/arm/mach-clps711x/reset.c +++ b/arch/arm/mach-clps711x/reset.c @@ -22,7 +22,7 @@ static void __noreturn clps711x_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(clps711x_restart_soc); + restart_handler_register_fn("vector", clps711x_restart_soc); return 0; } diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 4d1b570aa0..5b57fe6192 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -210,7 +210,7 @@ static void __noreturn davinci_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(davinci_restart_soc); + restart_handler_register_fn("soc-wdt", davinci_restart_soc); return 0; } diff --git a/arch/arm/mach-ep93xx/clocksource.c b/arch/arm/mach-ep93xx/clocksource.c index 4fdcc36b1c..1f3ff7f8f2 100644 --- a/arch/arm/mach-ep93xx/clocksource.c +++ b/arch/arm/mach-ep93xx/clocksource.c @@ -85,7 +85,7 @@ static void __noreturn ep92xx_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(ep92xx_restart_soc); + restart_handler_register_fn("soc", ep92xx_restart_soc); return 0; } diff --git a/arch/arm/mach-ep93xx/header.c b/arch/arm/mach-ep93xx/header.c index 4e6a2e57c8..a9dde2d8b0 100644 --- a/arch/arm/mach-ep93xx/header.c +++ b/arch/arm/mach-ep93xx/header.c @@ -2,6 +2,8 @@ #include <linux/compiler.h> #include <asm/barebox-arm-head.h> +void go(void); + void __naked __section(.flash_header_start) go(void) { barebox_arm_head(); diff --git a/arch/arm/mach-highbank/reset.c b/arch/arm/mach-highbank/reset.c index d73a0a76a5..ea3908ec2b 100644 --- a/arch/arm/mach-highbank/reset.c +++ b/arch/arm/mach-highbank/reset.c @@ -33,7 +33,7 @@ static void __noreturn highbank_poweroff(struct poweroff_handler *handler) static int highbank_init(void) { - restart_handler_register_fn(highbank_restart_soc); + restart_handler_register_fn("soc", highbank_restart_soc); poweroff_handler_register_fn(highbank_poweroff); return 0; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 6dd5cb2aca..dd49537fd5 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -146,7 +146,7 @@ config ARCH_IMX6 select ARCH_HAS_IMX_GPT select CPU_V7 select PINCTRL_IMX_IOMUX_V3 - select OFTREE + select OFDEVICE select COMMON_CLK_OF_PROVIDER select HW_HAS_PCI @@ -157,8 +157,6 @@ config ARCH_IMX6SL config ARCH_IMX6SX bool select ARCH_IMX6 - select OFTREE - select COMMON_CLK_OF_PROVIDER config ARCH_IMX6UL bool @@ -190,6 +188,10 @@ config ARCH_IMX8MM select ARCH_IMX8M bool +config ARCH_IMX8MP + select ARCH_IMX8M + bool + config ARCH_IMX8MQ select ARCH_IMX8M bool @@ -211,6 +213,7 @@ config ARCH_VF610 config IMX_MULTI_BOARDS bool "Allow multiple boards to be selected" select HAVE_PBL_MULTI_IMAGES + select RELOCATABLE if IMX_MULTI_BOARDS @@ -335,6 +338,14 @@ config MACH_PHYTEC_SOM_IMX6 bool "Phytec phyCARD-i.MX6 and phyFLEX-i.MX6" select ARCH_IMX6 select ARCH_IMX6UL + select I2C + select I2C_IMX + +config MACH_PROTONIC_IMX6 + bool "Protonic-Holland i.MX6 based boards" + select ARCH_IMX6 + select ARCH_IMX6UL + select ARM_USE_COMPRESSED_DTB config MACH_KONTRON_SAMX6I bool "Kontron sAMX6i" @@ -438,6 +449,7 @@ config MACH_GW_VENTANA config MACH_CM_FX6 bool "CM FX6" select ARCH_IMX6 + select MCI_IMX_ESDHC_PBL config MACH_ADVANTECH_ROM_742X bool "Advantech ROM 742X" @@ -448,6 +460,12 @@ config MACH_WARP7 bool "NXP i.MX7: element 14 WaRP7 Board" select ARCH_IMX7 +config MACH_AC_SXB + bool "Atlas Copco: SXB board" + select ARCH_IMX7 + select MCI_IMX_ESDHC_PBL + select ARM_USE_COMPRESSED_DTB + config MACH_VF610_TWR bool "Freescale VF610 Tower Board" select ARCH_VF610 @@ -515,6 +533,7 @@ config MACH_NXP_IMX6ULL_EVK config MACH_NXP_IMX8MM_EVK bool "NXP i.MX8MM EVK Board" select ARCH_IMX8MM + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN select FIRMWARE_IMX8MM_ATF select ARM_SMCCC select MCI_IMX_ESDHC_PBL @@ -522,6 +541,17 @@ config MACH_NXP_IMX8MM_EVK select I2C_IMX_EARLY select USB_GADGET_DRIVER_ARC_PBL +config MACH_NXP_IMX8MP_EVK + bool "NXP i.MX8MP EVK Board" + select ARCH_IMX8MP + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MP_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select IMX8M_DRAM + select I2C_IMX_EARLY + select USB_GADGET_DRIVER_ARC_PBL + config MACH_NXP_IMX8MQ_EVK bool "NXP i.MX8MQ EVK Board" select ARCH_IMX8MQ @@ -548,6 +578,11 @@ config MACH_DIGI_CCIMX6ULSBCPRO select ARCH_IMX6UL select ARM_USE_COMPRESSED_DTB +config MACH_WEBASTO_CCBV2 + bool "Webasto Common Communication Board V2" + select ARCH_IMX6UL + select ARM_USE_COMPRESSED_DTB + endif # ---------------------------------------------------------- diff --git a/arch/arm/mach-imx/atf.c b/arch/arm/mach-imx/atf.c index 4ced8cd083..03857e6b9b 100644 --- a/arch/arm/mach-imx/atf.c +++ b/arch/arm/mach-imx/atf.c @@ -47,6 +47,11 @@ void imx8mm_atf_load_bl31(const void *fw, size_t fw_size) imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MM_ATF_BL31_BASE_ADDR); } +void imx8mp_atf_load_bl31(const void *fw, size_t fw_size) +{ + imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MP_ATF_BL31_BASE_ADDR); +} + void imx8mq_atf_load_bl31(const void *fw, size_t fw_size) { imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MQ_ATF_BL31_BASE_ADDR); diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c index ef868301cd..c3cf4b85ff 100644 --- a/arch/arm/mach-imx/boot.c +++ b/arch/arm/mach-imx/boot.c @@ -28,6 +28,7 @@ #include <mach/imx6-regs.h> #include <mach/imx7-regs.h> #include <mach/imx8mm-regs.h> +#include <mach/imx8mp-regs.h> #include <mach/imx8mq-regs.h> #include <mach/vf610-regs.h> #include <mach/imx8mq.h> @@ -651,3 +652,19 @@ void imx8mm_boot_save_loc(void) { imx_boot_save_loc(imx8mm_get_boot_source); } + +void imx8mp_get_boot_source(enum bootsource *src, int *instance) +{ + unsigned long addr; + void __iomem *src_base = IOMEM(MX8MP_SRC_BASE_ADDR); + uint32_t sbmr2 = readl(src_base + 0x70); + + addr = IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0; + + __imx7_get_boot_source(src, instance, addr, sbmr2); +} + +void imx8mp_boot_save_loc(void) +{ + imx_boot_save_loc(imx8mp_get_boot_source); +} diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c index c6a0ac7c50..cc7a409e37 100644 --- a/arch/arm/mach-imx/cpu_init.c +++ b/arch/arm/mach-imx/cpu_init.c @@ -82,6 +82,11 @@ void imx8mm_cpu_lowlevel_init(void) imx8m_cpu_lowlevel_init(); } +void imx8mp_cpu_lowlevel_init(void) +{ + imx8m_cpu_lowlevel_init(); +} + void imx8mq_cpu_lowlevel_init(void) { imx8m_cpu_lowlevel_init(); diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index 5d595addb8..426a96a3c4 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -703,12 +703,7 @@ static struct driver_d imx_esdctl_driver = { .of_compatible = DRV_OF_COMPAT(imx_esdctl_dt_ids), }; -static int imx_esdctl_init(void) -{ - return platform_driver_register(&imx_esdctl_driver); -} - -mem_initcall(imx_esdctl_init); +mem_platform_driver(imx_esdctl_driver); /* * The i.MX SoCs usually have two SDRAM chipselects. The following @@ -889,6 +884,11 @@ void __noreturn imx8mm_barebox_entry(void *boarddata) imx8m_barebox_entry(boarddata); } +void __noreturn imx8mp_barebox_entry(void *boarddata) +{ + imx8m_barebox_entry(boarddata); +} + void __noreturn imx8mq_barebox_entry(void *boarddata) { imx8m_barebox_entry(boarddata); diff --git a/arch/arm/mach-imx/iim.c b/arch/arm/mach-imx/iim.c index 207e1879c3..b60c5de7e1 100644 --- a/arch/arm/mach-imx/iim.c +++ b/arch/arm/mach-imx/iim.c @@ -329,10 +329,10 @@ static int imx_iim_add_bank(struct iim_priv *iim, int num, int nregs) iim->bank[num] = bank; - bank->map_config.reg_bits = 8, - bank->map_config.val_bits = 8, - bank->map_config.reg_stride = 1, - bank->map_config.max_register = (nregs - 1), + bank->map_config.reg_bits = 8; + bank->map_config.val_bits = 8; + bank->map_config.reg_stride = 1; + bank->map_config.max_register = (nregs - 1); bank->map_config.name = xasprintf("bank%d", num); bank->map = regmap_init(&iim->dev, &imx_iim_regmap_bus, bank, &bank->map_config); @@ -586,10 +586,4 @@ static struct driver_d imx_iim_driver = { .of_compatible = DRV_OF_COMPAT(imx_iim_dt_ids), }; -static int imx_iim_init(void) -{ - platform_driver_register(&imx_iim_driver); - - return 0; -} -coredevice_initcall(imx_iim_init); +coredevice_platform_driver(imx_iim_driver); diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c index a922470988..1b3cb70da8 100644 --- a/arch/arm/mach-imx/imx-bbu-internal.c +++ b/arch/arm/mach-imx/imx-bbu-internal.c @@ -384,16 +384,21 @@ static enum filetype imx_bbu_expected_filetype(void) static unsigned long imx_bbu_flash_header_offset_mmc(void) { - unsigned long offset = SZ_1K; + /* + * i.MX8MQ moved the header by 32K to accomodate for GPT partition + * tables. The offset to the IVT is 1KiB. + */ + if (cpu_is_mx8mm() || cpu_is_mx8mq()) + return SZ_32K + SZ_1K; /* - * i.MX8MQ moved the header by 32K to accomodate for GPT - * partition tables + * i.MX8MP moved the header by 32K to accomodate for GPT partition + * tables, but the IVT is right at the beginning of the image. */ - if (cpu_is_mx8m()) - offset += SZ_32K; + if (cpu_is_mx8mp()) + return SZ_32K; - return offset; + return SZ_1K; } static int imx_bbu_update(struct bbu_handler *handler, struct bbu_data *data) diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c index 0bbe44e4dd..3d8c55c54e 100644 --- a/arch/arm/mach-imx/imx.c +++ b/arch/arm/mach-imx/imx.c @@ -82,6 +82,8 @@ static int imx_soc_from_dt(void) return IMX_CPU_IMX8MQ; if (of_machine_is_compatible("fsl,imx8mm")) return IMX_CPU_IMX8MM; + if (of_machine_is_compatible("fsl,imx8mp")) + return IMX_CPU_IMX8MP; if (of_machine_is_compatible("fsl,vf610")) return IMX_CPU_VF610; @@ -124,6 +126,8 @@ static int imx_init(void) ret = imx7_init(); else if (cpu_is_mx8mm()) ret = imx8mm_init(); + else if (cpu_is_mx8mp()) + ret = imx8mp_init(); else if (cpu_is_mx8mq()) ret = imx8mq_init(); else if (cpu_is_vf610()) diff --git a/arch/arm/mach-imx/imx5.c b/arch/arm/mach-imx/imx5.c index 96288f99e0..dd6c079fe3 100644 --- a/arch/arm/mach-imx/imx5.c +++ b/arch/arm/mach-imx/imx5.c @@ -37,10 +37,13 @@ void imx5_init_lowlevel(void) { u32 r; - /* ARM errata ID #468414 */ __asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r)); + + if (r & (1 << 1)) + return; + + /* ARM errata ID #468414 */ r |= (1 << 5); /* enable L1NEON bit */ - r &= ~(1 << 1); /* explicitly disable L2 cache */ __asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r)); /* reconfigure L2 cache aux control reg */ diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index d2ed7d52a9..b9e01a1d18 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -22,6 +22,7 @@ #include <mach/imx8m-ccm-regs.h> #include <mach/reset-reason.h> #include <mach/ocotp.h> +#include <mach/imx8mp-regs.h> #include <mach/imx8mq-regs.h> #include <mach/imx8m-ccm-regs.h> #include <soc/imx8m/clk-early.h> @@ -105,6 +106,29 @@ int imx8mm_init(void) return imx8m_init(cputypestr); } +int imx8mp_init(void) +{ + void __iomem *anatop = IOMEM(MX8MP_ANATOP_BASE_ADDR); + uint32_t type = FIELD_GET(DIGPROG_MAJOR, + readl(anatop + MX8MP_ANATOP_DIGPROG)); + const char *cputypestr; + + imx8mp_boot_save_loc(); + + switch (type) { + case IMX8M_CPUTYPE_IMX8MP: + cputypestr = "i.MX8MP"; + break; + default: + cputypestr = "unknown i.MX8M"; + break; + }; + + imx_set_silicon_revision(cputypestr, imx8mp_cpu_revision()); + + return imx8m_init(cputypestr); +} + int imx8mq_init(void) { void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR); diff --git a/arch/arm/mach-imx/include/mach/atf.h b/arch/arm/mach-imx/include/mach/atf.h index f64a9dd2ba..c21ffaeb56 100644 --- a/arch/arm/mach-imx/include/mach/atf.h +++ b/arch/arm/mach-imx/include/mach/atf.h @@ -7,12 +7,14 @@ #define MX8M_ATF_BL31_SIZE_LIMIT SZ_64K #define MX8MM_ATF_BL31_BASE_ADDR 0x00920000 +#define MX8MP_ATF_BL31_BASE_ADDR 0x00960000 #define MX8MQ_ATF_BL31_BASE_ADDR 0x00910000 #define MX8M_ATF_BL33_BASE_ADDR 0x40200000 #define MX8MM_ATF_BL33_BASE_ADDR MX8M_ATF_BL33_BASE_ADDR #define MX8MQ_ATF_BL33_BASE_ADDR MX8M_ATF_BL33_BASE_ADDR void imx8mm_atf_load_bl31(const void *fw, size_t fw_size); +void imx8mp_atf_load_bl31(const void *fw, size_t fw_size); void imx8mq_atf_load_bl31(const void *fw, size_t fw_size); -#endif
\ No newline at end of file +#endif diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h index 5eed01631c..a4c57c5d5a 100644 --- a/arch/arm/mach-imx/include/mach/debug_ll.h +++ b/arch/arm/mach-imx/include/mach/debug_ll.h @@ -15,7 +15,7 @@ #include <mach/imx53-regs.h> #include <mach/imx6-regs.h> #include <mach/imx7-regs.h> -#include <mach/imx8mq-regs.h> +#include <mach/imx8m-regs.h> #include <mach/vf610-regs.h> #include <serial/imx-uart.h> @@ -48,8 +48,8 @@ #define IMX_DEBUG_SOC MX6 #elif defined CONFIG_DEBUG_IMX7D_UART #define IMX_DEBUG_SOC MX7 -#elif defined CONFIG_DEBUG_IMX8MQ_UART -#define IMX_DEBUG_SOC MX8MQ +#elif defined CONFIG_DEBUG_IMX8M_UART +#define IMX_DEBUG_SOC MX8M #elif defined CONFIG_DEBUG_VF610_UART #define IMX_DEBUG_SOC VF610 #else @@ -102,7 +102,7 @@ static inline void imx8m_uart_setup_ll(void) { void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); - imx8mq_uart_setup(base); + imx8m_uart_setup(base); } static inline void PUTC_LL(int c) diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h index 41eb9f6729..e6bbc3145a 100644 --- a/arch/arm/mach-imx/include/mach/esdctl.h +++ b/arch/arm/mach-imx/include/mach/esdctl.h @@ -140,6 +140,7 @@ void __noreturn imx6q_barebox_entry(void *boarddata); void __noreturn imx6ul_barebox_entry(void *boarddata); void __noreturn vf610_barebox_entry(void *boarddata); void __noreturn imx8mm_barebox_entry(void *boarddata); +void __noreturn imx8mp_barebox_entry(void *boarddata); void __noreturn imx8mq_barebox_entry(void *boarddata); void __noreturn imx7d_barebox_entry(void *boarddata); #define imx6sx_barebox_entry(boarddata) imx6ul_barebox_entry(boarddata) diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index 7742a002ce..f30133a05a 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -17,6 +17,7 @@ void imx6_boot_save_loc(void); void imx7_boot_save_loc(void); void vf610_boot_save_loc(void); void imx8mm_boot_save_loc(void); +void imx8mp_boot_save_loc(void); void imx8mq_boot_save_loc(void); void imx25_get_boot_source(enum bootsource *src, int *instance); @@ -28,6 +29,7 @@ void imx6_get_boot_source(enum bootsource *src, int *instance); void imx7_get_boot_source(enum bootsource *src, int *instance); void vf610_get_boot_source(enum bootsource *src, int *instance); void imx8mm_get_boot_source(enum bootsource *src, int *instance); +void imx8mp_get_boot_source(enum bootsource *src, int *instance); void imx8mq_get_boot_source(enum bootsource *src, int *instance); int imx1_init(void); @@ -43,6 +45,7 @@ int imx6_init(void); int imx7_init(void); int vf610_init(void); int imx8mm_init(void); +int imx8mp_init(void); int imx8mq_init(void); int imx1_devices_init(void); @@ -63,6 +66,7 @@ void imx7_cpu_lowlevel_init(void); void vf610_cpu_lowlevel_init(void); void imx8mq_cpu_lowlevel_init(void); void imx8mm_cpu_lowlevel_init(void); +void imx8mp_cpu_lowlevel_init(void); /* There's a off-by-one betweem the gpio bank number and the gpiochip */ /* range e.g. GPIO_1_5 is gpio 5 under linux */ @@ -215,6 +219,18 @@ extern unsigned int __imx_cpu_type; # define cpu_is_mx8mm() (0) #endif +#ifdef CONFIG_ARCH_IMX8MP +# ifdef imx_cpu_type +# undef imx_cpu_type +# define imx_cpu_type __imx_cpu_type +# else +# define imx_cpu_type IMX_CPU_IMX8MP +# endif +# define cpu_is_mx8mp() (imx_cpu_type == IMX_CPU_IMX8MP) +#else +# define cpu_is_mx8mp() (0) +#endif + #ifdef CONFIG_ARCH_IMX8MQ # ifdef imx_cpu_type # undef imx_cpu_type @@ -251,6 +267,6 @@ extern unsigned int __imx_cpu_type; #define cpu_is_mx23() (0) #define cpu_is_mx28() (0) -#define cpu_is_mx8m() (cpu_is_mx8mq() || cpu_is_mx8mm()) +#define cpu_is_mx8m() (cpu_is_mx8mq() || cpu_is_mx8mm() || cpu_is_mx8mp()) #endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf-template.h b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf-template.h new file mode 100644 index 0000000000..668fb0646f --- /dev/null +++ b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf-template.h @@ -0,0 +1,64 @@ +/* + * This snippet can be included from a i.MX flash header configuration + * file for generating signed images. The necessary keys/certificates + * are expected in these config variables: + * + * CONFIG_HABV4_TABLE_BIN + * CONFIG_HABV4_CSF_CRT_PEM + * CONFIG_HABV4_IMG_CRT_PEM + */ + +#ifndef SETUP_HABV4_ENGINE +#error "SETUP_HABV4_ENGINE undefined" +#endif + +hab [Header] +hab Version = 4.1 +hab Hash Algorithm = sha256 +hab Engine Configuration = 0 +hab Certificate Format = X509 +hab Signature Format = CMS +hab Engine = SETUP_HABV4_ENGINE + +hab [Install SRK] +hab File = CONFIG_HABV4_TABLE_BIN +hab # SRK index within SRK-Table 0..3 +hab Source index = CONFIG_HABV4_SRK_INDEX + +hab [Install CSFK] +/* target key index in keystore 1 */ +hab File = CONFIG_HABV4_CSF_CRT_PEM + +hab [Authenticate CSF] + +hab [Unlock] +hab Engine = SETUP_HABV4_ENGINE +#ifdef SETUP_HABV4_FEATURES +hab Features = SETUP_HABV4_FEATURES +#endif + +hab [Install Key] +/* verification key index in key store (0, 2...4) */ +hab Verification index = 0 +/* target key index in key store (2...4) */ +hab Target index = 2 +hab File = CONFIG_HABV4_IMG_CRT_PEM + +hab [Authenticate Data] +/* verification key index in key store (2...4) */ +hab Verification index = 2 + +hab_blocks + +hab_encrypt [Install Secret Key] +hab_encrypt Verification index = 0 +hab_encrypt Target index = 0 +hab_encrypt_key +hab_encrypt_key_length 256 +hab_encrypt_blob_address + +hab_encrypt [Decrypt Data] +hab_encrypt Verification index = 0 +hab_encrypt Mac Bytes = 16 + +hab_encrypt_blocks diff --git a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h index 2961b97b79..ca741b2736 100644 --- a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h +++ b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h @@ -1,58 +1,5 @@ -/* - * This snippet can be included from a i.MX flash header configuration - * file for generating signed images. The necessary keys/certificates - * are expected in these config variables: - * - * CONFIG_HABV4_TABLE_BIN - * CONFIG_HABV4_CSF_CRT_PEM - * CONFIG_HABV4_IMG_CRT_PEM - */ -hab [Header] -hab Version = 4.1 -hab Hash Algorithm = sha256 -hab Engine Configuration = 0 -hab Certificate Format = X509 -hab Signature Format = CMS -hab Engine = CAAM +#define SETUP_HABV4_ENGINE CAAM +#define SETUP_HABV4_FEATURES RNG, MID -hab [Install SRK] -hab File = CONFIG_HABV4_TABLE_BIN -hab # SRK index within SRK-Table 0..3 -hab Source index = CONFIG_HABV4_SRK_INDEX - -hab [Install CSFK] -/* target key index in keystore 1 */ -hab File = CONFIG_HABV4_CSF_CRT_PEM - -hab [Authenticate CSF] - -hab [Unlock] -hab Engine = CAAM -hab Features = RNG - -hab [Install Key] -/* verification key index in key store (0, 2...4) */ -hab Verification index = 0 -/* target key index in key store (2...4) */ -hab Target index = 2 -hab File = CONFIG_HABV4_IMG_CRT_PEM - -hab [Authenticate Data] -/* verification key index in key store (2...4) */ -hab Verification index = 2 - -hab_blocks - -hab_encrypt [Install Secret Key] -hab_encrypt Verification index = 0 -hab_encrypt Target index = 0 -hab_encrypt_key -hab_encrypt_key_length 256 -hab_encrypt_blob_address - -hab_encrypt [Decrypt Data] -hab_encrypt Verification index = 0 -hab_encrypt Mac Bytes = 16 - -hab_encrypt_blocks +#include <mach/habv4-imx6-gencsf-template.h> diff --git a/arch/arm/mach-imx/include/mach/habv4-imx6ull-gencsf.h b/arch/arm/mach-imx/include/mach/habv4-imx6ull-gencsf.h new file mode 100644 index 0000000000..6a558b880b --- /dev/null +++ b/arch/arm/mach-imx/include/mach/habv4-imx6ull-gencsf.h @@ -0,0 +1,4 @@ + +#define SETUP_HABV4_ENGINE SW + +#include <mach/habv4-imx6-gencsf-template.h> diff --git a/arch/arm/mach-imx/include/mach/habv4-imx8-gencsf.h b/arch/arm/mach-imx/include/mach/habv4-imx8-gencsf.h index 9ed6893988..a3917cc74f 100644 --- a/arch/arm/mach-imx/include/mach/habv4-imx8-gencsf.h +++ b/arch/arm/mach-imx/include/mach/habv4-imx8-gencsf.h @@ -29,7 +29,7 @@ hab [Authenticate CSF] hab [Unlock] hab Engine = CAAM -hab Features = RNG +hab Features = RNG, MID hab [Install Key] /* verification key index in key store (0, 2...4) */ diff --git a/arch/arm/mach-imx/include/mach/imx-header.h b/arch/arm/mach-imx/include/mach/imx-header.h index dc8e2eee2f..f1e076dab9 100644 --- a/arch/arm/mach-imx/include/mach/imx-header.h +++ b/arch/arm/mach-imx/include/mach/imx-header.h @@ -94,7 +94,7 @@ static inline bool is_imx_flash_header_v2(const void *blob) struct config_data { uint32_t image_load_addr; - uint32_t image_dcd_offset; + uint32_t image_ivt_offset; uint32_t image_size; uint32_t max_load_size; uint32_t load_size; diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h index 1ba22b5bc6..7350ffd16f 100644 --- a/arch/arm/mach-imx/include/mach/imx6-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6-regs.h @@ -115,6 +115,7 @@ #define MX6_IP2APB_USBPHY1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x78000) #define MX6_IP2APB_USBPHY2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x7C000) +#define MX6_UART7_BASE_ADDR 0x02018000 #define MX6_SATA_BASE_ADDR 0x02200000 #define MX6_MMDC_PORT01_BASE_ADDR 0x10000000 diff --git a/arch/arm/mach-imx/include/mach/imx8mm-regs.h b/arch/arm/mach-imx/include/mach/imx8mm-regs.h index 1325c78dbc..e10ca42d2d 100644 --- a/arch/arm/mach-imx/include/mach/imx8mm-regs.h +++ b/arch/arm/mach-imx/include/mach/imx8mm-regs.h @@ -23,14 +23,10 @@ #define MX8MM_SYSCNT_RD_BASE_ADDR 0x306a0000 #define MX8MM_SYSCNT_CMP_BASE_ADDR 0x306b0000 #define MX8MM_SYSCNT_CTRL_BASE_ADDR 0x306c0000 -#define MX8MM_UART1_BASE_ADDR 0x30860000 -#define MX8MM_UART3_BASE_ADDR 0x30880000 -#define MX8MM_UART2_BASE_ADDR 0x30890000 #define MX8MM_I2C1_BASE_ADDR 0x30a20000 #define MX8MM_I2C2_BASE_ADDR 0x30a30000 #define MX8MM_I2C3_BASE_ADDR 0x30a40000 #define MX8MM_I2C4_BASE_ADDR 0x30a50000 -#define MX8MM_UART4_BASE_ADDR 0x30a60000 #define MX8MM_USDHC1_BASE_ADDR 0x30b40000 #define MX8MM_USDHC2_BASE_ADDR 0x30b50000 #define MX8MM_USDHC3_BASE_ADDR 0x30b60000 diff --git a/arch/arm/mach-imx/include/mach/imx8mp-regs.h b/arch/arm/mach-imx/include/mach/imx8mp-regs.h new file mode 100644 index 0000000000..ad53abbc9d --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx8mp-regs.h @@ -0,0 +1,42 @@ +#ifndef __MACH_IMX8MP_REGS_H +#define __MACH_IMX8MP_REGS_H + +#include <mach/imx8m-regs.h> + +#define MX8MP_M4_BOOTROM_BASE_ADDR 0x007e0000 + +#define MX8MP_GPIO1_BASE_ADDR 0x30200000 +#define MX8MP_GPIO2_BASE_ADDR 0x30210000 +#define MX8MP_GPIO3_BASE_ADDR 0x30220000 +#define MX8MP_GPIO4_BASE_ADDR 0x30230000 +#define MX8MP_GPIO5_BASE_ADDR 0x30240000 +#define MX8MP_WDOG1_BASE_ADDR 0x30280000 +#define MX8MP_WDOG2_BASE_ADDR 0x30290000 +#define MX8MP_WDOG3_BASE_ADDR 0x302a0000 +#define MX8MP_IOMUXC_BASE_ADDR 0x30330000 +#define MX8MP_IOMUXC_GPR_BASE_ADDR 0x30340000 +#define MX8MP_OCOTP_BASE_ADDR 0x30350000 +#define MX8MP_ANATOP_BASE_ADDR 0x30360000 +#define MX8MP_CCM_BASE_ADDR 0x30380000 +#define MX8MP_SRC_BASE_ADDR 0x30390000 +#define MX8MP_GPC_BASE_ADDR 0x303a0000 +#define MX8MP_SYSCNT_RD_BASE_ADDR 0x306a0000 +#define MX8MP_SYSCNT_CMP_BASE_ADDR 0x306b0000 +#define MX8MP_SYSCNT_CTRL_BASE_ADDR 0x306c0000 +#define MX8MP_I2C1_BASE_ADDR 0x30a20000 +#define MX8MP_I2C2_BASE_ADDR 0x30a30000 +#define MX8MP_I2C3_BASE_ADDR 0x30a40000 +#define MX8MP_I2C4_BASE_ADDR 0x30a50000 +#define MX8MP_USDHC1_BASE_ADDR 0x30b40000 +#define MX8MP_USDHC2_BASE_ADDR 0x30b50000 +#define MX8MP_USDHC3_BASE_ADDR 0x30b60000 +#define MX8MP_USB1_BASE_ADDR 0x32e40000 +#define MX8MP_USB2_BASE_ADDR 0x32e50000 +#define MX8MP_TZASC_BASE_ADDR 0x32f80000 +#define MX8MP_SRC_IPS_BASE_ADDR 0x30390000 +#define MX8MP_SRC_DDRC_RCR_ADDR 0x30391000 +#define MX8MP_SRC_DDRC2_RCR_ADDR 0x30391004 +#define MX8MP_DDRC_DDR_SS_GPR0 0x3d000000 +#define MX8MP_DDR_CSD1_BASE_ADDR 0x40000000 + +#endif /* __MACH_IMX8MP_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx8mq-regs.h b/arch/arm/mach-imx/include/mach/imx8mq-regs.h index 2f6488af33..50d02ba6a2 100644 --- a/arch/arm/mach-imx/include/mach/imx8mq-regs.h +++ b/arch/arm/mach-imx/include/mach/imx8mq-regs.h @@ -59,9 +59,6 @@ #define MX8MQ_ECSPI1_BASE_ADDR 0x30820000 #define MX8MQ_ECSPI2_BASE_ADDR 0x30830000 #define MX8MQ_ECSPI3_BASE_ADDR 0x30840000 -#define MX8MQ_UART1_BASE_ADDR 0x30860000 -#define MX8MQ_UART3_BASE_ADDR 0x30880000 -#define MX8MQ_UART2_BASE_ADDR 0x30890000 #define MX8MQ_SPDIF2_BASE_ADDR 0x308A0000 #define MX8MQ_SAI2_BASE_ADDR 0x308B0000 #define MX8MQ_SAI3_BASE_ADDR 0x308C0000 @@ -74,7 +71,6 @@ #define MX8MQ_I2C2_BASE_ADDR 0x30A30000 #define MX8MQ_I2C3_BASE_ADDR 0x30A40000 #define MX8MQ_I2C4_BASE_ADDR 0x30A50000 -#define MX8MQ_UART4_BASE_ADDR 0x30A60000 #define MX8MQ_MIPI_CSI_BASE_ADDR 0x30A70000 #define MX8MQ_MIPI_CSI_PHY1_BASE_ADDR 0x30A80000 #define MX8MQ_CSI1_BASE_ADDR 0x30A90000 diff --git a/arch/arm/mach-imx/include/mach/imx8mq.h b/arch/arm/mach-imx/include/mach/imx8mq.h index 2ef2987188..1494fd661f 100644 --- a/arch/arm/mach-imx/include/mach/imx8mq.h +++ b/arch/arm/mach-imx/include/mach/imx8mq.h @@ -5,6 +5,7 @@ #include <mach/generic.h> #include <mach/imx8mq-regs.h> #include <mach/imx8mm-regs.h> +#include <mach/imx8mp-regs.h> #include <mach/revision.h> #include <linux/bitfield.h> @@ -15,12 +16,14 @@ #define MX8MQ_ANATOP_DIGPROG 0x6c #define MX8MM_ANATOP_DIGPROG 0x800 +#define MX8MP_ANATOP_DIGPROG 0x800 #define DIGPROG_MAJOR GENMASK(23, 8) #define DIGPROG_MINOR GENMASK(7, 0) #define IMX8M_CPUTYPE_IMX8MQ 0x8240 #define IMX8M_CPUTYPE_IMX8MM 0x8241 +#define IMX8M_CPUTYPE_IMX8MP 0x8243 static inline int imx8mm_cpu_revision(void) { @@ -30,6 +33,14 @@ static inline int imx8mm_cpu_revision(void) return revision; } +static inline int imx8mp_cpu_revision(void) +{ + void __iomem *anatop = IOMEM(MX8MP_ANATOP_BASE_ADDR); + uint32_t revision = FIELD_GET(DIGPROG_MINOR, + readl(anatop + MX8MP_ANATOP_DIGPROG)); + return revision; +} + static inline int imx8mq_cpu_revision(void) { void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR); @@ -62,4 +73,4 @@ static inline int imx8mq_cpu_revision(void) u64 imx8m_uid(void); -#endif /* __MACH_IMX8_H */
\ No newline at end of file +#endif /* __MACH_IMX8_H */ diff --git a/arch/arm/mach-imx/include/mach/imx_cpu_types.h b/arch/arm/mach-imx/include/mach/imx_cpu_types.h index b3fccfadb5..6d96f7c590 100644 --- a/arch/arm/mach-imx/include/mach/imx_cpu_types.h +++ b/arch/arm/mach-imx/include/mach/imx_cpu_types.h @@ -14,6 +14,7 @@ #define IMX_CPU_IMX7 7 #define IMX_CPU_IMX8MQ 8 #define IMX_CPU_IMX8MM 81 +#define IMX_CPU_IMX8MP 83 #define IMX_CPU_VF610 610 #endif /* __MACH_IMX_CPU_TYPES_H */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx6ul.h b/arch/arm/mach-imx/include/mach/iomux-mx6ul.h new file mode 100644 index 0000000000..b7727191c2 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-mx6ul.h @@ -0,0 +1,1064 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_IMX6UL_PINS_H__ +#define __ASM_ARCH_IMX6UL_PINS_H__ + +#include <mach/iomux-v3.h> + +enum { + + MX6_PAD_BOOT_MODE0__GPIO5_IO10 = IOMUX_PAD(0x02A0, 0x0014, 5, 0x0000, 0, 0), + MX6_PAD_BOOT_MODE1__GPIO5_IO11 = IOMUX_PAD(0x02A4, 0x0018, 5, 0x0000, 0, 0), + /* + * The TAMPER Pin can be used for GPIO, which depends on + * fusemap TAMPER_PIN_DISABLE[1:0] settings. + */ + MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 = IOMUX_PAD(0x02A8, 0x001C, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 = IOMUX_PAD(0x02AC, 0x0020, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 = IOMUX_PAD(0x02B0, 0x0024, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 = IOMUX_PAD(0x02B4, 0x0028, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 = IOMUX_PAD(0x02B8, 0x002C, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 = IOMUX_PAD(0x02BC, 0x0030, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 = IOMUX_PAD(0x02C0, 0x0034, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 = IOMUX_PAD(0x02C4, 0x0038, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 = IOMUX_PAD(0x02C8, 0x003C, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 = IOMUX_PAD(0x02CC, 0x0040, 5, 0x0000, 0, 0), + + MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x02D0, 0x0044, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__GPT2_CLK = IOMUX_PAD(0x02D0, 0x0044, 1, 0x05A0, 0, 0), + MX6_PAD_JTAG_MOD__SPDIF_OUT = IOMUX_PAD(0x02D0, 0x0044, 2, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__ENET1_REF_CLK_25M = IOMUX_PAD(0x02D0, 0x0044, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__CCM_PMIC_RDY = IOMUX_PAD(0x02D0, 0x0044, 4, 0x04C0, 0, 0), + MX6_PAD_JTAG_MOD__GPIO1_IO10 = IOMUX_PAD(0x02D0, 0x0044, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02D0, 0x0044, 6, 0x0610, 0, 0), + + MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x02D4, 0x0048, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__GPT2_CAPTURE1 = IOMUX_PAD(0x02D4, 0x0048, 1, 0x0598, 0, 0), + MX6_PAD_JTAG_TMS__SAI2_MCLK = IOMUX_PAD(0x02D4, 0x0048, 2, 0x05F0, 0, 0), + MX6_PAD_JTAG_TMS__CCM_CLKO1 = IOMUX_PAD(0x02D4, 0x0048, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__CCM_WAIT = IOMUX_PAD(0x02D4, 0x0048, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__GPIO1_IO11 = IOMUX_PAD(0x02D4, 0x0048, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x02D4, 0x0048, 6, 0x0614, 0, 0), + MX6_PAD_JTAG_TMS__EPIT1_OUT = IOMUX_PAD(0x02D4, 0x0048, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x02D8, 0x004C, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__GPT2_CAPTURE2 = IOMUX_PAD(0x02D8, 0x004C, 1, 0x059C, 0, 0), + MX6_PAD_JTAG_TDO__SAI2_TX_SYNC = IOMUX_PAD(0x02D8, 0x004C, 2, 0x05FC, 0, 0), + MX6_PAD_JTAG_TDO__CCM_CLKO2 = IOMUX_PAD(0x02D8, 0x004C, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__CCM_STOP = IOMUX_PAD(0x02D8, 0x004C, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__GPIO1_IO12 = IOMUX_PAD(0x02D8, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__MQS_RIGHT = IOMUX_PAD(0x02D8, 0x004C, 6, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__EPIT2_OUT = IOMUX_PAD(0x02D8, 0x004C, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x02DC, 0x0050, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__GPT2_COMPARE1 = IOMUX_PAD(0x02DC, 0x0050, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__SAI2_TX_BCLK = IOMUX_PAD(0x02DC, 0x0050, 2, 0x05F8, 0, 0), + MX6_PAD_JTAG_TDI__PWM6_OUT = IOMUX_PAD(0x02DC, 0x0050, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__GPIO1_IO13 = IOMUX_PAD(0x02DC, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__MQS_LEFT = IOMUX_PAD(0x02DC, 0x0050, 6, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__SIM1_POWER_FAIL = IOMUX_PAD(0x02DC, 0x0050, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x02E0, 0x0054, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__GPT2_COMPARE2 = IOMUX_PAD(0x02E0, 0x0054, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__SAI2_RX_DATA = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0), + MX6_PAD_JTAG_TCK__PWM7_OUT = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__GPIO1_IO14 = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TRST_B__SJC_TRSTB = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__GPT2_COMPARE3 = IOMUX_PAD(0x02E4, 0x0058, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__PWM8_OUT = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__GPIO1_IO15 = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO00__I2C2_SCL = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0), + MX6_PAD_GPIO1_IO00__GPT1_CAPTURE1 = IOMUX_PAD(0x02E8, 0x005C, 1, 0x058C, 0, 0), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID = IOMUX_PAD(0x02E8, 0x005C, 2, 0x04B8, 0, 0), + MX6_PAD_GPIO1_IO00__ENET1_REF_CLK1 = IOMUX_PAD(0x02E8, 0x005C, 3, 0x0574, 0, 0), + MX6_PAD_GPIO1_IO00__MQS_RIGHT = IOMUX_PAD(0x02E8, 0x005C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__GPIO1_IO00 = IOMUX_PAD(0x02E8, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02E8, 0x005C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__SRC_SYSTEM_RESET = IOMUX_PAD(0x02E8, 0x005C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__WDOG3_WDOG_B = IOMUX_PAD(0x02E8, 0x005C, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO01__I2C2_SDA = IOMUX_PAD(0x02EC, 0x0060, IOMUX_CONFIG_SION | 0, 0x05B0, 1, 0), + MX6_PAD_GPIO1_IO01__GPT1_COMPARE1 = IOMUX_PAD(0x02EC, 0x0060, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__USB_OTG1_OC = IOMUX_PAD(0x02EC, 0x0060, 2, 0x0664, 0, 0), + MX6_PAD_GPIO1_IO01__ENET2_REF_CLK2 = IOMUX_PAD(0x02EC, 0x0060, 3, 0x057C, 0, 0), + MX6_PAD_GPIO1_IO01__MQS_LEFT = IOMUX_PAD(0x02EC, 0x0060, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__GPIO1_IO01 = IOMUX_PAD(0x02EC, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02EC, 0x0060, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__SRC_EARLY_RESET = IOMUX_PAD(0x02EC, 0x0060, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__WDOG1_WDOG_B = IOMUX_PAD(0x02EC, 0x0060, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO02__I2C1_SCL = IOMUX_PAD(0x02F0, 0x0064, IOMUX_CONFIG_SION | 0, 0x05A4, 0, 0), + MX6_PAD_GPIO1_IO02__GPT1_COMPARE2 = IOMUX_PAD(0x02F0, 0x0064, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR = IOMUX_PAD(0x02F0, 0x0064, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__ENET1_REF_CLK_25M = IOMUX_PAD(0x02F0, 0x0064, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__USDHC1_WP = IOMUX_PAD(0x02F0, 0x0064, 4, 0x066C, 0, 0), + MX6_PAD_GPIO1_IO02__GPIO1_IO02 = IOMUX_PAD(0x02F0, 0x0064, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02F0, 0x0064, 6, 0x0610, 1, 0), + MX6_PAD_GPIO1_IO02__SRC_ANY_PU_RESET = IOMUX_PAD(0x02F0, 0x0064, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__UART1_DCE_TX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__UART1_DTE_RX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0624, 0, 0), + + MX6_PAD_GPIO1_IO03__I2C1_SDA = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0), + MX6_PAD_GPIO1_IO03__GPT1_COMPARE3 = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__USB_OTG2_OC = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0), + MX6_PAD_GPIO1_IO03__USDHC1_CD_B = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0), + MX6_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__SRC_TESTER_ACK = IOMUX_PAD(0x02F4, 0x0068, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__UART1_DCE_RX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0624, 1, 0), + MX6_PAD_GPIO1_IO03__UART1_DTE_TX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1 = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0), + MX6_PAD_GPIO1_IO04__PWM3_OUT = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__USDHC1_RESET_B = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__UART5_DCE_TX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__UART5_DTE_RX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0644, 2, 0), + + MX6_PAD_GPIO1_IO05__ENET2_REF_CLK2 = IOMUX_PAD(0x02FC, 0x0070, 0, 0x057C, 1, 0), + MX6_PAD_GPIO1_IO05__PWM4_OUT = IOMUX_PAD(0x02FC, 0x0070, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID = IOMUX_PAD(0x02FC, 0x0070, 2, 0x04BC, 0, 0), + MX6_PAD_GPIO1_IO05__CSI_FIELD = IOMUX_PAD(0x02FC, 0x0070, 3, 0x0530, 0, 0), + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT = IOMUX_PAD(0x02FC, 0x0070, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__GPIO1_IO05 = IOMUX_PAD(0x02FC, 0x0070, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x02FC, 0x0070, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__UART5_DCE_RX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0644, 3, 0), + MX6_PAD_GPIO1_IO05__UART5_DTE_TX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO06__ENET1_MDIO = IOMUX_PAD(0x0300, 0x0074, 0, 0x0578, 0, 0), + MX6_PAD_GPIO1_IO06__ENET2_MDIO = IOMUX_PAD(0x0300, 0x0074, 1, 0x0580, 0, 0), + MX6_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE = IOMUX_PAD(0x0300, 0x0074, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CSI_MCLK = IOMUX_PAD(0x0300, 0x0074, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__USDHC2_WP = IOMUX_PAD(0x0300, 0x0074, 4, 0x069C, 0, 0), + MX6_PAD_GPIO1_IO06__GPIO1_IO06 = IOMUX_PAD(0x0300, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0300, 0x0074, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CCM_REF_EN_B = IOMUX_PAD(0x0300, 0x0074, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__UART1_DCE_CTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__UART1_DTE_RTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0620, 0, 0), + + MX6_PAD_GPIO1_IO07__ENET1_MDC = IOMUX_PAD(0x0304, 0x0078, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__ENET2_MDC = IOMUX_PAD(0x0304, 0x0078, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__USB_OTG_HOST_MODE = IOMUX_PAD(0x0304, 0x0078, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__CSI_PIXCLK = IOMUX_PAD(0x0304, 0x0078, 3, 0x0528, 0, 0), + MX6_PAD_GPIO1_IO07__USDHC2_CD_B = IOMUX_PAD(0x0304, 0x0078, 4, 0x0674, 1, 0), + MX6_PAD_GPIO1_IO07__GPIO1_IO07 = IOMUX_PAD(0x0304, 0x0078, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x0304, 0x0078, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__UART1_DCE_RTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0620, 1, 0), + MX6_PAD_GPIO1_IO07__UART1_DTE_CTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x0308, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x0308, 0x007C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__SPDIF_OUT = IOMUX_PAD(0x0308, 0x007C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__CSI_VSYNC = IOMUX_PAD(0x0308, 0x007C, 3, 0x052C, 1, 0), + MX6_PAD_GPIO1_IO08__USDHC2_VSELECT = IOMUX_PAD(0x0308, 0x007C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__GPIO1_IO08 = IOMUX_PAD(0x0308, 0x007C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY = IOMUX_PAD(0x0308, 0x007C, 6, 0x04C0, 1, 0), + MX6_PAD_GPIO1_IO08__UART5_DCE_RTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0640, 1, 0), + MX6_PAD_GPIO1_IO08__UART5_DTE_CTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x030C, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__WDOG1_WDOG_ANY = IOMUX_PAD(0x030C, 0x0080, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__SPDIF_IN = IOMUX_PAD(0x030C, 0x0080, 2, 0x0618, 0, 0), + MX6_PAD_GPIO1_IO09__CSI_HSYNC = IOMUX_PAD(0x030C, 0x0080, 3, 0x0524, 1, 0), + MX6_PAD_GPIO1_IO09__USDHC2_RESET_B = IOMUX_PAD(0x030C, 0x0080, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__GPIO1_IO09 = IOMUX_PAD(0x030C, 0x0080, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__USDHC1_RESET_B = IOMUX_PAD(0x030C, 0x0080, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__UART5_DCE_CTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__UART5_DTE_RTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0640, 2, 0), + + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0000, 0, 0), + + MX6_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0624, 2, 0), + MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 = IOMUX_PAD(0x0310, 0x0084, 1, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__I2C3_SCL = IOMUX_PAD(0x0310, 0x0084, IOMUX_CONFIG_SION | 2, 0x05B4, 0, 0), + MX6_PAD_UART1_TX_DATA__CSI_DATA02 = IOMUX_PAD(0x0310, 0x0084, 3, 0x04C4, 1, 0), + MX6_PAD_UART1_TX_DATA__GPT1_COMPARE1 = IOMUX_PAD(0x0310, 0x0084, 4, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__GPIO1_IO16 = IOMUX_PAD(0x0310, 0x0084, 5, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__SPDIF_OUT = IOMUX_PAD(0x0310, 0x0084, 8, 0x0000, 0, 0), + + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0624, 3, 0), + + MX6_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 = IOMUX_PAD(0x0314, 0x0088, 1, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__I2C3_SDA = IOMUX_PAD(0x0314, 0x0088, IOMUX_CONFIG_SION | 2, 0x05B8, 0, 0), + MX6_PAD_UART1_RX_DATA__CSI_DATA03 = IOMUX_PAD(0x0314, 0x0088, 3, 0x04C8, 1, 0), + MX6_PAD_UART1_RX_DATA__GPT1_CLK = IOMUX_PAD(0x0314, 0x0088, 4, 0x0594, 0, 0), + MX6_PAD_UART1_RX_DATA__GPIO1_IO17 = IOMUX_PAD(0x0314, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__SPDIF_IN = IOMUX_PAD(0x0314, 0x0088, 8, 0x0618, 1, 0), + + MX6_PAD_UART1_CTS_B__UART1_DCE_CTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0000, 0, 0), + + MX6_PAD_UART1_CTS_B__UART1_DTE_RTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0620, 2, 0), + MX6_PAD_UART1_CTS_B__ENET1_RX_CLK = IOMUX_PAD(0x0318, 0x008C, 1, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__USDHC1_WP = IOMUX_PAD(0x0318, 0x008C, 2, 0x066C, 1, 0), + MX6_PAD_UART1_CTS_B__CSI_DATA04 = IOMUX_PAD(0x0318, 0x008C, 3, 0x04D8, 0, 0), + MX6_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x0318, 0x008C, 4, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__GPIO1_IO18 = IOMUX_PAD(0x0318, 0x008C, 5, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__USDHC2_WP = IOMUX_PAD(0x0318, 0x008C, 8, 0x069C, 1, 0), + + MX6_PAD_UART1_RTS_B__UART1_DCE_RTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0620, 3, 0), + + MX6_PAD_UART1_RTS_B__UART1_DTE_CTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__ENET1_TX_ER = IOMUX_PAD(0x031C, 0x0090, 1, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__USDHC1_CD_B = IOMUX_PAD(0x031C, 0x0090, 2, 0x0668, 1, 0), + MX6_PAD_UART1_RTS_B__CSI_DATA05 = IOMUX_PAD(0x031C, 0x0090, 3, 0x04CC, 1, 0), + MX6_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x031C, 0x0090, 4, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__GPIO1_IO19 = IOMUX_PAD(0x031C, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__USDHC2_CD_B = IOMUX_PAD(0x031C, 0x0090, 8, 0x0674, 2, 0), + + MX6_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x0320, 0x0094, 0, 0x0000, 0, 0), + + MX6_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x0320, 0x0094, 0, 0x062C, 0, 0), + MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 = IOMUX_PAD(0x0320, 0x0094, 1, 0x0000, 0, 0), + MX6_PAD_UART2_TX_DATA__I2C4_SCL = IOMUX_PAD(0x0320, 0x0094, IOMUX_CONFIG_SION | 2, 0x05BC, 0, 0), + MX6_PAD_UART2_TX_DATA__CSI_DATA06 = IOMUX_PAD(0x0320, 0x0094, 3, 0x04DC, 0, 0), + MX6_PAD_UART2_TX_DATA__GPT1_CAPTURE1 = IOMUX_PAD(0x0320, 0x0094, 4, 0x058C, 1, 0), + MX6_PAD_UART2_TX_DATA__GPIO1_IO20 = IOMUX_PAD(0x0320, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_UART2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0320, 0x0094, 8, 0x0560, 0, 0), + + MX6_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x0098, 0, 0x062C, 1, 0), + + MX6_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x0098, 0, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 = IOMUX_PAD(0x0324, 0x0098, 1, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__I2C4_SDA = IOMUX_PAD(0x0324, 0x0098, IOMUX_CONFIG_SION | 2, 0x05C0, 0, 0), + MX6_PAD_UART2_RX_DATA__CSI_DATA07 = IOMUX_PAD(0x0324, 0x0098, 3, 0x04E0, 0, 0), + MX6_PAD_UART2_RX_DATA__GPT1_CAPTURE2 = IOMUX_PAD(0x0324, 0x0098, 4, 0x0590, 0, 0), + MX6_PAD_UART2_RX_DATA__GPIO1_IO21 = IOMUX_PAD(0x0324, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__SJC_DONE = IOMUX_PAD(0x0324, 0x0098, 7, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0324, 0x0098, 8, 0x0554, 0, 0), + + MX6_PAD_UART2_CTS_B__UART2_DCE_CTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0000, 0, 0), + + MX6_PAD_UART2_CTS_B__UART2_DTE_RTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0628, 0, 0), + MX6_PAD_UART2_CTS_B__ENET1_CRS = IOMUX_PAD(0x0328, 0x009C, 1, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__FLEXCAN2_TX = IOMUX_PAD(0x0328, 0x009C, 2, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__CSI_DATA08 = IOMUX_PAD(0x0328, 0x009C, 3, 0x04E4, 0, 0), + MX6_PAD_UART2_CTS_B__GPT1_COMPARE2 = IOMUX_PAD(0x0328, 0x009C, 4, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__GPIO1_IO22 = IOMUX_PAD(0x0328, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__SJC_DE_B = IOMUX_PAD(0x0328, 0x009C, 7, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__ECSPI3_MOSI = IOMUX_PAD(0x0328, 0x009C, 8, 0x055C, 0, 0), + + MX6_PAD_UART2_RTS_B__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0628, 1, 0), + + MX6_PAD_UART2_RTS_B__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__ENET1_COL = IOMUX_PAD(0x032C, 0x00A0, 1, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__FLEXCAN2_RX = IOMUX_PAD(0x032C, 0x00A0, 2, 0x0588, 0, 0), + MX6_PAD_UART2_RTS_B__CSI_DATA09 = IOMUX_PAD(0x032C, 0x00A0, 3, 0x04E8, 0, 0), + MX6_PAD_UART2_RTS_B__GPT1_COMPARE3 = IOMUX_PAD(0x032C, 0x00A0, 4, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__GPIO1_IO23 = IOMUX_PAD(0x032C, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__SJC_FAIL = IOMUX_PAD(0x032C, 0x00A0, 7, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__ECSPI3_MISO = IOMUX_PAD(0x032C, 0x00A0, 8, 0x0558, 0, 0), + + MX6_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0000, 0, 0), + + MX6_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0634, 0, 0), + MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 = IOMUX_PAD(0x0330, 0x00A4, 1, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__SIM1_PORT0_PD = IOMUX_PAD(0x0330, 0x00A4, 2, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__CSI_DATA01 = IOMUX_PAD(0x0330, 0x00A4, 3, 0x04D4, 0, 0), + MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0628, 2, 0), + MX6_PAD_UART3_TX_DATA__GPIO1_IO24 = IOMUX_PAD(0x0330, 0x00A4, 5, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__SJC_JTAG_ACT = IOMUX_PAD(0x0330, 0x00A4, 7, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__ANATOP_OTG1_ID = IOMUX_PAD(0x0330, 0x00A4, 8, 0x04B8, 1, 0), + + MX6_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0634, 1, 0), + + MX6_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 = IOMUX_PAD(0x0334, 0x00A8, 1, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__SIM2_PORT0_PD = IOMUX_PAD(0x0334, 0x00A8, 2, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__CSI_DATA00 = IOMUX_PAD(0x0334, 0x00A8, 3, 0x04D0, 0, 0), + MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0628, 3, 0), + MX6_PAD_UART3_RX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__GPIO1_IO25 = IOMUX_PAD(0x0334, 0x00A8, 5, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__EPIT1_OUT = IOMUX_PAD(0x0334, 0x00A8, 8, 0x0000, 0, 0), + + MX6_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0000, 0, 0), + + MX6_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0630, 0, 0), + MX6_PAD_UART3_CTS_B__ENET2_RX_CLK = IOMUX_PAD(0x0338, 0x00AC, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__FLEXCAN1_TX = IOMUX_PAD(0x0338, 0x00AC, 2, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__CSI_DATA10 = IOMUX_PAD(0x0338, 0x00AC, 3, 0x04EC, 0, 0), + MX6_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0338, 0x00AC, 4, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__GPIO1_IO26 = IOMUX_PAD(0x0338, 0x00AC, 5, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__EPIT2_OUT = IOMUX_PAD(0x0338, 0x00AC, 8, 0x0000, 0, 0), + + MX6_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0630, 1, 0), + + MX6_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__ENET2_TX_ER = IOMUX_PAD(0x033C, 0x00B0, 1, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__FLEXCAN1_RX = IOMUX_PAD(0x033C, 0x00B0, 2, 0x0584, 0, 0), + MX6_PAD_UART3_RTS_B__CSI_DATA11 = IOMUX_PAD(0x033C, 0x00B0, 3, 0x04F0, 0, 0), + MX6_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x033C, 0x00B0, 4, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__GPIO1_IO27 = IOMUX_PAD(0x033C, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__WDOG1_WDOG_B = IOMUX_PAD(0x033C, 0x00B0, 8, 0x0000, 0, 0), + + MX6_PAD_UART4_TX_DATA__UART4_DCE_TX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x0000, 0, 0), + + MX6_PAD_UART4_TX_DATA__UART4_DTE_RX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x063C, 0, 0), + MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 = IOMUX_PAD(0x0340, 0x00B4, 1, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__I2C1_SCL = IOMUX_PAD(0x0340, 0x00B4, IOMUX_CONFIG_SION | 2, 0x05A4, 1, 0), + MX6_PAD_UART4_TX_DATA__CSI_DATA12 = IOMUX_PAD(0x0340, 0x00B4, 3, 0x04F4, 0, 0), + MX6_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 = IOMUX_PAD(0x0340, 0x00B4, 4, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__GPIO1_IO28 = IOMUX_PAD(0x0340, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__ECSPI2_SCLK = IOMUX_PAD(0x0340, 0x00B4, 8, 0x0544, 1, 0), + + MX6_PAD_UART4_RX_DATA__UART4_DCE_RX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x063C, 1, 0), + + MX6_PAD_UART4_RX_DATA__UART4_DTE_TX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 = IOMUX_PAD(0x0344, 0x00B8, 1, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__I2C1_SDA = IOMUX_PAD(0x0344, 0x00B8, IOMUX_CONFIG_SION | 2, 0x05A8, 2, 0), + MX6_PAD_UART4_RX_DATA__CSI_DATA13 = IOMUX_PAD(0x0344, 0x00B8, 3, 0x04F8, 0, 0), + MX6_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 = IOMUX_PAD(0x0344, 0x00B8, 4, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__GPIO1_IO29 = IOMUX_PAD(0x0344, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__ECSPI2_SS0 = IOMUX_PAD(0x0344, 0x00B8, 8, 0x0550, 1, 0), + MX6_PAD_UART5_TX_DATA__GPIO1_IO30 = IOMUX_PAD(0x0348, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_UART5_TX_DATA__ECSPI2_MOSI = IOMUX_PAD(0x0348, 0x00BC, 8, 0x054C, 0, 0), + + MX6_PAD_UART5_TX_DATA__UART5_DCE_TX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0), + + MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 4, 0), + MX6_PAD_UART5_TX_DATA__ENET2_CRS = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0), + MX6_PAD_UART5_TX_DATA__I2C2_SCL = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0), + MX6_PAD_UART5_TX_DATA__CSI_DATA14 = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0), + MX6_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 = IOMUX_PAD(0x0348, 0x00BC, 4, 0x0000, 0, 0), + + MX6_PAD_UART5_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0644, 5, 0), + + MX6_PAD_UART5_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__ENET2_COL = IOMUX_PAD(0x034C, 0x00C0, 1, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__I2C2_SDA = IOMUX_PAD(0x034C, 0x00C0, IOMUX_CONFIG_SION | 2, 0x05B0, 2, 0), + MX6_PAD_UART5_RX_DATA__CSI_DATA15 = IOMUX_PAD(0x034C, 0x00C0, 3, 0x0500, 0, 0), + MX6_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB = IOMUX_PAD(0x034C, 0x00C0, 4, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__GPIO1_IO31 = IOMUX_PAD(0x034C, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__ECSPI2_MISO = IOMUX_PAD(0x034C, 0x00C0, 8, 0x0548, 1, 0), + + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 = IOMUX_PAD(0x0350, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__UART4_DCE_RTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0638, 0, 0), + MX6_PAD_ENET1_RX_DATA0__UART4_DTE_CTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__PWM1_OUT = IOMUX_PAD(0x0350, 0x00C4, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__CSI_DATA16 = IOMUX_PAD(0x0350, 0x00C4, 3, 0x0504, 0, 0), + MX6_PAD_ENET1_RX_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0350, 0x00C4, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 = IOMUX_PAD(0x0350, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__KPP_ROW00 = IOMUX_PAD(0x0350, 0x00C4, 6, 0x05D0, 0, 0), + MX6_PAD_ENET1_RX_DATA0__USDHC1_LCTL = IOMUX_PAD(0x0350, 0x00C4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 = IOMUX_PAD(0x0354, 0x00C8, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__UART4_DCE_CTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__UART4_DTE_RTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0638, 1, 0), + MX6_PAD_ENET1_RX_DATA1__PWM2_OUT = IOMUX_PAD(0x0354, 0x00C8, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__CSI_DATA17 = IOMUX_PAD(0x0354, 0x00C8, 3, 0x0508, 0, 0), + MX6_PAD_ENET1_RX_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0354, 0x00C8, 4, 0x0584, 1, 0), + MX6_PAD_ENET1_RX_DATA1__GPIO2_IO01 = IOMUX_PAD(0x0354, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__KPP_COL00 = IOMUX_PAD(0x0354, 0x00C8, 6, 0x05C4, 0, 0), + MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0), + MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0), + MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__GPIO2_IO02 = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__KPP_ROW01 = IOMUX_PAD(0x0358, 0x00CC, 6, 0x05D4, 0, 0), + MX6_PAD_ENET1_RX_EN__USDHC1_VSELECT = IOMUX_PAD(0x0358, 0x00CC, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0), + MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0), + MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0), + MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__KPP_COL01 = IOMUX_PAD(0x035C, 0x00D0, 6, 0x05C8, 0, 0), + MX6_PAD_ENET1_TX_DATA0__USDHC2_VSELECT = IOMUX_PAD(0x035C, 0x00D0, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 = IOMUX_PAD(0x0360, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__UART6_DCE_CTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__UART6_DTE_RTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0648, 2, 0), + MX6_PAD_ENET1_TX_DATA1__PWM5_OUT = IOMUX_PAD(0x0360, 0x00D4, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__CSI_DATA20 = IOMUX_PAD(0x0360, 0x00D4, 3, 0x0514, 0, 0), + MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO = IOMUX_PAD(0x0360, 0x00D4, 4, 0x0580, 1, 0), + MX6_PAD_ENET1_TX_DATA1__GPIO2_IO04 = IOMUX_PAD(0x0360, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__KPP_ROW02 = IOMUX_PAD(0x0360, 0x00D4, 6, 0x05D8, 0, 0), + MX6_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0360, 0x00D4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN = IOMUX_PAD(0x0364, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__UART6_DCE_RTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0648, 3, 0), + MX6_PAD_ENET1_TX_EN__UART6_DTE_CTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__PWM6_OUT = IOMUX_PAD(0x0364, 0x00D8, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__CSI_DATA21 = IOMUX_PAD(0x0364, 0x00D8, 3, 0x0518, 0, 0), + MX6_PAD_ENET1_TX_EN__ENET2_MDC = IOMUX_PAD(0x0364, 0x00D8, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__GPIO2_IO05 = IOMUX_PAD(0x0364, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__KPP_COL02 = IOMUX_PAD(0x0364, 0x00D8, 6, 0x05CC, 0, 0), + MX6_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x0364, 0x00D8, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x0368, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__UART7_DCE_CTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__UART7_DTE_RTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0650, 0, 0), + MX6_PAD_ENET1_TX_CLK__PWM7_OUT = IOMUX_PAD(0x0368, 0x00DC, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__CSI_DATA22 = IOMUX_PAD(0x0368, 0x00DC, 3, 0x051C, 0, 0), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 = IOMUX_PAD(0x0368, 0x00DC, IOMUX_CONFIG_SION | 4, 0x0574, 2, 0), + MX6_PAD_ENET1_TX_CLK__GPIO2_IO06 = IOMUX_PAD(0x0368, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__KPP_ROW03 = IOMUX_PAD(0x0368, 0x00DC, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__GPT1_CLK = IOMUX_PAD(0x0368, 0x00DC, 8, 0x0594, 1, 0), + + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER = IOMUX_PAD(0x036C, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__UART7_DCE_RTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0650, 1, 0), + MX6_PAD_ENET1_RX_ER__UART7_DTE_CTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__PWM8_OUT = IOMUX_PAD(0x036C, 0x00E0, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__CSI_DATA23 = IOMUX_PAD(0x036C, 0x00E0, 3, 0x0520, 0, 0), + MX6_PAD_ENET1_RX_ER__EIM_CRE = IOMUX_PAD(0x036C, 0x00E0, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__GPIO2_IO07 = IOMUX_PAD(0x036C, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__KPP_COL03 = IOMUX_PAD(0x036C, 0x00E0, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__GPT1_CAPTURE2 = IOMUX_PAD(0x036C, 0x00E0, 8, 0x0590, 1, 0), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 = IOMUX_PAD(0x0370, 0x00E4, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__UART6_DCE_TX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__UART6_DTE_RX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x064C, 1, 0), + MX6_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD = IOMUX_PAD(0x0370, 0x00E4, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__I2C3_SCL = IOMUX_PAD(0x0370, 0x00E4, IOMUX_CONFIG_SION | 3, 0x05B4, 1, 0), + MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO = IOMUX_PAD(0x0370, 0x00E4, 4, 0x0578, 1, 0), + MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08 = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__KPP_ROW04 = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0), + MX6_PAD_ENET2_RX_DATA1__UART6_DTE_TX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK = IOMUX_PAD(0x0374, 0x00E8, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__I2C3_SDA = IOMUX_PAD(0x0374, 0x00E8, IOMUX_CONFIG_SION | 3, 0x05B8, 1, 0), + MX6_PAD_ENET2_RX_DATA1__ENET1_MDC = IOMUX_PAD(0x0374, 0x00E8, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09 = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__KPP_COL04 = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0), + + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__UART7_DCE_TX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__UART7_DTE_RX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0654, 0, 0), + MX6_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B = IOMUX_PAD(0x0378, 0x00EC, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__I2C4_SCL = IOMUX_PAD(0x0378, 0x00EC, IOMUX_CONFIG_SION | 3, 0x05BC, 1, 0), + MX6_PAD_ENET2_RX_EN__EIM_ADDR26 = IOMUX_PAD(0x0378, 0x00EC, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__GPIO2_IO10 = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__KPP_ROW05 = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0), + MX6_PAD_ENET2_TX_DATA0__UART7_DTE_TX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN = IOMUX_PAD(0x037C, 0x00F0, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__I2C4_SDA = IOMUX_PAD(0x037C, 0x00F0, IOMUX_CONFIG_SION | 3, 0x05C0, 1, 0), + MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02 = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__KPP_COL05 = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__UART8_DTE_RX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x065C, 0, 0), + MX6_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD = IOMUX_PAD(0x0380, 0x00F4, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x0380, 0x00F4, 3, 0x0564, 0, 0), + MX6_PAD_ENET2_TX_DATA1__EIM_EB_B03 = IOMUX_PAD(0x0380, 0x00F4, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12 = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__KPP_ROW06 = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__UART8_DCE_RX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0), + MX6_PAD_ENET2_TX_EN__UART8_DTE_TX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__SIM2_PORT0_CLK = IOMUX_PAD(0x0384, 0x00F8, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__ECSPI4_MOSI = IOMUX_PAD(0x0384, 0x00F8, 3, 0x056C, 0, 0), + MX6_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN = IOMUX_PAD(0x0384, 0x00F8, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__GPIO2_IO13 = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__KPP_COL06 = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__USB_OTG2_OC = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0), + + MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__UART8_DTE_RTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0658, 0, 0), + MX6_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B = IOMUX_PAD(0x0388, 0x00FC, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__ECSPI4_MISO = IOMUX_PAD(0x0388, 0x00FC, 3, 0x0568, 0, 0), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 4, 0x057C, 2, 0), + MX6_PAD_ENET2_TX_CLK__GPIO2_IO14 = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__KPP_ROW07 = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0), + + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0), + MX6_PAD_ENET2_RX_ER__UART8_DTE_CTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN = IOMUX_PAD(0x038C, 0x0100, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__ECSPI4_SS0 = IOMUX_PAD(0x038C, 0x0100, 3, 0x0570, 0, 0), + MX6_PAD_ENET2_RX_ER__EIM_ADDR25 = IOMUX_PAD(0x038C, 0x0100, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__GPIO2_IO15 = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__KPP_COL07 = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_CLK__LCDIF_CLK = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__UART4_DCE_TX = IOMUX_PAD(0x0390, 0x0104, 2, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__UART4_DTE_RX = IOMUX_PAD(0x0390, 0x0104, 2, 0x063C, 2, 0), + MX6_PAD_LCD_CLK__SAI3_MCLK = IOMUX_PAD(0x0390, 0x0104, 3, 0x0600, 0, 0), + MX6_PAD_LCD_CLK__EIM_CS2_B = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__GPIO3_IO00 = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__LCDIF_RD_E = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__UART4_DCE_RX = IOMUX_PAD(0x0394, 0x0108, 2, 0x063C, 3, 0), + MX6_PAD_LCD_ENABLE__UART4_DTE_TX = IOMUX_PAD(0x0394, 0x0108, 2, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__SAI3_TX_SYNC = IOMUX_PAD(0x0394, 0x0108, 3, 0x060C, 0, 0), + MX6_PAD_LCD_ENABLE__EIM_CS3_B = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__GPIO3_IO01 = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0), + MX6_PAD_LCD_HSYNC__LCDIF_RS = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART4_DCE_CTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART4_DTE_RTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0638, 2, 0), + MX6_PAD_LCD_HSYNC__SAI3_TX_BCLK = IOMUX_PAD(0x0398, 0x010C, 3, 0x0608, 0, 0), + MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__GPIO3_IO02 = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__ECSPI2_SS1 = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__LCDIF_BUSY = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0), + MX6_PAD_LCD_VSYNC__UART4_DCE_RTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0638, 3, 0), + MX6_PAD_LCD_VSYNC__UART4_DTE_CTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__SAI3_RX_DATA = IOMUX_PAD(0x039C, 0x0110, 3, 0x0604, 0, 0), + MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__GPIO3_IO03 = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__ECSPI2_SS2 = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_RESET__LCDIF_RESET = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__LCDIF_CS = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__CA7_MX6UL_EVENTI = IOMUX_PAD(0x03A0, 0x0114, 2, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__SAI3_TX_DATA = IOMUX_PAD(0x03A0, 0x0114, 3, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__GPIO3_IO04 = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__ECSPI2_SS3 = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA00__LCDIF_DATA00 = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__I2C3_SDA = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0), + MX6_PAD_LCD_DATA00__GPIO3_IO05 = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__SRC_BT_CFG00 = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__SAI1_MCLK = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0), + + MX6_PAD_LCD_DATA01__LCDIF_DATA01 = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__I2C3_SCL = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0), + MX6_PAD_LCD_DATA01__GPIO3_IO06 = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__SRC_BT_CFG01 = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0), + + MX6_PAD_LCD_DATA02__LCDIF_DATA02 = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__I2C4_SDA = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0), + MX6_PAD_LCD_DATA02__GPIO3_IO07 = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__SRC_BT_CFG02 = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__SAI1_TX_BCLK = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0), + + MX6_PAD_LCD_DATA03__LCDIF_DATA03 = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__I2C4_SCL = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0), + MX6_PAD_LCD_DATA03__GPIO3_IO08 = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__SRC_BT_CFG03 = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__SAI1_RX_DATA = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0), + + MX6_PAD_LCD_DATA04__LCDIF_DATA04 = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__UART8_DCE_CTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__UART8_DTE_RTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0), + MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SPDIF_SR_CLK = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__GPIO3_IO09 = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SRC_BT_CFG04 = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SAI1_TX_DATA = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA05__LCDIF_DATA05 = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__UART8_DCE_RTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0), + MX6_PAD_LCD_DATA05__UART8_DTE_CTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__SPDIF_OUT = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__SRC_BT_CFG05 = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__ECSPI1_SS1 = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA06__LCDIF_DATA06 = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__UART7_DCE_CTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__UART7_DTE_RTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0), + MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__SPDIF_LOCK = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__SRC_BT_CFG06 = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__ECSPI1_SS2 = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA07__LCDIF_DATA07 = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__UART7_DCE_RTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0), + MX6_PAD_LCD_DATA07__UART7_DTE_CTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0), + MX6_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__SRC_BT_CFG07 = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__ECSPI1_SS3 = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA08__LCDIF_DATA08 = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__SPDIF_IN = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0), + MX6_PAD_LCD_DATA08__CSI_DATA16 = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0), + MX6_PAD_LCD_DATA08__EIM_DATA00 = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__SRC_BT_CFG08 = IOMUX_PAD(0x03C4, 0x0138, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__FLEXCAN1_TX = IOMUX_PAD(0x03C4, 0x0138, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA09__LCDIF_DATA09 = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__SAI3_MCLK = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0), + MX6_PAD_LCD_DATA09__CSI_DATA17 = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0), + MX6_PAD_LCD_DATA09__EIM_DATA01 = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__SRC_BT_CFG09 = IOMUX_PAD(0x03C8, 0x013C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__FLEXCAN1_RX = IOMUX_PAD(0x03C8, 0x013C, 8, 0x0584, 2, 0), + + MX6_PAD_LCD_DATA10__LCDIF_DATA10 = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__SAI3_RX_SYNC = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__CSI_DATA18 = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0), + MX6_PAD_LCD_DATA10__EIM_DATA02 = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__SRC_BT_CFG10 = IOMUX_PAD(0x03CC, 0x0140, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x0140, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA11__LCDIF_DATA11 = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__SAI3_RX_BCLK = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__CSI_DATA19 = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0), + MX6_PAD_LCD_DATA11__EIM_DATA03 = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__SRC_BT_CFG11 = IOMUX_PAD(0x03D0, 0x0144, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__FLEXCAN2_RX = IOMUX_PAD(0x03D0, 0x0144, 8, 0x0588, 2, 0), + + MX6_PAD_LCD_DATA12__LCDIF_DATA12 = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__SAI3_TX_SYNC = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0), + MX6_PAD_LCD_DATA12__CSI_DATA20 = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0), + MX6_PAD_LCD_DATA12__EIM_DATA04 = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__SRC_BT_CFG12 = IOMUX_PAD(0x03D4, 0x0148, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__ECSPI1_RDY = IOMUX_PAD(0x03D4, 0x0148, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA13__LCDIF_DATA13 = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__SAI3_TX_BCLK = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0), + MX6_PAD_LCD_DATA13__CSI_DATA21 = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0), + MX6_PAD_LCD_DATA13__EIM_DATA05 = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__SRC_BT_CFG13 = IOMUX_PAD(0x03D8, 0x014C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__USDHC2_RESET_B = IOMUX_PAD(0x03D8, 0x014C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA14__LCDIF_DATA14 = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__SAI3_RX_DATA = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0), + MX6_PAD_LCD_DATA14__CSI_DATA22 = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0), + MX6_PAD_LCD_DATA14__EIM_DATA06 = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__SRC_BT_CFG14 = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__USDHC2_DATA4 = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0), + + MX6_PAD_LCD_DATA15__LCDIF_DATA15 = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__SAI3_TX_DATA = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__CSI_DATA23 = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0), + MX6_PAD_LCD_DATA15__EIM_DATA07 = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__SRC_BT_CFG15 = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__USDHC2_DATA5 = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0), + + MX6_PAD_LCD_DATA16__LCDIF_DATA16 = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__UART7_DCE_TX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__UART7_DTE_RX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0), + MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0), + MX6_PAD_LCD_DATA16__EIM_DATA08 = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__SRC_BT_CFG24 = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__USDHC2_DATA6 = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0), + + MX6_PAD_LCD_DATA17__LCDIF_DATA17 = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0), + MX6_PAD_LCD_DATA17__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0), + MX6_PAD_LCD_DATA17__EIM_DATA09 = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__SRC_BT_CFG25 = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__USDHC2_DATA7 = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0), + + MX6_PAD_LCD_DATA18__LCDIF_DATA18 = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__PWM5_OUT = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__CA7_MX6UL_EVENTO = IOMUX_PAD(0x03EC, 0x0160, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__CSI_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 3, 0x04EC, 1, 0), + MX6_PAD_LCD_DATA18__EIM_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x03EC, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__SRC_BT_CFG26 = IOMUX_PAD(0x03EC, 0x0160, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__USDHC2_CMD = IOMUX_PAD(0x03EC, 0x0160, 8, 0x0678, 1, 0), + MX6_PAD_LCD_DATA19__EIM_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x03F0, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__SRC_BT_CFG27 = IOMUX_PAD(0x03F0, 0x0164, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__USDHC2_CLK = IOMUX_PAD(0x03F0, 0x0164, 8, 0x0670, 1, 0), + + MX6_PAD_LCD_DATA19__LCDIF_DATA19 = IOMUX_PAD(0x03F0, 0x0164, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__PWM6_OUT = IOMUX_PAD(0x03F0, 0x0164, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__WDOG1_WDOG_ANY = IOMUX_PAD(0x03F0, 0x0164, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__CSI_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 3, 0x04F0, 1, 0), + MX6_PAD_LCD_DATA20__EIM_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x03F4, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__SRC_BT_CFG28 = IOMUX_PAD(0x03F4, 0x0168, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__USDHC2_DATA0 = IOMUX_PAD(0x03F4, 0x0168, 8, 0x067C, 1, 0), + + MX6_PAD_LCD_DATA20__LCDIF_DATA20 = IOMUX_PAD(0x03F4, 0x0168, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__UART8_DCE_TX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__UART8_DTE_RX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x065C, 2, 0), + MX6_PAD_LCD_DATA20__ECSPI1_SCLK = IOMUX_PAD(0x03F4, 0x0168, 2, 0x0534, 0, 0), + MX6_PAD_LCD_DATA20__CSI_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 3, 0x04F4, 1, 0), + + MX6_PAD_LCD_DATA21__LCDIF_DATA21 = IOMUX_PAD(0x03F8, 0x016C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__UART8_DCE_RX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x065C, 3, 0), + MX6_PAD_LCD_DATA21__UART8_DTE_TX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__ECSPI1_SS0 = IOMUX_PAD(0x03F8, 0x016C, 2, 0x0540, 0, 0), + MX6_PAD_LCD_DATA21__CSI_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 3, 0x04F8, 1, 0), + MX6_PAD_LCD_DATA21__EIM_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__SRC_BT_CFG29 = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__USDHC2_DATA1 = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0), + + MX6_PAD_LCD_DATA22__LCDIF_DATA22 = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__MQS_RIGHT = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x0170, 2, 0x053C, 0, 0), + MX6_PAD_LCD_DATA22__CSI_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 3, 0x04FC, 1, 0), + MX6_PAD_LCD_DATA22__EIM_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x03FC, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__SRC_BT_CFG30 = IOMUX_PAD(0x03FC, 0x0170, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__USDHC2_DATA2 = IOMUX_PAD(0x03FC, 0x0170, 8, 0x0684, 0, 0), + + MX6_PAD_LCD_DATA23__LCDIF_DATA23 = IOMUX_PAD(0x0400, 0x0174, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__MQS_LEFT = IOMUX_PAD(0x0400, 0x0174, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x0174, 2, 0x0538, 0, 0), + MX6_PAD_LCD_DATA23__CSI_DATA15 = IOMUX_PAD(0x0400, 0x0174, 3, 0x0500, 1, 0), + MX6_PAD_LCD_DATA23__EIM_DATA15 = IOMUX_PAD(0x0400, 0x0174, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0400, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__SRC_BT_CFG31 = IOMUX_PAD(0x0400, 0x0174, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__USDHC2_DATA3 = IOMUX_PAD(0x0400, 0x0174, 8, 0x0688, 1, 0), + + MX6_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0404, 0x0178, 0, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__USDHC2_CLK = IOMUX_PAD(0x0404, 0x0178, 1, 0x0670, 2, 0), + MX6_PAD_NAND_RE_B__QSPI_B_SCLK = IOMUX_PAD(0x0404, 0x0178, 2, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__KPP_ROW00 = IOMUX_PAD(0x0404, 0x0178, 3, 0x05D0, 1, 0), + MX6_PAD_NAND_RE_B__EIM_EB_B00 = IOMUX_PAD(0x0404, 0x0178, 4, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__GPIO4_IO00 = IOMUX_PAD(0x0404, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__ECSPI3_SS2 = IOMUX_PAD(0x0404, 0x0178, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x0408, 0x017C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__USDHC2_CMD = IOMUX_PAD(0x0408, 0x017C, 1, 0x0678, 2, 0), + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B = IOMUX_PAD(0x0408, 0x017C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__KPP_COL00 = IOMUX_PAD(0x0408, 0x017C, 3, 0x05C4, 1, 0), + MX6_PAD_NAND_WE_B__EIM_EB_B01 = IOMUX_PAD(0x0408, 0x017C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__GPIO4_IO01 = IOMUX_PAD(0x0408, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__ECSPI3_SS3 = IOMUX_PAD(0x0408, 0x017C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x040C, 0x0180, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x040C, 0x0180, 1, 0x067C, 2, 0), + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B = IOMUX_PAD(0x040C, 0x0180, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__KPP_ROW01 = IOMUX_PAD(0x040C, 0x0180, 3, 0x05D4, 1, 0), + MX6_PAD_NAND_DATA00__EIM_AD08 = IOMUX_PAD(0x040C, 0x0180, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__GPIO4_IO02 = IOMUX_PAD(0x040C, 0x0180, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__ECSPI4_RDY = IOMUX_PAD(0x040C, 0x0180, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0410, 0x0184, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0410, 0x0184, 1, 0x0680, 2, 0), + MX6_PAD_NAND_DATA01__QSPI_B_DQS = IOMUX_PAD(0x0410, 0x0184, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__KPP_COL01 = IOMUX_PAD(0x0410, 0x0184, 3, 0x05C8, 1, 0), + MX6_PAD_NAND_DATA01__EIM_AD09 = IOMUX_PAD(0x0410, 0x0184, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__GPIO4_IO03 = IOMUX_PAD(0x0410, 0x0184, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__ECSPI4_SS1 = IOMUX_PAD(0x0410, 0x0184, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x0414, 0x0188, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0414, 0x0188, 1, 0x0684, 1, 0), + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 = IOMUX_PAD(0x0414, 0x0188, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__KPP_ROW02 = IOMUX_PAD(0x0414, 0x0188, 3, 0x05D8, 1, 0), + MX6_PAD_NAND_DATA02__EIM_AD10 = IOMUX_PAD(0x0414, 0x0188, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__GPIO4_IO04 = IOMUX_PAD(0x0414, 0x0188, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__ECSPI4_SS2 = IOMUX_PAD(0x0414, 0x0188, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0418, 0x018C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x0418, 0x018C, 1, 0x0688, 2, 0), + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 = IOMUX_PAD(0x0418, 0x018C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__KPP_COL02 = IOMUX_PAD(0x0418, 0x018C, 3, 0x05CC, 1, 0), + MX6_PAD_NAND_DATA03__EIM_AD11 = IOMUX_PAD(0x0418, 0x018C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__GPIO4_IO05 = IOMUX_PAD(0x0418, 0x018C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__ECSPI4_SS3 = IOMUX_PAD(0x0418, 0x018C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x041C, 0x0190, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x041C, 0x0190, 1, 0x068C, 1, 0), + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 = IOMUX_PAD(0x041C, 0x0190, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__ECSPI4_SCLK = IOMUX_PAD(0x041C, 0x0190, 3, 0x0564, 1, 0), + MX6_PAD_NAND_DATA04__EIM_AD12 = IOMUX_PAD(0x041C, 0x0190, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__GPIO4_IO06 = IOMUX_PAD(0x041C, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__UART2_DCE_TX = IOMUX_PAD(0x041C, 0x0190, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__UART2_DTE_RX = IOMUX_PAD(0x041C, 0x0190, 8, 0x062C, 2, 0), + + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0420, 0x0194, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0420, 0x0194, 1, 0x0690, 1, 0), + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 = IOMUX_PAD(0x0420, 0x0194, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__ECSPI4_MOSI = IOMUX_PAD(0x0420, 0x0194, 3, 0x056C, 1, 0), + MX6_PAD_NAND_DATA05__EIM_AD13 = IOMUX_PAD(0x0420, 0x0194, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__GPIO4_IO07 = IOMUX_PAD(0x0420, 0x0194, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__UART2_DCE_RX = IOMUX_PAD(0x0420, 0x0194, 8, 0x062C, 3, 0), + MX6_PAD_NAND_DATA05__UART2_DTE_TX = IOMUX_PAD(0x0420, 0x0194, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x0424, 0x0198, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0424, 0x0198, 1, 0x0694, 1, 0), + MX6_PAD_NAND_DATA06__SAI2_RX_BCLK = IOMUX_PAD(0x0424, 0x0198, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__ECSPI4_MISO = IOMUX_PAD(0x0424, 0x0198, 3, 0x0568, 1, 0), + MX6_PAD_NAND_DATA06__EIM_AD14 = IOMUX_PAD(0x0424, 0x0198, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__GPIO4_IO08 = IOMUX_PAD(0x0424, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__UART2_DCE_CTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__UART2_DTE_RTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0628, 4, 0), + + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0428, 0x019C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x0428, 0x019C, 1, 0x0698, 1, 0), + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x0428, 0x019C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__ECSPI4_SS0 = IOMUX_PAD(0x0428, 0x019C, 3, 0x0570, 1, 0), + MX6_PAD_NAND_DATA07__EIM_AD15 = IOMUX_PAD(0x0428, 0x019C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__GPIO4_IO09 = IOMUX_PAD(0x0428, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__UART2_DCE_RTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0628, 5, 0), + MX6_PAD_NAND_DATA07__UART2_DTE_CTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x042C, 0x01A0, 0, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__USDHC2_RESET_B = IOMUX_PAD(0x042C, 0x01A0, 1, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__QSPI_A_DQS = IOMUX_PAD(0x042C, 0x01A0, 2, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__PWM3_OUT = IOMUX_PAD(0x042C, 0x01A0, 3, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__EIM_ADDR17 = IOMUX_PAD(0x042C, 0x01A0, 4, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__GPIO4_IO10 = IOMUX_PAD(0x042C, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__ECSPI3_SS1 = IOMUX_PAD(0x042C, 0x01A0, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x0430, 0x01A4, 0, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__USDHC1_RESET_B = IOMUX_PAD(0x0430, 0x01A4, 1, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__QSPI_A_SCLK = IOMUX_PAD(0x0430, 0x01A4, 2, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__PWM4_OUT = IOMUX_PAD(0x0430, 0x01A4, 3, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__EIM_BCLK = IOMUX_PAD(0x0430, 0x01A4, 4, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__GPIO4_IO11 = IOMUX_PAD(0x0430, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__ECSPI3_RDY = IOMUX_PAD(0x0430, 0x01A4, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x0434, 0x01A8, 0, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__USDHC1_DATA4 = IOMUX_PAD(0x0434, 0x01A8, 1, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 = IOMUX_PAD(0x0434, 0x01A8, 2, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__ECSPI3_SS0 = IOMUX_PAD(0x0434, 0x01A8, 3, 0x0560, 1, 0), + MX6_PAD_NAND_READY_B__EIM_CS1_B = IOMUX_PAD(0x0434, 0x01A8, 4, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__GPIO4_IO12 = IOMUX_PAD(0x0434, 0x01A8, 5, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__UART3_DCE_TX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__UART3_DTE_RX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0634, 2, 0), + + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0438, 0x01AC, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 = IOMUX_PAD(0x0438, 0x01AC, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 = IOMUX_PAD(0x0438, 0x01AC, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__ECSPI3_SCLK = IOMUX_PAD(0x0438, 0x01AC, 3, 0x0554, 1, 0), + MX6_PAD_NAND_CE0_B__EIM_DTACK_B = IOMUX_PAD(0x0438, 0x01AC, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__GPIO4_IO13 = IOMUX_PAD(0x0438, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__UART3_DCE_RX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0634, 3, 0), + MX6_PAD_NAND_CE0_B__UART3_DTE_TX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x043C, 0x01B0, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 = IOMUX_PAD(0x043C, 0x01B0, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 = IOMUX_PAD(0x043C, 0x01B0, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__ECSPI3_MOSI = IOMUX_PAD(0x043C, 0x01B0, 3, 0x055C, 1, 0), + MX6_PAD_NAND_CE1_B__EIM_ADDR18 = IOMUX_PAD(0x043C, 0x01B0, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__GPIO4_IO14 = IOMUX_PAD(0x043C, 0x01B0, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__UART3_DCE_CTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__UART3_DTE_RTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0630, 2, 0), + + MX6_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0440, 0x01B4, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__USDHC1_DATA7 = IOMUX_PAD(0x0440, 0x01B4, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 = IOMUX_PAD(0x0440, 0x01B4, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__ECSPI3_MISO = IOMUX_PAD(0x0440, 0x01B4, 3, 0x0558, 1, 0), + MX6_PAD_NAND_CLE__EIM_ADDR16 = IOMUX_PAD(0x0440, 0x01B4, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__GPIO4_IO15 = IOMUX_PAD(0x0440, 0x01B4, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__UART3_DCE_RTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0630, 3, 0), + MX6_PAD_NAND_CLE__UART3_DTE_CTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0444, 0x01B8, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__CSI_FIELD = IOMUX_PAD(0x0444, 0x01B8, 1, 0x0530, 1, 0), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B = IOMUX_PAD(0x0444, 0x01B8, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__PWM5_OUT = IOMUX_PAD(0x0444, 0x01B8, 3, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__EIM_WAIT = IOMUX_PAD(0x0444, 0x01B8, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__GPIO4_IO16 = IOMUX_PAD(0x0444, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x0444, 0x01B8, 6, 0x0614, 1, 0), + MX6_PAD_NAND_DQS__SPDIF_EXT_CLK = IOMUX_PAD(0x0444, 0x01B8, 8, 0x061C, 1, 0), + + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0448, 0x01BC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPT2_COMPARE1 = IOMUX_PAD(0x0448, 0x01BC, 1, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SAI2_RX_SYNC = IOMUX_PAD(0x0448, 0x01BC, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SPDIF_OUT = IOMUX_PAD(0x0448, 0x01BC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__EIM_ADDR19 = IOMUX_PAD(0x0448, 0x01BC, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO2_IO16 = IOMUX_PAD(0x0448, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x0448, 0x01BC, 6, 0x0610, 2, 0), + MX6_PAD_SD1_CMD__USB_OTG1_PWR = IOMUX_PAD(0x0448, 0x01BC, 8, 0x0000, 0, 0), + + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x044C, 0x01C0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPT2_COMPARE2 = IOMUX_PAD(0x044C, 0x01C0, 1, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__SAI2_MCLK = IOMUX_PAD(0x044C, 0x01C0, 2, 0x05F0, 1, 0), + MX6_PAD_SD1_CLK__SPDIF_IN = IOMUX_PAD(0x044C, 0x01C0, 3, 0x0618, 3, 0), + MX6_PAD_SD1_CLK__EIM_ADDR20 = IOMUX_PAD(0x044C, 0x01C0, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPIO2_IO17 = IOMUX_PAD(0x044C, 0x01C0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__USB_OTG1_OC = IOMUX_PAD(0x044C, 0x01C0, 8, 0x0664, 2, 0), + + MX6_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0450, 0x01C4, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__GPT2_COMPARE3 = IOMUX_PAD(0x0450, 0x01C4, 1, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__SAI2_TX_SYNC = IOMUX_PAD(0x0450, 0x01C4, 2, 0x05FC, 1, 0), + MX6_PAD_SD1_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0450, 0x01C4, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__EIM_ADDR21 = IOMUX_PAD(0x0450, 0x01C4, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__GPIO2_IO18 = IOMUX_PAD(0x0450, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID = IOMUX_PAD(0x0450, 0x01C4, 8, 0x04B8, 2, 0), + + MX6_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0454, 0x01C8, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__GPT2_CLK = IOMUX_PAD(0x0454, 0x01C8, 1, 0x05A0, 1, 0), + MX6_PAD_SD1_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0454, 0x01C8, 2, 0x05F8, 1, 0), + MX6_PAD_SD1_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0454, 0x01C8, 3, 0x0584, 3, 0), + MX6_PAD_SD1_DATA1__EIM_ADDR22 = IOMUX_PAD(0x0454, 0x01C8, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__GPIO2_IO19 = IOMUX_PAD(0x0454, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0454, 0x01C8, 8, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0458, 0x01CC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__GPT2_CAPTURE1 = IOMUX_PAD(0x0458, 0x01CC, 1, 0x0598, 1, 0), + MX6_PAD_SD1_DATA2__SAI2_RX_DATA = IOMUX_PAD(0x0458, 0x01CC, 2, 0x05F4, 1, 0), + MX6_PAD_SD1_DATA2__FLEXCAN2_TX = IOMUX_PAD(0x0458, 0x01CC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__EIM_ADDR23 = IOMUX_PAD(0x0458, 0x01CC, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__GPIO2_IO20 = IOMUX_PAD(0x0458, 0x01CC, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__CCM_CLKO1 = IOMUX_PAD(0x0458, 0x01CC, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__USB_OTG2_OC = IOMUX_PAD(0x0458, 0x01CC, 8, 0x0660, 2, 0), + + MX6_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x045C, 0x01D0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__GPT2_CAPTURE2 = IOMUX_PAD(0x045C, 0x01D0, 1, 0x059C, 1, 0), + MX6_PAD_SD1_DATA3__SAI2_TX_DATA = IOMUX_PAD(0x045C, 0x01D0, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__FLEXCAN2_RX = IOMUX_PAD(0x045C, 0x01D0, 3, 0x0588, 3, 0), + MX6_PAD_SD1_DATA3__EIM_ADDR24 = IOMUX_PAD(0x045C, 0x01D0, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__GPIO2_IO21 = IOMUX_PAD(0x045C, 0x01D0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__CCM_CLKO2 = IOMUX_PAD(0x045C, 0x01D0, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID = IOMUX_PAD(0x045C, 0x01D0, 8, 0x04BC, 2, 0), + + MX6_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x0460, 0x01D4, 0, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__USDHC2_CD_B = IOMUX_PAD(0x0460, 0x01D4, 1, 0x0674, 0, 0), + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B = IOMUX_PAD(0x0460, 0x01D4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__I2C1_SDA = IOMUX_PAD(0x0460, 0x01D4, IOMUX_CONFIG_SION | 3, 0x05A8, 0, 0), + MX6_PAD_CSI_MCLK__EIM_CS0_B = IOMUX_PAD(0x0460, 0x01D4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__GPIO4_IO17 = IOMUX_PAD(0x0460, 0x01D4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL = IOMUX_PAD(0x0460, 0x01D4, 6, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__UART6_DCE_TX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__UART6_DTE_RX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x064C, 0, 0), + + MX6_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x0464, 0x01D8, 0, 0x0528, 1, 0), + MX6_PAD_CSI_PIXCLK__USDHC2_WP = IOMUX_PAD(0x0464, 0x01D8, 1, 0x069C, 2, 0), + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B = IOMUX_PAD(0x0464, 0x01D8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__I2C1_SCL = IOMUX_PAD(0x0464, 0x01D8, IOMUX_CONFIG_SION | 3, 0x05A4, 2, 0), + MX6_PAD_CSI_PIXCLK__EIM_OE = IOMUX_PAD(0x0464, 0x01D8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__GPIO4_IO18 = IOMUX_PAD(0x0464, 0x01D8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 = IOMUX_PAD(0x0464, 0x01D8, 6, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__UART6_DCE_RX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x064C, 3, 0), + MX6_PAD_CSI_PIXCLK__UART6_DTE_TX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x0468, 0x01DC, 0, 0x052C, 0, 0), + MX6_PAD_CSI_VSYNC__USDHC2_CLK = IOMUX_PAD(0x0468, 0x01DC, 1, 0x0670, 0, 0), + MX6_PAD_CSI_VSYNC__SIM1_PORT1_CLK = IOMUX_PAD(0x0468, 0x01DC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__I2C2_SDA = IOMUX_PAD(0x0468, 0x01DC, IOMUX_CONFIG_SION | 3, 0x05B0, 0, 0), + MX6_PAD_CSI_VSYNC__EIM_RW = IOMUX_PAD(0x0468, 0x01DC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__GPIO4_IO19 = IOMUX_PAD(0x0468, 0x01DC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__PWM7_OUT = IOMUX_PAD(0x0468, 0x01DC, 6, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__UART6_DCE_RTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0648, 0, 0), + MX6_PAD_CSI_VSYNC__UART6_DTE_CTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x046C, 0x01E0, 0, 0x0524, 0, 0), + MX6_PAD_CSI_HSYNC__USDHC2_CMD = IOMUX_PAD(0x046C, 0x01E0, 1, 0x0678, 0, 0), + MX6_PAD_CSI_HSYNC__SIM1_PORT1_PD = IOMUX_PAD(0x046C, 0x01E0, 2, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__I2C2_SCL = IOMUX_PAD(0x046C, 0x01E0, IOMUX_CONFIG_SION | 3, 0x05AC, 0, 0), + MX6_PAD_CSI_HSYNC__EIM_LBA_B = IOMUX_PAD(0x046C, 0x01E0, 4, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__GPIO4_IO20 = IOMUX_PAD(0x046C, 0x01E0, 5, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__PWM8_OUT = IOMUX_PAD(0x046C, 0x01E0, 6, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__UART6_DCE_CTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__UART6_DTE_RTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0648, 1, 0), + + MX6_PAD_CSI_DATA00__CSI_DATA02 = IOMUX_PAD(0x0470, 0x01E4, 0, 0x04C4, 0, 0), + MX6_PAD_CSI_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x0470, 0x01E4, 1, 0x067C, 0, 0), + MX6_PAD_CSI_DATA00__SIM1_PORT1_RST_B = IOMUX_PAD(0x0470, 0x01E4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__ECSPI2_SCLK = IOMUX_PAD(0x0470, 0x01E4, 3, 0x0544, 0, 0), + MX6_PAD_CSI_DATA00__EIM_AD00 = IOMUX_PAD(0x0470, 0x01E4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__GPIO4_IO21 = IOMUX_PAD(0x0470, 0x01E4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__SRC_INT_BOOT = IOMUX_PAD(0x0470, 0x01E4, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__UART5_DCE_TX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__UART5_DTE_RX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0644, 0, 0), + + MX6_PAD_CSI_DATA01__CSI_DATA03 = IOMUX_PAD(0x0474, 0x01E8, 0, 0x04C8, 0, 0), + MX6_PAD_CSI_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0474, 0x01E8, 1, 0x0680, 0, 0), + MX6_PAD_CSI_DATA01__SIM1_PORT1_SVEN = IOMUX_PAD(0x0474, 0x01E8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__ECSPI2_SS0 = IOMUX_PAD(0x0474, 0x01E8, 3, 0x0550, 0, 0), + MX6_PAD_CSI_DATA01__EIM_AD01 = IOMUX_PAD(0x0474, 0x01E8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__GPIO4_IO22 = IOMUX_PAD(0x0474, 0x01E8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__SAI1_MCLK = IOMUX_PAD(0x0474, 0x01E8, 6, 0x05E0, 0, 0), + MX6_PAD_CSI_DATA01__UART5_DCE_RX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0644, 1, 0), + MX6_PAD_CSI_DATA01__UART5_DTE_TX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA02__CSI_DATA04 = IOMUX_PAD(0x0478, 0x01EC, 0, 0x04D8, 1, 0), + MX6_PAD_CSI_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0478, 0x01EC, 1, 0x0684, 2, 0), + MX6_PAD_CSI_DATA02__SIM1_PORT1_TRXD = IOMUX_PAD(0x0478, 0x01EC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__ECSPI2_MOSI = IOMUX_PAD(0x0478, 0x01EC, 3, 0x054C, 1, 0), + MX6_PAD_CSI_DATA02__EIM_AD02 = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__GPIO4_IO23 = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__SAI1_RX_SYNC = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 5, 0), + MX6_PAD_CSI_DATA02__UART5_DTE_CTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA03__CSI_DATA05 = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0), + MX6_PAD_CSI_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x047C, 0x01F0, 1, 0x0688, 0, 0), + MX6_PAD_CSI_DATA03__SIM2_PORT1_PD = IOMUX_PAD(0x047C, 0x01F0, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__ECSPI2_MISO = IOMUX_PAD(0x047C, 0x01F0, 3, 0x0548, 0, 0), + MX6_PAD_CSI_DATA03__EIM_AD03 = IOMUX_PAD(0x047C, 0x01F0, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__GPIO4_IO24 = IOMUX_PAD(0x047C, 0x01F0, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__SAI1_RX_BCLK = IOMUX_PAD(0x047C, 0x01F0, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__UART5_DCE_CTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__UART5_DTE_RTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0640, 0, 0), + + MX6_PAD_CSI_DATA04__CSI_DATA06 = IOMUX_PAD(0x0480, 0x01F4, 0, 0x04DC, 1, 0), + MX6_PAD_CSI_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x0480, 0x01F4, 1, 0x068C, 2, 0), + MX6_PAD_CSI_DATA04__SIM2_PORT1_CLK = IOMUX_PAD(0x0480, 0x01F4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__ECSPI1_SCLK = IOMUX_PAD(0x0480, 0x01F4, 3, 0x0534, 1, 0), + MX6_PAD_CSI_DATA04__EIM_AD04 = IOMUX_PAD(0x0480, 0x01F4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__GPIO4_IO25 = IOMUX_PAD(0x0480, 0x01F4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__SAI1_TX_SYNC = IOMUX_PAD(0x0480, 0x01F4, 6, 0x05EC, 1, 0), + MX6_PAD_CSI_DATA04__USDHC1_WP = IOMUX_PAD(0x0480, 0x01F4, 8, 0x066C, 2, 0), + + MX6_PAD_CSI_DATA05__CSI_DATA07 = IOMUX_PAD(0x0484, 0x01F8, 0, 0x04E0, 1, 0), + MX6_PAD_CSI_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0484, 0x01F8, 1, 0x0690, 2, 0), + MX6_PAD_CSI_DATA05__SIM2_PORT1_RST_B = IOMUX_PAD(0x0484, 0x01F8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__ECSPI1_SS0 = IOMUX_PAD(0x0484, 0x01F8, 3, 0x0540, 1, 0), + MX6_PAD_CSI_DATA05__EIM_AD05 = IOMUX_PAD(0x0484, 0x01F8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__GPIO4_IO26 = IOMUX_PAD(0x0484, 0x01F8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__SAI1_TX_BCLK = IOMUX_PAD(0x0484, 0x01F8, 6, 0x05E8, 1, 0), + MX6_PAD_CSI_DATA05__USDHC1_CD_B = IOMUX_PAD(0x0484, 0x01F8, 8, 0x0668, 2, 0), + + MX6_PAD_CSI_DATA06__CSI_DATA08 = IOMUX_PAD(0x0488, 0x01FC, 0, 0x04E4, 1, 0), + MX6_PAD_CSI_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0488, 0x01FC, 1, 0x0694, 2, 0), + MX6_PAD_CSI_DATA06__SIM2_PORT1_SVEN = IOMUX_PAD(0x0488, 0x01FC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__ECSPI1_MOSI = IOMUX_PAD(0x0488, 0x01FC, 3, 0x053C, 1, 0), + MX6_PAD_CSI_DATA06__EIM_AD06 = IOMUX_PAD(0x0488, 0x01FC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__GPIO4_IO27 = IOMUX_PAD(0x0488, 0x01FC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__SAI1_RX_DATA = IOMUX_PAD(0x0488, 0x01FC, 6, 0x05E4, 1, 0), + MX6_PAD_CSI_DATA06__USDHC1_RESET_B = IOMUX_PAD(0x0488, 0x01FC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA07__CSI_DATA09 = IOMUX_PAD(0x048C, 0x0200, 0, 0x04E8, 1, 0), + MX6_PAD_CSI_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x048C, 0x0200, 1, 0x0698, 2, 0), + MX6_PAD_CSI_DATA07__SIM2_PORT1_TRXD = IOMUX_PAD(0x048C, 0x0200, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__ECSPI1_MISO = IOMUX_PAD(0x048C, 0x0200, 3, 0x0538, 1, 0), + MX6_PAD_CSI_DATA07__EIM_AD07 = IOMUX_PAD(0x048C, 0x0200, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__GPIO4_IO28 = IOMUX_PAD(0x048C, 0x0200, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__SAI1_TX_DATA = IOMUX_PAD(0x048C, 0x0200, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__USDHC1_VSELECT = IOMUX_PAD(0x048C, 0x0200, 8, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_IMX6UL_PINS_H__ */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8mp.h b/arch/arm/mach-imx/include/mach/iomux-mx8mp.h new file mode 100644 index 0000000000..2607ba21f6 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-mx8mp.h @@ -0,0 +1,1103 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __ASM_ARCH_IMX8MP_PINS_H__ +#define __ASM_ARCH_IMX8MP_PINS_H__ + +#include <mach/iomux-v3.h> +#include <mach/imx8mp-regs.h> +#include <mach/iomux-mx8m.h> + +enum { + MX8MP_PAD_GPIO1_IO00__GPIO1_IO00 = IOMUX_PAD(0x0274, 0x0014, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0274, 0x0014, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__MEDIAMIX_ISP_FL_TRIG_0 = IOMUX_PAD(0x0274, 0x0014, 3, 0x05D4, 0, 0), + MX8MP_PAD_GPIO1_IO00__ANAMIX_REF_CLK_32K = IOMUX_PAD(0x0274, 0x0014, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x0274, 0x0014, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__SJC_FAIL = IOMUX_PAD(0x0274, 0x0014, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO01__GPIO1_IO01 = IOMUX_PAD(0x0278, 0x0018, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0278, 0x0018, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__MEDIAMIX_ISP_SHUTTER_TRIG_0 = IOMUX_PAD(0x0278, 0x0018, 3, 0x05DC, 0, 0), + MX8MP_PAD_GPIO1_IO01__ANAMIX_REF_CLK_24M = IOMUX_PAD(0x0278, 0x0018, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2 = IOMUX_PAD(0x0278, 0x0018, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__SJC_ACTIVE = IOMUX_PAD(0x0278, 0x0018, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO02__GPIO1_IO02 = IOMUX_PAD(0x027C, 0x001C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x027C, 0x001C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__MEDIAMIX_ISP_FLASH_TRIG_0 = IOMUX_PAD(0x027C, 0x001C, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x027C, 0x001C, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__SJC_DE_B = IOMUX_PAD(0x027C, 0x001C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x0280, 0x0020, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x0280, 0x0020, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__MEDIAMIX_ISP_PRELIGHT_TRIG_0 = IOMUX_PAD(0x0280, 0x0020, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__SDMA1_EXT_EVENT00 = IOMUX_PAD(0x0280, 0x0020, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__ANAMIX_XTAL_OK = IOMUX_PAD(0x0280, 0x0020, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__SJC_DONE = IOMUX_PAD(0x0280, 0x0020, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x0284, 0x0024, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x0284, 0x0024, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__MEDIAMIX_ISP_SHUTTER_OPEN_0 = IOMUX_PAD(0x0284, 0x0024, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__SDMA1_EXT_EVENT01 = IOMUX_PAD(0x0284, 0x0024, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__ANAMIX_XTAL_OK_LV = IOMUX_PAD(0x0284, 0x0024, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__USDHC1_TEST_TRIG = IOMUX_PAD(0x0284, 0x0024, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO05__GPIO1_IO05 = IOMUX_PAD(0x0288, 0x0028, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO05__M7_NMI = IOMUX_PAD(0x0288, 0x0028, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO05__MEDIAMIX_ISP_FL_TRIG_1 = IOMUX_PAD(0x0288, 0x0028, 3, 0x05D8, 0, 0), + MX8MP_PAD_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x0288, 0x0028, 5, 0x0554, 0, 0), + MX8MP_PAD_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT = IOMUX_PAD(0x0288, 0x0028, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO05__USDHC2_TEST_TRIG = IOMUX_PAD(0x0288, 0x0028, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO06__GPIO1_IO06 = IOMUX_PAD(0x028C, 0x002C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__ENET_QOS_MDC = IOMUX_PAD(0x028C, 0x002C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__MEDIAMIX_ISP_SHUTTER_TRIG_1 = IOMUX_PAD(0x028C, 0x002C, 3, 0x05E0, 0, 0), + MX8MP_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x028C, 0x002C, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3 = IOMUX_PAD(0x028C, 0x002C, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__ECSPI1_TEST_TRIG = IOMUX_PAD(0x028C, 0x002C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO07__GPIO1_IO07 = IOMUX_PAD(0x0290, 0x0030, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__ENET_QOS_MDIO = IOMUX_PAD(0x0290, 0x0030, 1, 0x0590, 0, 0), + MX8MP_PAD_GPIO1_IO07__MEDIAMIX_ISP_FLASH_TRIG_1 = IOMUX_PAD(0x0290, 0x0030, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x0290, 0x0030, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4 = IOMUX_PAD(0x0290, 0x0030, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__ECSPI2_TEST_TRIG = IOMUX_PAD(0x0290, 0x0030, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO08__GPIO1_IO08 = IOMUX_PAD(0x0294, 0x0034, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN = IOMUX_PAD(0x0294, 0x0034, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x0294, 0x0034, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__MEDIAMIX_ISP_PRELIGHT_TRIG_1 = IOMUX_PAD(0x0294, 0x0034, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN = IOMUX_PAD(0x0294, 0x0034, 4, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x0294, 0x0034, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x0294, 0x0034, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__FLEXSPI_TEST_TRIG = IOMUX_PAD(0x0294, 0x0034, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO09__GPIO1_IO09 = IOMUX_PAD(0x0298, 0x0038, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT = IOMUX_PAD(0x0298, 0x0038, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x0298, 0x0038, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__MEDIAMIX_ISP_SHUTTER_OPEN_1 = IOMUX_PAD(0x0298, 0x0038, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__USDHC3_RESET_B = IOMUX_PAD(0x0298, 0x0038, 4, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__AUDIOMIX_EXT_EVENT00 = IOMUX_PAD(0x0298, 0x0038, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0298, 0x0038, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__RAWNAND_TEST_TRIG = IOMUX_PAD(0x0298, 0x0038, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x029C, 0x003C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO10__HSIOMIX_usb1_OTG_ID = IOMUX_PAD(0x029C, 0x003C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO10__PWM3_OUT = IOMUX_PAD(0x029C, 0x003C, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO10__OCOTP_FUSE_LATCHED = IOMUX_PAD(0x029C, 0x003C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02A0, 0x0040, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__HSIOMIX_usb2_OTG_ID = IOMUX_PAD(0x02A0, 0x0040, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__PWM2_OUT = IOMUX_PAD(0x02A0, 0x0040, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__USDHC3_VSELECT = IOMUX_PAD(0x02A0, 0x0040, 4, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x02A0, 0x0040, 5, 0x0554, 1, 0), + MX8MP_PAD_GPIO1_IO11__CCMSRCGPCMIX_OUT0 = IOMUX_PAD(0x02A0, 0x0040, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02A0, 0x0040, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02A4, 0x0044, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__HSIOMIX_usb1_OTG_PWR = IOMUX_PAD(0x02A4, 0x0044, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__AUDIOMIX_EXT_EVENT01 = IOMUX_PAD(0x02A4, 0x0044, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__CCMSRCGPCMIX_OUT1 = IOMUX_PAD(0x02A4, 0x0044, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT00 = IOMUX_PAD(0x02A4, 0x0044, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02A8, 0x0048, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__HSIOMIX_usb1_OTG_OC = IOMUX_PAD(0x02A8, 0x0048, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02A8, 0x0048, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__CCMSRCGPCMIX_OUT2 = IOMUX_PAD(0x02A8, 0x0048, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT01 = IOMUX_PAD(0x02A8, 0x0048, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02AC, 0x004C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR = IOMUX_PAD(0x02AC, 0x004C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__USDHC3_CD_B = IOMUX_PAD(0x02AC, 0x004C, 4, 0x0608, 0, 0), + MX8MP_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02AC, 0x004C, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x02AC, 0x004C, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT02 = IOMUX_PAD(0x02AC, 0x004C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02B0, 0x0050, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__HSIOMIX_usb2_OTG_OC = IOMUX_PAD(0x02B0, 0x0050, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__USDHC3_WP = IOMUX_PAD(0x02B0, 0x0050, 4, 0x0634, 0, 0), + MX8MP_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02B0, 0x0050, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x02B0, 0x0050, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02B0, 0x0050, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_MDC__ENET_QOS_MDC = IOMUX_PAD(0x02B4, 0x0054, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 = IOMUX_PAD(0x02B4, 0x0054, 2, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02B4, 0x0054, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDC__USDHC3_STROBE = IOMUX_PAD(0x02B4, 0x0054, 6, 0x0630, 0, 0), + MX8MP_PAD_ENET_MDC__SIM_M_HADDR15 = IOMUX_PAD(0x02B4, 0x0054, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_MDIO__ENET_QOS_MDIO = IOMUX_PAD(0x02B8, 0x0058, 0, 0x0590, 1, 0), + MX8MP_PAD_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC = IOMUX_PAD(0x02B8, 0x0058, 2, 0x0528, 0, 0), + MX8MP_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02B8, 0x0058, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDIO__USDHC3_DATA5 = IOMUX_PAD(0x02B8, 0x0058, 6, 0x0624, 0, 0), + MX8MP_PAD_ENET_MDIO__SIM_M_HADDR16 = IOMUX_PAD(0x02B8, 0x0058, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD3__ENET_QOS_RGMII_TD3 = IOMUX_PAD(0x02BC, 0x005C, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK = IOMUX_PAD(0x02BC, 0x005C, 2, 0x0524, 0, 0), + MX8MP_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02BC, 0x005C, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD3__USDHC3_DATA6 = IOMUX_PAD(0x02BC, 0x005C, 6, 0x0628, 0, 0), + MX8MP_PAD_ENET_TD3__SIM_M_HADDR17 = IOMUX_PAD(0x02BC, 0x005C, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD2__ENET_QOS_RGMII_TD2 = IOMUX_PAD(0x02C0, 0x0060, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK = IOMUX_PAD(0x02C0, 0x0060, 1, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 = IOMUX_PAD(0x02C0, 0x0060, 2, 0x051C, 0, 0), + MX8MP_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02C0, 0x0060, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD2__USDHC3_DATA7 = IOMUX_PAD(0x02C0, 0x0060, 6, 0x062C, 0, 0), + MX8MP_PAD_ENET_TD2__SIM_M_HADDR18 = IOMUX_PAD(0x02C0, 0x0060, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD1__ENET_QOS_RGMII_TD1 = IOMUX_PAD(0x02C4, 0x0064, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC = IOMUX_PAD(0x02C4, 0x0064, 2, 0x0520, 0, 0), + MX8MP_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02C4, 0x0064, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD1__USDHC3_CD_B = IOMUX_PAD(0x02C4, 0x0064, 6, 0x0608, 1, 0), + MX8MP_PAD_ENET_TD1__SIM_M_HADDR19 = IOMUX_PAD(0x02C4, 0x0064, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD0__ENET_QOS_RGMII_TD0 = IOMUX_PAD(0x02C8, 0x0068, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK = IOMUX_PAD(0x02C8, 0x0068, 2, 0x0518, 0, 0), + MX8MP_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02C8, 0x0068, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD0__USDHC3_WP = IOMUX_PAD(0x02C8, 0x0068, 6, 0x0634, 1, 0), + MX8MP_PAD_ENET_TD0__SIM_M_HADDR20 = IOMUX_PAD(0x02C8, 0x0068, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL = IOMUX_PAD(0x02CC, 0x006C, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK = IOMUX_PAD(0x02CC, 0x006C, 2, 0x0514, 0, 0), + MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x02CC, 0x006C, 3, 0x0000, 0, 0), + MX8MP_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02CC, 0x006C, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TX_CTL__USDHC3_DATA0 = IOMUX_PAD(0x02CC, 0x006C, 6, 0x0610, 0, 0), + MX8MP_PAD_ENET_TX_CTL__SIM_M_HADDR21 = IOMUX_PAD(0x02CC, 0x006C, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK = IOMUX_PAD(0x02D0, 0x0070, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__ENET_QOS_TX_ER = IOMUX_PAD(0x02D0, 0x0070, 1, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 = IOMUX_PAD(0x02D0, 0x0070, 2, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02D0, 0x0070, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__USDHC3_DATA1 = IOMUX_PAD(0x02D0, 0x0070, 6, 0x0614, 0, 0), + MX8MP_PAD_ENET_TXC__SIM_M_HADDR22 = IOMUX_PAD(0x02D0, 0x0070, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL = IOMUX_PAD(0x02D4, 0x0074, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC = IOMUX_PAD(0x02D4, 0x0074, 2, 0x0540, 0, 0), + MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x02D4, 0x0074, 3, 0x04CC, 0, 0), + MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02D4, 0x0074, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RX_CTL__USDHC3_DATA2 = IOMUX_PAD(0x02D4, 0x0074, 6, 0x0618, 0, 0), + MX8MP_PAD_ENET_RX_CTL__SIM_M_HADDR23 = IOMUX_PAD(0x02D4, 0x0074, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK = IOMUX_PAD(0x02D8, 0x0078, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RXC__ENET_QOS_RX_ER = IOMUX_PAD(0x02D8, 0x0078, 1, 0x0000, 0, 0), + MX8MP_PAD_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK = IOMUX_PAD(0x02D8, 0x0078, 2, 0x053C, 0, 0), + MX8MP_PAD_ENET_RXC__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x02D8, 0x0078, 3, 0x04C8, 0, 0), + MX8MP_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02D8, 0x0078, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RXC__USDHC3_DATA3 = IOMUX_PAD(0x02D8, 0x0078, 6, 0x061C, 0, 0), + MX8MP_PAD_ENET_RXC__SIM_M_HADDR24 = IOMUX_PAD(0x02D8, 0x0078, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD0__ENET_QOS_RGMII_RD0 = IOMUX_PAD(0x02DC, 0x007C, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 = IOMUX_PAD(0x02DC, 0x007C, 2, 0x0534, 0, 0), + MX8MP_PAD_ENET_RD0__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x02DC, 0x007C, 3, 0x04C4, 0, 0), + MX8MP_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02DC, 0x007C, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD0__USDHC3_DATA4 = IOMUX_PAD(0x02DC, 0x007C, 6, 0x0620, 0, 0), + MX8MP_PAD_ENET_RD0__SIM_M_HADDR25 = IOMUX_PAD(0x02DC, 0x007C, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD1__ENET_QOS_RGMII_RD1 = IOMUX_PAD(0x02E0, 0x0080, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC = IOMUX_PAD(0x02E0, 0x0080, 2, 0x0538, 0, 0), + MX8MP_PAD_ENET_RD1__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x02E0, 0x0080, 3, 0x04C0, 0, 0), + MX8MP_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02E0, 0x0080, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD1__USDHC3_RESET_B = IOMUX_PAD(0x02E0, 0x0080, 6, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD1__SIM_M_HADDR26 = IOMUX_PAD(0x02E0, 0x0080, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD2__ENET_QOS_RGMII_RD2 = IOMUX_PAD(0x02E4, 0x0084, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK = IOMUX_PAD(0x02E4, 0x0084, 2, 0x0530, 0, 0), + MX8MP_PAD_ENET_RD2__AUDIOMIX_CLK = IOMUX_PAD(0x02E4, 0x0084, 3, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x02E4, 0x0084, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD2__USDHC3_CLK = IOMUX_PAD(0x02E4, 0x0084, 6, 0x0604, 0, 0), + MX8MP_PAD_ENET_RD2__SIM_M_HADDR27 = IOMUX_PAD(0x02E4, 0x0084, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD3__ENET_QOS_RGMII_RD3 = IOMUX_PAD(0x02E8, 0x0088, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD3__AUDIOMIX_SAI7_MCLK = IOMUX_PAD(0x02E8, 0x0088, 2, 0x052C, 0, 0), + MX8MP_PAD_ENET_RD3__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x02E8, 0x0088, 3, 0x0544, 0, 0), + MX8MP_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x02E8, 0x0088, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD3__USDHC3_CMD = IOMUX_PAD(0x02E8, 0x0088, 6, 0x060C, 0, 0), + MX8MP_PAD_ENET_RD3__SIM_M_HADDR28 = IOMUX_PAD(0x02E8, 0x0088, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x02EC, 0x008C, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__ENET1_MDC = IOMUX_PAD(0x02EC, 0x008C, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__I2C5_SCL = IOMUX_PAD(0x02EC, 0x008C, 3 | IOMUX_CONFIG_SION, 0x05C4, 0, 0), + MX8MP_PAD_SD1_CLK__UART1_DCE_TX = IOMUX_PAD(0x02EC, 0x008C, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__UART1_DTE_RX = IOMUX_PAD(0x02EC, 0x008C, 4, 0x05E8, 0, 0), + MX8MP_PAD_SD1_CLK__GPIO2_IO00 = IOMUX_PAD(0x02EC, 0x008C, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__SIM_M_HADDR29 = IOMUX_PAD(0x02EC, 0x008C, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x02F0, 0x0090, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_CMD__ENET1_MDIO = IOMUX_PAD(0x02F0, 0x0090, 1, 0x057C, 0, 0), + MX8MP_PAD_SD1_CMD__I2C5_SDA = IOMUX_PAD(0x02F0, 0x0090, 3 | IOMUX_CONFIG_SION, 0x05C8, 0, 0), + MX8MP_PAD_SD1_CMD__UART1_DCE_RX = IOMUX_PAD(0x02F0, 0x0090, 4, 0x05E8, 1, 0), + MX8MP_PAD_SD1_CMD__UART1_DTE_TX = IOMUX_PAD(0x02F0, 0x0090, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_CMD__GPIO2_IO01 = IOMUX_PAD(0x02F0, 0x0090, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_CMD__SIM_M_HADDR30 = IOMUX_PAD(0x02F0, 0x0090, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x02F4, 0x0094, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__ENET1_RGMII_TD1 = IOMUX_PAD(0x02F4, 0x0094, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__I2C6_SCL = IOMUX_PAD(0x02F4, 0x0094, 3 | IOMUX_CONFIG_SION, 0x05CC, 0, 0), + MX8MP_PAD_SD1_DATA0__UART1_DCE_RTS = IOMUX_PAD(0x02F4, 0x0094, 4, 0x05E4, 0, 0), + MX8MP_PAD_SD1_DATA0__UART1_DTE_CTS = IOMUX_PAD(0x02F4, 0x0094, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__GPIO2_IO02 = IOMUX_PAD(0x02F4, 0x0094, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__SIM_M_HADDR31 = IOMUX_PAD(0x02F4, 0x0094, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x02F8, 0x0098, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__ENET1_RGMII_TD0 = IOMUX_PAD(0x02F8, 0x0098, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__I2C6_SDA = IOMUX_PAD(0x02F8, 0x0098, 3 | IOMUX_CONFIG_SION, 0x05D0, 0, 0), + MX8MP_PAD_SD1_DATA1__UART1_DCE_CTS = IOMUX_PAD(0x02F8, 0x0098, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__UART1_DTE_RTS = IOMUX_PAD(0x02F8, 0x0098, 4, 0x05E4, 1, 0), + MX8MP_PAD_SD1_DATA1__GPIO2_IO03 = IOMUX_PAD(0x02F8, 0x0098, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__SIM_M_HBURST00 = IOMUX_PAD(0x02F8, 0x0098, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x02FC, 0x009C, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA2__ENET1_RGMII_RD0 = IOMUX_PAD(0x02FC, 0x009C, 1, 0x0580, 0, 0), + MX8MP_PAD_SD1_DATA2__I2C4_SCL = IOMUX_PAD(0x02FC, 0x009C, 3 | IOMUX_CONFIG_SION, 0x05BC, 0, 0), + MX8MP_PAD_SD1_DATA2__UART2_DCE_TX = IOMUX_PAD(0x02FC, 0x009C, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA2__UART2_DTE_RX = IOMUX_PAD(0x02FC, 0x009C, 4, 0x05F0, 0, 0), + MX8MP_PAD_SD1_DATA2__GPIO2_IO04 = IOMUX_PAD(0x02FC, 0x009C, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA2__SIM_M_HBURST01 = IOMUX_PAD(0x02FC, 0x009C, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x0300, 0x00A0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA3__ENET1_RGMII_RD1 = IOMUX_PAD(0x0300, 0x00A0, 1, 0x0584, 0, 0), + MX8MP_PAD_SD1_DATA3__I2C4_SDA = IOMUX_PAD(0x0300, 0x00A0, 3 | IOMUX_CONFIG_SION, 0x05C0, 0, 0), + MX8MP_PAD_SD1_DATA3__UART2_DCE_RX = IOMUX_PAD(0x0300, 0x00A0, 4, 0x05F0, 1, 0), + MX8MP_PAD_SD1_DATA3__UART2_DTE_TX = IOMUX_PAD(0x0300, 0x00A0, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA3__GPIO2_IO05 = IOMUX_PAD(0x0300, 0x00A0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA3__SIM_M_HBURST02 = IOMUX_PAD(0x0300, 0x00A0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0304, 0x00A4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x0304, 0x00A4, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__I2C1_SCL = IOMUX_PAD(0x0304, 0x00A4, 3 | IOMUX_CONFIG_SION, 0x05A4, 0, 0), + MX8MP_PAD_SD1_DATA4__UART2_DCE_RTS = IOMUX_PAD(0x0304, 0x00A4, 4, 0x05EC, 0, 0), + MX8MP_PAD_SD1_DATA4__UART2_DTE_CTS = IOMUX_PAD(0x0304, 0x00A4, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__GPIO2_IO06 = IOMUX_PAD(0x0304, 0x00A4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__SIM_M_HRESP = IOMUX_PAD(0x0304, 0x00A4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0308, 0x00A8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__ENET1_TX_ER = IOMUX_PAD(0x0308, 0x00A8, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__I2C1_SDA = IOMUX_PAD(0x0308, 0x00A8, 3 | IOMUX_CONFIG_SION, 0x05A8, 0, 0), + MX8MP_PAD_SD1_DATA5__UART2_DCE_CTS = IOMUX_PAD(0x0308, 0x00A8, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__UART2_DTE_RTS = IOMUX_PAD(0x0308, 0x00A8, 4, 0x05EC, 1, 0), + MX8MP_PAD_SD1_DATA5__GPIO2_IO07 = IOMUX_PAD(0x0308, 0x00A8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__TPSMP_HDATA05 = IOMUX_PAD(0x0308, 0x00A8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x030C, 0x00AC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA6__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x030C, 0x00AC, 1, 0x0588, 0, 0), + MX8MP_PAD_SD1_DATA6__I2C2_SCL = IOMUX_PAD(0x030C, 0x00AC, 3 | IOMUX_CONFIG_SION, 0x05AC, 0, 0), + MX8MP_PAD_SD1_DATA6__UART3_DCE_TX = IOMUX_PAD(0x030C, 0x00AC, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA6__UART3_DTE_RX = IOMUX_PAD(0x030C, 0x00AC, 4, 0x05F8, 0, 0), + MX8MP_PAD_SD1_DATA6__GPIO2_IO08 = IOMUX_PAD(0x030C, 0x00AC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA6__TPSMP_HDATA06 = IOMUX_PAD(0x030C, 0x00AC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x0310, 0x00B0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA7__ENET1_RX_ER = IOMUX_PAD(0x0310, 0x00B0, 1, 0x058C, 0, 0), + MX8MP_PAD_SD1_DATA7__I2C2_SDA = IOMUX_PAD(0x0310, 0x00B0, 3 | IOMUX_CONFIG_SION, 0x05B0, 0, 0), + MX8MP_PAD_SD1_DATA7__UART3_DCE_RX = IOMUX_PAD(0x0310, 0x00B0, 4, 0x05F8, 1, 0), + MX8MP_PAD_SD1_DATA7__UART3_DTE_TX = IOMUX_PAD(0x0310, 0x00B0, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA7__GPIO2_IO09 = IOMUX_PAD(0x0310, 0x00B0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA7__TPSMP_HDATA07 = IOMUX_PAD(0x0310, 0x00B0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0314, 0x00B4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_RESET_B__ENET1_TX_CLK = IOMUX_PAD(0x0314, 0x00B4, 1, 0x0578, 0, 0), + MX8MP_PAD_SD1_RESET_B__I2C3_SCL = IOMUX_PAD(0x0314, 0x00B4, 3 | IOMUX_CONFIG_SION, 0x05B4, 0, 0), + MX8MP_PAD_SD1_RESET_B__UART3_DCE_RTS = IOMUX_PAD(0x0314, 0x00B4, 4, 0x05F4, 0, 0), + MX8MP_PAD_SD1_RESET_B__UART3_DTE_CTS = IOMUX_PAD(0x0314, 0x00B4, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0314, 0x00B4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_RESET_B__ECSPI3_TEST_TRIG = IOMUX_PAD(0x0314, 0x00B4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0318, 0x00B8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_STROBE__I2C3_SDA = IOMUX_PAD(0x0318, 0x00B8, 3 | IOMUX_CONFIG_SION, 0x05B8, 0, 0), + MX8MP_PAD_SD1_STROBE__UART3_DCE_CTS = IOMUX_PAD(0x0318, 0x00B8, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_STROBE__UART3_DTE_RTS = IOMUX_PAD(0x0318, 0x00B8, 4, 0x05F4, 1, 0), + MX8MP_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0318, 0x00B8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_STROBE__USDHC3_TEST_TRIG = IOMUX_PAD(0x0318, 0x00B8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x031C, 0x00BC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x031C, 0x00BC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK = IOMUX_PAD(0x031C, 0x00BC, 6, 0x0000, 0, 0), + + MX8MP_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x0320, 0x00C0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__ECSPI2_SCLK = IOMUX_PAD(0x0320, 0x00C0, 2, 0x0568, 0, 0), + MX8MP_PAD_SD2_CLK__UART4_DCE_RX = IOMUX_PAD(0x0320, 0x00C0, 3, 0x0600, 0, 0), + MX8MP_PAD_SD2_CLK__UART4_DTE_TX = IOMUX_PAD(0x0320, 0x00C0, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x0320, 0x00C0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 = IOMUX_PAD(0x0320, 0x00C0, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__OBSERVE_MUX_OUT00 = IOMUX_PAD(0x0320, 0x00C0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0324, 0x00C4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__ECSPI2_MOSI = IOMUX_PAD(0x0324, 0x00C4, 2, 0x0570, 0, 0), + MX8MP_PAD_SD2_CMD__UART4_DCE_TX = IOMUX_PAD(0x0324, 0x00C4, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__UART4_DTE_RX = IOMUX_PAD(0x0324, 0x00C4, 3, 0x0600, 1, 0), + MX8MP_PAD_SD2_CMD__AUDIOMIX_CLK = IOMUX_PAD(0x0324, 0x00C4, 4, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0324, 0x00C4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 = IOMUX_PAD(0x0324, 0x00C4, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__OBSERVE_MUX_OUT01 = IOMUX_PAD(0x0324, 0x00C4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0328, 0x00C8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0328, 0x00C8, 2 | IOMUX_CONFIG_SION, 0x05C0, 1, 0), + MX8MP_PAD_SD2_DATA0__UART2_DCE_RX = IOMUX_PAD(0x0328, 0x00C8, 3, 0x05F0, 2, 0), + MX8MP_PAD_SD2_DATA0__UART2_DTE_TX = IOMUX_PAD(0x0328, 0x00C8, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0328, 0x00C8, 4, 0x04C0, 1, 0), + MX8MP_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0328, 0x00C8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 = IOMUX_PAD(0x0328, 0x00C8, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__OBSERVE_MUX_OUT02 = IOMUX_PAD(0x0328, 0x00C8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x032C, 0x00CC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x032C, 0x00CC, 2 | IOMUX_CONFIG_SION, 0x05BC, 1, 0), + MX8MP_PAD_SD2_DATA1__UART2_DCE_TX = IOMUX_PAD(0x032C, 0x00CC, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__UART2_DTE_RX = IOMUX_PAD(0x032C, 0x00CC, 3, 0x05F0, 3, 0), + MX8MP_PAD_SD2_DATA1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x032C, 0x00CC, 4, 0x04C4, 1, 0), + MX8MP_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x032C, 0x00CC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x032C, 0x00CC, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__OBSERVE_MUX_OUT03 = IOMUX_PAD(0x032C, 0x00CC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x0330, 0x00D0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__ECSPI2_SS0 = IOMUX_PAD(0x0330, 0x00D0, 2, 0x0574, 0, 0), + MX8MP_PAD_SD2_DATA2__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0330, 0x00D0, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0330, 0x00D0, 4, 0x04C8, 1, 0), + MX8MP_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x0330, 0x00D0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0330, 0x00D0, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__OBSERVE_MUX_OUT04 = IOMUX_PAD(0x0330, 0x00D0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0334, 0x00D4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA3__ECSPI2_MISO = IOMUX_PAD(0x0334, 0x00D4, 2, 0x056C, 0, 0), + MX8MP_PAD_SD2_DATA3__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0334, 0x00D4, 3, 0x0544, 1, 0), + MX8MP_PAD_SD2_DATA3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0334, 0x00D4, 4, 0x04CC, 1, 0), + MX8MP_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0334, 0x00D4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET = IOMUX_PAD(0x0334, 0x00D4, 6, 0x0000, 0, 0), + + MX8MP_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0338, 0x00D8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0338, 0x00D8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET = IOMUX_PAD(0x0338, 0x00D8, 6, 0x0000, 0, 0), + + MX8MP_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x033C, 0x00DC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x033C, 0x00DC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_WP__CORESIGHT_EVENTI = IOMUX_PAD(0x033C, 0x00DC, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_WP__SIM_M_HMASTLOCK = IOMUX_PAD(0x033C, 0x00DC, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x0340, 0x00E0, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__FLEXSPI_A_SCLK = IOMUX_PAD(0x0340, 0x00E0, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK = IOMUX_PAD(0x0340, 0x00E0, 2, 0x04E8, 0, 0), + MX8MP_PAD_NAND_ALE__MEDIAMIX_ISP_FL_TRIG_0 = IOMUX_PAD(0x0340, 0x00E0, 3, 0x05D4, 1, 0), + MX8MP_PAD_NAND_ALE__UART3_DCE_RX = IOMUX_PAD(0x0340, 0x00E0, 4, 0x05F8, 2, 0), + MX8MP_PAD_NAND_ALE__UART3_DTE_TX = IOMUX_PAD(0x0340, 0x00E0, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__GPIO3_IO00 = IOMUX_PAD(0x0340, 0x00E0, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__CORESIGHT_TRACE_CLK = IOMUX_PAD(0x0340, 0x00E0, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__SIM_M_HPROT00 = IOMUX_PAD(0x0340, 0x00E0, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0344, 0x00E4, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__FLEXSPI_A_SS0_B = IOMUX_PAD(0x0344, 0x00E4, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 = IOMUX_PAD(0x0344, 0x00E4, 2, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__MEDIAMIX_ISP_SHUTTER_TRIG_0 = IOMUX_PAD(0x0344, 0x00E4, 3, 0x05DC, 1, 0), + MX8MP_PAD_NAND_CE0_B__UART3_DCE_TX = IOMUX_PAD(0x0344, 0x00E4, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__UART3_DTE_RX = IOMUX_PAD(0x0344, 0x00E4, 4, 0x05F8, 3, 0), + MX8MP_PAD_NAND_CE0_B__GPIO3_IO01 = IOMUX_PAD(0x0344, 0x00E4, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__CORESIGHT_TRACE_CTL = IOMUX_PAD(0x0344, 0x00E4, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__SIM_M_HPROT01 = IOMUX_PAD(0x0344, 0x00E4, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0348, 0x00E8, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__FLEXSPI_A_SS1_B = IOMUX_PAD(0x0348, 0x00E8, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE = IOMUX_PAD(0x0348, 0x00E8, 2, 0x0630, 1, 0), + MX8MP_PAD_NAND_CE1_B__I2C4_SCL = IOMUX_PAD(0x0348, 0x00E8, 4 | IOMUX_CONFIG_SION, 0x05BC, 2, 0), + MX8MP_PAD_NAND_CE1_B__GPIO3_IO02 = IOMUX_PAD(0x0348, 0x00E8, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__CORESIGHT_TRACE00 = IOMUX_PAD(0x0348, 0x00E8, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__SIM_M_HPROT02 = IOMUX_PAD(0x0348, 0x00E8, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x034C, 0x00EC, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__FLEXSPI_B_SS0_B = IOMUX_PAD(0x034C, 0x00EC, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 = IOMUX_PAD(0x034C, 0x00EC, 2, 0x0624, 1, 0), + MX8MP_PAD_NAND_CE2_B__I2C4_SDA = IOMUX_PAD(0x034C, 0x00EC, 4 | IOMUX_CONFIG_SION, 0x05C0, 2, 0), + MX8MP_PAD_NAND_CE2_B__GPIO3_IO03 = IOMUX_PAD(0x034C, 0x00EC, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__CORESIGHT_TRACE01 = IOMUX_PAD(0x034C, 0x00EC, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__SIM_M_HPROT03 = IOMUX_PAD(0x034C, 0x00EC, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x0350, 0x00F0, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__FLEXSPI_B_SS1_B = IOMUX_PAD(0x0350, 0x00F0, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 = IOMUX_PAD(0x0350, 0x00F0, 2, 0x0628, 1, 0), + MX8MP_PAD_NAND_CE3_B__I2C3_SDA = IOMUX_PAD(0x0350, 0x00F0, 4 | IOMUX_CONFIG_SION, 0x05B8, 1, 0), + MX8MP_PAD_NAND_CE3_B__GPIO3_IO04 = IOMUX_PAD(0x0350, 0x00F0, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__CORESIGHT_TRACE02 = IOMUX_PAD(0x0350, 0x00F0, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__SIM_M_HADDR00 = IOMUX_PAD(0x0350, 0x00F0, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0354, 0x00F4, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__FLEXSPI_B_SCLK = IOMUX_PAD(0x0354, 0x00F4, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__USDHC3_DATA7 = IOMUX_PAD(0x0354, 0x00F4, 2, 0x062C, 1, 0), + MX8MP_PAD_NAND_CLE__UART4_DCE_RX = IOMUX_PAD(0x0354, 0x00F4, 4, 0x0600, 2, 0), + MX8MP_PAD_NAND_CLE__UART4_DTE_TX = IOMUX_PAD(0x0354, 0x00F4, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__GPIO3_IO05 = IOMUX_PAD(0x0354, 0x00F4, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__CORESIGHT_TRACE03 = IOMUX_PAD(0x0354, 0x00F4, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__SIM_M_HADDR01 = IOMUX_PAD(0x0354, 0x00F4, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__FLEXSPI_A_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 2, 0x04E4, 0, 0), + MX8MP_PAD_NAND_DATA00__MEDIAMIX_ISP_FLASH_TRIG_0 = IOMUX_PAD(0x0358, 0x00F8, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__UART4_DCE_RX = IOMUX_PAD(0x0358, 0x00F8, 4, 0x0600, 3, 0), + MX8MP_PAD_NAND_DATA00__UART4_DTE_TX = IOMUX_PAD(0x0358, 0x00F8, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__GPIO3_IO06 = IOMUX_PAD(0x0358, 0x00F8, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__CORESIGHT_TRACE04 = IOMUX_PAD(0x0358, 0x00F8, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__SIM_M_HADDR02 = IOMUX_PAD(0x0358, 0x00F8, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x035C, 0x00FC, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__FLEXSPI_A_DATA01 = IOMUX_PAD(0x035C, 0x00FC, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC = IOMUX_PAD(0x035C, 0x00FC, 2, 0x04EC, 0, 0), + MX8MP_PAD_NAND_DATA01__MEDIAMIX_ISP_PRELIGHT_TRIG_0 = IOMUX_PAD(0x035C, 0x00FC, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__UART4_DCE_TX = IOMUX_PAD(0x035C, 0x00FC, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__UART4_DTE_RX = IOMUX_PAD(0x035C, 0x00FC, 4, 0x0600, 4, 0), + MX8MP_PAD_NAND_DATA01__GPIO3_IO07 = IOMUX_PAD(0x035C, 0x00FC, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__CORESIGHT_TRACE05 = IOMUX_PAD(0x035C, 0x00FC, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__SIM_M_HADDR03 = IOMUX_PAD(0x035C, 0x00FC, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x0360, 0x0100, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__FLEXSPI_A_DATA02 = IOMUX_PAD(0x0360, 0x0100, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__USDHC3_CD_B = IOMUX_PAD(0x0360, 0x0100, 2, 0x0608, 2, 0), + MX8MP_PAD_NAND_DATA02__UART4_DCE_CTS = IOMUX_PAD(0x0360, 0x0100, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__UART4_DTE_RTS = IOMUX_PAD(0x0360, 0x0100, 3, 0x05FC, 0, 0), + MX8MP_PAD_NAND_DATA02__I2C4_SDA = IOMUX_PAD(0x0360, 0x0100, 4 | IOMUX_CONFIG_SION, 0x05C0, 3, 0), + MX8MP_PAD_NAND_DATA02__GPIO3_IO08 = IOMUX_PAD(0x0360, 0x0100, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__CORESIGHT_TRACE06 = IOMUX_PAD(0x0360, 0x0100, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__SIM_M_HADDR04 = IOMUX_PAD(0x0360, 0x0100, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0364, 0x0104, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__FLEXSPI_A_DATA03 = IOMUX_PAD(0x0364, 0x0104, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__USDHC3_WP = IOMUX_PAD(0x0364, 0x0104, 2, 0x0634, 2, 0), + MX8MP_PAD_NAND_DATA03__UART4_DCE_RTS = IOMUX_PAD(0x0364, 0x0104, 3, 0x05FC, 1, 0), + MX8MP_PAD_NAND_DATA03__UART4_DTE_CTS = IOMUX_PAD(0x0364, 0x0104, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__MEDIAMIX_ISP_FL_TRIG_1 = IOMUX_PAD(0x0364, 0x0104, 4, 0x05D8, 1, 0), + MX8MP_PAD_NAND_DATA03__GPIO3_IO09 = IOMUX_PAD(0x0364, 0x0104, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__CORESIGHT_TRACE07 = IOMUX_PAD(0x0364, 0x0104, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__SIM_M_HADDR05 = IOMUX_PAD(0x0364, 0x0104, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0368, 0x0108, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__FLEXSPI_B_DATA00 = IOMUX_PAD(0x0368, 0x0108, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 = IOMUX_PAD(0x0368, 0x0108, 2, 0x0610, 1, 0), + MX8MP_PAD_NAND_DATA04__FLEXSPI_A_DATA04 = IOMUX_PAD(0x0368, 0x0108, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__MEDIAMIX_ISP_SHUTTER_TRIG_1 = IOMUX_PAD(0x0368, 0x0108, 4, 0x05E0, 1, 0), + MX8MP_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0368, 0x0108, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__CORESIGHT_TRACE08 = IOMUX_PAD(0x0368, 0x0108, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__SIM_M_HADDR06 = IOMUX_PAD(0x0368, 0x0108, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x036C, 0x010C, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__FLEXSPI_B_DATA01 = IOMUX_PAD(0x036C, 0x010C, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 = IOMUX_PAD(0x036C, 0x010C, 2, 0x0614, 1, 0), + MX8MP_PAD_NAND_DATA05__FLEXSPI_A_DATA05 = IOMUX_PAD(0x036C, 0x010C, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__MEDIAMIX_ISP_FLASH_TRIG_1 = IOMUX_PAD(0x036C, 0x010C, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x036C, 0x010C, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__CORESIGHT_TRACE09 = IOMUX_PAD(0x036C, 0x010C, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__SIM_M_HADDR07 = IOMUX_PAD(0x036C, 0x010C, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x0370, 0x0110, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__FLEXSPI_B_DATA02 = IOMUX_PAD(0x0370, 0x0110, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 = IOMUX_PAD(0x0370, 0x0110, 2, 0x0618, 1, 0), + MX8MP_PAD_NAND_DATA06__FLEXSPI_A_DATA06 = IOMUX_PAD(0x0370, 0x0110, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__MEDIAMIX_ISP_PRELIGHT_TRIG_1 = IOMUX_PAD(0x0370, 0x0110, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x0370, 0x0110, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__CORESIGHT_TRACE10 = IOMUX_PAD(0x0370, 0x0110, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__SIM_M_HADDR08 = IOMUX_PAD(0x0370, 0x0110, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0374, 0x0114, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__FLEXSPI_B_DATA03 = IOMUX_PAD(0x0374, 0x0114, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 = IOMUX_PAD(0x0374, 0x0114, 2, 0x061C, 1, 0), + MX8MP_PAD_NAND_DATA07__FLEXSPI_A_DATA07 = IOMUX_PAD(0x0374, 0x0114, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__MEDIAMIX_ISP_SHUTTER_OPEN_1 = IOMUX_PAD(0x0374, 0x0114, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0374, 0x0114, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__CORESIGHT_TRACE11 = IOMUX_PAD(0x0374, 0x0114, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__SIM_M_HADDR09 = IOMUX_PAD(0x0374, 0x0114, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0378, 0x0118, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__FLEXSPI_A_DQS = IOMUX_PAD(0x0378, 0x0118, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0378, 0x0118, 2, 0x04E0, 0, 0), + MX8MP_PAD_NAND_DQS__MEDIAMIX_ISP_SHUTTER_OPEN_0 = IOMUX_PAD(0x0378, 0x0118, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__I2C3_SCL = IOMUX_PAD(0x0378, 0x0118, 4 | IOMUX_CONFIG_SION, 0x05B4, 1, 0), + MX8MP_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0378, 0x0118, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__CORESIGHT_TRACE12 = IOMUX_PAD(0x0378, 0x0118, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__SIM_M_HADDR10 = IOMUX_PAD(0x0378, 0x0118, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x037C, 0x011C, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__FLEXSPI_B_DQS = IOMUX_PAD(0x037C, 0x011C, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 = IOMUX_PAD(0x037C, 0x011C, 2, 0x0620, 1, 0), + MX8MP_PAD_NAND_RE_B__UART4_DCE_TX = IOMUX_PAD(0x037C, 0x011C, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__UART4_DTE_RX = IOMUX_PAD(0x037C, 0x011C, 4, 0x0600, 5, 0), + MX8MP_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x037C, 0x011C, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__CORESIGHT_TRACE13 = IOMUX_PAD(0x037C, 0x011C, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__SIM_M_HADDR11 = IOMUX_PAD(0x037C, 0x011C, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x0380, 0x0120, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B = IOMUX_PAD(0x0380, 0x0120, 2, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__I2C3_SCL = IOMUX_PAD(0x0380, 0x0120, 4 | IOMUX_CONFIG_SION, 0x05B4, 2, 0), + MX8MP_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x0380, 0x0120, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__CORESIGHT_TRACE14 = IOMUX_PAD(0x0380, 0x0120, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__SIM_M_HADDR12 = IOMUX_PAD(0x0380, 0x0120, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x0384, 0x0124, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_WE_B__USDHC3_CLK = IOMUX_PAD(0x0384, 0x0124, 2, 0x0604, 1, 0), + MX8MP_PAD_NAND_WE_B__I2C3_SDA = IOMUX_PAD(0x0384, 0x0124, 4 | IOMUX_CONFIG_SION, 0x05B8, 2, 0), + MX8MP_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x0384, 0x0124, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_WE_B__CORESIGHT_TRACE15 = IOMUX_PAD(0x0384, 0x0124, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_WE_B__SIM_M_HADDR13 = IOMUX_PAD(0x0384, 0x0124, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x0388, 0x0128, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_WP_B__USDHC3_CMD = IOMUX_PAD(0x0388, 0x0128, 2, 0x060C, 1, 0), + MX8MP_PAD_NAND_WP_B__I2C4_SCL = IOMUX_PAD(0x0388, 0x0128, 4 | IOMUX_CONFIG_SION, 0x05BC, 3, 0), + MX8MP_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x0388, 0x0128, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_WP_B__CORESIGHT_EVENTO = IOMUX_PAD(0x0388, 0x0128, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_WP_B__SIM_M_HADDR14 = IOMUX_PAD(0x0388, 0x0128, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x038C, 0x012C, 0, 0x0508, 0, 0), + MX8MP_PAD_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 = IOMUX_PAD(0x038C, 0x012C, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXFS__PWM4_OUT = IOMUX_PAD(0x038C, 0x012C, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXFS__I2C6_SCL = IOMUX_PAD(0x038C, 0x012C, 3 | IOMUX_CONFIG_SION, 0x05CC, 1, 0), + MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x038C, 0x012C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK = IOMUX_PAD(0x0390, 0x0130, 0, 0x04F4, 0, 0), + MX8MP_PAD_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x0390, 0x0130, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXC__PWM3_OUT = IOMUX_PAD(0x0390, 0x0130, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXC__I2C6_SDA = IOMUX_PAD(0x0390, 0x0130, 3 | IOMUX_CONFIG_SION, 0x05D0, 1, 0), + MX8MP_PAD_SAI5_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x0390, 0x0130, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x0390, 0x0130, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 = IOMUX_PAD(0x0394, 0x0134, 0, 0x04F8, 0, 0), + MX8MP_PAD_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 = IOMUX_PAD(0x0394, 0x0134, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD0__PWM2_OUT = IOMUX_PAD(0x0394, 0x0134, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD0__I2C5_SCL = IOMUX_PAD(0x0394, 0x0134, 3 | IOMUX_CONFIG_SION, 0x05C4, 1, 0), + MX8MP_PAD_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0394, 0x0134, 4, 0x04C0, 2, 0), + MX8MP_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x0394, 0x0134, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 = IOMUX_PAD(0x0398, 0x0138, 0, 0x04FC, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 = IOMUX_PAD(0x0398, 0x0138, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x0398, 0x0138, 2, 0x04D8, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC = IOMUX_PAD(0x0398, 0x0138, 3, 0x0510, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0398, 0x0138, 4, 0x04C4, 2, 0), + MX8MP_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x0398, 0x0138, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD1__CAN1_TX = IOMUX_PAD(0x0398, 0x0138, 6, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 = IOMUX_PAD(0x039C, 0x013C, 0, 0x0500, 0, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 = IOMUX_PAD(0x039C, 0x013C, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x039C, 0x013C, 2, 0x04D8, 1, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x039C, 0x013C, 3, 0x050C, 0, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x039C, 0x013C, 4, 0x04C8, 2, 0), + MX8MP_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x039C, 0x013C, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD2__CAN1_RX = IOMUX_PAD(0x039C, 0x013C, 6, 0x054C, 0, 0), + + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 = IOMUX_PAD(0x03A0, 0x0140, 0, 0x0504, 0, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 = IOMUX_PAD(0x03A0, 0x0140, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x03A0, 0x0140, 2, 0x04D8, 2, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x03A0, 0x0140, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x03A0, 0x0140, 4, 0x04CC, 2, 0), + MX8MP_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03A0, 0x0140, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD3__CAN2_TX = IOMUX_PAD(0x03A0, 0x0140, 6, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x03A4, 0x0144, 0, 0x04F0, 0, 0), + MX8MP_PAD_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK = IOMUX_PAD(0x03A4, 0x0144, 1, 0x04D4, 0, 0), + MX8MP_PAD_SAI5_MCLK__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0144, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_MCLK__I2C5_SDA = IOMUX_PAD(0x03A4, 0x0144, 3 | IOMUX_CONFIG_SION, 0x05C8, 1, 0), + MX8MP_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03A4, 0x0144, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_MCLK__CAN2_RX = IOMUX_PAD(0x03A4, 0x0144, 6, 0x0550, 0, 0), + + MX8MP_PAD_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC = IOMUX_PAD(0x03A8, 0x0148, 0, 0x04D0, 0, 0), + MX8MP_PAD_SAI1_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0148, 1, 0x0508, 1, 0), + MX8MP_PAD_SAI1_RXFS__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x03A8, 0x0148, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXFS__GPIO4_IO00 = IOMUX_PAD(0x03A8, 0x0148, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK = IOMUX_PAD(0x03AC, 0x014C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXC__AUDIOMIX_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x014C, 1, 0x04F4, 1, 0), + MX8MP_PAD_SAI1_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x03AC, 0x014C, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXC__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x03AC, 0x014C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXC__GPIO4_IO01 = IOMUX_PAD(0x03AC, 0x014C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 = IOMUX_PAD(0x03B0, 0x0150, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00 = IOMUX_PAD(0x03B0, 0x0150, 1, 0x04F8, 1, 0), + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x03B0, 0x0150, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x03B0, 0x0150, 3, 0x04C0, 3, 0), + MX8MP_PAD_SAI1_RXD0__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x03B0, 0x0150, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 = IOMUX_PAD(0x03B0, 0x0150, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 = IOMUX_PAD(0x03B4, 0x0154, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01 = IOMUX_PAD(0x03B4, 0x0154, 1, 0x04FC, 1, 0), + MX8MP_PAD_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x03B4, 0x0154, 3, 0x04C4, 3, 0), + MX8MP_PAD_SAI1_RXD1__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x03B4, 0x0154, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD1__GPIO4_IO03 = IOMUX_PAD(0x03B4, 0x0154, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 = IOMUX_PAD(0x03B8, 0x0158, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02 = IOMUX_PAD(0x03B8, 0x0158, 1, 0x0500, 1, 0), + MX8MP_PAD_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x03B8, 0x0158, 3, 0x04C8, 3, 0), + MX8MP_PAD_SAI1_RXD2__ENET1_MDC = IOMUX_PAD(0x03B8, 0x0158, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD2__GPIO4_IO04 = IOMUX_PAD(0x03B8, 0x0158, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 = IOMUX_PAD(0x03BC, 0x015C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03 = IOMUX_PAD(0x03BC, 0x015C, 1, 0x0504, 1, 0), + MX8MP_PAD_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x03BC, 0x015C, 3, 0x04CC, 3, 0), + MX8MP_PAD_SAI1_RXD3__ENET1_MDIO = IOMUX_PAD(0x03BC, 0x015C, 4, 0x057C, 1, 0), + MX8MP_PAD_SAI1_RXD3__GPIO4_IO05 = IOMUX_PAD(0x03BC, 0x015C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 = IOMUX_PAD(0x03C0, 0x0160, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK = IOMUX_PAD(0x03C0, 0x0160, 1, 0x0524, 1, 0), + MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK = IOMUX_PAD(0x03C0, 0x0160, 2, 0x0518, 1, 0), + MX8MP_PAD_SAI1_RXD4__ENET1_RGMII_RD0 = IOMUX_PAD(0x03C0, 0x0160, 4, 0x0580, 1, 0), + MX8MP_PAD_SAI1_RXD4__GPIO4_IO06 = IOMUX_PAD(0x03C0, 0x0160, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 = IOMUX_PAD(0x03C4, 0x0164, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 = IOMUX_PAD(0x03C4, 0x0164, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 = IOMUX_PAD(0x03C4, 0x0164, 2, 0x051C, 1, 0), + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x0164, 3, 0x04D0, 1, 0), + MX8MP_PAD_SAI1_RXD5__ENET1_RGMII_RD1 = IOMUX_PAD(0x03C4, 0x0164, 4, 0x0584, 1, 0), + MX8MP_PAD_SAI1_RXD5__GPIO4_IO07 = IOMUX_PAD(0x03C4, 0x0164, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 = IOMUX_PAD(0x03C8, 0x0168, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC = IOMUX_PAD(0x03C8, 0x0168, 1, 0x0528, 1, 0), + MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC = IOMUX_PAD(0x03C8, 0x0168, 2, 0x0520, 1, 0), + MX8MP_PAD_SAI1_RXD6__ENET1_RGMII_RD2 = IOMUX_PAD(0x03C8, 0x0168, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD6__GPIO4_IO08 = IOMUX_PAD(0x03C8, 0x0168, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 = IOMUX_PAD(0x03CC, 0x016C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI6_MCLK = IOMUX_PAD(0x03CC, 0x016C, 1, 0x0514, 1, 0), + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x03CC, 0x016C, 2, 0x04D8, 3, 0), + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 = IOMUX_PAD(0x03CC, 0x016C, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD7__ENET1_RGMII_RD3 = IOMUX_PAD(0x03CC, 0x016C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD7__GPIO4_IO09 = IOMUX_PAD(0x03CC, 0x016C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x03D0, 0x0170, 0, 0x04D8, 4, 0), + MX8MP_PAD_SAI1_TXFS__AUDIOMIX_SAI5_TX_SYNC = IOMUX_PAD(0x03D0, 0x0170, 1, 0x0510, 1, 0), + MX8MP_PAD_SAI1_TXFS__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x03D0, 0x0170, 4, 0x0588, 1, 0), + MX8MP_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03D0, 0x0170, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK = IOMUX_PAD(0x03D4, 0x0174, 0, 0x04D4, 1, 0), + MX8MP_PAD_SAI1_TXC__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x03D4, 0x0174, 1, 0x050C, 1, 0), + MX8MP_PAD_SAI1_TXC__ENET1_RGMII_RXC = IOMUX_PAD(0x03D4, 0x0174, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03D4, 0x0174, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 = IOMUX_PAD(0x03D8, 0x0178, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD0__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x03D8, 0x0178, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x03D8, 0x0178, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03D8, 0x0178, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x03DC, 0x017C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD1__AUDIOMIX_SAI5_TX_DATA01 = IOMUX_PAD(0x03DC, 0x017C, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x03DC, 0x017C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03DC, 0x017C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 = IOMUX_PAD(0x03E0, 0x0180, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD2__AUDIOMIX_SAI5_TX_DATA02 = IOMUX_PAD(0x03E0, 0x0180, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x03E0, 0x0180, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03E0, 0x0180, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 = IOMUX_PAD(0x03E4, 0x0184, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD3__AUDIOMIX_SAI5_TX_DATA03 = IOMUX_PAD(0x03E4, 0x0184, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x03E4, 0x0184, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x03E4, 0x0184, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 = IOMUX_PAD(0x03E8, 0x0188, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK = IOMUX_PAD(0x03E8, 0x0188, 1, 0x0518, 2, 0), + MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK = IOMUX_PAD(0x03E8, 0x0188, 2, 0x0524, 2, 0), + MX8MP_PAD_SAI1_TXD4__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x03E8, 0x0188, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD4__GPIO4_IO16 = IOMUX_PAD(0x03E8, 0x0188, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 = IOMUX_PAD(0x03EC, 0x018C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 = IOMUX_PAD(0x03EC, 0x018C, 1, 0x051C, 2, 0), + MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 = IOMUX_PAD(0x03EC, 0x018C, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD5__ENET1_RGMII_TXC = IOMUX_PAD(0x03EC, 0x018C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD5__GPIO4_IO17 = IOMUX_PAD(0x03EC, 0x018C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 = IOMUX_PAD(0x03F0, 0x0190, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC = IOMUX_PAD(0x03F0, 0x0190, 1, 0x0520, 2, 0), + MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC = IOMUX_PAD(0x03F0, 0x0190, 2, 0x0528, 2, 0), + MX8MP_PAD_SAI1_TXD6__ENET1_RX_ER = IOMUX_PAD(0x03F0, 0x0190, 4, 0x058C, 1, 0), + MX8MP_PAD_SAI1_TXD6__GPIO4_IO18 = IOMUX_PAD(0x03F0, 0x0190, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 = IOMUX_PAD(0x03F4, 0x0194, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD7__AUDIOMIX_SAI6_MCLK = IOMUX_PAD(0x03F4, 0x0194, 1, 0x0514, 2, 0), + MX8MP_PAD_SAI1_TXD7__AUDIOMIX_CLK = IOMUX_PAD(0x03F4, 0x0194, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD7__ENET1_TX_ER = IOMUX_PAD(0x03F4, 0x0194, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x03F4, 0x0194, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI1_MCLK = IOMUX_PAD(0x03F8, 0x0198, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x03F8, 0x0198, 1, 0x04F0, 1, 0), + MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK = IOMUX_PAD(0x03F8, 0x0198, 2, 0x04D4, 2, 0), + MX8MP_PAD_SAI1_MCLK__ENET1_TX_CLK = IOMUX_PAD(0x03F8, 0x0198, 4, 0x0578, 1, 0), + MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x03F8, 0x0198, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC = IOMUX_PAD(0x03FC, 0x019C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC = IOMUX_PAD(0x03FC, 0x019C, 1, 0x0510, 2, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 = IOMUX_PAD(0x03FC, 0x019C, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 = IOMUX_PAD(0x03FC, 0x019C, 3, 0x04DC, 0, 0), + MX8MP_PAD_SAI2_RXFS__UART1_DCE_TX = IOMUX_PAD(0x03FC, 0x019C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__UART1_DTE_RX = IOMUX_PAD(0x03FC, 0x019C, 4, 0x05E8, 2, 0), + MX8MP_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x03FC, 0x019C, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x03FC, 0x019C, 6, 0x04C8, 4, 0), + MX8MP_PAD_SAI2_RXFS__SIM_M_HSIZE00 = IOMUX_PAD(0x03FC, 0x019C, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK = IOMUX_PAD(0x0400, 0x01A0, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x0400, 0x01A0, 1, 0x050C, 2, 0), + MX8MP_PAD_SAI2_RXC__CAN1_TX = IOMUX_PAD(0x0400, 0x01A0, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__UART1_DCE_RX = IOMUX_PAD(0x0400, 0x01A0, 4, 0x05E8, 3, 0), + MX8MP_PAD_SAI2_RXC__UART1_DTE_TX = IOMUX_PAD(0x0400, 0x01A0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x0400, 0x01A0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0400, 0x01A0, 6, 0x04C4, 4, 0), + MX8MP_PAD_SAI2_RXC__SIM_M_HSIZE01 = IOMUX_PAD(0x0400, 0x01A0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 = IOMUX_PAD(0x0404, 0x01A4, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x0404, 0x01A4, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT = IOMUX_PAD(0x0404, 0x01A4, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 = IOMUX_PAD(0x0404, 0x01A4, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__UART1_DCE_RTS = IOMUX_PAD(0x0404, 0x01A4, 4, 0x05E4, 2, 0), + MX8MP_PAD_SAI2_RXD0__UART1_DTE_CTS = IOMUX_PAD(0x0404, 0x01A4, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0404, 0x01A4, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0404, 0x01A4, 6, 0x04CC, 4, 0), + MX8MP_PAD_SAI2_RXD0__SIM_M_HSIZE02 = IOMUX_PAD(0x0404, 0x01A4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC = IOMUX_PAD(0x0408, 0x01A8, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 = IOMUX_PAD(0x0408, 0x01A8, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT = IOMUX_PAD(0x0408, 0x01A8, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 = IOMUX_PAD(0x0408, 0x01A8, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__UART1_DCE_CTS = IOMUX_PAD(0x0408, 0x01A8, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__UART1_DTE_RTS = IOMUX_PAD(0x0408, 0x01A8, 4, 0x05E4, 3, 0), + MX8MP_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0408, 0x01A8, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0408, 0x01A8, 6, 0x04C8, 5, 0), + MX8MP_PAD_SAI2_TXFS__SIM_M_HWRITE = IOMUX_PAD(0x0408, 0x01A8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK = IOMUX_PAD(0x040C, 0x01AC, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 = IOMUX_PAD(0x040C, 0x01AC, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXC__CAN1_RX = IOMUX_PAD(0x040C, 0x01AC, 3, 0x054C, 1, 0), + MX8MP_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x040C, 0x01AC, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXC__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x040C, 0x01AC, 6, 0x04C4, 5, 0), + MX8MP_PAD_SAI2_TXC__SIM_M_HREADYOUT = IOMUX_PAD(0x040C, 0x01AC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 = IOMUX_PAD(0x0410, 0x01B0, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 = IOMUX_PAD(0x0410, 0x01B0, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN = IOMUX_PAD(0x0410, 0x01B0, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__CAN2_TX = IOMUX_PAD(0x0410, 0x01B0, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN = IOMUX_PAD(0x0410, 0x01B0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x0410, 0x01B0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE04 = IOMUX_PAD(0x0410, 0x01B0, 6, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__TPSMP_CLK = IOMUX_PAD(0x0410, 0x01B0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI2_MCLK = IOMUX_PAD(0x0414, 0x01B4, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01B4, 1, 0x04F0, 2, 0), + MX8MP_PAD_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN = IOMUX_PAD(0x0414, 0x01B4, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__CAN2_RX = IOMUX_PAD(0x0414, 0x01B4, 3, 0x0550, 1, 0), + MX8MP_PAD_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN = IOMUX_PAD(0x0414, 0x01B4, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0414, 0x01B4, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0414, 0x01B4, 6, 0x04E0, 1, 0), + MX8MP_PAD_SAI2_MCLK__TPSMP_HDATA_DIR = IOMUX_PAD(0x0414, 0x01B4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC = IOMUX_PAD(0x0418, 0x01B8, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 = IOMUX_PAD(0x0418, 0x01B8, 1, 0x04DC, 1, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x0418, 0x01B8, 2, 0x0508, 2, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 = IOMUX_PAD(0x0418, 0x01B8, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0418, 0x01B8, 4, 0x0544, 2, 0), + MX8MP_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0418, 0x01B8, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0418, 0x01B8, 6, 0x04C0, 4, 0), + MX8MP_PAD_SAI3_RXFS__TPSMP_HTRANS00 = IOMUX_PAD(0x0418, 0x01B8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK = IOMUX_PAD(0x041C, 0x01BC, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 = IOMUX_PAD(0x041C, 0x01BC, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK = IOMUX_PAD(0x041C, 0x01BC, 2, 0x04F4, 2, 0), + MX8MP_PAD_SAI3_RXC__GPT1_CLK = IOMUX_PAD(0x041C, 0x01BC, 3, 0x059C, 0, 0), + MX8MP_PAD_SAI3_RXC__UART2_DCE_CTS = IOMUX_PAD(0x041C, 0x01BC, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__UART2_DTE_RTS = IOMUX_PAD(0x041C, 0x01BC, 4, 0x05EC, 2, 0), + MX8MP_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x041C, 0x01BC, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x041C, 0x01BC, 6, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__TPSMP_HTRANS01 = IOMUX_PAD(0x041C, 0x01BC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 = IOMUX_PAD(0x0420, 0x01C0, 0, 0x04E4, 1, 0), + MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 = IOMUX_PAD(0x0420, 0x01C0, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 = IOMUX_PAD(0x0420, 0x01C0, 2, 0x04F8, 2, 0), + MX8MP_PAD_SAI3_RXD__UART2_DCE_RTS = IOMUX_PAD(0x0420, 0x01C0, 4, 0x05EC, 3, 0), + MX8MP_PAD_SAI3_RXD__UART2_DTE_CTS = IOMUX_PAD(0x0420, 0x01C0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x0420, 0x01C0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXD__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0420, 0x01C0, 6, 0x04C4, 6, 0), + MX8MP_PAD_SAI3_RXD__TPSMP_HDATA00 = IOMUX_PAD(0x0420, 0x01C0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC = IOMUX_PAD(0x0424, 0x01C4, 0, 0x04EC, 1, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 = IOMUX_PAD(0x0424, 0x01C4, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 = IOMUX_PAD(0x0424, 0x01C4, 2, 0x04FC, 2, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 = IOMUX_PAD(0x0424, 0x01C4, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__UART2_DCE_RX = IOMUX_PAD(0x0424, 0x01C4, 4, 0x05F0, 4, 0), + MX8MP_PAD_SAI3_TXFS__UART2_DTE_TX = IOMUX_PAD(0x0424, 0x01C4, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0424, 0x01C4, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0424, 0x01C4, 6, 0x04CC, 5, 0), + MX8MP_PAD_SAI3_TXFS__TPSMP_HDATA01 = IOMUX_PAD(0x0424, 0x01C4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK = IOMUX_PAD(0x0428, 0x01C8, 0, 0x04E8, 1, 0), + MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 = IOMUX_PAD(0x0428, 0x01C8, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 = IOMUX_PAD(0x0428, 0x01C8, 2, 0x0500, 2, 0), + MX8MP_PAD_SAI3_TXC__GPT1_CAPTURE1 = IOMUX_PAD(0x0428, 0x01C8, 3, 0x0594, 0, 0), + MX8MP_PAD_SAI3_TXC__UART2_DCE_TX = IOMUX_PAD(0x0428, 0x01C8, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXC__UART2_DTE_RX = IOMUX_PAD(0x0428, 0x01C8, 4, 0x05F0, 5, 0), + MX8MP_PAD_SAI3_TXC__GPIO5_IO00 = IOMUX_PAD(0x0428, 0x01C8, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXC__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0428, 0x01C8, 6, 0x04C8, 6, 0), + MX8MP_PAD_SAI3_TXC__TPSMP_HDATA02 = IOMUX_PAD(0x0428, 0x01C8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 = IOMUX_PAD(0x042C, 0x01CC, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 = IOMUX_PAD(0x042C, 0x01CC, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 = IOMUX_PAD(0x042C, 0x01CC, 2, 0x0504, 2, 0), + MX8MP_PAD_SAI3_TXD__GPT1_CAPTURE2 = IOMUX_PAD(0x042C, 0x01CC, 3, 0x0598, 0, 0), + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SPDIF_EXT_CLK = IOMUX_PAD(0x042C, 0x01CC, 4, 0x0548, 0, 0), + MX8MP_PAD_SAI3_TXD__GPIO5_IO01 = IOMUX_PAD(0x042C, 0x01CC, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE05 = IOMUX_PAD(0x042C, 0x01CC, 6, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__TPSMP_HDATA03 = IOMUX_PAD(0x042C, 0x01CC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0430, 0x01D0, 0, 0x04E0, 2, 0), + MX8MP_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x0430, 0x01D0, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01D0, 2, 0x04F0, 3, 0), + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0430, 0x01D0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_MCLK__GPIO5_IO02 = IOMUX_PAD(0x0430, 0x01D0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0430, 0x01D0, 6, 0x0544, 3, 0), + MX8MP_PAD_SAI3_MCLK__TPSMP_HDATA04 = IOMUX_PAD(0x0430, 0x01D0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SPDIF_TX__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0434, 0x01D4, 0, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0434, 0x01D4, 1, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__I2C5_SCL = IOMUX_PAD(0x0434, 0x01D4, 2 | IOMUX_CONFIG_SION, 0x05C4, 2, 0), + MX8MP_PAD_SPDIF_TX__GPT1_COMPARE1 = IOMUX_PAD(0x0434, 0x01D4, 3, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__CAN1_TX = IOMUX_PAD(0x0434, 0x01D4, 4, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__GPIO5_IO03 = IOMUX_PAD(0x0434, 0x01D4, 5, 0x0000, 0, 0), + + MX8MP_PAD_SPDIF_RX__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0438, 0x01D8, 0, 0x0544, 4, 0), + MX8MP_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0438, 0x01D8, 1, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_RX__I2C5_SDA = IOMUX_PAD(0x0438, 0x01D8, 2 | IOMUX_CONFIG_SION, 0x05C8, 2, 0), + MX8MP_PAD_SPDIF_RX__GPT1_COMPARE2 = IOMUX_PAD(0x0438, 0x01D8, 3, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_RX__CAN1_RX = IOMUX_PAD(0x0438, 0x01D8, 4, 0x054C, 2, 0), + MX8MP_PAD_SPDIF_RX__GPIO5_IO04 = IOMUX_PAD(0x0438, 0x01D8, 5, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_EXT_CLK__GPT1_COMPARE3 = IOMUX_PAD(0x043C, 0x01DC, 3, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_EXT_CLK__GPIO5_IO05 = IOMUX_PAD(0x043C, 0x01DC, 5, 0x0000, 0, 0), + + MX8MP_PAD_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK = IOMUX_PAD(0x043C, 0x01DC, 0, 0x0548, 1, 0), + MX8MP_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x043C, 0x01DC, 1, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x0440, 0x01E0, 0, 0x0558, 0, 0), + MX8MP_PAD_ECSPI1_SCLK__UART3_DCE_RX = IOMUX_PAD(0x0440, 0x01E0, 1, 0x05F8, 4, 0), + MX8MP_PAD_ECSPI1_SCLK__UART3_DTE_TX = IOMUX_PAD(0x0440, 0x01E0, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SCLK__I2C1_SCL = IOMUX_PAD(0x0440, 0x01E0, 2 | IOMUX_CONFIG_SION, 0x05A4, 1, 0), + MX8MP_PAD_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC = IOMUX_PAD(0x0440, 0x01E0, 3, 0x0538, 1, 0), + MX8MP_PAD_ECSPI1_SCLK__GPIO5_IO06 = IOMUX_PAD(0x0440, 0x01E0, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SCLK__TPSMP_HDATA08 = IOMUX_PAD(0x0440, 0x01E0, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0444, 0x01E4, 0, 0x0560, 0, 0), + MX8MP_PAD_ECSPI1_MOSI__UART3_DCE_TX = IOMUX_PAD(0x0444, 0x01E4, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MOSI__UART3_DTE_RX = IOMUX_PAD(0x0444, 0x01E4, 1, 0x05F8, 5, 0), + MX8MP_PAD_ECSPI1_MOSI__I2C1_SDA = IOMUX_PAD(0x0444, 0x01E4, 2 | IOMUX_CONFIG_SION, 0x05A8, 1, 0), + MX8MP_PAD_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK = IOMUX_PAD(0x0444, 0x01E4, 3, 0x0530, 1, 0), + MX8MP_PAD_ECSPI1_MOSI__GPIO5_IO07 = IOMUX_PAD(0x0444, 0x01E4, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MOSI__TPSMP_HDATA09 = IOMUX_PAD(0x0444, 0x01E4, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0448, 0x01E8, 0, 0x055C, 0, 0), + MX8MP_PAD_ECSPI1_MISO__UART3_DCE_CTS = IOMUX_PAD(0x0448, 0x01E8, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MISO__UART3_DTE_RTS = IOMUX_PAD(0x0448, 0x01E8, 1, 0x05F4, 2, 0), + MX8MP_PAD_ECSPI1_MISO__I2C2_SCL = IOMUX_PAD(0x0448, 0x01E8, 2 | IOMUX_CONFIG_SION, 0x05AC, 1, 0), + MX8MP_PAD_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 = IOMUX_PAD(0x0448, 0x01E8, 3, 0x0534, 1, 0), + MX8MP_PAD_ECSPI1_MISO__GPIO5_IO08 = IOMUX_PAD(0x0448, 0x01E8, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MISO__TPSMP_HDATA10 = IOMUX_PAD(0x0448, 0x01E8, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x044C, 0x01EC, 0, 0x0564, 0, 0), + MX8MP_PAD_ECSPI1_SS0__UART3_DCE_RTS = IOMUX_PAD(0x044C, 0x01EC, 1, 0x05F4, 3, 0), + MX8MP_PAD_ECSPI1_SS0__UART3_DTE_CTS = IOMUX_PAD(0x044C, 0x01EC, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SS0__I2C2_SDA = IOMUX_PAD(0x044C, 0x01EC, 2 | IOMUX_CONFIG_SION, 0x05B0, 1, 0), + MX8MP_PAD_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC = IOMUX_PAD(0x044C, 0x01EC, 3, 0x0540, 1, 0), + MX8MP_PAD_ECSPI1_SS0__GPIO5_IO09 = IOMUX_PAD(0x044C, 0x01EC, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SS0__TPSMP_HDATA11 = IOMUX_PAD(0x044C, 0x01EC, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x0450, 0x01F0, 0, 0x0568, 1, 0), + MX8MP_PAD_ECSPI2_SCLK__UART4_DCE_RX = IOMUX_PAD(0x0450, 0x01F0, 1, 0x0600, 6, 0), + MX8MP_PAD_ECSPI2_SCLK__UART4_DTE_TX = IOMUX_PAD(0x0450, 0x01F0, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SCLK__I2C3_SCL = IOMUX_PAD(0x0450, 0x01F0, 2 | IOMUX_CONFIG_SION, 0x05B4, 3, 0), + MX8MP_PAD_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK = IOMUX_PAD(0x0450, 0x01F0, 3, 0x053C, 1, 0), + MX8MP_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x0450, 0x01F0, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SCLK__TPSMP_HDATA12 = IOMUX_PAD(0x0450, 0x01F0, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0454, 0x01F4, 0, 0x0570, 1, 0), + MX8MP_PAD_ECSPI2_MOSI__UART4_DCE_TX = IOMUX_PAD(0x0454, 0x01F4, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MOSI__UART4_DTE_RX = IOMUX_PAD(0x0454, 0x01F4, 1, 0x0600, 7, 0), + MX8MP_PAD_ECSPI2_MOSI__I2C3_SDA = IOMUX_PAD(0x0454, 0x01F4, 2 | IOMUX_CONFIG_SION, 0x05B8, 3, 0), + MX8MP_PAD_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 = IOMUX_PAD(0x0454, 0x01F4, 3, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0454, 0x01F4, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MOSI__TPSMP_HDATA13 = IOMUX_PAD(0x0454, 0x01F4, 7, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0458, 0x01F8, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MISO__TPSMP_HDATA14 = IOMUX_PAD(0x0458, 0x01F8, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0458, 0x01F8, 0, 0x056C, 1, 0), + MX8MP_PAD_ECSPI2_MISO__UART4_DCE_CTS = IOMUX_PAD(0x0458, 0x01F8, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MISO__UART4_DTE_RTS = IOMUX_PAD(0x0458, 0x01F8, 1, 0x05FC, 2, 0), + MX8MP_PAD_ECSPI2_MISO__I2C4_SCL = IOMUX_PAD(0x0458, 0x01F8, 2 | IOMUX_CONFIG_SION, 0x05BC, 4, 0), + MX8MP_PAD_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK = IOMUX_PAD(0x0458, 0x01F8, 3, 0x052C, 1, 0), + MX8MP_PAD_ECSPI2_MISO__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x0458, 0x01F8, 4, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x045C, 0x01FC, 0, 0x0574, 1, 0), + MX8MP_PAD_ECSPI2_SS0__UART4_DCE_RTS = IOMUX_PAD(0x045C, 0x01FC, 1, 0x05FC, 3, 0), + MX8MP_PAD_ECSPI2_SS0__UART4_DTE_CTS = IOMUX_PAD(0x045C, 0x01FC, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SS0__I2C4_SDA = IOMUX_PAD(0x045C, 0x01FC, 2 | IOMUX_CONFIG_SION, 0x05C0, 4, 0), + MX8MP_PAD_ECSPI2_SS0__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x045C, 0x01FC, 4, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x045C, 0x01FC, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SS0__TPSMP_HDATA15 = IOMUX_PAD(0x045C, 0x01FC, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x0460, 0x0200, 0 | IOMUX_CONFIG_SION, 0x05A4, 2, 0), + MX8MP_PAD_I2C1_SCL__ENET_QOS_MDC = IOMUX_PAD(0x0460, 0x0200, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C1_SCL__ECSPI1_SCLK = IOMUX_PAD(0x0460, 0x0200, 3, 0x0558, 1, 0), + MX8MP_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x0460, 0x0200, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C1_SCL__TPSMP_HDATA16 = IOMUX_PAD(0x0460, 0x0200, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0464, 0x0204, 0 | IOMUX_CONFIG_SION, 0x05A8, 2, 0), + MX8MP_PAD_I2C1_SDA__ENET_QOS_MDIO = IOMUX_PAD(0x0464, 0x0204, 1, 0x0590, 2, 0), + MX8MP_PAD_I2C1_SDA__ECSPI1_MOSI = IOMUX_PAD(0x0464, 0x0204, 3, 0x0560, 1, 0), + MX8MP_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0464, 0x0204, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C1_SDA__TPSMP_HDATA17 = IOMUX_PAD(0x0464, 0x0204, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0468, 0x0208, 0 | IOMUX_CONFIG_SION, 0x05AC, 2, 0), + MX8MP_PAD_I2C2_SCL__ENET_QOS_1588_EVENT1_IN = IOMUX_PAD(0x0468, 0x0208, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SCL__USDHC3_CD_B = IOMUX_PAD(0x0468, 0x0208, 2, 0x0608, 3, 0), + MX8MP_PAD_I2C2_SCL__ECSPI1_MISO = IOMUX_PAD(0x0468, 0x0208, 3, 0x055C, 1, 0), + MX8MP_PAD_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN = IOMUX_PAD(0x0468, 0x0208, 4, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0468, 0x0208, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SCL__TPSMP_HDATA18 = IOMUX_PAD(0x0468, 0x0208, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x046C, 0x020C, 0 | IOMUX_CONFIG_SION, 0x05B0, 2, 0), + MX8MP_PAD_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT = IOMUX_PAD(0x046C, 0x020C, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SDA__USDHC3_WP = IOMUX_PAD(0x046C, 0x020C, 2, 0x0634, 3, 0), + MX8MP_PAD_I2C2_SDA__ECSPI1_SS0 = IOMUX_PAD(0x046C, 0x020C, 3, 0x0564, 1, 0), + MX8MP_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x046C, 0x020C, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SDA__TPSMP_HDATA19 = IOMUX_PAD(0x046C, 0x020C, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x0470, 0x0210, 0 | IOMUX_CONFIG_SION, 0x05B4, 4, 0), + MX8MP_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x0470, 0x0210, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x0470, 0x0210, 2, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SCL__ECSPI2_SCLK = IOMUX_PAD(0x0470, 0x0210, 3, 0x0568, 2, 0), + MX8MP_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x0470, 0x0210, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SCL__TPSMP_HDATA20 = IOMUX_PAD(0x0470, 0x0210, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0474, 0x0214, 0 | IOMUX_CONFIG_SION, 0x05B8, 4, 0), + MX8MP_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0474, 0x0214, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0474, 0x0214, 2, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SDA__ECSPI2_MOSI = IOMUX_PAD(0x0474, 0x0214, 3, 0x0570, 2, 0), + MX8MP_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0474, 0x0214, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SDA__TPSMP_HDATA21 = IOMUX_PAD(0x0474, 0x0214, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0478, 0x0218, 0 | IOMUX_CONFIG_SION, 0x05BC, 5, 0), + MX8MP_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0478, 0x0218, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B = IOMUX_PAD(0x0478, 0x0218, 2, 0x05A0, 0, 0), + MX8MP_PAD_I2C4_SCL__ECSPI2_MISO = IOMUX_PAD(0x0478, 0x0218, 3, 0x056C, 2, 0), + MX8MP_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0478, 0x0218, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SCL__TPSMP_HDATA22 = IOMUX_PAD(0x0478, 0x0218, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x047C, 0x021C, 0 | IOMUX_CONFIG_SION, 0x05C0, 5, 0), + MX8MP_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x047C, 0x021C, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SDA__ECSPI2_SS0 = IOMUX_PAD(0x047C, 0x021C, 3, 0x0574, 2, 0), + MX8MP_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x047C, 0x021C, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SDA__TPSMP_HDATA23 = IOMUX_PAD(0x047C, 0x021C, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART1_RXD__UART1_DCE_RX = IOMUX_PAD(0x0480, 0x0220, 0, 0x05E8, 4, 0), + + MX8MP_PAD_UART1_RXD__UART1_DTE_TX = IOMUX_PAD(0x0480, 0x0220, 0, 0x0000, 0, 0), + MX8MP_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x0480, 0x0220, 1, 0x0000, 0, 0), + MX8MP_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x0480, 0x0220, 5, 0x0000, 0, 0), + MX8MP_PAD_UART1_RXD__TPSMP_HDATA24 = IOMUX_PAD(0x0480, 0x0220, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART1_TXD__UART1_DCE_TX = IOMUX_PAD(0x0484, 0x0224, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART1_TXD__UART1_DTE_RX = IOMUX_PAD(0x0484, 0x0224, 0, 0x05E8, 5, 0), + MX8MP_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x0484, 0x0224, 1, 0x0000, 0, 0), + MX8MP_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x0484, 0x0224, 5, 0x0000, 0, 0), + MX8MP_PAD_UART1_TXD__TPSMP_HDATA25 = IOMUX_PAD(0x0484, 0x0224, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART2_RXD__UART2_DCE_RX = IOMUX_PAD(0x0488, 0x0228, 0, 0x05F0, 6, 0), + + MX8MP_PAD_UART2_RXD__UART2_DTE_TX = IOMUX_PAD(0x0488, 0x0228, 0, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x0488, 0x0228, 1, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__GPT1_COMPARE3 = IOMUX_PAD(0x0488, 0x0228, 3, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x0488, 0x0228, 5, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__TPSMP_HDATA26 = IOMUX_PAD(0x0488, 0x0228, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART2_TXD__UART2_DCE_TX = IOMUX_PAD(0x048C, 0x022C, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART2_TXD__UART2_DTE_RX = IOMUX_PAD(0x048C, 0x022C, 0, 0x05F0, 7, 0), + MX8MP_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x048C, 0x022C, 1, 0x0000, 0, 0), + MX8MP_PAD_UART2_TXD__GPT1_COMPARE2 = IOMUX_PAD(0x048C, 0x022C, 3, 0x0000, 0, 0), + MX8MP_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x048C, 0x022C, 5, 0x0000, 0, 0), + MX8MP_PAD_UART2_TXD__TPSMP_HDATA27 = IOMUX_PAD(0x048C, 0x022C, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART3_RXD__UART3_DCE_RX = IOMUX_PAD(0x0490, 0x0230, 0, 0x05F8, 6, 0), + + MX8MP_PAD_UART3_RXD__UART3_DTE_TX = IOMUX_PAD(0x0490, 0x0230, 0, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__UART1_DCE_CTS = IOMUX_PAD(0x0490, 0x0230, 1, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__UART1_DTE_RTS = IOMUX_PAD(0x0490, 0x0230, 1, 0x05E4, 4, 0), + MX8MP_PAD_UART3_RXD__USDHC3_RESET_B = IOMUX_PAD(0x0490, 0x0230, 2, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__GPT1_CAPTURE2 = IOMUX_PAD(0x0490, 0x0230, 3, 0x0598, 1, 0), + MX8MP_PAD_UART3_RXD__CAN2_TX = IOMUX_PAD(0x0490, 0x0230, 4, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x0490, 0x0230, 5, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__TPSMP_HDATA28 = IOMUX_PAD(0x0490, 0x0230, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART3_TXD__UART3_DCE_TX = IOMUX_PAD(0x0494, 0x0234, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART3_TXD__UART3_DTE_RX = IOMUX_PAD(0x0494, 0x0234, 0, 0x05F8, 7, 0), + MX8MP_PAD_UART3_TXD__UART1_DCE_RTS = IOMUX_PAD(0x0494, 0x0234, 1, 0x05E4, 5, 0), + MX8MP_PAD_UART3_TXD__UART1_DTE_CTS = IOMUX_PAD(0x0494, 0x0234, 1, 0x0000, 0, 0), + MX8MP_PAD_UART3_TXD__USDHC3_VSELECT = IOMUX_PAD(0x0494, 0x0234, 2, 0x0000, 0, 0), + MX8MP_PAD_UART3_TXD__GPT1_CLK = IOMUX_PAD(0x0494, 0x0234, 3, 0x059C, 1, 0), + MX8MP_PAD_UART3_TXD__CAN2_RX = IOMUX_PAD(0x0494, 0x0234, 4, 0x0550, 2, 0), + MX8MP_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x0494, 0x0234, 5, 0x0000, 0, 0), + MX8MP_PAD_UART3_TXD__TPSMP_HDATA29 = IOMUX_PAD(0x0494, 0x0234, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART4_RXD__UART4_DCE_RX = IOMUX_PAD(0x0498, 0x0238, 0, 0x0600, 8, 0), + + MX8MP_PAD_UART4_RXD__UART4_DTE_TX = IOMUX_PAD(0x0498, 0x0238, 0, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__UART2_DCE_CTS = IOMUX_PAD(0x0498, 0x0238, 1, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__UART2_DTE_RTS = IOMUX_PAD(0x0498, 0x0238, 1, 0x05EC, 4, 0), + MX8MP_PAD_UART4_RXD__HSIOMIX_PCIE_CLKREQ_B = IOMUX_PAD(0x0498, 0x0238, 2, 0x05A0, 1, 0), + MX8MP_PAD_UART4_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x0498, 0x0238, 3, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__I2C6_SCL = IOMUX_PAD(0x0498, 0x0238, 4 | IOMUX_CONFIG_SION, 0x05CC, 2, 0), + MX8MP_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x0498, 0x0238, 5, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__TPSMP_HDATA30 = IOMUX_PAD(0x0498, 0x0238, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART4_TXD__UART4_DCE_TX = IOMUX_PAD(0x049C, 0x023C, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART4_TXD__UART4_DTE_RX = IOMUX_PAD(0x049C, 0x023C, 0, 0x0600, 9, 0), + MX8MP_PAD_UART4_TXD__UART2_DCE_RTS = IOMUX_PAD(0x049C, 0x023C, 1, 0x05EC, 5, 0), + MX8MP_PAD_UART4_TXD__UART2_DTE_CTS = IOMUX_PAD(0x049C, 0x023C, 1, 0x0000, 0, 0), + MX8MP_PAD_UART4_TXD__GPT1_CAPTURE1 = IOMUX_PAD(0x049C, 0x023C, 3, 0x0594, 1, 0), + MX8MP_PAD_UART4_TXD__I2C6_SDA = IOMUX_PAD(0x049C, 0x023C, 4 | IOMUX_CONFIG_SION, 0x05D0, 2, 0), + MX8MP_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x049C, 0x023C, 5, 0x0000, 0, 0), + MX8MP_PAD_UART4_TXD__TPSMP_HDATA31 = IOMUX_PAD(0x049C, 0x023C, 7, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_DDC_SCL__HDMIMIX_EARC_SCL = IOMUX_PAD(0x04A0, 0x0240, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SCL__I2C5_SCL = IOMUX_PAD(0x04A0, 0x0240, 3 | IOMUX_CONFIG_SION, 0x05C4, 3, 0), + MX8MP_PAD_HDMI_DDC_SCL__CAN1_TX = IOMUX_PAD(0x04A0, 0x0240, 4, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SCL__GPIO3_IO26 = IOMUX_PAD(0x04A0, 0x0240, 5, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SCL__AUDIOMIX_test_out00 = IOMUX_PAD(0x04A0, 0x0240, 6, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_DDC_SDA__HDMIMIX_EARC_SDA = IOMUX_PAD(0x04A4, 0x0244, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SDA__I2C5_SDA = IOMUX_PAD(0x04A4, 0x0244, 3 | IOMUX_CONFIG_SION, 0x05C8, 3, 0), + MX8MP_PAD_HDMI_DDC_SDA__CAN1_RX = IOMUX_PAD(0x04A4, 0x0244, 4, 0x054C, 3, 0), + MX8MP_PAD_HDMI_DDC_SDA__GPIO3_IO27 = IOMUX_PAD(0x04A4, 0x0244, 5, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SDA__AUDIOMIX_test_out01 = IOMUX_PAD(0x04A4, 0x0244, 6, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_CEC__HDMIMIX_EARC_CEC = IOMUX_PAD(0x04A8, 0x0248, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_CEC__I2C6_SCL = IOMUX_PAD(0x04A8, 0x0248, 3 | IOMUX_CONFIG_SION, 0x05CC, 3, 0), + MX8MP_PAD_HDMI_CEC__CAN2_TX = IOMUX_PAD(0x04A8, 0x0248, 4, 0x0000, 0, 0), + MX8MP_PAD_HDMI_CEC__GPIO3_IO28 = IOMUX_PAD(0x04A8, 0x0248, 5, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_HPD__HDMIMIX_EARC_DC_HPD = IOMUX_PAD(0x04AC, 0x024C, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_HPD__AUDIOMIX_EARC_HDMI_HPD_O = IOMUX_PAD(0x04AC, 0x024C, 1, 0x0000, 0, 0), + MX8MP_PAD_HDMI_HPD__I2C6_SDA = IOMUX_PAD(0x04AC, 0x024C, 3 | IOMUX_CONFIG_SION, 0x05D0, 3, 0), + MX8MP_PAD_HDMI_HPD__CAN2_RX = IOMUX_PAD(0x04AC, 0x024C, 4, 0x0550, 3, 0), + MX8MP_PAD_HDMI_HPD__GPIO3_IO29 = IOMUX_PAD(0x04AC, 0x024C, 5, 0x0000, 0, 0), +}; + +#define MX8MP_PAD_CTL_DSE1 (0 << 1) +#define MX8MP_PAD_CTL_DSE2 (1 << 1) +#define MX8MP_PAD_CTL_DSE4 (2 << 1) +#define MX8MP_PAD_CTL_DSE6 (3 << 1) +#define MX8MP_PAD_CTL_FSEL BIT(4) +#define MX8MP_PAD_CTL_ODE BIT(5) +#define MX8MP_PAD_CTL_PUE BIT(6) +#define MX8MP_PAD_CTL_HYS BIT(7) +#define MX8MP_PAD_CTL_PE BIT(8) + +static inline void imx8mp_setup_pad(iomux_v3_cfg_t pad) +{ + void __iomem *iomux = IOMEM(MX8MP_IOMUXC_BASE_ADDR); + + imx8m_setup_pad(iomux, pad); +} + +#define MX8MP_IOMUXC_GPR1 0x4 +#define MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN BIT(22) + +#endif /* __ASM_ARCH_IMX8MP_PINS_H__ */ diff --git a/arch/arm/mach-imx/include/mach/xload.h b/arch/arm/mach-imx/include/mach/xload.h index dca05aa5d4..94b2f37616 100644 --- a/arch/arm/mach-imx/include/mach/xload.h +++ b/arch/arm/mach-imx/include/mach/xload.h @@ -5,7 +5,9 @@ int imx53_nand_start_image(void); int imx6_spi_load_image(int instance, unsigned int flash_offset, void *buf, int len); int imx6_spi_start_image(int instance); int imx6_esdhc_start_image(int instance); +int imx7_esdhc_start_image(int instance); int imx8m_esdhc_load_image(int instance, bool start); +int imx8mp_esdhc_load_image(int instance, bool start); int imx_image_size(void); int piggydata_size(void); diff --git a/arch/arm/mach-layerscape/ppa.c b/arch/arm/mach-layerscape/ppa.c index 477e894781..53e73f6a58 100644 --- a/arch/arm/mach-layerscape/ppa.c +++ b/arch/arm/mach-layerscape/ppa.c @@ -69,16 +69,15 @@ static int ppa_init(void *ppa, size_t ppa_size, void *sec_firmware_addr) fit = fit_open_buf(ppa, ppa_size, false, BOOTM_VERIFY_AVAILABLE); if (IS_ERR(fit)) { - pr_err("Cannot open ppa FIT image: %s\n", strerrorp(fit)); + pr_err("Cannot open ppa FIT image: %pe\n", fit); return PTR_ERR(fit); } conf = fit_open_configuration(fit, NULL); if (IS_ERR(conf)) { - pr_err("Cannot open default config in ppa FIT image: %s\n", - strerrorp(conf)); - fit_close(fit); - return PTR_ERR(fit); + pr_err("Cannot open default config in ppa FIT image: %pe\n", conf); + ret = PTR_ERR(conf); + goto err; } @@ -86,7 +85,6 @@ static int ppa_init(void *ppa, size_t ppa_size, void *sec_firmware_addr) if (ret) { pr_err("Cannot open firmware image in ppa FIT image: %s\n", strerror(-ret)); - ret = PTR_ERR(fit); goto err; } @@ -107,7 +105,7 @@ static int ppa_init(void *ppa, size_t ppa_size, void *sec_firmware_addr) err: fit_close(fit); - return 0; + return ret; } int ls1046a_ppa_init(resource_size_t ppa_start, resource_size_t ppa_size) diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 2589f4fe72..9a35c51985 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -132,7 +132,7 @@ static int armada_370_xp_init_soc(void) if (!of_machine_is_compatible("marvell,armada-370-xp")) return 0; - restart_handler_register_fn(armada_370_xp_restart_soc); + restart_handler_register_fn("soc", armada_370_xp_restart_soc); barebox_set_model("Marvell Armada 370/XP"); barebox_set_hostname("armada"); diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c index 37fde63f18..3c6302dd2d 100644 --- a/arch/arm/mach-mvebu/dove.c +++ b/arch/arm/mach-mvebu/dove.c @@ -36,7 +36,7 @@ static int dove_init_soc(void) if (!of_machine_is_compatible("marvell,dove")) return 0; - restart_handler_register_fn(dove_restart_soc); + restart_handler_register_fn("soc", dove_restart_soc); barebox_set_model("Marvell Dove"); barebox_set_hostname("dove"); diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c index 59fb95ff4a..e50d7501c8 100644 --- a/arch/arm/mach-mvebu/kirkwood.c +++ b/arch/arm/mach-mvebu/kirkwood.c @@ -34,7 +34,7 @@ static int kirkwood_init_soc(void) if (!of_machine_is_compatible("marvell,kirkwood")) return 0; - restart_handler_register_fn(kirkwood_restart_soc); + restart_handler_register_fn("soc", kirkwood_restart_soc); barebox_set_model("Marvell Kirkwood"); barebox_set_hostname("kirkwood"); diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c index f230d9ad89..a4df39c2e9 100644 --- a/arch/arm/mach-mxs/ocotp.c +++ b/arch/arm/mach-mxs/ocotp.c @@ -229,13 +229,7 @@ static struct driver_d mxs_ocotp_driver = { .of_compatible = DRV_OF_COMPAT(mxs_ocotp_compatible), }; -static int mxs_ocotp_init(void) -{ - platform_driver_register(&mxs_ocotp_driver); - - return 0; -} -coredevice_initcall(mxs_ocotp_init); +coredevice_platform_driver(mxs_ocotp_driver); int mxs_ocotp_read(void *buf, int count, int offset) { diff --git a/arch/arm/mach-mxs/soc-imx23.c b/arch/arm/mach-mxs/soc-imx23.c index f25fff18c3..8c47c766cc 100644 --- a/arch/arm/mach-mxs/soc-imx23.c +++ b/arch/arm/mach-mxs/soc-imx23.c @@ -49,7 +49,7 @@ static int imx23_devices_init(void) add_generic_device("imx23-gpio", 0, NULL, IMX_IOMUXC_BASE, 0x2000, IORESOURCE_MEM, NULL); add_generic_device("imx23-gpio", 1, NULL, IMX_IOMUXC_BASE, 0x2000, IORESOURCE_MEM, NULL); add_generic_device("imx23-gpio", 2, NULL, IMX_IOMUXC_BASE, 0x2000, IORESOURCE_MEM, NULL); - restart_handler_register_fn(imx23_restart_soc); + restart_handler_register_fn("soc", imx23_restart_soc); return 0; } diff --git a/arch/arm/mach-mxs/soc-imx28.c b/arch/arm/mach-mxs/soc-imx28.c index 49f870b5bf..a214e2b7a6 100644 --- a/arch/arm/mach-mxs/soc-imx28.c +++ b/arch/arm/mach-mxs/soc-imx28.c @@ -51,7 +51,7 @@ static int imx28_init(void) HW_CLKCTRL_WDOG_POR_DISABLE; writel(reg, IMX_CCM_BASE + HW_CLKCTRL_RESET); - restart_handler_register_fn(imx28_restart_soc); + restart_handler_register_fn("soc", imx28_restart_soc); arm_add_mem_device("ram0", IMX_MEMORY_BASE, imx28_get_memsize()); diff --git a/arch/arm/mach-nomadik/reset.c b/arch/arm/mach-nomadik/reset.c index 8bdaada8a1..d5266068e2 100644 --- a/arch/arm/mach-nomadik/reset.c +++ b/arch/arm/mach-nomadik/reset.c @@ -35,7 +35,7 @@ static void __noreturn nomadik_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(nomadik_restart_soc); + restart_handler_register_fn("soc", nomadik_restart_soc); return 0; } diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c index 0a49038270..8fa2c70aa2 100644 --- a/arch/arm/mach-omap/am33xx_clock.c +++ b/arch/arm/mach-omap/am33xx_clock.c @@ -165,6 +165,10 @@ void am33xx_enable_per_clocks(void) __raw_writel(PRCM_MOD_EN, CM_PER_USB0_CLKCTRL); while ((__raw_readl(CM_PER_USB0_CLKCTRL) & 0x30000) != 0x0); + /* TSC & ADC */ + __raw_writel(PRCM_MOD_EN, CM_WKUP_ADC_TSC_CLKCTRL); + while (__raw_readl(CM_WKUP_ADC_TSC_CLKCTRL) != PRCM_MOD_EN); + clkdcoldo = __raw_readl(CM_CLKDCOLDO_DPLL_PER); clkdcoldo = clkdcoldo | 0x100; __raw_writel(clkdcoldo, CM_CLKDCOLDO_DPLL_PER); diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c index 7577df761c..3c5cdf065c 100644 --- a/arch/arm/mach-omap/am33xx_generic.c +++ b/arch/arm/mach-omap/am33xx_generic.c @@ -244,7 +244,7 @@ int am33xx_init(void) { omap_gpmc_base = (void *)AM33XX_GPMC_BASE; - restart_handler_register_fn(am33xx_restart_soc); + restart_handler_register_fn("soc", am33xx_restart_soc); am33xx_enable_per_clocks(); diff --git a/arch/arm/mach-omap/am33xx_scrm.c b/arch/arm/mach-omap/am33xx_scrm.c index f03fb2bf6a..80510cf5b4 100644 --- a/arch/arm/mach-omap/am33xx_scrm.c +++ b/arch/arm/mach-omap/am33xx_scrm.c @@ -43,9 +43,4 @@ static struct driver_d am33xx_scrm_driver = { .of_compatible = DRV_OF_COMPAT(am33xx_scrm_dt_ids), }; -static int am33xx_scrm_init(void) -{ - return platform_driver_register(&am33xx_scrm_driver); -} - -mem_initcall(am33xx_scrm_init); +mem_platform_driver(am33xx_scrm_driver); diff --git a/arch/arm/mach-omap/boot_order.c b/arch/arm/mach-omap/boot_order.c index db22513bde..4b74fdba66 100644 --- a/arch/arm/mach-omap/boot_order.c +++ b/arch/arm/mach-omap/boot_order.c @@ -70,13 +70,13 @@ static int cmd_boot_order(int argc, char *argv[]) } BAREBOX_CMD_HELP_START(boot_order) -BAREBOX_CMD_HELP_TEXT("Set warm boot order of up to four devices. Each device can be one of:") +BAREBOX_CMD_HELP_TEXT("Set OMAP warm boot order of up to four devices. Each device can be one of:") BAREBOX_CMD_HELP_TEXT("xip xipwait nand onenand mmc1 mmc2_1 mmc2_2 uart usb_1 usb_ulpi usb_2") BAREBOX_CMD_HELP_END BAREBOX_CMD_START(boot_order) .cmd = cmd_boot_order, - BAREBOX_CMD_DESC("set warm boot order") + BAREBOX_CMD_DESC("set OMAP warm boot order") BAREBOX_CMD_OPTS("DEVICE...") BAREBOX_CMD_GROUP(CMD_GRP_BOOT) BAREBOX_CMD_HELP(cmd_boot_order_help) diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h index 284d5f8cf6..e71ecbcd24 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-clock.h +++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h @@ -138,6 +138,7 @@ #define CM_PER_I2C1_CLKCTRL (CM_PER + 0x48) /* I2C1 */ #define CM_PER_I2C2_CLKCTRL (CM_PER + 0x44) /* I2C2 */ #define CM_WKUP_GPIO0_CLKCTRL (CM_WKUP + 0x8) /* GPIO0 */ +#define CM_WKUP_ADC_TSC_CLKCTRL (CM_WKUP + 0xbc)/* TSCADC */ #define CM_PER_MMC0_CLKCTRL (CM_PER + 0x3C) #define CM_PER_MMC1_CLKCTRL (CM_PER + 0xF4) diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c index cff4a4fb11..3f6a346277 100644 --- a/arch/arm/mach-omap/omap3_generic.c +++ b/arch/arm/mach-omap/omap3_generic.c @@ -540,7 +540,7 @@ int omap3_init(void) { omap_gpmc_base = (void *)OMAP3_GPMC_BASE; - restart_handler_register_fn(omap3_restart_soc); + restart_handler_register_fn("soc", omap3_restart_soc); if (IS_ENABLED(CONFIG_RESET_SOURCE)) omap3_detect_reset_reason(); diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c index 1f71153848..848a664064 100644 --- a/arch/arm/mach-omap/omap4_generic.c +++ b/arch/arm/mach-omap/omap4_generic.c @@ -535,7 +535,7 @@ int omap4_init(void) { omap_gpmc_base = (void *)OMAP44XX_GPMC_BASE; - restart_handler_register_fn(omap4_restart_soc); + restart_handler_register_fn("soc", omap4_restart_soc); return omap4_bootsource(); } diff --git a/arch/arm/mach-pxa/common.c b/arch/arm/mach-pxa/common.c index 106ca3020e..5b980cb81b 100644 --- a/arch/arm/mach-pxa/common.c +++ b/arch/arm/mach-pxa/common.c @@ -41,7 +41,7 @@ static void __noreturn pxa_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(pxa_restart_soc); + restart_handler_register_fn("soc-wdt", pxa_restart_soc); return 0; } diff --git a/arch/arm/mach-rockchip/rk3188.c b/arch/arm/mach-rockchip/rk3188.c index e7cbf36457..572e9dc58f 100644 --- a/arch/arm/mach-rockchip/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188.c @@ -29,7 +29,7 @@ static void __noreturn rockchip_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(rockchip_restart_soc); + restart_handler_register_fn("soc", rockchip_restart_soc); return 0; } diff --git a/arch/arm/mach-rockchip/rk3288.c b/arch/arm/mach-rockchip/rk3288.c index 4e8fb4a123..9076fd9227 100644 --- a/arch/arm/mach-rockchip/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288.c @@ -60,7 +60,7 @@ static void rk3288_detect_reset_reason(void) static int rk3288_init(void) { - restart_handler_register_fn(rockchip_restart_soc); + restart_handler_register_fn("soc", rockchip_restart_soc); if (IS_ENABLED(CONFIG_RESET_SOURCE)) rk3288_detect_reset_reason(); diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c index de38d47e21..ed3d30d995 100644 --- a/arch/arm/mach-samsung/generic.c +++ b/arch/arm/mach-samsung/generic.c @@ -44,7 +44,7 @@ static void __noreturn samsung_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(samsung_restart_soc); + restart_handler_register_fn("soc-wdt", samsung_restart_soc); return 0; } diff --git a/arch/arm/mach-socfpga/arria10-generic.c b/arch/arm/mach-socfpga/arria10-generic.c index 53ec278739..38558309f8 100644 --- a/arch/arm/mach-socfpga/arria10-generic.c +++ b/arch/arm/mach-socfpga/arria10-generic.c @@ -70,7 +70,7 @@ static int arria10_generic_init(void) arria10_init_emac(); pr_debug("Register restart handler\n"); - restart_handler_register_fn(arria10_restart_soc); + restart_handler_register_fn("soc", arria10_restart_soc); return 0; } diff --git a/arch/arm/mach-socfpga/cyclone5-reset-manager.c b/arch/arm/mach-socfpga/cyclone5-reset-manager.c index 8635806846..4ee90b1bb0 100644 --- a/arch/arm/mach-socfpga/cyclone5-reset-manager.c +++ b/arch/arm/mach-socfpga/cyclone5-reset-manager.c @@ -37,7 +37,7 @@ static void __noreturn socfpga_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(socfpga_restart_soc); + restart_handler_register_fn("soc", socfpga_restart_soc); return 0; } diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c index 9b58c452d4..e5ecb0f1b8 100644 --- a/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c +++ b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c @@ -221,7 +221,7 @@ static int check_test_mem(int start) #endif // TEST_SIZE -static void SECT(set_failing_group_stage)(uint32_t group, uint32_t stage, uint32_t substage) +static void set_failing_group_stage(uint32_t group, uint32_t stage, uint32_t substage) { if (gbl->error_stage == CAL_STAGE_NIL) { gbl->error_substage = substage; @@ -313,7 +313,7 @@ static void initialize(void) } } -static void SECT(set_rank_and_odt_mask)(uint32_t rank, uint32_t odt_mode) +static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode) { uint32_t odt_mask_0 = 0; uint32_t odt_mask_1 = 0; @@ -485,7 +485,7 @@ static inline void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase) } -static void SECT(scc_mgr_set_dqs_en_phase_all_ranks)(uint32_t read_group, uint32_t phase) +static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group, uint32_t phase) { uint32_t r; uint32_t update_scan_chains; @@ -513,7 +513,7 @@ static inline void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t } -static void SECT(scc_mgr_set_dqdqs_output_phase_all_ranks)(uint32_t write_group, uint32_t phase) +static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group, uint32_t phase) { uint32_t r; uint32_t update_scan_chains; @@ -541,7 +541,7 @@ static inline void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay) } -static void SECT(scc_mgr_set_dqs_en_delay_all_ranks)(uint32_t read_group, uint32_t delay) +static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group, uint32_t delay) { uint32_t r; @@ -562,7 +562,7 @@ static void SECT(scc_mgr_set_dqs_en_delay_all_ranks)(uint32_t read_group, uint32 } } -static void SECT(scc_mgr_set_oct_out1_delay)(uint32_t write_group, uint32_t delay) +static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay) { uint32_t read_group; @@ -581,7 +581,7 @@ static void SECT(scc_mgr_set_oct_out1_delay)(uint32_t write_group, uint32_t dela } -static void SECT(scc_mgr_set_oct_out2_delay)(uint32_t write_group, uint32_t delay) +static void scc_mgr_set_oct_out2_delay(uint32_t write_group, uint32_t delay) { uint32_t read_group; @@ -692,7 +692,7 @@ static inline void scc_mgr_set_dm_in_delay(uint32_t write_group, uint32_t dm, ui WRITE_SCC_DM_IO_IN_DELAY(dm, delay); } -static inline void SECT(scc_mgr_set_dm_bypass)(uint32_t write_group, uint32_t dm, uint32_t bypass) +static inline void scc_mgr_set_dm_bypass(uint32_t write_group, uint32_t dm, uint32_t bypass) { // Load the setting in the SCC manager WRITE_SCC_DM_BYPASS(dm, bypass); @@ -700,7 +700,7 @@ static inline void SECT(scc_mgr_set_dm_bypass)(uint32_t write_group, uint32_t dm //USER Zero all DQS config // TODO: maybe rename to scc_mgr_zero_dqs_config (or something) -static void SECT(scc_mgr_zero_all)(void) +static void scc_mgr_zero_all(void) { uint32_t i, r; @@ -735,7 +735,7 @@ static void SECT(scc_mgr_zero_all)(void) } } -static void SECT(scc_set_bypass_mode)(uint32_t write_group, uint32_t mode) +static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode) { // mode = 0 : Do NOT bypass - Half Rate Mode // mode = 1 : Bypass - Full Rate Mode @@ -763,7 +763,7 @@ static void SECT(scc_set_bypass_mode)(uint32_t write_group, uint32_t mode) } // Moving up to avoid warnings -static void SECT(scc_mgr_load_dqs_for_write_group)(uint32_t write_group) +static void scc_mgr_load_dqs_for_write_group(uint32_t write_group) { uint32_t read_group; @@ -780,7 +780,7 @@ static void SECT(scc_mgr_load_dqs_for_write_group)(uint32_t write_group) } } -static void SECT(scc_mgr_zero_group)(uint32_t write_group, uint32_t test_begin, int32_t out_only) +static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin, int32_t out_only) { uint32_t i, r; @@ -861,7 +861,7 @@ static void scc_mgr_load_dm(uint32_t dm) //USER apply and load a particular input delay for the DQ pins in a group //USER group_bgn is the index of the first dq pin (in the write group) -static void SECT(scc_mgr_apply_group_dq_in_delay)(uint32_t write_group, uint32_t group_bgn, +static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group, uint32_t group_bgn, uint32_t delay) { uint32_t i, p; @@ -874,7 +874,7 @@ static void SECT(scc_mgr_apply_group_dq_in_delay)(uint32_t write_group, uint32_t //USER apply and load a particular output delay for the DQ pins in a group -static void SECT(scc_mgr_apply_group_dq_out1_delay)(uint32_t write_group, uint32_t group_bgn, +static void scc_mgr_apply_group_dq_out1_delay(uint32_t write_group, uint32_t group_bgn, uint32_t delay1) { uint32_t i, p; @@ -887,7 +887,7 @@ static void SECT(scc_mgr_apply_group_dq_out1_delay)(uint32_t write_group, uint32 //USER apply and load a particular output delay for the DM pins in a group -static void SECT(scc_mgr_apply_group_dm_out1_delay)(uint32_t write_group, uint32_t delay1) +static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group, uint32_t delay1) { uint32_t i; @@ -898,7 +898,7 @@ static void SECT(scc_mgr_apply_group_dm_out1_delay)(uint32_t write_group, uint32 } //USER apply and load delay on both DQS and OCT out1 -static void SECT(scc_mgr_apply_group_dqs_io_and_oct_out1)(uint32_t write_group, uint32_t delay) +static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group, uint32_t delay) { scc_mgr_set_dqs_out1_delay(write_group, delay); scc_mgr_load_dqs_io(); @@ -910,7 +910,7 @@ static void SECT(scc_mgr_apply_group_dqs_io_and_oct_out1)(uint32_t write_group, //USER set delay on both DQS and OCT out1 by incrementally changing //USER the settings one dtap at a time towards the target value, to avoid //USER breaking the lock of the DLL/PLL on the memory device. -static void SECT(scc_mgr_set_group_dqs_io_and_oct_out1_gradual)(uint32_t write_group, uint32_t delay) +static void scc_mgr_set_group_dqs_io_and_oct_out1_gradual(uint32_t write_group, uint32_t delay) { uint32_t d = READ_SCC_DQS_IO_OUT1_DELAY(); @@ -934,7 +934,7 @@ static void SECT(scc_mgr_set_group_dqs_io_and_oct_out1_gradual)(uint32_t write_g //USER apply a delay to the entire output side: DQ, DM, DQS, OCT -static void SECT(scc_mgr_apply_group_all_out_delay)(uint32_t write_group, uint32_t group_bgn, +static void scc_mgr_apply_group_all_out_delay(uint32_t write_group, uint32_t group_bgn, uint32_t delay) { //USER dq shift @@ -951,7 +951,7 @@ static void SECT(scc_mgr_apply_group_all_out_delay)(uint32_t write_group, uint32 } //USER apply a delay to the entire output side (DQ, DM, DQS, OCT) and to all ranks -static void SECT(scc_mgr_apply_group_all_out_delay_all_ranks)(uint32_t write_group, uint32_t group_bgn, +static void scc_mgr_apply_group_all_out_delay_all_ranks(uint32_t write_group, uint32_t group_bgn, uint32_t delay) { uint32_t r; @@ -968,7 +968,7 @@ static void SECT(scc_mgr_apply_group_all_out_delay_all_ranks)(uint32_t write_gro //USER apply a delay to the entire output side: DQ, DM, DQS, OCT -static void SECT(scc_mgr_apply_group_all_out_delay_add)(uint32_t write_group, uint32_t group_bgn, +static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group, uint32_t group_bgn, uint32_t delay) { uint32_t i, p, new_delay; @@ -1046,7 +1046,7 @@ static void SECT(scc_mgr_apply_group_all_out_delay_add)(uint32_t write_group, ui } //USER apply a delay to the entire output side (DQ, DM, DQS, OCT) and to all ranks -static void SECT(scc_mgr_apply_group_all_out_delay_add_all_ranks)(uint32_t write_group, +static void scc_mgr_apply_group_all_out_delay_add_all_ranks(uint32_t write_group, uint32_t group_bgn, uint32_t delay) { uint32_t r; @@ -1067,7 +1067,7 @@ static inline void scc_mgr_spread_out2_delay_all_ranks(uint32_t write_group, uin // optimization used to recover some slots in ddr3 inst_rom // could be applied to other protocols if we wanted to -static void SECT(set_jump_as_return)(void) +static void set_jump_as_return(void) { // to save space, we replace return with jump to special shared RETURN instruction // so we set the counter to large value so that we always jump @@ -1077,7 +1077,7 @@ static void SECT(set_jump_as_return)(void) } // should always use constants as argument to ensure all computations are performed at compile time -static inline void SECT(delay_for_n_mem_clocks)(const uint32_t clocks) +static inline void delay_for_n_mem_clocks(const uint32_t clocks) { uint32_t afi_clocks; uint8_t inner; @@ -1145,7 +1145,7 @@ static inline void SECT(delay_for_n_mem_clocks)(const uint32_t clocks) } // should always use constants as argument to ensure all computations are performed at compile time -static inline void SECT(delay_for_n_ns)(const uint32_t nanoseconds) +static inline void delay_for_n_ns(const uint32_t nanoseconds) { delay_for_n_mem_clocks((1000 * nanoseconds) / (1000000 / AFI_CLK_FREQ) * AFI_RATE_RATIO); } @@ -1161,7 +1161,7 @@ static void rw_mgr_rdimm_initialize(void) { } -static void SECT(rw_mgr_mem_initialize)(void) +static void rw_mgr_mem_initialize(void) { uint32_t r; @@ -1273,7 +1273,7 @@ static void rw_mgr_mem_dll_lock_wait(void) //USER At the end of calibration we have to program the user settings in, and //USER hand off the memory to the user. -static void SECT(rw_mgr_mem_handoff)(void) +static void rw_mgr_mem_handoff(void) { uint32_t r; @@ -1325,7 +1325,7 @@ static void SECT(rw_mgr_mem_handoff)(void) } //USER performs a guaranteed read on the patterns we are going to use during a read test to ensure memory works -static uint32_t SECT(rw_mgr_mem_calibrate_read_test_patterns)(uint32_t rank_bgn, uint32_t group, +static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn, uint32_t group, uint32_t num_tries, t_btfld * bit_chk, uint32_t all_ranks) { @@ -1387,7 +1387,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_read_test_patterns)(uint32_t rank_bgn, return (*bit_chk == param->read_correct_mask); } -static uint32_t SECT(rw_mgr_mem_calibrate_read_test_patterns_all_ranks)(uint32_t group, +static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks(uint32_t group, uint32_t num_tries, t_btfld * bit_chk) { @@ -1410,7 +1410,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_read_test_patterns_all_ranks)(uint32_t } //USER load up the patterns we are going to use during a read test -static void SECT(rw_mgr_mem_calibrate_read_load_patterns)(uint32_t rank_bgn, uint32_t all_ranks) +static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn, uint32_t all_ranks) { uint32_t r; uint32_t rank_end = @@ -1445,7 +1445,7 @@ static void SECT(rw_mgr_mem_calibrate_read_load_patterns)(uint32_t rank_bgn, uin set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); } -static inline void SECT(rw_mgr_mem_calibrate_read_load_patterns_all_ranks)(void) +static inline void rw_mgr_mem_calibrate_read_load_patterns_all_ranks(void) { rw_mgr_mem_calibrate_read_load_patterns(0, 1); } @@ -1564,7 +1564,7 @@ static inline void SECT(rw_mgr_mem_calibrate_read_load_patterns_all_ranks)(void) //USER try a read and see if it returns correct data back. has dummy reads inserted into the mix //USER used to align dqs enable. has more thorough checks than the regular read test. -static uint32_t SECT(rw_mgr_mem_calibrate_read_test)(uint32_t rank_bgn, uint32_t group, +static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group, uint32_t num_tries, uint32_t all_correct, t_btfld * bit_chk, uint32_t all_groups, uint32_t all_ranks) @@ -1651,7 +1651,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_read_test)(uint32_t rank_bgn, uint32_t } } -static inline uint32_t SECT(rw_mgr_mem_calibrate_read_test_all_ranks)(uint32_t group, uint32_t num_tries, +static inline uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group, uint32_t num_tries, uint32_t all_correct, t_btfld * bit_chk, uint32_t all_groups) @@ -1660,7 +1660,7 @@ static inline uint32_t SECT(rw_mgr_mem_calibrate_read_test_all_ranks)(uint32_t g 1); } -static void SECT(rw_mgr_incr_vfifo)(uint32_t grp, uint32_t * v) +static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t * v) { //USER fiddle with FIFO if (HARD_PHY) { @@ -1691,7 +1691,7 @@ static void SECT(rw_mgr_incr_vfifo)(uint32_t grp, uint32_t * v) } //Used in quick cal to properly loop through the duplicated VFIFOs in AV QDRII/RLDRAM -static inline void SECT(rw_mgr_incr_vfifo_all)(uint32_t grp, uint32_t * v) +static inline void rw_mgr_incr_vfifo_all(uint32_t grp, uint32_t * v) { #if VFIFO_CONTROL_WIDTH_PER_DQS == 1 rw_mgr_incr_vfifo(grp, v); @@ -1706,7 +1706,7 @@ static inline void SECT(rw_mgr_incr_vfifo_all)(uint32_t grp, uint32_t * v) #endif } -static void SECT(rw_mgr_decr_vfifo)(uint32_t grp, uint32_t * v) +static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t * v) { uint32_t i; @@ -1722,7 +1722,7 @@ static void SECT(rw_mgr_decr_vfifo)(uint32_t grp, uint32_t * v) // Navid's version -static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase)(uint32_t grp) +static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) { uint32_t i, d, v, p; uint32_t max_working_cnt; @@ -2415,7 +2415,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) #else // Val's original version -static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase)(uint32_t grp) +static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) { uint32_t i, j, v, d; uint32_t min_working_d, max_working_cnt; @@ -2532,7 +2532,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase)(uint32_t grp) #endif // Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different dq_in_delay values -static inline uint32_t SECT(rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay)(uint32_t +static inline uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(uint32_t write_group, uint32_t read_group, @@ -2584,7 +2584,7 @@ static inline uint32_t SECT(rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_d #if NEWVERSION_RDDESKEW -static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_center)(uint32_t rank_bgn, uint32_t write_group, +static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t write_group, uint32_t read_group, uint32_t test_bgn, uint32_t use_read_test, uint32_t update_fom) { @@ -2902,7 +2902,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_center)(uint32_t rank_bgn, uint3 #else -static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_center)(uint32_t rank_bgn, uint32_t grp, +static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t grp, uint32_t test_bgn, uint32_t use_read_test) { uint32_t i, p, d; @@ -3037,7 +3037,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_center)(uint32_t rank_bgn, uint3 #if NEWVERSION_GW //USER VFIFO Calibration -- Full Calibration -static uint32_t SECT(rw_mgr_mem_calibrate_vfifo)(uint32_t read_group, uint32_t test_bgn) +static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, uint32_t test_bgn) { uint32_t p, d, rank_bgn, sr; uint32_t dtaps_per_ptap; @@ -3201,7 +3201,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_vfifo)(uint32_t read_group, uint32_t t #else //USER VFIFO Calibration -- Full Calibration -static uint32_t SECT(rw_mgr_mem_calibrate_vfifo)(uint32_t g, uint32_t test_bgn) +static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t g, uint32_t test_bgn) { uint32_t p, rank_bgn, sr; uint32_t grp_calibrated; @@ -3272,7 +3272,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_vfifo)(uint32_t g, uint32_t test_bgn) #endif //USER VFIFO Calibration -- Read Deskew Calibration after write deskew -static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_end)(uint32_t read_group, uint32_t test_bgn) +static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group, uint32_t test_bgn) { uint32_t rank_bgn, sr; uint32_t grp_calibrated; @@ -3323,7 +3323,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_end)(uint32_t read_group, uint32 //USER Calibrate LFIFO to find smallest read latency -static uint32_t SECT(rw_mgr_mem_calibrate_lfifo)(void) +static uint32_t rw_mgr_mem_calibrate_lfifo(void) { uint32_t found_one; t_btfld bit_chk; @@ -3381,7 +3381,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_lfifo)(void) //USER two variants are provided. one that just tests a write pattern and another that //USER tests datamask functionality. -static void SECT(rw_mgr_mem_calibrate_write_test_issue)(uint32_t group, uint32_t test_dm) +static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group, uint32_t test_dm) { uint32_t mcc_instruction; uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) @@ -3486,7 +3486,7 @@ static void SECT(rw_mgr_mem_calibrate_write_test_issue)(uint32_t group, uint32_t //USER Test writes, can check for a single bit pass or multiple bit pass -static uint32_t SECT(rw_mgr_mem_calibrate_write_test)(uint32_t rank_bgn, uint32_t write_group, +static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn, uint32_t write_group, uint32_t use_dm, uint32_t all_correct, t_btfld * bit_chk, uint32_t all_ranks) { @@ -3552,7 +3552,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_write_test)(uint32_t rank_bgn, uint32_ } } -static inline uint32_t SECT(rw_mgr_mem_calibrate_write_test_all_ranks)(uint32_t write_group, +static inline uint32_t rw_mgr_mem_calibrate_write_test_all_ranks(uint32_t write_group, uint32_t use_dm, uint32_t all_correct, t_btfld * bit_chk) @@ -3565,7 +3565,7 @@ static inline uint32_t SECT(rw_mgr_mem_calibrate_write_test_all_ranks)(uint32_t #if NEWVERSION_WL //USER Write Levelling -- Full Calibration -static uint32_t SECT(rw_mgr_mem_calibrate_wlevel)(uint32_t g, uint32_t test_bgn) +static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) { uint32_t p, d; @@ -3805,7 +3805,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_wlevel)(uint32_t g, uint32_t test_bgn) #else //USER Write Levelling -- Full Calibration -static uint32_t SECT(rw_mgr_mem_calibrate_wlevel)(uint32_t g, uint32_t test_bgn) +static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) { uint32_t p, d; t_btfld bit_chk; @@ -3934,7 +3934,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_wlevel)(uint32_t g, uint32_t test_bgn) #if NEWVERSION_WRDESKEW -static uint32_t SECT(rw_mgr_mem_calibrate_writes_center)(uint32_t rank_bgn, uint32_t write_group, +static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t write_group, uint32_t test_bgn) { uint32_t i, p, min_index; @@ -4307,7 +4307,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_writes_center)(uint32_t rank_bgn, uint #else // !NEWVERSION_WRDESKEW -static uint32_t SECT(rw_mgr_mem_calibrate_writes_center)(uint32_t rank_bgn, uint32_t write_group, +static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t write_group, uint32_t test_bgn) { uint32_t i, p, d; @@ -4488,7 +4488,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_writes_center)(uint32_t rank_bgn, uint //USER calibrate the write operations -static uint32_t SECT(rw_mgr_mem_calibrate_writes)(uint32_t rank_bgn, uint32_t g, uint32_t test_bgn) +static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g, uint32_t test_bgn) { reg_file_set_stage(CAL_STAGE_WRITES); @@ -4509,7 +4509,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_writes)(uint32_t rank_bgn, uint32_t g, } //USER precharge all banks and activate row 0 in bank "000..." and bank "111..." -static void SECT(mem_precharge_and_activate)(void) +static void mem_precharge_and_activate(void) { uint32_t r; @@ -4540,7 +4540,7 @@ static void SECT(mem_precharge_and_activate)(void) //USER Configure various memory related parameters. -static void SECT(mem_config)(void) +static void mem_config(void) { uint32_t rlat, wlat; uint32_t rw_wl_nop_cycles; @@ -4629,7 +4629,7 @@ static void SECT(mem_config)(void) //USER Set VFIFO and LFIFO to instant-on settings in skip calibration mode -static void SECT(mem_skip_calibrate)(void) +static void mem_skip_calibrate(void) { uint32_t vfifo_offset; uint32_t i, j, r; @@ -4707,7 +4707,7 @@ static void SECT(mem_skip_calibrate)(void) //USER Memory calibration entry point -static uint32_t SECT(mem_calibrate)(void) +static uint32_t mem_calibrate(void) { uint32_t i; uint32_t rank_bgn, sr; @@ -4914,7 +4914,7 @@ static uint32_t SECT(mem_calibrate)(void) return 1; } -static uint32_t SECT(run_mem_calibrate)(void) +static uint32_t run_mem_calibrate(void) { uint32_t pass; @@ -5011,7 +5011,7 @@ static uint32_t SECT(run_mem_calibrate)(void) } -static void SECT(hc_initialize_rom_data)(void) +static void hc_initialize_rom_data(void) { uint32_t i; @@ -5026,7 +5026,7 @@ static void SECT(hc_initialize_rom_data)(void) } } -static void SECT(initialize_reg_file)(void) +static void initialize_reg_file(void) { // Initialize the register file with the correct data IOWR_32DIRECT(REG_FILE_SIGNATURE, 0, REG_FILE_INIT_SEQ_SIGNATURE); @@ -5038,7 +5038,7 @@ static void SECT(initialize_reg_file)(void) IOWR_32DIRECT(REG_FILE_DEBUG2, 0, 0); } -static void SECT(initialize_hps_phy)(void) +static void initialize_hps_phy(void) { // These may need to be included also: // wrap_back_en (false) @@ -5131,7 +5131,7 @@ static void initialize_tracking(void) IOWR_32DIRECT(REG_FILE_TRK_RFSH, 0, concatenated_refresh); } -static int SECT(socfpga_mem_calibration)(void) +static int socfpga_mem_calibration(void) { param_t my_param; gbl_t my_gbl; diff --git a/arch/arm/mach-socfpga/include/mach/lowlevel.h b/arch/arm/mach-socfpga/include/mach/lowlevel.h index 657e07a881..8134a02357 100644 --- a/arch/arm/mach-socfpga/include/mach/lowlevel.h +++ b/arch/arm/mach-socfpga/include/mach/lowlevel.h @@ -13,7 +13,7 @@ #include <mach/pll_config.h> #include <mach/cyclone5-sequencer.c> -static noinline void SECT(start_socfpga_c5_common)(uint32_t size, void *fdt_blob) +static void __noreturn start_socfpga_c5_common(uint32_t size, void *fdt_blob) { void *fdt; @@ -32,7 +32,7 @@ static noinline void SECT(start_socfpga_c5_common)(uint32_t size, void *fdt_blob start_socfpga_c5_common(memory_size, __dtb_##fdt_name##_start); \ } -static noinline void SECT(start_socfpga_c5_xload_common)(uint32_t size) +static noinline void start_socfpga_c5_xload_common(uint32_t size) { struct socfpga_io_config io_config; int ret; diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 6e816ef9d1..b8ccbaab67 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -8,12 +8,19 @@ config ARCH_STM32MP157 select ARM_PSCI_CLIENT bool -config MACH_STM32MP157C_DK2 +config MACH_STM32MP15XX_DKX select ARCH_STM32MP157 - bool "STM32MP157C-DK2 board" + bool "STM32MP157 DK1 and DK2 boards" + help + builds a single barebox-stm32mp15xx-dkx.img that can be deployed + as SSBL on both the stm32mp157a-dk1 and stm32mp157c-dk2 config MACH_LXA_MC1 select ARCH_STM32MP157 bool "Linux Automation MC-1 board" +config MACH_SEEED_ODYSSEY + select ARCH_STM32MP157 + bool "Seeed Studio Odyssey" + endif diff --git a/arch/arm/mach-stm32mp/ddrctrl.c b/arch/arm/mach-stm32mp/ddrctrl.c index 962d4c0d52..646fe4401a 100644 --- a/arch/arm/mach-stm32mp/ddrctrl.c +++ b/arch/arm/mach-stm32mp/ddrctrl.c @@ -148,8 +148,4 @@ static struct driver_d stm32mp1_ddr_driver = { .of_compatible = DRV_OF_COMPAT(stm32mp1_ddr_dt_ids), }; -static int stm32mp1_ddr_init(void) -{ - return platform_driver_register(&stm32mp1_ddr_driver); -} -mem_initcall(stm32mp1_ddr_init); +mem_platform_driver(stm32mp1_ddr_driver); diff --git a/arch/arm/mach-stm32mp/include/mach/bootsource.h b/arch/arm/mach-stm32mp/include/mach/bootsource.h index 1b6f562ac3..5750dc1448 100644 --- a/arch/arm/mach-stm32mp/include/mach/bootsource.h +++ b/arch/arm/mach-stm32mp/include/mach/bootsource.h @@ -18,16 +18,4 @@ enum stm32mp_boot_device { STM32MP_BOOT_SERIAL_USB_OTG = 0x62, }; -enum stm32mp_forced_boot_mode { - STM32MP_BOOT_NORMAL = 0x00, - STM32MP_BOOT_FASTBOOT = 0x01, - STM32MP_BOOT_RECOVERY = 0x02, - STM32MP_BOOT_STM32PROG = 0x03, - STM32MP_BOOT_UMS_MMC0 = 0x10, - STM32MP_BOOT_UMS_MMC1 = 0x11, - STM32MP_BOOT_UMS_MMC2 = 0x12, -}; - -enum stm32mp_forced_boot_mode st32mp_get_forced_boot_mode(void); - #endif diff --git a/arch/arm/mach-stm32mp/include/mach/revision.h b/arch/arm/mach-stm32mp/include/mach/revision.h index 2eb4d44b33..2ef8ef30c3 100644 --- a/arch/arm/mach-stm32mp/include/mach/revision.h +++ b/arch/arm/mach-stm32mp/include/mach/revision.h @@ -6,6 +6,9 @@ #ifndef __MACH_CPUTYPE_H__ #define __MACH_CPUTYPE_H__ +#include <mach/bsec.h> +#include <asm/io.h> +#include <mach/stm32.h> /* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) * 157X: 2x Cortex-A7, Cortex-M4, CAN FD, GPU, DSI @@ -45,4 +48,52 @@ int stm32mp_package(void); #define cpu_is_stm32mp151c() (stm32mp_cputype() == CPU_STM32MP151Cxx) #define cpu_is_stm32mp151a() (stm32mp_cputype() == CPU_STM32MP151Axx) +/* DBGMCU register */ +#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) +#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) +#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) +#define DBGMCU_IDC_DEV_ID_SHIFT 0 +#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) +#define DBGMCU_IDC_REV_ID_SHIFT 16 + +#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) +#define RCC_DBGCFGR_DBGCKEN BIT(8) + +/* BSEC OTP index */ +#define BSEC_OTP_RPN 1 +#define BSEC_OTP_PKG 16 + +/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(7, 0) + +static inline u32 stm32mp_read_idc(void) +{ + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + return readl(IOMEM(DBGMCU_IDC)); +} + +/* Get Device Part Number (RPN) from OTP */ +static inline int __stm32mp_get_cpu_rpn(u32 *rpn) +{ + int ret = bsec_read_field(BSEC_OTP_RPN, rpn); + if (ret) + return ret; + + *rpn = (*rpn >> RPN_SHIFT) & RPN_MASK; + return 0; +} + +static inline int __stm32mp_get_cpu_type(u32 *type) +{ + u32 id; + int ret = __stm32mp_get_cpu_rpn(type); + if (ret) + return ret; + + id = (stm32mp_read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; + *type |= id << 16; + return 0; +} + #endif /* __MACH_CPUTYPE_H__ */ diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c index 7f687fa4f2..01961ae456 100644 --- a/arch/arm/mach-stm32mp/init.c +++ b/arch/arm/mach-stm32mp/init.c @@ -15,26 +15,6 @@ #include <bootsource.h> #include <dt-bindings/pinctrl/stm32-pinfunc.h> -/* DBGMCU register */ -#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) -#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) -#define DBGMCU_APB4FZ1_IWDG2 BIT(2) -#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) -#define DBGMCU_IDC_DEV_ID_SHIFT 0 -#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) -#define DBGMCU_IDC_REV_ID_SHIFT 16 - -#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) -#define RCC_DBGCFGR_DBGCKEN BIT(8) - -/* BSEC OTP index */ -#define BSEC_OTP_RPN 1 -#define BSEC_OTP_PKG 16 - -/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ -#define RPN_SHIFT 0 -#define RPN_MASK GENMASK(7, 0) - /* Package = bit 27:29 of OTP16 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm @@ -80,12 +60,6 @@ #define FIXUP_CPU_NUM(mask) ((mask) >> 16) #define FIXUP_CPU_HZ(mask) (((mask) & GENMASK(15, 0)) * 1000UL * 1000UL) -static enum stm32mp_forced_boot_mode __stm32mp_forced_boot_mode; -enum stm32mp_forced_boot_mode st32mp_get_forced_boot_mode(void) -{ - return __stm32mp_forced_boot_mode; -} - static void setup_boot_mode(void) { u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); @@ -121,17 +95,11 @@ static void setup_boot_mode(void) break; } - __stm32mp_forced_boot_mode = boot_ctx & TAMP_BOOT_FORCED_MASK; - - pr_debug("[boot_ctx=0x%x] => mode=0x%x, instance=%d forced=0x%x\n", - boot_ctx, boot_mode, instance, __stm32mp_forced_boot_mode); + pr_debug("[boot_ctx=0x%x] => mode=0x%x, instance=%d\n", + boot_ctx, boot_mode, instance); bootsource_set(src); bootsource_set_instance(instance); - - /* clear TAMP for next reboot */ - clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, - STM32MP_BOOT_NORMAL); } static int __stm32mp_cputype; @@ -152,38 +120,9 @@ int stm32mp_package(void) return __stm32mp_package; } -static inline u32 read_idc(void) -{ - setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); - return readl(IOMEM(DBGMCU_IDC)); -} - -/* Get Device Part Number (RPN) from OTP */ -static int get_cpu_rpn(u32 *rpn) -{ - int ret = bsec_read_field(BSEC_OTP_RPN, rpn); - if (ret) - return ret; - - *rpn = (*rpn >> RPN_SHIFT) & RPN_MASK; - return 0; -} - static u32 get_cpu_revision(void) { - return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; -} - -static int get_cpu_type(u32 *type) -{ - u32 id; - int ret = get_cpu_rpn(type); - if (ret) - return ret; - - id = (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; - *type |= id << 16; - return 0; + return (stm32mp_read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; } static int get_cpu_package(u32 *pkg) @@ -250,7 +189,7 @@ static int setup_cpu_type(void) u32 pkg; int ret; - get_cpu_type(&__stm32mp_cputype); + __stm32mp_get_cpu_type(&__stm32mp_cputype); switch (__stm32mp_cputype) { case CPU_STM32MP157Fxx: cputypestr = "157F"; @@ -366,4 +305,4 @@ static int stm32mp_init(void) return 0; } -postcore_initcall(stm32mp_init); +core_initcall(stm32mp_init); diff --git a/arch/arm/mach-stm32mp/stm32image.c b/arch/arm/mach-stm32mp/stm32image.c index 84975c5c3b..207df6894d 100644 --- a/arch/arm/mach-stm32mp/stm32image.c +++ b/arch/arm/mach-stm32mp/stm32image.c @@ -43,8 +43,6 @@ static struct image_handler image_handler_stm32_image_v1_handler = { static int stm32mp_register_stm32image_image_handler(void) { - register_image_handler(&image_handler_stm32_image_v1_handler); - - return 0; + return register_image_handler(&image_handler_stm32_image_v1_handler); } late_initcall(stm32mp_register_stm32image_image_handler); diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 7547951752..60aae41ea0 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,5 +1,5 @@ CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t -CFLAGS_pbl-tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t +CFLAGS_tegra_avp_init.pbl.o := -mcpu=arm7tdmi -march=armv4t lwl-y += tegra_avp_init.o lwl-y += tegra_maincomplex_init.o obj-y += tegra20.o diff --git a/arch/arm/mach-tegra/tegra20-pmc.c b/arch/arm/mach-tegra/tegra20-pmc.c index f7c7ac918f..a252c995ea 100644 --- a/arch/arm/mach-tegra/tegra20-pmc.c +++ b/arch/arm/mach-tegra/tegra20-pmc.c @@ -246,7 +246,7 @@ static struct driver_d tegra20_pmc_driver = { static int tegra20_pmc_init(void) { - restart_handler_register_fn(tegra20_restart_soc); + restart_handler_register_fn("soc", tegra20_restart_soc); return platform_driver_register(&tegra20_pmc_driver); } coredevice_initcall(tegra20_pmc_init); diff --git a/arch/arm/mach-tegra/tegra20-timer.c b/arch/arm/mach-tegra/tegra20-timer.c index 2ba58bd65e..34d34f7723 100644 --- a/arch/arm/mach-tegra/tegra20-timer.c +++ b/arch/arm/mach-tegra/tegra20-timer.c @@ -104,8 +104,4 @@ static struct driver_d tegra20_timer_driver = { .of_compatible = DRV_OF_COMPAT(tegra20_timer_dt_ids), }; -static int tegra20_timer_init(void) -{ - return platform_driver_register(&tegra20_timer_driver); -} -core_initcall(tegra20_timer_init); +core_platform_driver(tegra20_timer_driver); diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 7c6e9523a2..eb94a07dc9 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -75,19 +75,6 @@ void clk_disable(struct clk *clk) } EXPORT_SYMBOL(clk_disable); -/* Create a clock structure with the given name */ -int vpb_clk_create(struct clk *clk, const char *dev_id) -{ - struct clk_lookup *clkdev; - - clkdev = clkdev_alloc(clk, NULL, dev_id); - if (!clkdev) - return -ENOMEM; - - clkdev_add(clkdev); - return 0; -} - /* 1Mhz / 256 */ #define TIMER_FREQ (1000000/256) @@ -205,7 +192,7 @@ static int versatile_init(void) amba_apb_device_add(NULL, "pl061_gpio", 1, 0x101e5000, 4096, NULL, 0); amba_apb_device_add(NULL, "pl061_gpio", 2, 0x101e6000, 4096, NULL, 0); amba_apb_device_add(NULL, "pl061_gpio", 3, 0x101e7000, 4096, NULL, 0); - restart_handler_register_fn(versatile_reset_soc); + restart_handler_register_fn("soc", versatile_reset_soc); return 0; } coredevice_initcall(versatile_init); diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h index 29c4d922b0..6f4b00360f 100644 --- a/arch/arm/mach-versatile/include/mach/platform.h +++ b/arch/arm/mach-versatile/include/mach/platform.h @@ -1,21 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2003 ARM Limited */ + /* - * ach-arm926ejs/include/mach/platform.h - * * Borrowed from Linux v2.6.35 * arch/arm/mach-versatile/include/mach/platform.h - * - * Copyright (c) ARM Limited 2003. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #ifndef __address_h diff --git a/arch/arm/mach-vexpress/reset.c b/arch/arm/mach-vexpress/reset.c index 3164ae3079..78e452936d 100644 --- a/arch/arm/mach-vexpress/reset.c +++ b/arch/arm/mach-vexpress/reset.c @@ -24,7 +24,7 @@ static void vexpress_reset_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(vexpress_reset_soc); + restart_handler_register_fn("soc-wdt", vexpress_reset_soc); return 0; } diff --git a/arch/arm/mach-zynq/bootm-zynqimg.c b/arch/arm/mach-zynq/bootm-zynqimg.c index e903ab6679..77ed6880e4 100644 --- a/arch/arm/mach-zynq/bootm-zynqimg.c +++ b/arch/arm/mach-zynq/bootm-zynqimg.c @@ -42,8 +42,6 @@ static struct image_handler zynq_image_handler = { static int zynq_register_image_handler(void) { - register_image_handler(&zynq_image_handler); - - return 0; + return register_image_handler(&zynq_image_handler); } late_initcall(zynq_register_image_handler); diff --git a/arch/arm/mach-zynq/zynq.c b/arch/arm/mach-zynq/zynq.c index 79a6b908e0..806aeb9130 100644 --- a/arch/arm/mach-zynq/zynq.c +++ b/arch/arm/mach-zynq/zynq.c @@ -69,7 +69,7 @@ static int zynq_init(void) writel(val, 0xf8f00000); dmb(); - restart_handler_register_fn(zynq_restart_soc); + restart_handler_register_fn("soc", zynq_restart_soc); bootsource_set(zynq_bootsource_get()); diff --git a/arch/arm/mach-zynqmp/firmware-zynqmp.c b/arch/arm/mach-zynqmp/firmware-zynqmp.c index 6123aa1ea4..c23b434031 100644 --- a/arch/arm/mach-zynqmp/firmware-zynqmp.c +++ b/arch/arm/mach-zynqmp/firmware-zynqmp.c @@ -637,8 +637,4 @@ static struct driver_d zynqmp_firmware_driver = { .of_compatible = DRV_OF_COMPAT(zynqmp_firmware_id_table), }; -static int zynqmp_firmware_init(void) -{ - return platform_driver_register(&zynqmp_firmware_driver); -} -core_initcall(zynqmp_firmware_init); +core_platform_driver(zynqmp_firmware_driver); diff --git a/arch/kvx/Kconfig b/arch/kvx/Kconfig index 5463bb4f14..3327021e1a 100644 --- a/arch/kvx/Kconfig +++ b/arch/kvx/Kconfig @@ -1,9 +1,14 @@ config KVX bool select 64BIT + select BOOTM + select BOOTM_ELF + select BOOTM_OFTREE + select BOOTM_INITRD select CLKDEV_LOOKUP select COMMON_CLK select COMMON_CLK_OF_PROVIDER + select ELF select FLEXIBLE_BOOTARGS select GENERIC_FIND_NEXT_BIT select LIBFDT diff --git a/arch/kvx/Makefile b/arch/kvx/Makefile index c97cff3456..13c4e24319 100644 --- a/arch/kvx/Makefile +++ b/arch/kvx/Makefile @@ -2,8 +2,6 @@ KBUILD_DEFCONFIG := generic_defconfig KBUILD_CPPFLAGS += -fno-strict-aliasing -board-$(CONFIG_GENERIC) := generic - KALLSYMS += --symbol-prefix=_ ifeq ($(CROSS_COMPILE),) @@ -32,6 +30,6 @@ lds-y += arch/kvx/cpu/barebox.lds cmd_barebox__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_barebox) -o $@ \ -T $(BAREBOX_LDS) \ - --start-group $(BAREBOX_OBJS) --end-group \ + --whole-archive $(BAREBOX_OBJS) --no-whole-archive \ -L$(LIBGCC_PATH) -lgcc \ $(filter-out $(BAREBOX_LDS) $(BAREBOX_OBJS) FORCE ,$^) diff --git a/arch/kvx/configs/generic_defconfig b/arch/kvx/configs/generic_defconfig index f9ff773a0e..0d971ff3d5 100644 --- a/arch/kvx/configs/generic_defconfig +++ b/arch/kvx/configs/generic_defconfig @@ -1,14 +1,13 @@ CONFIG_AUTO_COMPLETE=y -CONFIG_BAUDRATE=115200 -# CONFIG_BOOTM is not set -CONFIG_CLOCKSOURCE_KVX=y +CONFIG_CONSOLE_RATP=y +CONFIG_CMD_BOOT=y +CONFIG_CMD_RESET=y CONFIG_CMD_CMP=y -CONFIG_CMD_OF_DUMP=y CONFIG_CMD_POWEROFF=y -CONFIG_CMD_RESET=y CONFIG_CMD_WD=y -CONFIG_CONSOLE_RATP=y +CONFIG_CMD_OF_DUMP=y CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_PINCTRL_SINGLE=y +CONFIG_CLOCKSOURCE_KVX=y CONFIG_WATCHDOG=y CONFIG_WATCHDOG_KVX=y +CONFIG_PINCTRL_SINGLE=y diff --git a/arch/kvx/cpu/barebox.lds.S b/arch/kvx/cpu/barebox.lds.S index 8d1944afbf..77ebaf0aea 100644 --- a/arch/kvx/cpu/barebox.lds.S +++ b/arch/kvx/cpu/barebox.lds.S @@ -3,7 +3,6 @@ * Copyright (C) 2019 Kalray Inc. */ -#include <config.h> #include <asm/common.h> #include <asm/sys_arch.h> #include <asm-generic/barebox.lds.h> @@ -11,8 +10,6 @@ OUTPUT_FORMAT("elf64-kvx") OUTPUT_ARCH("kvx:kv3-1:64") -#define DTB_DEFAULT_SIZE (24 * 1024) - SECTIONS { . = CONFIG_ARCH_TEXT_BASE; @@ -55,13 +52,6 @@ SECTIONS RO_DATA_SECTION } - .dtb ALIGN(16): - { - __dtb_start = .; - . += DTB_DEFAULT_SIZE; - __dtb_end = .; - } - _etext = .; /* End of text and rodata section */ .data ALIGN(4): { diff --git a/arch/kvx/cpu/reset.c b/arch/kvx/cpu/reset.c index c7f2018e00..df36764cb6 100644 --- a/arch/kvx/cpu/reset.c +++ b/arch/kvx/cpu/reset.c @@ -60,7 +60,7 @@ static int kvx_reset_init(void) break; } - restart_handler_register_fn(kvx_restart_soc); + restart_handler_register_fn("soc", kvx_restart_soc); return 0; } diff --git a/arch/kvx/cpu/start.S b/arch/kvx/cpu/start.S index a02900fb93..d90272c71f 100644 --- a/arch/kvx/cpu/start.S +++ b/arch/kvx/cpu/start.S @@ -3,7 +3,6 @@ * Copyright (C) 2019 Kalray Inc. */ -#include <config.h> #include <linux/linkage.h> #include <asm/privilege.h> #include <asm/sys_arch.h> diff --git a/arch/kvx/dts/Makefile b/arch/kvx/dts/Makefile index 9d5e94ae10..d4221d2c1b 100644 --- a/arch/kvx/dts/Makefile +++ b/arch/kvx/dts/Makefile @@ -4,10 +4,9 @@ obj- += dummy.o BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) ifneq ($(BUILTIN_DTB),) -obj-dtb-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o +obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o endif -obj-dtb-$(CONFIG_BOARD_K200) += k200.dtb.o +obj-$(CONFIG_BOARD_K200) += k200.dtb.o -always := $(dtb-y) clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts diff --git a/arch/kvx/include/asm/bootm.h b/arch/kvx/include/asm/bootm.h new file mode 100644 index 0000000000..7ad7e2e878 --- /dev/null +++ b/arch/kvx/include/asm/bootm.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_BOOTM_H +#define _ASM_KVX_BOOTM_H + +#define LINUX_BOOT_PARAM_MAGIC 0x31564752414E494CULL + +#endif /* _ASM_KVX_BOOTM_H */ diff --git a/arch/kvx/include/asm/cache.h b/arch/kvx/include/asm/cache.h new file mode 100644 index 0000000000..3be1767250 --- /dev/null +++ b/arch/kvx/include/asm/cache.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef __KVX_CACHE_H +#define __KVX_CACHE_H + +#include <linux/types.h> + +static inline void sync_caches_for_execution(void) +{ + __builtin_kvx_fence(); + __builtin_kvx_iinval(); + __builtin_kvx_barrier(); +} + +#endif /* __KVX_CACHE_H */ diff --git a/arch/kvx/include/asm/elf.h b/arch/kvx/include/asm/elf.h index 7cc09d7bac..2975ad1b90 100644 --- a/arch/kvx/include/asm/elf.h +++ b/arch/kvx/include/asm/elf.h @@ -11,6 +11,9 @@ */ #include <linux/types.h> +#define EM_KVX 256 + +#define ELF_ARCH EM_KVX #define ELF_CLASS ELFCLASS32 #define ELF_DATA ELFDATA2MSB diff --git a/arch/kvx/lib/Makefile b/arch/kvx/lib/Makefile index 352e7034a6..6e56462daa 100644 --- a/arch/kvx/lib/Makefile +++ b/arch/kvx/lib/Makefile @@ -3,4 +3,4 @@ # Copyright (C) 2019 Kalray Inc. # -obj-y += cpuinfo.o board.o dtb.o poweroff.o +obj-y += cpuinfo.o board.o dtb.o poweroff.o bootm.o diff --git a/arch/kvx/lib/board.c b/arch/kvx/lib/board.c index 4d6ca6983d..78fa83e02b 100644 --- a/arch/kvx/lib/board.c +++ b/arch/kvx/lib/board.c @@ -103,15 +103,54 @@ err: while (1); } +/** + * exclude_dtb_from_alloc - Find best zone to allocate without overwriting dtb + * + * @fdt: fdt blob + * @alloc_start: start of allocation zone + * @alloc_end: end of allocation zone + */ +static void exclude_dtb_from_alloc(void *fdt, u64 *alloc_start, u64 *alloc_end) +{ + const struct fdt_header *fdth = fdt; + u64 fdt_start = (u64) fdt; + u64 fdt_end = fdt_start + be32_to_cpu(fdth->totalsize); + u64 start_size = 0, end_size = 0; + + /* + * If the device tree is inside the malloc zone, we must exclude it to + * avoid allocating memory over it while unflattening it + */ + if (fdt_end < *alloc_start || fdt_start > (*alloc_end)) + return; + + /* Compute the largest remaining chunk when removing the dtb */ + if (fdt_start >= *alloc_start) + start_size = (fdt_start - *alloc_start); + + if (fdt_end <= *alloc_end) + end_size = *alloc_end - fdt_end; + + /* Modify start/end to reflect the maximum area we found */ + if (start_size >= end_size) + *alloc_end = fdt_start; + else + *alloc_start = fdt_end; +} + void __noreturn kvx_start_barebox(void) { u64 memsize = 0, membase = 0; u64 barebox_text_end = (u64) &__end; + u64 alloc_start, alloc_end; of_find_mem(boot_dtb, barebox_text_end, &membase, &memsize); - mem_malloc_init((void *) barebox_text_end, - (void *) (membase + memsize)); + alloc_start = barebox_text_end; + alloc_end = (membase + memsize); + exclude_dtb_from_alloc(boot_dtb, &alloc_start, &alloc_end); + + mem_malloc_init((void *) alloc_start, (void *) alloc_end); start_barebox(); diff --git a/arch/kvx/lib/bootm.c b/arch/kvx/lib/bootm.c new file mode 100644 index 0000000000..198eef7980 --- /dev/null +++ b/arch/kvx/lib/bootm.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2019 Kalray Inc. + */ + +#include <elf.h> +#include <boot.h> +#include <init.h> +#include <bootm.h> +#include <binfmt.h> +#include <common.h> +#include <libfile.h> +#include <linux/kernel.h> + +#include <asm/cache.h> +#include <asm/bootm.h> + +typedef void __noreturn (*boot_func_entry)(unsigned long, void *); + +static int do_boot_entry(struct image_data *data, boot_func_entry entry, + void *fdt_load_addr) +{ + printf("starting elf (entry at %p)\n", entry); + + if (data->dryrun) + return 0; + + shutdown_barebox(); + + /* Synchronize I-cache with D-cache */ + sync_caches_for_execution(); + + /** + * Parameters passing + * r0: boot magic + * r1: device tree pointer + */ + entry(LINUX_BOOT_PARAM_MAGIC, (void *) fdt_load_addr); + + /* should never return ! */ + panic("Returned from boot program !\n"); + + return -EINVAL; +} + +static int do_boot_elf(struct image_data *data, struct elf_image *elf) +{ + int ret; + void *fdt; + boot_func_entry entry; + unsigned long load_addr, initrd_address; + + /* load initrd after the elf */ + load_addr = PAGE_ALIGN((unsigned long) elf->high_addr); + if (bootm_has_initrd(data)) { + if (data->initrd_address != UIMAGE_INVALID_ADDRESS) + initrd_address = data->initrd_address; + else + initrd_address = load_addr; + + printf("Loading initrd at 0x%lx\n", initrd_address); + ret = bootm_load_initrd(data, initrd_address); + if (ret) { + printf("Failed to load initrd\n"); + return ret; + } + + if (data->initrd_address == UIMAGE_INVALID_ADDRESS) { + load_addr += resource_size(data->initrd_res); + load_addr = PAGE_ALIGN(load_addr); + } + } + + fdt = bootm_get_devicetree(data); + if (IS_ERR(fdt)) { + printf("Failed to load dtb\n"); + return PTR_ERR(fdt); + } + + printf("Loading device tree at %lx\n", load_addr); + /* load device tree after the initrd if any */ + ret = bootm_load_devicetree(data, fdt, load_addr); + if (ret) { + printf("Failed to load device tree: %d\n", ret); + goto err_free_fdt; + } + + entry = (boot_func_entry) data->os_address; + + ret = do_boot_entry(data, entry, fdt); + +err_free_fdt: + free(fdt); + + return ret; +} + +static int do_bootm_elf(struct image_data *data) +{ + int ret; + + ret = bootm_load_os(data, data->os_address); + if (ret) + return ret; + + return do_boot_elf(data, data->elf); +} + +static struct image_handler elf_handler = { + .name = "ELF", + .bootm = do_bootm_elf, + .filetype = filetype_elf, +}; + +static struct binfmt_hook binfmt_elf_hook = { + .type = filetype_elf, + .exec = "bootm", +}; + +static int kvx_register_image_handler(void) +{ + register_image_handler(&elf_handler); + + binfmt_register(&binfmt_elf_hook); + + return 0; +} + +late_initcall(kvx_register_image_handler); diff --git a/arch/kvx/lib/dtb.c b/arch/kvx/lib/dtb.c index 17dcab197f..54ffddaf0a 100644 --- a/arch/kvx/lib/dtb.c +++ b/arch/kvx/lib/dtb.c @@ -12,17 +12,7 @@ static int of_kvx_init(void) int ret; struct device_node *root; - root = of_unflatten_dtb(boot_dtb); - if (IS_ERR(root)) { - ret = PTR_ERR(root); - panic("Failed to parse DTB: %d\n", ret); - } - - ret = of_set_root_node(root); - if (ret) - panic("Failed to set of root node\n"); - - of_probe(); + barebox_register_fdt(boot_dtb); return 0; } diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 5604a0a10d..4eb6ba7721 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -102,7 +102,7 @@ lds-$(CONFIG_GENERIC_LINKER_SCRIPT) := arch/mips/lib/barebox.lds cmd_barebox__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_barebox) -o $@ \ -T $(BAREBOX_LDS) \ - --start-group $(BAREBOX_OBJS) --end-group \ + --whole-archive $(BAREBOX_OBJS) --no-whole-archive \ $(filter-out $(BAREBOX_LDS) $(BAREBOX_OBJS) FORCE ,$^); \ $(objtree)/scripts/mips-relocs $@ diff --git a/arch/mips/boards/Makefile b/arch/mips/boards/Makefile index e85647a0e5..5f9b61e754 100644 --- a/arch/mips/boards/Makefile +++ b/arch/mips/boards/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_BOARD_CI20) += img-ci20/ obj-$(CONFIG_BOARD_DLINK_DIR320) += dlink-dir-320/ obj-$(CONFIG_BOARD_DPTECHNICS_DPT_MODULE) += dptechnics-dpt-module/ obj-$(CONFIG_BOARD_OPENEMBEDED_SOM9331) += openembed-som9331/ +obj-$(CONFIG_BOARD_OKUD_MAX9331) += okud-max9331/ obj-$(CONFIG_BOARD_LOONGSON_TECH_LS1B) += loongson-ls1b/ obj-$(CONFIG_BOARD_NETGEAR_WG102) += netgear-wg102/ obj-$(CONFIG_BOARD_QEMU_MALTA) += qemu-malta/ diff --git a/arch/mips/boards/okud-max9331/Makefile b/arch/mips/boards/okud-max9331/Makefile new file mode 100644 index 0000000000..c58bf72354 --- /dev/null +++ b/arch/mips/boards/okud-max9331/Makefile @@ -0,0 +1,2 @@ +lwl-y += lowlevel.o +lwl-y += lowlevel_boot0.o diff --git a/arch/mips/boards/okud-max9331/lowlevel.S b/arch/mips/boards/okud-max9331/lowlevel.S new file mode 100644 index 0000000000..c5a288557f --- /dev/null +++ b/arch/mips/boards/okud-max9331/lowlevel.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2017 Oleksij Rempel <linux@rempel-privat.de> + * Copyright (C) 2019 Du Huanpeng <u74147@gmail.com> + */ + +#define BOARD_PBL_START start_okud_max9331 + +#include <mach/debug_ll.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/asm.h> +#include <asm/pbl_macros.h> +#include <mach/pbl_macros.h> +#include <asm/pbl_nmon.h> +#include <linux/sizes.h> + +ENTRY_FUNCTION(BOARD_PBL_START) + + ar9331_pbl_generic_start + +ENTRY_FUNCTION_END(BOARD_PBL_START, ar9331_okud_max9331, SZ_64M) diff --git a/arch/mips/boards/okud-max9331/lowlevel_boot0.S b/arch/mips/boards/okud-max9331/lowlevel_boot0.S new file mode 100644 index 0000000000..b0a0e22683 --- /dev/null +++ b/arch/mips/boards/okud-max9331/lowlevel_boot0.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2018 Oleksij Rempel <linux@rempel-privat.de> + * Copyright (C) 2019 Du Huanpeng <u74147@gmail.com> + */ + +#define BOARD_PBL_START start_okud_max9331_boot0 + +#include <mach/debug_ll.h> +#include <asm/asm.h> +#include <asm/pbl_macros.h> +#include <mach/pbl_macros.h> +#include <asm/pbl_nmon.h> + +ENTRY_FUNCTION(BOARD_PBL_START) + + li ra, 0xbfc20000 + jr ra + nop + + +STOP_WITH_DEBUG_EVENT diff --git a/arch/mips/boot/dtb.c b/arch/mips/boot/dtb.c index 5e316270f6..2aff4adbe7 100644 --- a/arch/mips/boot/dtb.c +++ b/arch/mips/boot/dtb.c @@ -42,13 +42,7 @@ static int of_mips_init(void) if (!fdt) fdt = __dtb_start; - root = of_unflatten_dtb(fdt); - if (!IS_ERR(root)) { - pr_debug("using internal DTB\n"); - of_set_root_node(root); - if (IS_ENABLED(CONFIG_OFDEVICE)) - of_probe(); - } + barebox_register_fdt(fdt); return 0; } diff --git a/arch/mips/configs/ath79_defconfig b/arch/mips/configs/ath79_defconfig index ab68f12533..64321ceddd 100644 --- a/arch/mips/configs/ath79_defconfig +++ b/arch/mips/configs/ath79_defconfig @@ -2,6 +2,7 @@ CONFIG_MACH_MIPS_ATH79=y CONFIG_BOARD_8DEVICES_LIMA=y CONFIG_BOARD_DPTECHNICS_DPT_MODULE=y CONFIG_BOARD_OPENEMBEDED_SOM9331=y +CONFIG_BOARD_OKUD_MAX9331=y CONFIG_BOARD_TPLINK_MR3020=y CONFIG_BOARD_TPLINK_WDR4300=y CONFIG_BOARD_BLACK_SWIFT=y diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig index 0cd0e9e650..9cf172a70e 100644 --- a/arch/mips/configs/bcm47xx_defconfig +++ b/arch/mips/configs/bcm47xx_defconfig @@ -9,7 +9,6 @@ CONFIG_MENU=y CONFIG_BOOTM_SHOW_TYPE=y CONFIG_PARTITION=y # CONFIG_DEFAULT_ENVIRONMENT is not set -CONFIG_POLLER=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y CONFIG_CMD_MEMINFO=y diff --git a/arch/mips/configs/qemu-malta_defconfig b/arch/mips/configs/qemu-malta_defconfig index 2465c0260d..ac0577c217 100644 --- a/arch/mips/configs/qemu-malta_defconfig +++ b/arch/mips/configs/qemu-malta_defconfig @@ -12,7 +12,6 @@ CONFIG_BOOTM_SHOW_TYPE=y CONFIG_CONSOLE_ALLOW_COLOR=y CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_POLLER=y CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 9e8a6a6aaf..e5900c971b 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -1,18 +1,19 @@ BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) ifneq ($(BUILTIN_DTB),) -obj-dtb-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o +obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o endif -pbl-dtb-$(CONFIG_BOARD_8DEVICES_LIMA) += qca4531-8devices-lima.dtb.o -pbl-dtb-$(CONFIG_BOARD_BLACK_SWIFT) += black-swift.dtb.o -pbl-dtb-$(CONFIG_BOARD_CI20) += img-ci20.dtb.o -pbl-dtb-$(CONFIG_BOARD_DLINK_DIR320) += dlink-dir-320.dtb.o -pbl-dtb-$(CONFIG_BOARD_DPTECHNICS_DPT_MODULE) += ar9331-dptechnics-dpt-module.dtb.o -pbl-dtb-$(CONFIG_BOARD_OPENEMBEDED_SOM9331) += ar9331-openembed-som9331-board.dtb.o -pbl-dtb-$(CONFIG_BOARD_LOONGSON_TECH_LS1B) += loongson-ls1b.dtb.o -pbl-dtb-$(CONFIG_BOARD_QEMU_MALTA) += qemu-malta.dtb.o -pbl-dtb-$(CONFIG_BOARD_RZX50) += rzx50.dtb.o -pbl-dtb-$(CONFIG_BOARD_TPLINK_MR3020) += ar9331_tl_mr3020.dtb.o -pbl-dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += ar9344-tl-wdr4300-v1.7.dtb.o +pbl-$(CONFIG_BOARD_8DEVICES_LIMA) += qca4531-8devices-lima.dtb.o +pbl-$(CONFIG_BOARD_BLACK_SWIFT) += black-swift.dtb.o +pbl-$(CONFIG_BOARD_CI20) += img-ci20.dtb.o +pbl-$(CONFIG_BOARD_DLINK_DIR320) += dlink-dir-320.dtb.o +pbl-$(CONFIG_BOARD_DPTECHNICS_DPT_MODULE) += ar9331-dptechnics-dpt-module.dtb.o +pbl-$(CONFIG_BOARD_OKUD_MAX9331) += ar9331-okud-max9331.dtb.o +pbl-$(CONFIG_BOARD_OPENEMBEDED_SOM9331) += ar9331-openembed-som9331-board.dtb.o +pbl-$(CONFIG_BOARD_LOONGSON_TECH_LS1B) += loongson-ls1b.dtb.o +pbl-$(CONFIG_BOARD_QEMU_MALTA) += qemu-malta.dtb.o +pbl-$(CONFIG_BOARD_RZX50) += rzx50.dtb.o +pbl-$(CONFIG_BOARD_TPLINK_MR3020) += ar9331_tl_mr3020.dtb.o +pbl-$(CONFIG_BOARD_TPLINK_WDR4300) += ar9344-tl-wdr4300-v1.7.dtb.o clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo diff --git a/arch/mips/dts/ar9331-okud-max9331.dts b/arch/mips/dts/ar9331-okud-max9331.dts new file mode 100644 index 0000000000..53350899f9 --- /dev/null +++ b/arch/mips/dts/ar9331-okud-max9331.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include <mips/qca/ar9331.dtsi> + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +#include "ar9331.dtsi" + +/ { + model = "o&kud max9331"; + compatible = "okud,max9331"; + + aliases { + spiflash = &spiflash; + serial0 = &uart; + }; + + chosen { + environment { + compatible = "barebox,environment"; + device-path = &spiflash, "partname:barebox-environment"; + }; + + art@0 { + compatible = "qca,art-ar9331", "qca,art"; + device-path = &spiflash_art; + barebox,provide-mac-address = <ð0>; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + /* FIXME: leds and gpio */ + leds { + compatible = "gpio-leds"; + + net { + label = "board:LED1:system"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + barebox,default-trigger = "net"; + }; + + panic { + label = "board:LED2:system"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + barebox,default-trigger = "panic"; + }; + + system { + label = "board:LED3:system"; + gpios = <&gpio 27 GPIO_ACTIVE_LOW>; + default-state = "off"; + barebox,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + label = "reset"; + linux,code = <KEY_ENTER>; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð0 { + status = "okay"; +}; + +&ref { + clock-frequency = <25000000>; +}; + +&uart { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&usb { + dr_mode = "host"; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&spi { + num-chipselects = <1>; + status = "okay"; + + /* Spansion FL128SA SPI flash */ + spiflash: s25fl128s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl128s1", "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; + +&spiflash { + partition@0 { + label = "boot0"; + reg = <0 0x10000>; + }; + + partition@10000 { + label = "barebox-environment"; + reg = <0x10000 0x10000>; + }; + + partition@20000 { + label = "barebox"; + reg = <0x20000 0x80000>; + }; + + partition@a0000 { + label = "kernel"; + reg = <0xA0000 0xF50000>; + }; + + spiflash_art: partition@ff0000 { + label = "art"; + reg = <0xff0000 0x10000>; + }; +}; diff --git a/arch/mips/include/asm/debug_ll_ns16550.h b/arch/mips/include/asm/debug_ll_ns16550.h index df58c4cf0d..703bfaee77 100644 --- a/arch/mips/include/asm/debug_ll_ns16550.h +++ b/arch/mips/include/asm/debug_ll_ns16550.h @@ -58,14 +58,14 @@ static inline void PUTC_LL(char ch) * Macros for use in assembly language code */ -.macro debug_ll_ns16550_init +.macro debug_ll_ns16550_init divisor=DEBUG_LL_UART_DIVISOR #ifdef CONFIG_DEBUG_LL la t0, DEBUG_LL_UART_ADDR li t1, UART_LCR_DLAB /* DLAB on */ sb t1, UART_LCR(t0) /* Write it out */ - li t1, DEBUG_LL_UART_DIVISOR + li t1, \divisor sb t1, UART_DLL(t0) /* write low order byte */ srl t1, t1, 8 sb t1, UART_DLM(t0) /* write high order byte */ diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index c155199430..4df9853680 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -39,7 +39,11 @@ static inline unsigned long virt_to_phys(const void *address) */ static inline void *phys_to_virt(unsigned long address) { - return (void *)CKSEG0ADDR(address); + if (IS_ENABLED(CONFIG_MMU)) { + return (void *)CKSEG0ADDR(address); + } + + return (void *)CKSEG1ADDR(address); } #define IO_SPACE_LIMIT 0 diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 5bb09cc2de..6c56202ea9 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -46,43 +46,36 @@ static struct binfmt_hook binfmt_barebox_hook = { static int do_bootm_elf(struct image_data *data) { void (*entry)(int, void *); - struct elf_image *elf; - void *fdt, *buf; + void *fdt; int ret = 0; - buf = read_file(data->os_file, NULL); - if (!buf) - return -EINVAL; - - elf = elf_load_image(buf); - if (IS_ERR(elf)) - return PTR_ERR(elf); + ret = bootm_load_os(data, data->os_address); + if (ret) + return ret; fdt = bootm_get_devicetree(data); if (IS_ERR(fdt)) { ret = PTR_ERR(fdt); - goto bootm_elf_done; + goto bootm_free_fdt; } pr_info("Starting application at 0x%08lx, dts 0x%08lx...\n", - phys_to_virt(elf->entry), data->of_root_node); + phys_to_virt(data->os_address), data->of_root_node); if (data->dryrun) - goto bootm_elf_done; + goto bootm_free_fdt; shutdown_barebox(); - entry = (void *) (unsigned long) elf->entry; + entry = (void *) (unsigned long) data->os_address; entry(-2, phys_to_virt((unsigned long)fdt)); pr_err("ELF application terminated\n"); ret = -EINVAL; -bootm_elf_done: - elf_release_image(elf); +bootm_free_fdt: free(fdt); - free(buf); return ret; } diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c index 4b0e252352..b084a88be7 100644 --- a/arch/mips/lib/reloc.c +++ b/arch/mips/lib/reloc.c @@ -120,7 +120,11 @@ void relocate_code(void *fdt, u32 fdt_size, u32 ram_size) length = __bss_stop - __image_start; relocaddr = ALIGN_DOWN(ram_size - length, SZ_64K); - relocaddr = KSEG0ADDR(relocaddr); + if (IS_ENABLED(CONFIG_MMU)) { + relocaddr = KSEG0ADDR(relocaddr); + } else { + relocaddr = KSEG1ADDR(relocaddr); + } new_stack = relocaddr - MALLOC_SIZE - 16; /* diff --git a/arch/mips/mach-ar231x/ar231x_reset.c b/arch/mips/mach-ar231x/ar231x_reset.c index f88167ba4c..91414edd26 100644 --- a/arch/mips/mach-ar231x/ar231x_reset.c +++ b/arch/mips/mach-ar231x/ar231x_reset.c @@ -68,7 +68,7 @@ static struct driver_d ar231x_reset_driver = { static int ar231x_reset_init(void) { - restart_handler_register_fn(ar2312x_restart_soc); + restart_handler_register_fn("soc-wdt", ar2312x_restart_soc); return platform_driver_register(&ar231x_reset_driver); } coredevice_initcall(ar231x_reset_init); diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index 9dab5fc92a..2dfe0e587a 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -43,6 +43,13 @@ config BOARD_OPENEMBEDED_SOM9331 select HAVE_IMAGE_COMPRESSION select HAS_NMON +config BOARD_OKUD_MAX9331 + bool "The Useless Board Max9331" + select SOC_QCA_AR9331 + select HAVE_PBL_IMAGE + select HAVE_IMAGE_COMPRESSION + select HAS_NMON + config BOARD_TPLINK_MR3020 bool "TP-LINK MR3020" select SOC_QCA_AR9331 diff --git a/arch/mips/mach-ath79/art.c b/arch/mips/mach-ath79/art.c index 44118c19e9..d119ca6d1a 100644 --- a/arch/mips/mach-ath79/art.c +++ b/arch/mips/mach-ath79/art.c @@ -103,10 +103,4 @@ static struct driver_d art_driver = { .of_compatible = art_dt_ids, }; -static int art_of_driver_init(void) -{ - platform_driver_register(&art_driver); - - return 0; -} -late_initcall(art_of_driver_init); +late_platform_driver(art_driver); diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c index b756c859d8..393ca00b08 100644 --- a/arch/mips/mach-ath79/reset.c +++ b/arch/mips/mach-ath79/reset.c @@ -22,7 +22,7 @@ static void __noreturn ath79_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(ath79_restart_soc); + restart_handler_register_fn("soc", ath79_restart_soc); return 0; } diff --git a/arch/mips/mach-bcm47xx/reset.c b/arch/mips/mach-bcm47xx/reset.c index 33dfb7b3b5..3ab9b0ce4b 100644 --- a/arch/mips/mach-bcm47xx/reset.c +++ b/arch/mips/mach-bcm47xx/reset.c @@ -19,7 +19,7 @@ static void __noreturn bcm47xx_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(bcm47xx_restart_soc); + restart_handler_register_fn("soc", bcm47xx_restart_soc); return 0; } diff --git a/arch/mips/mach-loongson/loongson1_reset.c b/arch/mips/mach-loongson/loongson1_reset.c index a6c05905de..85752f4ab8 100644 --- a/arch/mips/mach-loongson/loongson1_reset.c +++ b/arch/mips/mach-loongson/loongson1_reset.c @@ -20,7 +20,7 @@ static void __noreturn longhorn_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(longhorn_restart_soc); + restart_handler_register_fn("soc-wdt", longhorn_restart_soc); return 0; } diff --git a/arch/mips/mach-malta/reset.c b/arch/mips/mach-malta/reset.c index df7be0ae55..ad0de2741b 100644 --- a/arch/mips/mach-malta/reset.c +++ b/arch/mips/mach-malta/reset.c @@ -24,7 +24,7 @@ static void __noreturn malta_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(malta_restart_soc); + restart_handler_register_fn("soc", malta_restart_soc); return 0; } diff --git a/arch/mips/pbl/Makefile b/arch/mips/pbl/Makefile index 535bb4bf55..f85c7a6d6d 100644 --- a/arch/mips/pbl/Makefile +++ b/arch/mips/pbl/Makefile @@ -31,7 +31,7 @@ zbarebox-lds := $(obj)/zbarebox.lds quiet_cmd_zbarebox__ ?= LD $@ cmd_zbarebox__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_zbarebox) -o $@ \ -T $(zbarebox-lds) \ - --start-group $(zbarebox-common) --end-group \ + --whole-archive $(zbarebox-common) --no-whole-archive \ $(filter-out $(zbarebox-lds) $(zbarebox-common) FORCE ,$^) $(obj)/zbarebox: $(zbarebox-lds) $(zbarebox-common) FORCE diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 62bcf40f63..9f86c911cc 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -30,7 +30,7 @@ static void __noreturn nios2_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - return restart_handler_register_fn(nios2_restart_soc); + return restart_handler_register_fn("vector", nios2_restart_soc); } coredevice_initcall(restart_register_feature); diff --git a/arch/nios2/include/asm/int-ll64.h b/arch/nios2/include/asm/int-ll64.h deleted file mode 100644 index f394147c07..0000000000 --- a/arch/nios2/include/asm/int-ll64.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * asm-generic/int-ll64.h - * - * Integer declarations for architectures which use "long long" - * for 64-bit types. - */ - -#ifndef _ASM_GENERIC_INT_LL64_H -#define _ASM_GENERIC_INT_LL64_H - -#include <asm/bitsperlong.h> - -#ifndef __ASSEMBLY__ -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#ifdef __GNUC__ -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#else -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -#endif /* __ASSEMBLY__ */ - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define S8_C(x) x -#define U8_C(x) x ## U -#define S16_C(x) x -#define U16_C(x) x ## U -#define S32_C(x) x -#define U32_C(x) x ## U -#define S64_C(x) x ## LL -#define U64_C(x) x ## ULL - -#else /* __ASSEMBLY__ */ - -#define S8_C(x) x -#define U8_C(x) x -#define S16_C(x) x -#define U16_C(x) x -#define S32_C(x) x -#define U32_C(x) x -#define S64_C(x) x -#define U64_C(x) x - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_GENERIC_INT_LL64_H */ diff --git a/arch/nios2/include/asm/types.h b/arch/nios2/include/asm/types.h index 0067ea83c1..380ad340c3 100644 --- a/arch/nios2/include/asm/types.h +++ b/arch/nios2/include/asm/types.h @@ -1,6 +1,6 @@ #ifndef __ASM_TYPES_H #define __ASM_TYPES_H -#include <asm/int-ll64.h> +#include <asm-generic/int-ll64.h> #endif diff --git a/arch/nios2/lib/libgcc.c b/arch/nios2/lib/libgcc.c index abf93fdd71..814df73310 100644 --- a/arch/nios2/lib/libgcc.c +++ b/arch/nios2/lib/libgcc.c @@ -319,15 +319,15 @@ DWtype __divdi3(DWtype u, DWtype v) DWunion vv = {.ll = v}; DWtype w; - if (uu.s.high < 0) - c = ~c, - - uu.ll = -uu.ll; - - if (vv.s.high < 0) - c = ~c, + if (uu.s.high < 0) { + c = ~c; + uu.ll = -uu.ll; + } - vv.ll = -vv.ll; + if (vv.s.high < 0) { + c = ~c; + vv.ll = -vv.ll; + } w = __udivmoddi4(uu.ll, vv.ll, (UDWtype *) 0); @@ -366,9 +366,10 @@ DWtype __moddi3(DWtype u, DWtype v) DWunion vv = {.ll = v}; DWtype w; - if (uu.s.high < 0) - c = ~c, + if (uu.s.high < 0) { + c = ~c; uu.ll = -uu.ll; + } if (vv.s.high < 0) vv.ll = -vv.ll; diff --git a/arch/openrisc/cpu/cache.c b/arch/openrisc/cpu/cache.c index 1da2380c03..a124d6612c 100644 --- a/arch/openrisc/cpu/cache.c +++ b/arch/openrisc/cpu/cache.c @@ -17,6 +17,7 @@ #include <common.h> #include <init.h> #include <asm/system.h> +#include <asm/cache.h> void flush_dcache_range(unsigned long addr, unsigned long stop) { @@ -130,7 +131,7 @@ void icache_disable(void) mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE); } -int cache_init(void) +static int cache_init(void) { if (mfspr(SPR_UPR) & SPR_UPR_ICP) { icache_disable(); diff --git a/arch/openrisc/cpu/cpu.c b/arch/openrisc/cpu/cpu.c index 8afd22bdea..47d8ab4288 100644 --- a/arch/openrisc/cpu/cpu.c +++ b/arch/openrisc/cpu/cpu.c @@ -33,6 +33,6 @@ static void __noreturn openrisc_restart_cpu(struct restart_handler *rst) static int restart_register_feature(void) { - return restart_handler_register_fn(openrisc_restart_cpu); + return restart_handler_register_fn("vector", openrisc_restart_cpu); } coredevice_initcall(restart_register_feature); diff --git a/arch/openrisc/cpu/exceptions.c b/arch/openrisc/cpu/exceptions.c index d01fbfbb1c..c69ceafe80 100644 --- a/arch/openrisc/cpu/exceptions.c +++ b/arch/openrisc/cpu/exceptions.c @@ -16,6 +16,7 @@ #include <common.h> #include <asm/system.h> +#include <asm/openrisc_exc.h> static const char * const excp_table[] = { "Unknown exception", @@ -69,6 +70,9 @@ static void exception_hang(int vect) hang(); } +/* Called from assembly */ +void exception_handler(int vect); + void exception_handler(int vect) { int exception = vect >> 8; diff --git a/arch/openrisc/include/asm/types.h b/arch/openrisc/include/asm/types.h index 8ee6bb00f9..21a45b74cd 100644 --- a/arch/openrisc/include/asm/types.h +++ b/arch/openrisc/include/asm/types.h @@ -16,52 +16,6 @@ #ifndef _ASM_TYPES_H #define _ASM_TYPES_H -/* - * This file is never included by application software unless - * explicitly requested (e.g., via linux/types.h) in which case the - * application is Linux specific so (user-) name space pollution is - * not a major issue. However, for interoperability, libraries still - * need to be careful to avoid a name clashes. - */ - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#include <asm/bitsperlong.h> - -#endif /* __KERNEL__ */ +#include <asm-generic/int-ll64.h> #endif /* _ASM_TYPES_H */ diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c index 67ea96fc02..9591120fee 100644 --- a/arch/openrisc/lib/board.c +++ b/arch/openrisc/lib/board.c @@ -19,6 +19,9 @@ #include <memory.h> #include <asm-generic/memory_layout.h> +/* Called from assembly */ +void openrisc_start_barebox(void); + void __noreturn openrisc_start_barebox(void) { mem_malloc_init((void *)(OPENRISC_SOPC_TEXT_BASE - MALLOC_SIZE), diff --git a/arch/openrisc/lib/cpuinfo.c b/arch/openrisc/lib/cpuinfo.c index 4c52a65421..d94178ea59 100644 --- a/arch/openrisc/lib/cpuinfo.c +++ b/arch/openrisc/lib/cpuinfo.c @@ -95,7 +95,7 @@ static void cpu_implementation(ulong vr2, char *string) } } -int checkcpu(void) +static int checkcpu(void) { ulong upr = mfspr(SPR_UPR); ulong vr = mfspr(SPR_VR); diff --git a/arch/openrisc/lib/dtb.c b/arch/openrisc/lib/dtb.c index 2dd8e4e014..61cf35ddf3 100644 --- a/arch/openrisc/lib/dtb.c +++ b/arch/openrisc/lib/dtb.c @@ -28,13 +28,7 @@ static int of_openrisc_init(void) if (root) return 0; - root = of_unflatten_dtb(__dtb_start); - if (!IS_ERR(root)) { - pr_debug("using internal DTB\n"); - of_set_root_node(root); - if (IS_ENABLED(CONFIG_OFDEVICE)) - of_probe(); - } + barebox_register_fdt(__dtb_start); return 0; } diff --git a/arch/powerpc/Kbuild b/arch/powerpc/Kbuild index 503ce631c0..65e2493386 100644 --- a/arch/powerpc/Kbuild +++ b/arch/powerpc/Kbuild @@ -1,2 +1,4 @@ obj-$(CONFIG_ARCH_MPC85XX) += cpu-85xx/ obj-y += lib/ +obj-$(CONFIG_FSL_DDR2) += ddr-8xxx/ +obj-$(CONFIG_FSL_DDR3) += ddr-8xxx/ diff --git a/arch/powerpc/boards/freescale-p1010rdb/ddr.c b/arch/powerpc/boards/freescale-p1010rdb/ddr.c index 18069f4df1..14fa426726 100644 --- a/arch/powerpc/boards/freescale-p1010rdb/ddr.c +++ b/arch/powerpc/boards/freescale-p1010rdb/ddr.c @@ -20,7 +20,7 @@ static const u8 spd_addr = 0x52; -int fsl_ddr_board_info(struct ddr_board_info_s *info) +void fsl_ddr_board_info(struct ddr_board_info_s *info) { p1010rdb_early_init(); @@ -34,8 +34,6 @@ int fsl_ddr_board_info(struct ddr_board_info_s *info) info->i2c_speed = 400000; info->i2c_base = IOMEM(I2C2_BASE_ADDR); info->spd_i2c_addr = &spd_addr; - - return 0; } void fsl_ddr_board_options(struct memctl_options_s *popts, diff --git a/arch/powerpc/boards/freescale-p1010rdb/p1010rdb.c b/arch/powerpc/boards/freescale-p1010rdb/p1010rdb.c index b163327597..f2f6d00b77 100644 --- a/arch/powerpc/boards/freescale-p1010rdb/p1010rdb.c +++ b/arch/powerpc/boards/freescale-p1010rdb/p1010rdb.c @@ -37,6 +37,8 @@ #include <mach/early_udelay.h> #include <of.h> +#include "p1010rdb.h" + static struct gfar_info_struct gfar_info[] = { { .phyaddr = 1, diff --git a/arch/powerpc/boards/freescale-p1022ds/ddr.c b/arch/powerpc/boards/freescale-p1022ds/ddr.c index 1944518c79..3a8298f928 100644 --- a/arch/powerpc/boards/freescale-p1022ds/ddr.c +++ b/arch/powerpc/boards/freescale-p1022ds/ddr.c @@ -19,7 +19,7 @@ static const u8 spd_addr = 0x51; -int fsl_ddr_board_info(struct ddr_board_info_s *info) +void fsl_ddr_board_info(struct ddr_board_info_s *info) { /* * Early mapping is needed to access the clock @@ -37,8 +37,6 @@ int fsl_ddr_board_info(struct ddr_board_info_s *info) info->i2c_speed = 400000; info->i2c_base = IOMEM(I2C2_BASE_ADDR); info->spd_i2c_addr = &spd_addr; - - return 0; } struct board_specific_parameters { diff --git a/arch/powerpc/boards/freescale-p1022ds/p1022ds.c b/arch/powerpc/boards/freescale-p1022ds/p1022ds.c index d80c234ea9..956b830c5d 100644 --- a/arch/powerpc/boards/freescale-p1022ds/p1022ds.c +++ b/arch/powerpc/boards/freescale-p1022ds/p1022ds.c @@ -34,6 +34,8 @@ #include <mach/clock.h> #include <mach/early_udelay.h> +#include "p1022ds.h" + /* Define attributes for eTSEC1 and eTSEC2 */ static struct gfar_info_struct gfar_info[] = { { diff --git a/arch/powerpc/boards/pcm030/pcm030.c b/arch/powerpc/boards/pcm030/pcm030.c index 330d29868e..c603643d58 100644 --- a/arch/powerpc/boards/pcm030/pcm030.c +++ b/arch/powerpc/boards/pcm030/pcm030.c @@ -143,6 +143,9 @@ static void sdram_start (int hi_addr) __asm__ volatile ("sync"); } +/* Called from assembly */ +void initdram(int board_type); + void initdram (int board_type) { ulong dramsize = 0; diff --git a/arch/powerpc/cpu-85xx/traps.c b/arch/powerpc/cpu-85xx/traps.c index 0a8862191f..51c85775fc 100644 --- a/arch/powerpc/cpu-85xx/traps.c +++ b/arch/powerpc/cpu-85xx/traps.c @@ -61,7 +61,7 @@ static inline unsigned long get_esr(void) /* * Trap & Exception support */ -void print_backtrace(unsigned long *sp) +static void print_backtrace(unsigned long *sp) { int cnt = 0; unsigned long i; @@ -82,7 +82,7 @@ void print_backtrace(unsigned long *sp) printf("\n"); } -void show_regs(struct pt_regs *regs) +static void show_regs(struct pt_regs *regs) { int i; @@ -107,7 +107,7 @@ void show_regs(struct pt_regs *regs) } } -void _exception(int signr, struct pt_regs *regs) +static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); diff --git a/arch/powerpc/ddr-8xxx/ctrl_regs.c b/arch/powerpc/ddr-8xxx/ctrl_regs.c index e3d43ab09e..187f450c39 100644 --- a/arch/powerpc/ddr-8xxx/ctrl_regs.c +++ b/arch/powerpc/ddr-8xxx/ctrl_regs.c @@ -411,7 +411,8 @@ set_ddr_sdram_interval(struct fsl_ddr_cfg_regs_s *ddr, ddr->ddr_sdram_interval = (((refint & 0xFFFF) << 16) | ((bstopre & 0x3FFF) << 0)); } -void set_ddr3_sdram_mode(struct fsl_ddr_cfg_regs_s *ddr, + +static void set_ddr3_sdram_mode(struct fsl_ddr_cfg_regs_s *ddr, const struct memctl_options_s *popts, const struct common_timing_params_s *dimm, uint32_t cas_latency, uint32_t additive_latency) @@ -508,7 +509,7 @@ void set_ddr3_sdram_mode(struct fsl_ddr_cfg_regs_s *ddr, ); } -void set_ddr2_sdram_mode(struct fsl_ddr_cfg_regs_s *ddr, +static void set_ddr2_sdram_mode(struct fsl_ddr_cfg_regs_s *ddr, const struct memctl_options_s *popts, const struct common_timing_params_s *dimm, uint32_t cas_latency, uint32_t additive_latency) @@ -571,7 +572,7 @@ void set_ddr2_sdram_mode(struct fsl_ddr_cfg_regs_s *ddr, | ((sdmode & 0xFFFF) << 0)); } -void set_ddrx_sdram_mode(struct fsl_ddr_cfg_regs_s *ddr, +static void set_ddrx_sdram_mode(struct fsl_ddr_cfg_regs_s *ddr, const struct memctl_options_s *popts, const struct common_timing_params_s *dimm, uint32_t cas_latency, uint32_t additive_latency) diff --git a/arch/powerpc/ddr-8xxx/ddr.h b/arch/powerpc/ddr-8xxx/ddr.h index 2ef87f2776..8560e37167 100644 --- a/arch/powerpc/ddr-8xxx/ddr.h +++ b/arch/powerpc/ddr-8xxx/ddr.h @@ -109,8 +109,4 @@ int fsl_ddr_get_spd( struct ddr_board_info_s *binfo); int fsl_ddr_set_memctl_regs( const struct fsl_ddr_info_s *info); -void fsl_ddr_board_options( - struct memctl_options_s *popts, - struct dimm_params_s *pdimm); -void fsl_ddr_board_info(struct ddr_board_info_s *info); #endif diff --git a/arch/powerpc/ddr-8xxx/ddr2_dimm_params.c b/arch/powerpc/ddr-8xxx/ddr2_dimm_params.c index 22c05ca6da..3ae88b7c49 100644 --- a/arch/powerpc/ddr-8xxx/ddr2_dimm_params.c +++ b/arch/powerpc/ddr-8xxx/ddr2_dimm_params.c @@ -164,7 +164,7 @@ static uint32_t determine_refresh_rate_ps(const uint32_t spd_refresh) /* CL2 CL3 CL4 CL5 CL6 CL7 */ uint16_t ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 }; -uint32_t compute_derated_DDR2_CAS_latency(uint32_t mclk_ps) +static uint32_t compute_derated_DDR2_CAS_latency(uint32_t mclk_ps) { const uint32_t num_speed_bins = ARRAY_SIZE(ddr2_speed_bins); uint32_t lowest_tCKmin_found = 0, lowest_tCKmin_CL = 0, i, x; diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index f4732389f6..b6c0b4dd7a 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -184,4 +184,12 @@ struct memctl_options_s { extern phys_size_t fsl_ddr_sdram(void); extern phys_size_t fixed_sdram(void); + +struct dimm_params_s; + +void fsl_ddr_board_options( + struct memctl_options_s *popts, + struct dimm_params_s *pdimm); +void fsl_ddr_board_info(struct ddr_board_info_s *info); + #endif diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 39a89a9d15..f4677d11e1 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1109,6 +1109,14 @@ void ll_puts(const char *); /* In misc.c */ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); +void CritcalInputException(struct pt_regs *regs); +void MachineCheckException(struct pt_regs *regs); +void AlignmentException(struct pt_regs *regs); +void ProgramCheckException(struct pt_regs *regs); +void PITException(struct pt_regs *regs); +void UnknownException(struct pt_regs *regs); +void DebugException(struct pt_regs *regs); + #endif /* ndef ASSEMBLY*/ #ifdef CONFIG_MACH_SPECIFIC diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h index 2d3ce0a283..f3d41905ca 100644 --- a/arch/powerpc/include/asm/types.h +++ b/arch/powerpc/include/asm/types.h @@ -1,45 +1,14 @@ #ifndef _PPC_TYPES_H #define _PPC_TYPES_H -#ifndef __ASSEMBLY__ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; +#include <asm-generic/int-ll64.h> -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif +#ifndef __ASSEMBLY__ typedef struct { __u32 u[4]; } __attribute((aligned(16))) vector128; -#ifdef __KERNEL__ -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#include <asm-generic/bitsperlong.h> - -#endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 9031b37ada..a6111606b6 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -33,6 +33,9 @@ ************************************************************************ */ +/* Called from assembly */ +void board_init_r (ulong end_of_ram); + void board_init_r (ulong end_of_ram) { unsigned long malloc_end; diff --git a/arch/powerpc/mach-mpc5xxx/Makefile b/arch/powerpc/mach-mpc5xxx/Makefile index c532a6d1ee..101d061815 100644 --- a/arch/powerpc/mach-mpc5xxx/Makefile +++ b/arch/powerpc/mach-mpc5xxx/Makefile @@ -7,8 +7,3 @@ obj-y += time.o extra-y += start.o obj-$(CONFIG_MPC5200) += firmware_sc_task_bestcomm.impl.o obj-$(CONFIG_REGINFO) += reginfo.o - -#obj-y += firmware_sc_task.impl.o -#obj-y += io.o -#obj-y += ide.o -#obj-y += pci_mpc5200.o diff --git a/arch/powerpc/mach-mpc5xxx/cpu.c b/arch/powerpc/mach-mpc5xxx/cpu.c index a85e1667bc..9c99bdd26f 100644 --- a/arch/powerpc/mach-mpc5xxx/cpu.c +++ b/arch/powerpc/mach-mpc5xxx/cpu.c @@ -33,30 +33,6 @@ #include <asm-generic/memory_layout.h> #include <memory.h> -int checkcpu (void) -{ - ulong clock = get_cpu_clock(); - uint svr, pvr; - - puts ("CPU: "); - - svr = get_svr(); - pvr = get_pvr(); - switch (SVR_VER (svr)) { - case SVR_MPC5200: - printf ("MPC5200"); - break; - default: - printf ("MPC52?? (SVR %08x)", svr); - break; - } - - printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr), - PVR_MAJ(pvr), PVR_MIN(pvr)); - printf (" at %ld Hz\n", clock); - return 0; -} - /* ------------------------------------------------------------------------- */ static int mpc5xxx_reserve_region(void) @@ -92,7 +68,7 @@ static void __noreturn mpc5xxx_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - return restart_handler_register_fn(mpc5xxx_restart_soc); + return restart_handler_register_fn("soc-wdt", mpc5xxx_restart_soc); } coredevice_initcall(restart_register_feature); diff --git a/arch/powerpc/mach-mpc5xxx/firmware_sc_task.impl.S b/arch/powerpc/mach-mpc5xxx/firmware_sc_task.impl.S deleted file mode 100644 index b668ee5cf8..0000000000 --- a/arch/powerpc/mach-mpc5xxx/firmware_sc_task.impl.S +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Copyright (C) 2001, Software Center, Motorola China. - * - * This file contains microcode for the FEC controller of the MGT5100 CPU. - */ - -#include <config.h> - -#if defined(CONFIG_MGT5100) - -/* sas/sccg, gas target */ -.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ -.section smartdmaTaskTable,"aw",@progbits /* Task tables */ -.globl taskTable -taskTable: -.globl scEthernetRecv_Entry -scEthernetRecv_Entry: /* Task 0 */ -.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */ -.long scEthernetRecv_TDT - taskTable + 0x000000a4 -.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */ -.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ -.long 0xf0000000 -.globl scEthernetXmit_Entry -scEthernetXmit_Entry: /* Task 1 */ -.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ -.long scEthernetXmit_TDT - taskTable + 0x000000d0 -.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */ -.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ -.long 0xf0000000 - - -.globl scEthernetRecv_TDT -scEthernetRecv_TDT: /* Task 0 Descriptor Table */ -.long 0xc4c50000 /* 0000: LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */ -.long 0x84c5e000 /* 0004: LCD: idx1 = var9 + var11; ; idx1 += inc0 */ -.long 0x10001f08 /* 0008: DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000380 /* 000C: DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f88 /* 0010: DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x010c504c /* 0020: DRD2B1: var4 = EU1(); EU1(var1,var12) */ -.long 0x82180349 /* 0024: LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */ -.long 0x81c68004 /* 0028: LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x70000000 /* 002C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018c504e /* 0030: DRD2B1: var6 = EU1(); EU1(var1,var14) */ -.long 0x70000000 /* 0034: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x020c504f /* 0038: DRD2B1: var8 = EU1(); EU1(var1,var15) */ -.long 0x00000b88 /* 003C: DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d184 /* 0040: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0xc6990452 /* 0044: LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */ -.long 0x81486010 /* 0048: LCD: idx3 = var2 + var16; ; idx3 += inc2 */ -.long 0x006acf88 /* 004C: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 0050: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x86810492 /* 0054: LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */ -.long 0x006acf88 /* 0058: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 005C: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x868184d2 /* 0060: LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */ -.long 0x000acf88 /* 0064: DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */ -.long 0xc318839b /* 0068: LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */ -.long 0x80190000 /* 006C: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008468 /* 0070: DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4038358 /* 0074: LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */ -.long 0x81c50000 /* 0078: LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */ -.long 0x1000cb18 /* 007C: DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 0080: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188364 /* 0084: LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */ -.long 0x83990000 /* 0088: LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */ -.long 0x10000c00 /* 008C: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x0000c800 /* 0090: DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 0094: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 0098: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 009C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080c504c /* 00A0: DRD2B1: idx0 = EU1(); EU1(var1,var12) */ -.long 0x000001f8 /* 00A4(:0): NOP */ - - -.globl scEthernetXmit_TDT -scEthernetXmit_TDT: /* Task 1 Descriptor Table */ -.long 0x80014800 /* 0000: LCDEXT: idx0 = 0xf0004800; ; */ -.long 0x85c60004 /* 0004: LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x10002308 /* 0008: DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000f88 /* 000C: DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000380 /* 0010: DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x024c504d /* 0020: DRD2B1: var9 = EU1(); EU1(var1,var13) */ -.long 0x84980309 /* 0024: LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */ -.long 0xc0004003 /* 0028: LCDEXT: idx1 = 0x00000003; ; */ -.long 0x81c60004 /* 002C: LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ -.long 0x70000000 /* 0030: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x010c504e /* 0034: DRD2B1: var4 = EU1(); EU1(var1,var14) */ -.long 0x70000000 /* 0038: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x014c504f /* 003C: DRD2B1: var5 = EU1(); EU1(var1,var15) */ -.long 0x70000000 /* 0040: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x028c5050 /* 0044: DRD2B1: var10 = EU1(); EU1(var1,var16) */ -.long 0x70000000 /* 0048: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018c5051 /* 004C: DRD2B1: var6 = EU1(); EU1(var1,var17) */ -.long 0x10000b90 /* 0050: DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 0054: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x01cc50a1 /* 0058: DRD2B1: var7 = EU1(); EU1(var2,idx1) */ -.long 0xc2988312 /* 005C: LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */ -.long 0x83490000 /* 0060: LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */ -.long 0x00001b10 /* 0064: DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d1a4 /* 0068: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0x8301031c /* 006C: LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */ -.long 0x008ac798 /* 0070: DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */ -.long 0x8000d1a4 /* 0074: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0xc1430000 /* 0078: LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */ -.long 0x82998312 /* 007C: LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */ -.long 0x088ac790 /* 0080: DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */ -.long 0x81988000 /* 0084: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x60000100 /* 0088: DRD2A: EU0=0 EU1=1 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x0c4c5c4d /* 008C: DRD2B1: *idx1 = EU1(); EU1(*idx1,var13) */ -.long 0xc21883ad /* 0090: LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */ -.long 0x80190000 /* 0094: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008460 /* 0098: DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4052305 /* 009C: LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */ -.long 0x81c98000 /* 00A0: LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */ -.long 0x1000c718 /* 00A4: DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 00A8: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188000 /* 00AC: LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */ -.long 0x85190312 /* 00B0: LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */ -.long 0x10000c00 /* 00B4: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x1000c400 /* 00B8: DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00008860 /* 00BC: DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 00C0: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 00C4: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 00C8: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080c504d /* 00CC: DRD2B1: idx0 = EU1(); EU1(var1,var13) */ -.long 0x000001f8 /* 00D0(:0): NOP */ - -.align 8 - -.globl scEthernetRecv_VarTab -scEthernetRecv_VarTab: /* Task 0 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0xf0004800 /* var[9] */ -.long 0x00000008 /* var[10] */ -.long 0x0000000c /* var[11] */ -.long 0x80000000 /* var[12] */ -.long 0x00000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x20000000 /* var[15] */ -.long 0x000005e4 /* var[16] */ -.long 0x0000000e /* var[17] */ -.long 0x000005e0 /* var[18] */ -.long 0x00000004 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x20000001 /* inc[2] */ -.long 0x80000000 /* inc[3] */ -.long 0x40000000 /* inc[4] */ -.long 0x00000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetXmit_VarTab -scEthernetXmit_VarTab: /* Task 1 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0x00000000 /* var[9] */ -.long 0x00000000 /* var[10] */ -.long 0xf0004800 /* var[11] */ -.long 0x00000000 /* var[12] */ -.long 0x80000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x08000000 /* var[15] */ -.long 0x20000000 /* var[16] */ -.long 0x0000ffff /* var[17] */ -.long 0xffffffff /* var[18] */ -.long 0x00000008 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x40000000 /* inc[2] */ -.long 0x4000ffff /* inc[3] */ -.long 0xe0000001 /* inc[4] */ -.long 0x80000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetRecv_FDT -scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x05800000 /* and(), EU# 1 */ -.long 0x05400000 /* andn(), EU# 1 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - -.align 8 - -.globl scEthernetXmit_FDT -scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x05800000 /* and(), EU# 1 */ -.long 0x05400000 /* andn(), EU# 1 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - - -.align 8 -.globl scEthernetRecv_CSave -scEthernetRecv_CSave: /* Task 0 context save space */ -.space 256, 0x0 - - -.align 8 -.globl scEthernetXmit_CSave -scEthernetXmit_CSave: /* Task 1 context save space */ -.space 256, 0x0 - -#endif /* CONFIG_MGT5100 */ diff --git a/arch/powerpc/mach-mpc5xxx/io.S b/arch/powerpc/mach-mpc5xxx/io.S deleted file mode 100644 index 871d65ae38..0000000000 --- a/arch/powerpc/mach-mpc5xxx/io.S +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> - * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> - * Copyright (C) 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Andreas Heppel <aheppel@sysgo.de> - * Copyright (C) 2003 Wolfgang Denk <wd@denx.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <config.h> -#include <ppc_asm.tmpl> - -/* ------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in8 -in8: - lbz r3,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in16 */ -/* Description: Input 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in16 -in16: - lhz r3,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in16r */ -/* Description: Input 16 bits and byte reverse */ -/* ------------------------------------------------------------------------------- */ - .globl in16r -in16r: - lhbrx r3,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in32 -in32: - lwz 3,0(3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in32r */ -/* Description: Input 32 bits and byte reverse */ -/* ------------------------------------------------------------------------------- */ - .globl in32r -in32r: - lwbrx r3,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out8 -out8: - stb r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out16 */ -/* Description: Output 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out16 -out16: - sth r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out16r */ -/* Description: Byte reverse and output 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out16r -out16r: - sthbrx r4,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out32 -out32: - stw r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out32r */ -/* Description: Byte reverse and output 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out32r -out32r: - stwbrx r4,0,r3 - sync - blr diff --git a/arch/powerpc/mach-mpc5xxx/pci_mpc5200.c b/arch/powerpc/mach-mpc5xxx/pci_mpc5200.c deleted file mode 100644 index a3d62a168d..0000000000 --- a/arch/powerpc/mach-mpc5xxx/pci_mpc5200.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <common.h> - -#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200) - -#include <asm/processor.h> -#include <io.h> -#include <pci.h> -#include <mpc5xxx.h> - -/* System RAM mapped over PCI */ -#define CONFIG_PCI_MEMORY_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE -#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024) - -/* PCIIWCR bit fields */ -#define IWCR_MEM (0 << 3) -#define IWCR_IO (1 << 3) -#define IWCR_READ (0 << 1) -#define IWCR_READLINE (1 << 1) -#define IWCR_READMULT (2 << 1) -#define IWCR_EN (1 << 0) - -static int mpc5200_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32* value) -{ - *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; - eieio(); - udelay(10); -#if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200) - if (dev & 0x00ff0000) { - u32 val; - val = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2)); - udelay(10); - val = val << 16; - val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0)); - *value = val; - } else { - *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); - } - udelay(10); -#else - *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); -#endif - eieio(); - *(volatile u32 *)MPC5XXX_PCI_CAR = 0; - udelay(10); - return 0; -} - -static int mpc5200_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; - eieio(); - udelay(10); - out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value); - eieio(); - *(volatile u32 *)MPC5XXX_PCI_CAR = 0; - udelay(10); - return 0; -} - -void pci_mpc5xxx_init (struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEMORY_BUS, - CONFIG_PCI_MEMORY_PHYS, - CONFIG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose(hose); - - /* GPIO Multiplexing - enable PCI */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15); - - /* Set host bridge as pci master and enable memory decoding */ - *(vu_long *)MPC5XXX_PCI_CMD |= - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - - /* Set maximum latency timer */ - *(vu_long *)MPC5XXX_PCI_CFG |= (0xf800); - - /* Set cache line size */ - *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) | - (CACHELINE_SIZE / 4); - - /* Map MBAR to PCI space */ - *(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR; - *(vu_long *)MPC5XXX_PCI_TBATR0 = CFG_MBAR | 1; - - /* Map RAM to PCI space */ - *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3); - *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1; - - /* Park XLB on PCI */ - *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5)); - *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5); - - /* Disable interrupts from PCI controller */ - *(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12); - *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24); - - /* Set PCI retry counter to 0 = infinite retry. */ - /* The default of 255 is too short for slow devices. */ - *(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00; - - /* Disable initiator windows */ - *(vu_long *)MPC5XXX_PCI_IWCR = 0; - - /* Map PCI memory to physical space */ - *(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS | - (((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) | - (CONFIG_PCI_MEM_BUS >> 16); - *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24; - - /* Map PCI I/O to physical space */ - *(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS | - (((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) | - (CONFIG_PCI_IO_BUS >> 16); - *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16; - - /* Reset the PCI bus */ - *(vu_long *)MPC5XXX_PCI_GSCR |= 1; - udelay(1000); - *(vu_long *)MPC5XXX_PCI_GSCR &= ~1; - udelay(1000); - - pci_set_ops(hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - mpc5200_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - mpc5200_write_config_dword); - - udelay(1000); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - - hose->last_busno = pci_hose_scan(hose); -} -#endif /* CONFIG_PCI && CONFIG_MPC5200 */ diff --git a/arch/powerpc/mach-mpc5xxx/reginfo.c b/arch/powerpc/mach-mpc5xxx/reginfo.c index e41d235a5d..8b646e7d04 100644 --- a/arch/powerpc/mach-mpc5xxx/reginfo.c +++ b/arch/powerpc/mach-mpc5xxx/reginfo.c @@ -1,4 +1,5 @@ #include <stdio.h> +#include <common.h> #include <config.h> #include <mach/mpc5xxx.h> #include <asm/io.h> diff --git a/arch/powerpc/mach-mpc5xxx/speed.c b/arch/powerpc/mach-mpc5xxx/speed.c index 0cec9522e5..760d923bcf 100644 --- a/arch/powerpc/mach-mpc5xxx/speed.c +++ b/arch/powerpc/mach-mpc5xxx/speed.c @@ -19,6 +19,7 @@ #include <init.h> #include <asm/processor.h> #include <types.h> +#include <mach/clock.h> /* Bus-to-Core Multipliers */ @@ -87,7 +88,7 @@ unsigned long get_timebase_clock(void) return (get_bus_clock() + 3L) / 4L; } -int prt_mpc5xxx_clks (void) +static int prt_mpc5xxx_clks (void) { printf(" Bus %ld MHz, IPB %ld MHz, PCI %ld MHz\n", get_bus_clock() / 1000000, get_ipb_clock() / 1000000, diff --git a/arch/powerpc/mach-mpc5xxx/time.c b/arch/powerpc/mach-mpc5xxx/time.c index d1864673bd..8981b14eeb 100644 --- a/arch/powerpc/mach-mpc5xxx/time.c +++ b/arch/powerpc/mach-mpc5xxx/time.c @@ -20,7 +20,7 @@ #include <mach/clock.h> #include <asm/common.h> -uint64_t ppc_clocksource_read(void) +static uint64_t ppc_clocksource_read(void) { return get_ticks(); } diff --git a/arch/powerpc/mach-mpc5xxx/traps.c b/arch/powerpc/mach-mpc5xxx/traps.c index 501a76252c..e93b5d6d75 100644 --- a/arch/powerpc/mach-mpc5xxx/traps.c +++ b/arch/powerpc/mach-mpc5xxx/traps.c @@ -41,7 +41,7 @@ int (*debugger_exception_handler)(struct pt_regs *) = 0; * Trap & Exception support */ -void +static void print_backtrace(unsigned long *sp) { int cnt = 0; @@ -62,7 +62,7 @@ print_backtrace(unsigned long *sp) printf("\n"); } -void show_regs(struct pt_regs * regs) +static void show_regs(struct pt_regs * regs) { int i; @@ -90,7 +90,7 @@ void show_regs(struct pt_regs * regs) } -void +static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); @@ -169,19 +169,6 @@ ProgramCheckException(struct pt_regs *regs) } void -SoftEmuException(struct pt_regs *regs) -{ -#ifdef CONFIG_KGDB - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void UnknownException(struct pt_regs *regs) { #ifdef CONFIG_KGDB @@ -207,12 +194,3 @@ DebugException(struct pt_regs *regs) do_bedbug_breakpoint( regs ); #endif } - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int -addr_probe(uint *addr) -{ - return 0; -} diff --git a/arch/powerpc/mach-mpc85xx/Makefile b/arch/powerpc/mach-mpc85xx/Makefile index de4f5efde2..9886c7da45 100644 --- a/arch/powerpc/mach-mpc85xx/Makefile +++ b/arch/powerpc/mach-mpc85xx/Makefile @@ -9,6 +9,4 @@ obj-y += fsl_i2c.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_OFTREE) += fdt.o obj-$(CONFIG_DRIVER_NET_GIANFAR) += eth-devices.o -obj-$(CONFIG_FSL_DDR2) += ../ddr-8xxx/ -obj-$(CONFIG_FSL_DDR3) += ../ddr-8xxx/ extra-y += barebox.lds diff --git a/arch/powerpc/mach-mpc85xx/cpu.c b/arch/powerpc/mach-mpc85xx/cpu.c index 7c8a59edc9..2119352f84 100644 --- a/arch/powerpc/mach-mpc85xx/cpu.c +++ b/arch/powerpc/mach-mpc85xx/cpu.c @@ -28,6 +28,7 @@ #include <asm-generic/memory_layout.h> #include <mach/mmu.h> #include <mach/immap_85xx.h> +#include <mach/mpc85xx.h> static void __noreturn mpc85xx_restart_soc(struct restart_handler *rst) { @@ -42,12 +43,15 @@ static void __noreturn mpc85xx_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(mpc85xx_restart_soc); + restart_handler_register_fn("soc", mpc85xx_restart_soc); return 0; } coredevice_initcall(restart_register_feature); +/* Called from assembly */ +long int initdram(int board_type); + long int initdram(int board_type) { phys_size_t dram_size = 0; diff --git a/arch/powerpc/mach-mpc85xx/cpu_init.c b/arch/powerpc/mach-mpc85xx/cpu_init.c index 4e13404aff..3259945fda 100644 --- a/arch/powerpc/mach-mpc85xx/cpu_init.c +++ b/arch/powerpc/mach-mpc85xx/cpu_init.c @@ -34,7 +34,7 @@ /* NOR workaround for P1010 erratum A003399 */ #if defined(CONFIG_FSL_ERRATUM_P1010_A003549) #define SRAM_BASE_ADDR 0x100 -void setup_ifc(void) +static void setup_ifc(void) { u32 mas0, mas1, mas2, mas3, mas7; phys_addr_t flash_phys = CFG_FLASH_BASE_PHYS; @@ -89,7 +89,7 @@ void setup_ifc(void) set_ifc_amask(0, CFG_IFC_AMASK0); } -void fsl_erratum_ifc_a003399(void) +static void fsl_erratum_ifc_a003399(void) { u32 mas0, mas1, mas2, mas3, mas7; void __iomem *l2cache = IOMEM(MPC85xx_L2_ADDR); @@ -127,7 +127,7 @@ void fsl_erratum_ifc_a003399(void) out_be32(l2cache + MPC85xx_L2_L2SRBAR0_OFFSET, 0x0); } #else -void fsl_erratum_ifc_a003399(void) {} +static void fsl_erratum_ifc_a003399(void) {} #endif int fsl_l2_cache_init(void) @@ -173,7 +173,7 @@ int fsl_l2_cache_init(void) } #if defined(CONFIG_FSL_ERRATUM_P1010_A003549) -void fsl_erratum_p1010_a003549(void) +static void fsl_erratum_p1010_a003549(void) { void __iomem *guts = IOMEM(MPC85xx_GUTS_ADDR); @@ -181,9 +181,12 @@ void fsl_erratum_p1010_a003549(void) MPC85xx_PMUXCR_LCLK_IFC_CS3); } #else -void fsl_erratum_p1010_a003549(void) {} +static void fsl_erratum_p1010_a003549(void) {} #endif +/* Called from assembly */ +void cpu_init_early_f(void); + void cpu_init_early_f(void) { u32 mas0, mas1, mas2, mas3, mas7; diff --git a/arch/powerpc/mach-mpc85xx/cpuid.c b/arch/powerpc/mach-mpc85xx/cpuid.c index ae82e3fd3f..28f08ca292 100644 --- a/arch/powerpc/mach-mpc85xx/cpuid.c +++ b/arch/powerpc/mach-mpc85xx/cpuid.c @@ -23,6 +23,7 @@ #include <asm/cache.h> #include <asm/io.h> #include <mach/immap_85xx.h> +#include <mach/mpc85xx.h> struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(8544, 8544, 1), diff --git a/arch/powerpc/mach-mpc85xx/fsl_gpio.c b/arch/powerpc/mach-mpc85xx/fsl_gpio.c index 468c780ff8..85994dcf1b 100644 --- a/arch/powerpc/mach-mpc85xx/fsl_gpio.c +++ b/arch/powerpc/mach-mpc85xx/fsl_gpio.c @@ -28,39 +28,4 @@ void fsl_enable_gpiout(void) out_be32(gpiocr, in_be32(gpiocr) | MPC85xx_GPIOCR_GPOUT); } - -void gpio_set_value(unsigned gpio, int val) -{ - void __iomem *gpout = IOMEM(MPC85xx_GUTS_ADDR + MPC85xx_GPOUTDR_OFFSET); - int gpoutdr; - - if (gpio >= 8) - return; - - gpoutdr = in_be32(gpout); - if (val) - gpoutdr |= MPC85xx_GPIOBIT(gpio); - else - gpoutdr &= ~MPC85xx_GPIOBIT(gpio); - out_be32(gpout, gpoutdr); -} -#else -int gpio_direction_output(unsigned gpio, int val) -{ - void __iomem *gpior = IOMEM(MPC85xx_GPIO_ADDR); - - if (gpio >= 16) - return -EINVAL; - - if (val) - setbits_be32(gpior + MPC85xx_GPIO_GPDAT_OFFSET, - 1 << (32 - gpio)); - else - clrbits_be32(gpior + MPC85xx_GPIO_GPDAT_OFFSET, - 1 << (32 - gpio)); - - setbits_be32(gpior + MPC85xx_GPIO_GPDIR_OFFSET, 1 << (32 - gpio)); - - return 0; -} #endif diff --git a/arch/powerpc/mach-mpc85xx/fsl_i2c.c b/arch/powerpc/mach-mpc85xx/fsl_i2c.c index 51fcc64c26..8cf80713f6 100644 --- a/arch/powerpc/mach-mpc85xx/fsl_i2c.c +++ b/arch/powerpc/mach-mpc85xx/fsl_i2c.c @@ -21,6 +21,7 @@ #include <mach/clock.h> #include <mach/immap_85xx.h> #include <mach/early_udelay.h> +#include <mach/fsl_i2c.h> /* FSL I2C registers */ #define FSL_I2C_ADR 0x00 diff --git a/arch/powerpc/mach-mpc85xx/speed.c b/arch/powerpc/mach-mpc85xx/speed.c index 7f3cfc4dcd..16ce72d846 100644 --- a/arch/powerpc/mach-mpc85xx/speed.c +++ b/arch/powerpc/mach-mpc85xx/speed.c @@ -85,15 +85,6 @@ void fsl_get_sys_info(struct sys_info *sysInfo) } } -unsigned long fsl_get_local_freq(void) -{ - struct sys_info sys_info; - - fsl_get_sys_info(&sys_info); - - return sys_info.freqLocalBus; -} - unsigned long fsl_get_bus_freq(ulong dummy) { struct sys_info sys_info; diff --git a/arch/powerpc/mach-mpc85xx/time.c b/arch/powerpc/mach-mpc85xx/time.c index f0acd91a1d..067bce8ea6 100644 --- a/arch/powerpc/mach-mpc85xx/time.c +++ b/arch/powerpc/mach-mpc85xx/time.c @@ -20,7 +20,7 @@ #include <init.h> #include <mach/clock.h> -uint64_t ppc_clocksource_read(void) +static uint64_t ppc_clocksource_read(void) { return get_ticks(); } diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index c71319507c..8cd5f51e30 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -3,7 +3,8 @@ KBUILD_DEFCONFIG := erizo_generic_defconfig KBUILD_CPPFLAGS += -fno-strict-aliasing ifeq ($(CONFIG_ARCH_RV32I),y) - cflags-y += -march=rv32im + cflags-y += -march=rv32im -mabi=ilp32 + riscv-ldflags-y += -melf32lriscv endif cflags-y += -fno-pic -pipe @@ -14,6 +15,8 @@ LDFLAGS_barebox += -nostdlib machine-$(CONFIG_MACH_ERIZO) := erizo +LDFLAGS_barebox += $(riscv-ldflags-y) + TEXT_BASE = $(CONFIG_TEXT_BASE) KBUILD_CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE) diff --git a/arch/riscv/boot/dtb.c b/arch/riscv/boot/dtb.c index 5d73413a43..b9b68fc7f2 100644 --- a/arch/riscv/boot/dtb.c +++ b/arch/riscv/boot/dtb.c @@ -18,19 +18,7 @@ extern char __dtb_start[]; static int of_riscv_init(void) { - struct device_node *root; - - root = of_get_root_node(); - if (root) - return 0; - - root = of_unflatten_dtb(__dtb_start); - if (!IS_ERR(root)) { - pr_debug("using internal DTB\n"); - of_set_root_node(root); - if (IS_ENABLED(CONFIG_OFDEVICE)) - of_probe(); - } + barebox_register_fdt(__dtb_start); return 0; } diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 903fe8ff34..6bd4e5a925 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,13 +1,12 @@ BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) ifneq ($(BUILTIN_DTB),) -obj-dtb-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o +obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o endif -obj-dtb-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o +obj-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o # just to build a built-in.o. Otherwise compilation fails when no devicetree is # created. obj- += dummy.o -always := $(dtb-y) clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts diff --git a/arch/riscv/include/asm/debug_ll_ns16550.h b/arch/riscv/include/asm/debug_ll_ns16550.h index e891cbda25..f1c2ccbd0a 100644 --- a/arch/riscv/include/asm/debug_ll_ns16550.h +++ b/arch/riscv/include/asm/debug_ll_ns16550.h @@ -88,14 +88,14 @@ static inline void debug_ll_ns16550_init(void) * Macros for use in assembly language code */ -.macro debug_ll_ns16550_init +.macro debug_ll_ns16550_init divisor=DEBUG_LL_UART_DIVISOR #ifdef CONFIG_DEBUG_LL li t0, DEBUG_LL_UART_ADDR li t1, UART_LCR_DLAB /* DLAB on */ UART_REG_S t1, UART_LCR(t0) /* Write it out */ - li t1, DEBUG_LL_UART_DIVISOR + li t1, \divisor UART_REG_S t1, UART_DLL(t0) /* write low order byte */ srl t1, t1, 8 UART_REG_S t1, UART_DLM(t0) /* write high order byte */ diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index 8200a03349..af37d7738c 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -1,6 +1,8 @@ #ifndef __ASM_RISCV_TYPES_H #define __ASM_RISCV_TYPES_H +#include <asm-generic/int-ll64.h> + #ifdef __riscv64 /* * This is used in dlmalloc. On RISCV64 we need it to be 64 bit @@ -15,44 +17,4 @@ #endif -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#include <asm/bitsperlong.h> - -#endif /* __KERNEL__ */ - #endif /* __ASM_RISCV_TYPES_H */ diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 6ec71a99e5..113b619fc3 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -1,9 +1,16 @@ +source "scripts/Kconfig.include" + config SANDBOX bool select OFTREE select GPIOLIB select ARCH_HAS_UBSAN_SANITIZE_ALL - select HAVE_ARCH_KASAN + select HAVE_ARCH_ASAN + select HAS_DMA + select BLOCK + select BLOCK_WRITE + select PARTITION_DISK + select ARCH_HAS_STACK_DUMP if ASAN default y config ARCH_TEXT_BASE @@ -15,8 +22,28 @@ config LINUX default y select GENERIC_FIND_NEXT_BIT -config SANDBOX_UNWIND +config SANDBOX_REEXEC + prompt "exec(2) reset handler" + def_bool y + help + The normal reset handler hangs barebox. On Linux, barebox + instead can exec itself to simulate a reset. + +config PHYS_ADDR_T_64BIT bool - default y - select ARCH_HAS_STACK_DUMP - depends on UBSAN || KASAN + +config CC_IS_64BIT + def_bool $(success,$(srctree)/scripts/gcc-64bitptr.sh $(CC)) + +config CC_HAS_LINUX_I386_SUPPORT + def_bool $(cc-option,-m32) && $(ld-option,-m elf_i386) + +config 64BIT + bool + default n if SANDBOX_LINUX_I386 + default CC_IS_64BIT + select ARCH_DMA_ADDR_T_64BIT + select PHYS_ADDR_T_64BIT + +config SANDBOX_LINUX_I386 + bool "32-bit x86 barebox" if CC_HAS_LINUX_I386_SUPPORT diff --git a/arch/sandbox/Makefile b/arch/sandbox/Makefile index 3d2eb5bc11..17f9a298d7 100644 --- a/arch/sandbox/Makefile +++ b/arch/sandbox/Makefile @@ -12,6 +12,7 @@ lds-y := $(BOARD)/barebox.lds TEXT_BASE = $(CONFIG_TEXT_BASE) KBUILD_CFLAGS += -Dmalloc=barebox_malloc -Dcalloc=barebox_calloc \ + -Dmalloc_stats=barebox_malloc_stats -Dmemalign=barebox_memalign \ -Dfree=barebox_free -Drealloc=barebox_realloc \ -Dread=barebox_read -Dwrite=barebox_write \ -Dopen=barebox_open -Dclose=barebox_close \ @@ -23,8 +24,9 @@ KBUILD_CFLAGS += -Dmalloc=barebox_malloc -Dcalloc=barebox_calloc \ -Dgetenv=barebox_getenv -Dprintf=barebox_printf \ -Dglob=barebox_glob -Dglobfree=barebox_globfree \ -Dioctl=barebox_ioctl -Dfstat=barebox_fstat \ + -Dftruncate=barebox_ftruncate -Dasprintf=barebox_asprintf \ -Dopendir=barebox_opendir -Dreaddir=barebox_readdir \ - -Dclosedir=barebox_closedir \ + -Dclosedir=barebox_closedir -Dreadlink=barebox_readlink \ -Doptarg=barebox_optarg -Doptind=barebox_optind machdirs := $(patsubst %,arch/sandbox/mach-%/,$(machine-y)) @@ -43,7 +45,7 @@ ifeq ($(CONFIG_GPIO_LIBFTDI1),y) FTDI1_LIBS := $(shell pkg-config libftdi1 --libs) endif -ifeq ($(CONFIG_KASAN),y) +ifeq ($(CONFIG_ASAN),y) KBUILD_CPPFLAGS += -fsanitize=address SANITIZER_LIBS += -fsanitize=address endif @@ -52,11 +54,21 @@ ifeq ($(CONFIG_UBSAN),y) SANITIZER_LIBS += -fsanitize=undefined endif -cmd_barebox__ = $(CC) -o $@ -Wl,-T,$(BAREBOX_LDS) \ - -Wl,--start-group $(BAREBOX_OBJS) -Wl,--end-group \ +ifeq ($(CONFIG_SANDBOX_LINUX_I386),y) +KBUILD_CFLAGS += -m32 +KBUILD_LDFLAGS += -m elf_i386 +KBUILD_AFLAGS += -m32 +BAREBOX_LDFLAGS += -m32 +endif + +BAREBOX_LDFLAGS += \ + -Wl,-T,$(BAREBOX_LDS) \ + -Wl,--whole-archive $(BAREBOX_OBJS) -Wl,--no-whole-archive \ -lrt -lpthread $(SDL_LIBS) $(FTDI1_LIBS) \ $(SANITIZER_LIBS) +cmd_barebox__ = $(CC) -o $@ $(BAREBOX_LDFLAGS) + common-y += $(BOARD) arch/sandbox/os/ arch/sandbox/lib/ common-$(CONFIG_OFTREE) += arch/sandbox/dts/ diff --git a/arch/sandbox/board/Makefile b/arch/sandbox/board/Makefile index 26f6cb1922..c504c967de 100644 --- a/arch/sandbox/board/Makefile +++ b/arch/sandbox/board/Makefile @@ -4,7 +4,8 @@ obj-y += hostfile.o obj-y += console.o obj-y += devices.o obj-y += dtb.o -obj-y += poweroff.o +obj-y += power.o obj-y += dev-random.o +obj-y += watchdog.o extra-y += barebox.lds diff --git a/arch/sandbox/board/devices.c b/arch/sandbox/board/devices.c index 72e62552a3..26152a8b90 100644 --- a/arch/sandbox/board/devices.c +++ b/arch/sandbox/board/devices.c @@ -9,6 +9,9 @@ #include <mach/linux.h> #include <init.h> #include <mach/linux.h> +#include <asm/io.h> + +unsigned char __pci_iobase[IO_SPACE_LIMIT]; static LIST_HEAD(sandbox_device_list); @@ -23,9 +26,6 @@ static int sandbox_device_init(void) { struct device_d *dev, *tmp; - barebox_set_model("barebox sandbox"); - barebox_set_hostname("barebox"); - list_for_each_entry_safe(dev, tmp, &sandbox_device_list, list) { /* reset the list_head before registering for real */ dev->list.prev = NULL; diff --git a/arch/sandbox/board/dtb.c b/arch/sandbox/board/dtb.c index 74ecbadf42..4a8cbfb26f 100644 --- a/arch/sandbox/board/dtb.c +++ b/arch/sandbox/board/dtb.c @@ -32,32 +32,14 @@ int barebox_register_dtb(const void *new_dtb) return 0; } +extern char __dtb_sandbox_start[]; + static int of_sandbox_init(void) { - struct device_node *root; - int ret; - - if (dtb) { - root = of_unflatten_dtb(dtb); - } else { - root = of_new_node(NULL, NULL); - - ret = of_property_write_u32(root, "#address-cells", 2); - if (ret) - return ret; - - ret = of_property_write_u32(root, "#size-cells", 1); - if (ret) - return ret; - } - - if (IS_ERR(root)) - return PTR_ERR(root); + if (!dtb) + dtb = __dtb_sandbox_start; - of_set_root_node(root); - of_fix_tree(root); - if (IS_ENABLED(CONFIG_OFDEVICE)) - of_probe(); + barebox_register_fdt(dtb); return 0; } diff --git a/arch/sandbox/board/env/init/state b/arch/sandbox/board/env/init/state new file mode 100644 index 0000000000..0b8e40409f --- /dev/null +++ b/arch/sandbox/board/env/init/state @@ -0,0 +1,12 @@ +if [ "x$state.dirty" != "x1" -o $global.system.reset != "POR" ]; then + exit +fi + +source /env/data/ansi-colors + +echo -e $CYAN +echo "******************************************************************" +echo "*** Inconsistent barebox state buckets detected on first boot ***" +echo "*** barebox will repair them on next shutdown ***" +echo "*****************************************************************" +echo -e -n $NC diff --git a/arch/sandbox/board/hostfile.c b/arch/sandbox/board/hostfile.c index 5f0d7e0a4b..e3e38b7119 100644 --- a/arch/sandbox/board/hostfile.c +++ b/arch/sandbox/board/hostfile.c @@ -16,6 +16,8 @@ #include <common.h> #include <driver.h> +#include <block.h> +#include <disks.h> #include <malloc.h> #include <mach/linux.h> #include <init.h> @@ -27,14 +29,16 @@ #include <linux/err.h> struct hf_priv { - struct cdev cdev; + union { + struct block_device blk; + struct cdev cdev; + }; const char *filename; int fd; }; -static ssize_t hf_read(struct cdev *cdev, void *buf, size_t count, loff_t offset, ulong flags) +static ssize_t hf_read(struct hf_priv *priv, void *buf, size_t count, loff_t offset, ulong flags) { - struct hf_priv *priv= cdev->priv; int fd = priv->fd; if (linux_lseek(fd, offset) != offset) @@ -43,9 +47,8 @@ static ssize_t hf_read(struct cdev *cdev, void *buf, size_t count, loff_t offset return linux_read(fd, buf, count); } -static ssize_t hf_write(struct cdev *cdev, const void *buf, size_t count, loff_t offset, ulong flags) +static ssize_t hf_write(struct hf_priv *priv, const void *buf, size_t count, loff_t offset, ulong flags) { - struct hf_priv *priv = cdev->priv; int fd = priv->fd; if (linux_lseek(fd, offset) != offset) @@ -54,6 +57,40 @@ static ssize_t hf_write(struct cdev *cdev, const void *buf, size_t count, loff_t return linux_write(fd, buf, count); } +static ssize_t hf_cdev_read(struct cdev *cdev, void *buf, size_t count, loff_t offset, ulong flags) +{ + return hf_read(cdev->priv, buf, count, offset, flags); +} + +static ssize_t hf_cdev_write(struct cdev *cdev, const void *buf, size_t count, loff_t offset, ulong flags) +{ + return hf_write(cdev->priv, buf, count, offset, flags); +} + +static struct cdev_operations hf_cdev_ops = { + .read = hf_cdev_read, + .write = hf_cdev_write, +}; + +static int hf_blk_read(struct block_device *blk, void *buf, int block, int num_blocks) +{ + ssize_t ret = hf_read(container_of(blk, struct hf_priv, blk), buf, + num_blocks << SECTOR_SHIFT, block << SECTOR_SHIFT, 0); + return ret > 0 ? 0 : ret; +} + +static int hf_blk_write(struct block_device *blk, const void *buf, int block, int num_blocks) +{ + ssize_t ret = hf_write(container_of(blk, struct hf_priv, blk), buf, + num_blocks << SECTOR_SHIFT, block << SECTOR_SHIFT, 0); + return ret > 0 ? 0 : ret; +} + +static struct block_device_ops hf_blk_ops = { + .read = hf_blk_read, + .write = hf_blk_write, +}; + static void hf_info(struct device_d *dev) { struct hf_priv *priv = dev->priv; @@ -61,50 +98,76 @@ static void hf_info(struct device_d *dev) printf("file: %s\n", priv->filename); } -static struct cdev_operations hf_fops = { - .read = hf_read, - .write = hf_write, -}; - static int hf_probe(struct device_d *dev) { + struct device_node *np = dev->device_node; struct hf_priv *priv = xzalloc(sizeof(*priv)); struct resource *res; + struct cdev *cdev; + bool is_blockdev; + resource_size_t size; int err; res = dev_get_resource(dev, IORESOURCE_MEM, 0); if (IS_ERR(res)) return PTR_ERR(res); - priv->cdev.size = resource_size(res); + size = resource_size(res); - if (!dev->device_node) + if (!np) return -ENODEV; - of_property_read_u32(dev->device_node, "barebox,fd", &priv->fd); + of_property_read_u32(np, "barebox,fd", &priv->fd); - err = of_property_read_string(dev->device_node, "barebox,filename", + err = of_property_read_string(np, "barebox,filename", &priv->filename); if (err) return err; - if (!priv->fd) - priv->fd = linux_open(priv->filename, true); - - priv->cdev.name = dev->device_node->name; - priv->cdev.dev = dev; - priv->cdev.ops = &hf_fops; - priv->cdev.priv = priv; + if (priv->fd < 0) + return priv->fd; dev->info = hf_info; dev->priv = priv; - err = devfs_create(&priv->cdev); - if (err) - return err; + is_blockdev = of_property_read_bool(np, "barebox,blockdev"); + + cdev = is_blockdev ? &priv->blk.cdev : &priv->cdev; + + cdev->device_node = np; + + if (is_blockdev) { + cdev->name = np->name; + priv->blk.dev = dev; + priv->blk.ops = &hf_blk_ops; + priv->blk.blockbits = SECTOR_SHIFT; + priv->blk.num_blocks = size / SECTOR_SIZE; + + err = blockdevice_register(&priv->blk); + if (err) + return err; + + err = parse_partition_table(&priv->blk); + if (err) + dev_warn(dev, "No partition table found\n"); + + dev_info(dev, "registered as block device\n"); + } else { + cdev->name = np->name; + cdev->dev = dev; + cdev->ops = &hf_cdev_ops; + cdev->size = size; + cdev->priv = priv; + + err = devfs_create(cdev); + if (err) + return err; + + dev_info(dev, "registered as character device\n"); + } - of_parse_partitions(&priv->cdev, dev->device_node); - of_partitions_register_fixup(&priv->cdev); + of_parse_partitions(cdev, np); + of_partitions_register_fixup(cdev); return 0; } @@ -122,39 +185,104 @@ static struct driver_d hf_drv = { .of_compatible = DRV_OF_COMPAT(hostfile_dt_ids), .probe = hf_probe, }; -coredevice_platform_driver(hf_drv); +device_platform_driver(hf_drv); static int of_hostfile_fixup(struct device_node *root, void *ctx) { struct hf_info *hf = ctx; struct device_node *node; - uint32_t reg[] = { - hf->base >> 32, - hf->base, - hf->size - }; + bool name_only = false; int ret; - node = of_new_node(root, hf->devname); + node = of_get_child_by_name(root, hf->devname); + if (node) + name_only = true; + else + node = of_new_node(root, hf->devname); - ret = of_property_write_string(node, "compatible", hostfile_dt_ids->compatible); + ret = of_property_write_string(node, "barebox,filename", hf->filename); if (ret) return ret; - ret = of_property_write_u32_array(node, "reg", reg, ARRAY_SIZE(reg)); + if (name_only) + return 0; + + ret = of_property_write_string(node, "compatible", hostfile_dt_ids->compatible); if (ret) return ret; - ret = of_property_write_u32(node, "barebox,fd", hf->fd); + ret = of_property_write_bool(node, "barebox,blockdev", hf->is_blockdev); if (ret) return ret; - ret = of_property_write_string(node, "barebox,filename", hf->filename); + ret = of_property_write_bool(node, "barebox,cdev", hf->is_cdev); + if (ret) + return ret; - return ret; + return of_property_write_bool(node, "barebox,read-only", hf->is_readonly); } int barebox_register_filedev(struct hf_info *hf) { return of_register_fixup(of_hostfile_fixup, hf); } + +static int of_hostfile_map_fixup(struct device_node *root, void *ctx) +{ + struct device_node *node; + int ret; + + for_each_compatible_node_from(node, root, NULL, hostfile_dt_ids->compatible) { + struct hf_info hf = {}; + uint64_t reg[2] = {}; + bool no_filename; + + hf.devname = node->name; + + ret = of_property_read_string(node, "barebox,filename", &hf.filename); + no_filename = ret; + + hf.is_blockdev = of_property_read_bool(node, "barebox,blockdev"); + hf.is_cdev = of_property_read_bool(node, "barebox,cdev"); + hf.is_readonly = of_property_read_bool(node, "barebox,read-only"); + + of_property_read_u64_array(node, "reg", reg, ARRAY_SIZE(reg)); + + hf.base = reg[0]; + hf.size = reg[1]; + + ret = linux_open_hostfile(&hf); + if (ret) + goto out; + + reg[0] = hf.base; + reg[1] = hf.size; + + ret = of_property_write_u64_array(node, "reg", reg, ARRAY_SIZE(reg)); + if (ret) + goto out; + + ret = of_property_write_bool(node, "barebox,blockdev", hf.is_blockdev); + if (ret) + goto out; + + if (no_filename) { + ret = of_property_write_string(node, "barebox,filename", hf.filename); + if (ret) + goto out; + } + + ret = of_property_write_u32(node, "barebox,fd", hf.fd); +out: + if (ret) + pr_err("error fixing up %s: %pe\n", hf.devname, ERR_PTR(ret)); + } + + return 0; +} + +static int barebox_fixup_filedevs(void) +{ + return of_register_fixup(of_hostfile_map_fixup, NULL); +} +pure_initcall(barebox_fixup_filedevs); diff --git a/arch/sandbox/board/power.c b/arch/sandbox/board/power.c new file mode 100644 index 0000000000..3cc9447958 --- /dev/null +++ b/arch/sandbox/board/power.c @@ -0,0 +1,82 @@ +#include <common.h> +#include <driver.h> +#include <poweroff.h> +#include <restart.h> +#include <mach/linux.h> +#include <reset_source.h> +#include <mfd/syscon.h> + +struct sandbox_power { + struct restart_handler rst_hang, rst_reexec; + struct regmap *src; + u32 src_offset; +}; + +static void sandbox_poweroff(struct poweroff_handler *poweroff) +{ + linux_exit(); +} + +static void sandbox_rst_hang(struct restart_handler *rst) +{ + linux_hang(); +} + +static void sandbox_rst_reexec(struct restart_handler *rst) +{ + struct sandbox_power *power = container_of(rst, struct sandbox_power, rst_reexec); + regmap_update_bits(power->src, power->src_offset, 0xff, RESET_RST); + linux_reexec(); +} + +static int sandbox_power_probe(struct device_d *dev) +{ + struct sandbox_power *power = xzalloc(sizeof(*power)); + unsigned int rst; + int ret; + + poweroff_handler_register_fn(sandbox_poweroff); + + power->rst_hang = (struct restart_handler) { + .name = "hang", + .restart = sandbox_rst_hang + }; + + power->rst_reexec = (struct restart_handler) { + .name = "reexec", .priority = 200, + .restart = sandbox_rst_reexec, + }; + + restart_handler_register(&power->rst_hang); + + if (IS_ENABLED(CONFIG_SANDBOX_REEXEC)) + restart_handler_register(&power->rst_reexec); + + power->src = syscon_regmap_lookup_by_phandle(dev->device_node, "barebox,reset-source"); + if (IS_ERR(power->src)) + return 0; + + ret = of_property_read_u32_index(dev->device_node, "barebox,reset-source", 1, + &power->src_offset); + if (ret) + return 0; + + ret = regmap_read(power->src, power->src_offset, &rst); + if (ret == 0 && rst == 0) + rst = RESET_POR; + + reset_source_set_prinst(rst, RESET_SOURCE_DEFAULT_PRIORITY, 0); + return 0; +} + +static __maybe_unused struct of_device_id sandbox_power_dt_ids[] = { + { .compatible = "barebox,sandbox-power" }, + { /* sentinel */ } +}; + +static struct driver_d sandbox_power_drv = { + .name = "sandbox-power", + .of_compatible = sandbox_power_dt_ids, + .probe = sandbox_power_probe, +}; +coredevice_platform_driver(sandbox_power_drv); diff --git a/arch/sandbox/board/poweroff.c b/arch/sandbox/board/poweroff.c deleted file mode 100644 index 6b5a6dff15..0000000000 --- a/arch/sandbox/board/poweroff.c +++ /dev/null @@ -1,17 +0,0 @@ -#include <common.h> -#include <init.h> -#include <poweroff.h> -#include <mach/linux.h> - -static void sandbox_poweroff(struct poweroff_handler *poweroff) -{ - linux_exit(); -} - -static int poweroff_register_feature(void) -{ - poweroff_handler_register_fn(sandbox_poweroff); - - return 0; -} -coredevice_initcall(poweroff_register_feature); diff --git a/arch/sandbox/board/watchdog.c b/arch/sandbox/board/watchdog.c new file mode 100644 index 0000000000..336451282f --- /dev/null +++ b/arch/sandbox/board/watchdog.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <errno.h> +#include <driver.h> +#include <mach/linux.h> +#include <of.h> +#include <watchdog.h> +#include <mfd/syscon.h> +#include <reset_source.h> + +struct sandbox_watchdog { + struct watchdog wdd; + bool cant_disable :1; +}; + +static inline struct sandbox_watchdog *to_sandbox_watchdog(struct watchdog *wdd) +{ + return container_of(wdd, struct sandbox_watchdog, wdd); +} + +static int sandbox_watchdog_set_timeout(struct watchdog *wdd, unsigned int timeout) +{ + struct sandbox_watchdog *wd = to_sandbox_watchdog(wdd); + + if (!timeout && wd->cant_disable) + return -ENOSYS; + + if (timeout > wdd->timeout_max) + return -EINVAL; + + return linux_watchdog_set_timeout(timeout); +} + +static int sandbox_watchdog_probe(struct device_d *dev) +{ + struct device_node *np = dev->device_node; + struct sandbox_watchdog *wd; + struct watchdog *wdd; + struct regmap *src; + u32 src_offset; + int ret; + + wd = xzalloc(sizeof(*wd)); + + wdd = &wd->wdd; + wdd->hwdev = dev; + wdd->set_timeout = sandbox_watchdog_set_timeout; + wdd->timeout_max = 1000; + + wd->cant_disable = of_property_read_bool(np, "barebox,cant-disable"); + + ret = watchdog_register(wdd); + if (ret) { + dev_err(dev, "Failed to register watchdog device\n"); + return ret; + } + + src = syscon_regmap_lookup_by_phandle(np, "barebox,reset-source"); + if (IS_ERR(src)) + return 0; + + ret = of_property_read_u32_index(np, "barebox,reset-source", 1, &src_offset); + if (ret) + return 0; + + regmap_update_bits(src, src_offset, 0xff, RESET_WDG); + + dev_info(dev, "probed\n"); + return 0; +} + + +static __maybe_unused struct of_device_id sandbox_watchdog_dt_ids[] = { + { .compatible = "barebox,sandbox-watchdog" }, + { /* sentinel */ } +}; + +static struct driver_d sandbox_watchdog_drv = { + .name = "sandbox-watchdog", + .of_compatible = sandbox_watchdog_dt_ids, + .probe = sandbox_watchdog_probe, +}; +device_platform_driver(sandbox_watchdog_drv); diff --git a/arch/sandbox/configs/hosttools_defconfig b/arch/sandbox/configs/hosttools_defconfig new file mode 100644 index 0000000000..72ec0fc462 --- /dev/null +++ b/arch/sandbox/configs/hosttools_defconfig @@ -0,0 +1,7 @@ +CONFIG_IMD=y +CONFIG_COMPILE_HOST_TOOLS=y +CONFIG_ARCH_IMX_USBLOADER=y +CONFIG_MVEBU_HOSTTOOLS=y +CONFIG_MXS_HOSTTOOLS=y +CONFIG_OMAP3_USB_LOADER=y +CONFIG_OMAP4_HOSTTOOL_USBBOOT=y diff --git a/arch/sandbox/configs/sandbox_defconfig b/arch/sandbox/configs/sandbox_defconfig index c343f053fa..ca24d81aca 100644 --- a/arch/sandbox/configs/sandbox_defconfig +++ b/arch/sandbox/configs/sandbox_defconfig @@ -2,20 +2,34 @@ CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y +CONFIG_CONSOLE_ALLOW_COLOR=y CONFIG_PARTITION=y +CONFIG_PARTITION_DISK_EFI=y CONFIG_DEFAULT_COMPRESSION_GZIP=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW_REBOOT_MODE=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/sandbox/board/env" +CONFIG_STATE=y +CONFIG_STATE_CRYPTO=y +CONFIG_RESET_SOURCE=y CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y CONFIG_CMD_IMD=y CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_BOOTM is not set +CONFIG_CMD_POLLER=y +CONFIG_CMD_SLICE=y CONFIG_CMD_GO=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_RESET=y +CONFIG_CMD_SAVES=y CONFIG_CMD_UIMAGE=y CONFIG_CMD_PARTITION=y CONFIG_CMD_EXPORT=y CONFIG_CMD_DEFAULTENV=y +CONFIG_CMD_LOADENV=y CONFIG_CMD_PRINTENV=y CONFIG_CMD_MAGICVAR=y CONFIG_CMD_MAGICVAR_HELP=y @@ -39,14 +53,18 @@ CONFIG_CMD_PING=y CONFIG_CMD_TFTP=y CONFIG_CMD_ECHO_E=y CONFIG_CMD_EDIT=y +CONFIG_CMD_LOGIN=y CONFIG_CMD_MENU=y CONFIG_CMD_MENU_MANAGEMENT=y CONFIG_CMD_MENUTREE=y +CONFIG_CMD_PASSWD=y CONFIG_CMD_SPLASH=y +CONFIG_CMD_FBTEST=y CONFIG_CMD_READLINE=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_CRC=y CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_MM=y CONFIG_CMD_DETECT=y CONFIG_CMD_FLASH=y @@ -56,18 +74,31 @@ CONFIG_CMD_LED=y CONFIG_CMD_POWEROFF=y CONFIG_CMD_SPI=y CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_WD=y CONFIG_CMD_2048=y +CONFIG_CMD_KEYSTORE=y +CONFIG_CMD_LINUX_EXEC=y +CONFIG_CMD_OF_DIFF=y CONFIG_CMD_OF_NODE=y CONFIG_CMD_OF_PROPERTY=y CONFIG_CMD_OF_DISPLAY_TIMINGS=y +CONFIG_CMD_OF_FIXUP_STATUS=y +CONFIG_CMD_OF_OVERLAY=y CONFIG_CMD_OFTREE=y CONFIG_CMD_TIME=y +CONFIG_CMD_STATE=y +CONFIG_CMD_DHRYSTONE=y CONFIG_CMD_SPD_DECODE=y +CONFIG_CMD_SEED=y CONFIG_NET=y CONFIG_NET_NFS=y CONFIG_NET_NETCONSOLE=y +CONFIG_NET_SNTP=y +CONFIG_NET_FASTBOOT=y CONFIG_OFDEVICE=y CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_OF_BAREBOX_ENV_IN_FS=y +CONFIG_OF_OVERLAY_LIVE=y CONFIG_DRIVER_NET_TAP=y CONFIG_DRIVER_SPI_GPIO=y CONFIG_I2C=y @@ -76,6 +107,9 @@ CONFIG_MTD=y CONFIG_MTD_M25P80=y CONFIG_VIDEO=y CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_MFD_SYSCON=y +CONFIG_STATE_DRV=y +CONFIG_UBOOTVAR=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_LED_GPIO_OF=y @@ -84,9 +118,12 @@ CONFIG_LED_GPIO_BICOLOR=y CONFIG_LED_TRIGGERS=y CONFIG_EEPROM_AT25=y CONFIG_EEPROM_AT24=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_POLLER=y # CONFIG_PINCTRL is not set CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y +CONFIG_SYSCON_REBOOT_MODE=y CONFIG_FS_CRAMFS=y CONFIG_FS_EXT4=y CONFIG_FS_TFTP=y @@ -94,12 +131,17 @@ CONFIG_FS_NFS=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y +CONFIG_FS_JFFS2=y CONFIG_FS_BPKFS=y CONFIG_FS_UIMAGEFS=y +CONFIG_FS_PSTORE=y +CONFIG_FS_PSTORE_CONSOLE=y CONFIG_FS_SQUASHFS=y +CONFIG_FS_UBOOTVARFS=y CONFIG_BZLIB=y CONFIG_LZ4_DECOMPRESS=y CONFIG_XZ_DECOMPRESS=y +CONFIG_BASE64=y CONFIG_LZO_DECOMPRESS=y CONFIG_BMP=y CONFIG_PNG=y @@ -112,4 +154,3 @@ CONFIG_BAREBOX_LOGO_240=y CONFIG_BAREBOX_LOGO_320=y CONFIG_BAREBOX_LOGO_400=y CONFIG_BAREBOX_LOGO_640=y -CONFIG_DIGEST_HMAC_GENERIC=y diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile index 6f68388578..c8d83141ce 100644 --- a/arch/sandbox/dts/Makefile +++ b/arch/sandbox/dts/Makefile @@ -1,11 +1,8 @@ -ifeq ($(CONFIG_OFTREE),y) -dtb-y += \ - sandbox.dtb -endif +obj-$(CONFIG_OFTREE) += \ + sandbox.dtb.o # just to build a built-in.o. Otherwise compilation fails when no devicetree is # created. obj- += dummy.o -always := $(dtb-y) clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts diff --git a/arch/sandbox/dts/sandbox-state-example.dtsi b/arch/sandbox/dts/sandbox-state-example.dtsi deleted file mode 100644 index fc17bd0788..0000000000 --- a/arch/sandbox/dts/sandbox-state-example.dtsi +++ /dev/null @@ -1,50 +0,0 @@ -/ { - aliases { - state = &state; - }; - - disk { - compatible = "barebox,hostfile"; - barebox,filename = "disk"; - reg = <0x0 0x0 0x100000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - hostfile_state: state@0 { - reg = <0x0 0x1000>; - label = "state"; - }; - }; - }; - - state: state { - magic = <0xaa3b86a6>; - compatible = "barebox,state"; - backend-type = "raw"; - backend = <&hostfile_state>; - backend-storage-type = "direct"; - backend-stridesize = <64>; - - #address-cells = <1>; - #size-cells = <1>; - vars { - #address-cells = <1>; - #size-cells = <1>; - - x { - reg = <0x0 0x4>; - type = "uint32"; - default = <1>; - }; - - y { - reg = <0x4 0x4>; - type = "uint32"; - default = <3>; - }; - }; - }; -}; diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 2595aa13fa..afe48154c4 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -1,7 +1,97 @@ /dts-v1/; -#include "skeleton.dtsi" - / { + model = "Sandbox"; + compatible = "barebox,sandbox"; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + bmode = &bmode; + state = &state; + }; + + chosen { + environment { + compatible = "barebox,environment"; + device-path = &part_env; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0 0 0>; + }; + + state: state { + magic = <0xaa3b86a6>; + compatible = "barebox,state"; + backend-type = "raw"; + backend = <&part_state>; + backend-storage-type = "direct"; + backend-stridesize = <64>; + + #address-cells = <1>; + #size-cells = <1>; + + vars { + #address-cells = <1>; + #size-cells = <1>; + + x { + reg = <0x0 0x4>; + type = "uint32"; + default = <1>; + }; + + y { + reg = <0x4 0x4>; + type = "uint32"; + default = <3>; + }; + }; + }; + + stickypage: stickypage { + compatible = "barebox,hostfile", "syscon", "simple-mfd"; + reg = <0 0 0 4096>; + barebox,cdev; /* no caching allowed */ + + bmode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0>; + mask = <0xffffff00>; + mode-normal = <0x00000000>; + mode-loader = <0xbbbbbb00>; + }; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* 0x00+4 reserved for syscon use */ + + part_env: env@400 { + reg = <0x400 0x800>; + label = "env"; + }; + + part_state: state@800 { + reg = <0xC00 0x400>; + label = "state"; + }; + }; + }; + + power { + compatible = "barebox,sandbox-power"; + barebox,reset-source = <&stickypage 0>; + }; + watchdog { + compatible = "barebox,sandbox-watchdog"; + barebox,reset-source = <&stickypage 0>; + }; }; diff --git a/arch/sandbox/dts/skeleton.dtsi b/arch/sandbox/dts/skeleton.dtsi deleted file mode 100644 index 38ead821bb..0000000000 --- a/arch/sandbox/dts/skeleton.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Skeleton device tree; the bare minimum needed to boot; just include and - * add a compatible value. The bootloader will typically populate the memory - * node. - */ - -/ { - #address-cells = <2>; - #size-cells = <1>; - chosen { }; - aliases { }; - memory { device_type = "memory"; reg = <0 0 0>; }; -}; diff --git a/arch/sandbox/include/asm/atomic.h b/arch/sandbox/include/asm/atomic.h new file mode 100644 index 0000000000..af12dee130 --- /dev/null +++ b/arch/sandbox/include/asm/atomic.h @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <asm-generic/atomic.h> diff --git a/arch/sandbox/include/asm/bitsperlong.h b/arch/sandbox/include/asm/bitsperlong.h index 00c1fc2625..6dc0bb0c13 100644 --- a/arch/sandbox/include/asm/bitsperlong.h +++ b/arch/sandbox/include/asm/bitsperlong.h @@ -1,10 +1 @@ -#ifndef __ASM_BITSPERLONG_H -#define __ASM_BITSPERLONG_H - -#ifdef __x86_64__ -#define BITS_PER_LONG 64 -#else -#define BITS_PER_LONG 32 -#endif - -#endif /* __ASM_BITSPERLONG_H */ +#include <asm-generic/bitsperlong.h> diff --git a/arch/sandbox/include/asm/dma.h b/arch/sandbox/include/asm/dma.h index 459536779e..5e72d8e7df 100644 --- a/arch/sandbox/include/asm/dma.h +++ b/arch/sandbox/include/asm/dma.h @@ -8,6 +8,57 @@ #ifndef __ASM_DMA_H #define __ASM_DMA_H -/* empty*/ +#include <linux/kernel.h> +#include <linux/string.h> +#include <driver.h> + +#define dma_alloc dma_alloc +static inline void *dma_alloc(size_t size) +{ + return xmemalign(64, ALIGN(size, 64)); +} + +static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle) +{ + void *ret = xmemalign(4096, size); + if (dma_handle) + *dma_handle = (dma_addr_t)ret; + + memset(ret, 0, size); + + return ret; +} + +static inline void *dma_alloc_writecombine(size_t size, dma_addr_t *dma_handle) +{ + return dma_alloc_coherent(size, dma_handle); +} + +static inline void dma_free_coherent(void *mem, dma_addr_t dma_handle, + size_t size) +{ + free(mem); +} + +static inline dma_addr_t dma_map_single(struct device_d *dev, void *ptr, size_t size, + enum dma_data_direction dir) +{ + return (dma_addr_t)ptr; +} + +static inline void dma_unmap_single(struct device_d *dev, dma_addr_t addr, size_t size, + enum dma_data_direction dir) +{ +} + +static inline void dma_sync_single_for_cpu(dma_addr_t address, size_t size, + enum dma_data_direction dir) +{ +} + +static inline void dma_sync_single_for_device(dma_addr_t address, size_t size, + enum dma_data_direction dir) +{ +} #endif /* __ASM_DMA_H */ diff --git a/arch/sandbox/include/asm/elf.h b/arch/sandbox/include/asm/elf.h index 3939336ccb..e71a60aeb9 100644 --- a/arch/sandbox/include/asm/elf.h +++ b/arch/sandbox/include/asm/elf.h @@ -3,7 +3,6 @@ #if __SIZEOF_POINTER__ == 8 #define ELF_CLASS ELFCLASS64 -#define CONFIG_PHYS_ADDR_T_64BIT #else #define ELF_CLASS ELFCLASS32 #endif diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index cb891df5c8..9f9cd3a42a 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -1,8 +1,23 @@ #ifndef __ASM_SANDBOX_IO_H #define __ASM_SANDBOX_IO_H -#define IO_SPACE_LIMIT 0 +#define IO_SPACE_LIMIT 0xffff +/* pacify static analyzers */ +#define PCI_IOBASE ((void __iomem *)__pci_iobase) + +extern unsigned char __pci_iobase[IO_SPACE_LIMIT]; #include <asm-generic/io.h> +#include <asm-generic/bitio.h> + +static inline void *phys_to_virt(unsigned long phys) +{ + return (void *)phys; +} + +static inline unsigned long virt_to_phys(volatile void *mem) +{ + return (unsigned long)mem; +} #endif /* __ASM_SANDBOX_IO_H */ diff --git a/arch/sandbox/include/asm/types.h b/arch/sandbox/include/asm/types.h index 8426de4cc2..7b356a99eb 100644 --- a/arch/sandbox/include/asm/types.h +++ b/arch/sandbox/include/asm/types.h @@ -1,59 +1,6 @@ -#ifndef __ASM_I386_TYPES_H -#define __ASM_I386_TYPES_H +#ifndef __ASM_SANDBOX_TYPES_H +#define __ASM_SANDBOX_TYPES_H -#ifdef __x86_64__ -/* - * This is used in dlmalloc. On X86_64 we need it to be - * 64 bit - */ -#define INTERNAL_SIZE_T unsigned long - -/* - * This is a Kconfig variable in the Kernel, but we want to detect - * this during compile time, so we set it here. - */ -#define CONFIG_PHYS_ADDR_T_64BIT - -#endif - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#include <asm/bitsperlong.h> - -#endif /* __KERNEL__ */ +#include <asm-generic/int-ll64.h> #endif diff --git a/arch/sandbox/lib/unwind.c b/arch/sandbox/lib/unwind.c index 15a2798cc4..f46365ac2b 100644 --- a/arch/sandbox/lib/unwind.c +++ b/arch/sandbox/lib/unwind.c @@ -7,5 +7,5 @@ void __sanitizer_print_stack_trace(void); void dump_stack(void) { - __sanitizer_print_stack_trace(); + __sanitizer_print_stack_trace(); } diff --git a/arch/sandbox/mach-sandbox/include/mach/hostfile.h b/arch/sandbox/mach-sandbox/include/mach/hostfile.h index 54f690be5f..3ef34bcc1c 100644 --- a/arch/sandbox/mach-sandbox/include/mach/hostfile.h +++ b/arch/sandbox/mach-sandbox/include/mach/hostfile.h @@ -4,9 +4,12 @@ struct hf_info { int fd; unsigned long long base; - size_t size; + unsigned long long size; const char *devname; const char *filename; + unsigned int is_blockdev:1; + unsigned int is_cdev:1; + unsigned int is_readonly:1; }; int barebox_register_filedev(struct hf_info *hf); diff --git a/arch/sandbox/mach-sandbox/include/mach/linux.h b/arch/sandbox/mach-sandbox/include/mach/linux.h index 9759a376ec..b26bfc24a2 100644 --- a/arch/sandbox/mach-sandbox/include/mach/linux.h +++ b/arch/sandbox/mach-sandbox/include/mach/linux.h @@ -1,6 +1,8 @@ #ifndef __ASM_ARCH_LINUX_H #define __ASM_ARCH_LINUX_H +struct hf_info; + struct device_d; int sandbox_add_device(struct device_d *dev); @@ -11,15 +13,20 @@ int linux_register_device(const char *name, void *start, void *end); int tap_alloc(const char *dev); uint64_t linux_get_time(void); int linux_open(const char *filename, int readwrite); +int linux_open_hostfile(struct hf_info *hf); int linux_read(int fd, void *buf, size_t count); int linux_read_nonblock(int fd, void *buf, size_t count); ssize_t linux_write(int fd, const void *buf, size_t count); off_t linux_lseek(int fildes, off_t offset); int linux_tstc(int fd); void __attribute__((noreturn)) linux_exit(void); +void linux_hang(void); +void linux_reexec(void); int linux_execve(const char * filename, char *const argv[], char *const envp[]); +int linux_watchdog_set_timeout(unsigned int timeout); + int barebox_register_console(int stdinfd, int stdoutfd); int barebox_register_dtb(const void *dtb); diff --git a/arch/sandbox/os/Makefile b/arch/sandbox/os/Makefile index c012c9cf01..15d688bfdd 100644 --- a/arch/sandbox/os/Makefile +++ b/arch/sandbox/os/Makefile @@ -7,9 +7,15 @@ KBUILD_CPPFLAGS = $(patsubst %,-I$(srctree)/%include,$(machdirs)) KBUILD_CPPFLAGS += -DCONFIG_MALLOC_SIZE=$(CONFIG_MALLOC_SIZE) KBUILD_CFLAGS := -Wall + NOSTDINC_FLAGS := +ifeq ($(CONFIG_SANDBOX_LINUX_I386),y) +KBUILD_CFLAGS += -m32 +endif + obj-y = common.o tap.o +obj-$(CONFIG_MALLOC_LIBC) += libc_malloc.o CFLAGS_sdl.o = $(shell pkg-config sdl --cflags) obj-$(CONFIG_DRIVER_VIDEO_SDL) += sdl.o diff --git a/arch/sandbox/os/common.c b/arch/sandbox/os/common.c index e67ea14138..da87be29c7 100644 --- a/arch/sandbox/os/common.c +++ b/arch/sandbox/os/common.c @@ -19,6 +19,7 @@ * These are host includes. Never include any barebox header * files here... */ +#define _GNU_SOURCE #include <stdio.h> #include <stdlib.h> #include <stdint.h> @@ -38,12 +39,18 @@ #include <sys/wait.h> #include <sys/ioctl.h> #include <linux/fs.h> +#include <sys/time.h> +#include <signal.h> /* * ...except the ones needed to connect with barebox */ #include <mach/linux.h> #include <mach/hostfile.h> +#define DELETED_OFFSET (sizeof(" (deleted)") - 1) + +void __sanitizer_set_death_callback(void (*callback)(void)); + int sdl_xres; int sdl_yres; @@ -120,9 +127,41 @@ void __attribute__((noreturn)) linux_exit(void) exit(0); } +static size_t saved_argv_len; +static char **saved_argv; + +void linux_reexec(void) +{ + char buf[4097]; + ssize_t ret; + + cookmode(); + + /* we must follow the symlink, so we can exec an updated executable */ + ret = readlink("/proc/self/exe", buf, sizeof(buf) - 1); + if (0 < ret && ret < sizeof(buf) - 1) { + buf[ret] = '\0'; + execv(buf, saved_argv); + if (!strcmp(&buf[ret - DELETED_OFFSET], " (deleted)")) { + printf("barebox image on disk changed. Loading new.\n"); + buf[ret - DELETED_OFFSET] = '\0'; + execv(buf, saved_argv); + } + } + + printf("exec(%s) failed: %d\n", buf, errno); + /* falls through to generic hang() */ +} + +void linux_hang(void) +{ + cookmode(); + /* falls through to generic hang() */ +} + int linux_open(const char *filename, int readwrite) { - return open(filename, readwrite ? O_RDWR : O_RDONLY); + return open(filename, (readwrite ? O_RDWR : O_RDONLY) | O_CLOEXEC); } int linux_read(int fd, void *buf, size_t count) @@ -207,44 +246,125 @@ int linux_execve(const char * filename, char *const argv[], char *const envp[]) } } +static void linux_watchdog(int signo) +{ + linux_reexec(); + _exit(0); +} + +int linux_watchdog_set_timeout(unsigned int timeout) +{ + static int signal_handler_installed; + + if (!signal_handler_installed) { + struct sigaction sact = { + .sa_flags = SA_NODEFER, .sa_handler = linux_watchdog + }; + + sigemptyset(&sact.sa_mask); + sigaction(SIGALRM, &sact, NULL); + signal_handler_installed = 1; + } + + return alarm(timeout); +} + extern void start_barebox(void); extern void mem_malloc_init(void *start, void *end); -static int add_image(char *str, char *devname_template, int *devname_number) +extern char * strsep_unescaped(char **s, const char *ct); + +static int add_image(const char *_str, char *devname_template, int *devname_number) { struct hf_info *hf = malloc(sizeof(struct hf_info)); - char *filename, *devname; + char *str, *filename, *devname; char tmp[16]; - int readonly = 0; - struct stat s; char *opt; - int fd, ret; + int ret; if (!hf) return -1; - filename = strtok(str, ","); - while ((opt = strtok(NULL, ","))) { + str = strdup(_str); + + filename = strsep_unescaped(&str, ","); + while ((opt = strsep_unescaped(&str, ","))) { if (!strcmp(opt, "ro")) - readonly = 1; + hf->is_readonly = 1; + if (!strcmp(opt, "cdev")) + hf->is_cdev = 1; + if (!strcmp(opt, "blkdev")) + hf->is_blockdev = 1; } /* parses: "devname=filename" */ - devname = strtok(filename, "="); - filename = strtok(NULL, "="); + devname = strsep_unescaped(&filename, "="); + filename = strsep_unescaped(&filename, "="); if (!filename) { filename = devname; snprintf(tmp, sizeof(tmp), devname_template, (*devname_number)++); - devname = strdup(tmp); + devname = tmp; } - printf("add %s backed by file %s%s\n", devname, - filename, readonly ? "(ro)" : ""); - - fd = open(filename, readonly ? O_RDONLY : O_RDWR); - hf->fd = fd; hf->filename = filename; + hf->devname = strdup(devname); + + ret = barebox_register_filedev(hf); + if (ret) + free(hf); + + return ret; +} + +int linux_open_hostfile(struct hf_info *hf) +{ + char *buf = NULL; + struct stat s; + int fd; + + printf("add %s %sbacked by file %s%s\n", hf->devname, + hf->filename ? "" : "initially un", hf->filename ?: "", + hf->is_readonly ? "(ro)" : ""); + + if (hf->filename) { + fd = hf->fd = open(hf->filename, (hf->is_readonly ? O_RDONLY : O_RDWR) | O_CLOEXEC); + } else { + char *filename; + int ret; + + ret = asprintf(&buf, "--image=%s=/tmp/barebox-hostfileXXXXXX", hf->devname); + if (ret < 0) { + perror("asprintf"); + goto err_out; + } + + filename = buf + strlen("--image==") + strlen(hf->devname); + + fd = hf->fd = mkstemp(filename); + if (fd >= 0) { + ret = fcntl(fd, F_SETFD, FD_CLOEXEC); + if (ret < 0) { + perror("fcntl"); + goto err_out; + } + + ret = ftruncate(fd, hf->size); + if (ret < 0) { + perror("ftruncate"); + goto err_out; + } + + hf->filename = filename; + + saved_argv = realloc(saved_argv, + ++saved_argv_len * sizeof(*saved_argv)); + if (!saved_argv) + exit(1); + saved_argv[saved_argv_len - 2] = buf; + saved_argv[saved_argv_len - 1] = NULL; + } + } if (fd < 0) { perror("open"); @@ -256,30 +376,41 @@ static int add_image(char *str, char *devname_template, int *devname_number) goto err_out; } + hf->base = (unsigned long)MAP_FAILED; hf->size = s.st_size; - hf->devname = strdup(devname); if (S_ISBLK(s.st_mode)) { if (ioctl(fd, BLKGETSIZE64, &hf->size) == -1) { perror("ioctl"); goto err_out; } + if (!hf->is_cdev) + hf->is_blockdev = 1; + } + if (hf->size <= SIZE_MAX) { + hf->base = (unsigned long)mmap(NULL, hf->size, + PROT_READ | (hf->is_readonly ? 0 : PROT_WRITE), + MAP_SHARED, fd, 0); + + if (hf->base == (unsigned long)MAP_FAILED) + printf("warning: mmapping %s failed: %s\n", + hf->filename, strerror(errno)); + } else { + printf("warning: %s: contiguous map failed\n", hf->filename); + } + + if (hf->is_blockdev && hf->size % 512 != 0) { + printf("warning: registering %s as block device failed: invalid block size\n", + hf->filename); + return -EINVAL; } - hf->base = (unsigned long)mmap(NULL, hf->size, - PROT_READ | (readonly ? 0 : PROT_WRITE), - MAP_SHARED, fd, 0); - if ((void *)hf->base == MAP_FAILED) - printf("warning: mmapping %s failed: %s\n", filename, strerror(errno)); - ret = barebox_register_filedev(hf); - if (ret) - goto err_out; return 0; err_out: if (fd > 0) close(fd); - free(hf); + free(buf); return -1; } @@ -289,7 +420,7 @@ static int add_dtb(const char *file) void *dtb = NULL; int fd; - fd = open(file, O_RDONLY); + fd = open(file, O_RDONLY | O_CLOEXEC); if (fd < 0) { perror("open"); goto err_out; @@ -345,6 +476,10 @@ int main(int argc, char *argv[]) int fdno = 0, envno = 0, option_index = 0; char *aux; +#ifdef CONFIG_ASAN + __sanitizer_set_death_callback(cookmode); +#endif + while (1) { option_index = 0; opt = getopt_long(argc, argv, optstring, @@ -382,6 +517,12 @@ int main(int argc, char *argv[]) } } + saved_argv_len = argc + 1; + saved_argv = calloc(saved_argv_len, sizeof(*saved_argv)); + if (!saved_argv) + exit(1); + memcpy(saved_argv, argv, saved_argv_len * sizeof(*saved_argv)); + ram = malloc(malloc_size); if (!ram) { printf("unable to get malloc space\n"); @@ -416,7 +557,7 @@ int main(int argc, char *argv[]) exit(1); break; case 'O': - fd = open(optarg, O_WRONLY); + fd = open(optarg, O_WRONLY | O_CLOEXEC); if (fd < 0) { perror("open"); exit(1); @@ -425,7 +566,7 @@ int main(int argc, char *argv[]) barebox_register_console(-1, fd); break; case 'I': - fd = open(optarg, O_RDWR); + fd = open(optarg, O_RDWR | O_CLOEXEC); if (fd < 0) { perror("open"); exit(1); @@ -441,7 +582,7 @@ int main(int argc, char *argv[]) } /* open stdout file */ - fd = open(aux + 1, O_WRONLY); + fd = open(aux + 1, O_WRONLY | O_CLOEXEC); if (fd < 0) { perror("open stdout"); exit(1); @@ -449,7 +590,7 @@ int main(int argc, char *argv[]) /* open stdin file */ aux = strndup(optarg, aux - optarg); - fd2 = open(aux, O_RDWR); + fd2 = open(aux, O_RDWR | O_CLOEXEC); if (fd2 < 0) { perror("open stdin"); exit(1); diff --git a/arch/sandbox/os/libc_malloc.c b/arch/sandbox/os/libc_malloc.c new file mode 100644 index 0000000000..74e3e26805 --- /dev/null +++ b/arch/sandbox/os/libc_malloc.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2020 Ahmad Fatoum <a.fatoum@pengutronix.de> + */ + +#include <stdlib.h> +#include <malloc.h> + +void barebox_malloc_stats(void) +{ +} + +void *barebox_memalign(size_t alignment, size_t bytes) +{ + return memalign(alignment, bytes); +} + +void *barebox_malloc(size_t size) +{ + return malloc(size); +} + +void barebox_free(void *ptr) +{ + free(ptr); +} + +void *barebox_realloc(void *ptr, size_t size) +{ + return realloc(ptr, size); +} + +void *barebox_calloc(size_t n, size_t elem_size) +{ + return calloc(n, elem_size); +} diff --git a/arch/sandbox/os/tap.c b/arch/sandbox/os/tap.c index 72b7fbb5ac..83b97ffd49 100644 --- a/arch/sandbox/os/tap.c +++ b/arch/sandbox/os/tap.c @@ -30,7 +30,7 @@ int tap_alloc(const char *dev) struct ifreq ifr; int fd, err; - if ((fd = open("/dev/net/tun", O_RDWR)) < 0) { + if ((fd = open("/dev/net/tun", O_RDWR | O_CLOEXEC)) < 0) { perror("could not open /dev/net/tun"); return -1; } diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 19009442a4..0e3e5d6187 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -25,6 +25,7 @@ menu "ARCH specific settings" config 64BIT def_bool y if X86_EFI + select ARCH_DMA_ADDR_T_64BIT help Say yes to build a 64-bit binary - formerly known as x86_64 Say no to build a 32-bit binary - formerly known as i386. diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 97f6d85f2f..61e51abc71 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -73,8 +73,8 @@ lds-$(CONFIG_X86_64) := arch/x86/mach-efi/elf_x86_64_efi.lds cmd_barebox__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_barebox) -o $@ \ -T $(lds-y) \ -shared -Bsymbolic -nostdlib -znocombreloc \ - --start-group $(BAREBOX_OBJS) \ - --end-group \ + --whole-archive $(BAREBOX_OBJS) \ + --no-whole-archive \ $(filter-out $(BAREBOX_LDS) $(BAREBOX_OBJS) FORCE ,$^) quiet_cmd_efi_image = EFI-IMG $@ diff --git a/arch/x86/bios/bios_disk.S b/arch/x86/bios/bios_disk.S index cce33e67af..c2a824ed6e 100644 --- a/arch/x86/bios/bios_disk.S +++ b/arch/x86/bios/bios_disk.S @@ -1,21 +1,8 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * Mostly stolen from the GRUB2 project - * Copyright (C) 1999,2000,2001,2002,2003,2004,2005,2006,2007,2008 Free Software Foundation, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix */ +/* SPDX-FileCopyrightText: 1999-2008 Free Software Foundation, Inc. */ + +/* Mostly stolen from the GRUB2 project */ /** * @file diff --git a/arch/x86/bios/memory16.S b/arch/x86/bios/memory16.S index 76ee72b56c..e4aef2f256 100644 --- a/arch/x86/bios/memory16.S +++ b/arch/x86/bios/memory16.S @@ -1,20 +1,7 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This code was inspired by the GRUB2 project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix */ + +/* This code was inspired by the GRUB2 project. */ /** * @file diff --git a/arch/x86/bios/traveler.S b/arch/x86/bios/traveler.S index 113b19802e..1c11c9dc74 100644 --- a/arch/x86/bios/traveler.S +++ b/arch/x86/bios/traveler.S @@ -1,20 +1,7 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * Mostly stolen from the GRUB2 project - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix */ + +/* Mostly stolen from the GRUB2 project */ /** * @file diff --git a/arch/x86/boards/x86_generic/disk_bios_drive.c b/arch/x86/boards/x86_generic/disk_bios_drive.c index f33f48c3fb..c8e9ae8523 100644 --- a/arch/x86/boards/x86_generic/disk_bios_drive.c +++ b/arch/x86/boards/x86_generic/disk_bios_drive.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix /** * @file diff --git a/arch/x86/boards/x86_generic/envsector.h b/arch/x86/boards/x86_generic/envsector.h index 86511c8af7..57a6d2a21f 100644 --- a/arch/x86/boards/x86_generic/envsector.h +++ b/arch/x86/boards/x86_generic/envsector.h @@ -1,16 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /** * @file diff --git a/arch/x86/boards/x86_generic/generic_pc.c b/arch/x86/boards/x86_generic/generic_pc.c index 482889f2d9..2f1db7aca1 100644 --- a/arch/x86/boards/x86_generic/generic_pc.c +++ b/arch/x86/boards/x86_generic/generic_pc.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix #include <common.h> #include <types.h> diff --git a/arch/x86/boards/x86_generic/intf_platform_ide.c b/arch/x86/boards/x86_generic/intf_platform_ide.c index 528e721d56..0db031484f 100644 --- a/arch/x86/boards/x86_generic/intf_platform_ide.c +++ b/arch/x86/boards/x86_generic/intf_platform_ide.c @@ -1,19 +1,6 @@ -/* - * Copyright (C) 2014 Juergen Beisert, Pengutronix, Michel Stam, - * Fugro Intersite - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Juergen Beisert, Pengutronix +// SPDX-FileCopyrightText: 2014 Michel Stam, Fugro Intersite /** * @file diff --git a/arch/x86/boards/x86_generic/serial_ns16550.c b/arch/x86/boards/x86_generic/serial_ns16550.c index abc1047a50..4159bc39fb 100644 --- a/arch/x86/boards/x86_generic/serial_ns16550.c +++ b/arch/x86/boards/x86_generic/serial_ns16550.c @@ -1,19 +1,6 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix, Michel Stam, - * Fugro Intersite - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix +// SPDX-FileCopyrightText: 2009 Michel Stam, Fugro Intersite /** * @file diff --git a/arch/x86/boot/a20.c b/arch/x86/boot/a20.c index ddb40ee5c2..f501feeedd 100644 --- a/arch/x86/boot/a20.c +++ b/arch/x86/boot/a20.c @@ -1,13 +1,9 @@ -/* -*- linux-c -*- ------------------------------------------------------- * - * - * Copyright (C) 1991, 1992 Linus Torvalds - * Copyright 2007-2008 rPath, Inc. - All Rights Reserved - * Copyright 2009 Intel Corporation; author H. Peter Anvin - * - * This file is part of the Linux kernel, and is made available under - * the terms of the GNU General Public License version 2. - * - * ----------------------------------------------------------------------- */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 1991,1992 Linus Torvalds +// SPDX-FileCopyrightText: 2007-2008 rPath, Inc. +// SPDX-FileCopyrightText: 2009 Intel Corporation + +/* Author: H. Peter Anvin and others */ /* * Enable A20 gate (return -1 on failure) diff --git a/arch/x86/boot/bioscall.S b/arch/x86/boot/bioscall.S index e60072992b..6cda1eb40a 100644 --- a/arch/x86/boot/bioscall.S +++ b/arch/x86/boot/bioscall.S @@ -1,12 +1,7 @@ -/* ----------------------------------------------------------------------- - * - * Copyright 2009 Intel Corporation; author H. Peter Anvin - * - * This file is part of the Linux kernel, and is made available under - * the terms of the GNU General Public License version 2 or (at your - * option) any later version; incorporated herein by reference. - * - * ----------------------------------------------------------------------- */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2009 Intel Corporation */ + +/* Author: H. Peter Anvin */ /* * "Glove box" for BIOS calls. Avoids the constant problems with BIOSes diff --git a/arch/x86/boot/boot.h b/arch/x86/boot/boot.h index d98b0661cd..54483c46c6 100644 --- a/arch/x86/boot/boot.h +++ b/arch/x86/boot/boot.h @@ -1,13 +1,9 @@ -/* -*- linux-c -*- ------------------------------------------------------- * - * - * Copyright (C) 1991, 1992 Linus Torvalds - * Copyright 2007 rPath, Inc. - All Rights Reserved - * Copyright 2009 Intel Corporation; author H. Peter Anvin - * - * This file is part of the Linux kernel, and is made available under - * the terms of the GNU General Public License version 2. - * - * ----------------------------------------------------------------------- */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 1991,1992 Linus Torvalds */ +/* SPDX-FileCopyrightText: 2007 rPath, Inc. */ +/* SPDX-FileCopyrightText: 2009 Intel Corporation */ + +/* Author: H. Peter Anvin and others */ /** * @file diff --git a/arch/x86/boot/boot_main.S b/arch/x86/boot/boot_main.S index a952c8d279..632b3f4ffa 100644 --- a/arch/x86/boot/boot_main.S +++ b/arch/x86/boot/boot_main.S @@ -1,20 +1,7 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This code was inspired by the GRUB2 project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: Juergen Beisert, Pengutronix */ + +/* This code was inspired by the GRUB2 project. */ /** * @file diff --git a/arch/x86/boot/main_entry.c b/arch/x86/boot/main_entry.c index afb7e32dfc..b37aa38fca 100644 --- a/arch/x86/boot/main_entry.c +++ b/arch/x86/boot/main_entry.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix /** * @file diff --git a/arch/x86/boot/pmjump.S b/arch/x86/boot/pmjump.S index 09bfc6ea86..4dd1881e65 100644 --- a/arch/x86/boot/pmjump.S +++ b/arch/x86/boot/pmjump.S @@ -1,12 +1,6 @@ -/* ----------------------------------------------------------------------- * - * - * Copyright (C) 1991, 1992 Linus Torvalds - * Copyright 2007 rPath, Inc. - All Rights Reserved - * - * This file is part of the Linux kernel, and is made available under - * the terms of the GNU General Public License version 2. - * - * ----------------------------------------------------------------------- */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 1991,1992 Linus Torvalds */ +/* SPDX-FileCopyrightText: 2007 rPath, Inc. */ /** * @file diff --git a/arch/x86/boot/prepare_uboot.c b/arch/x86/boot/prepare_uboot.c index 79e6fb0cbe..9cac594a46 100644 --- a/arch/x86/boot/prepare_uboot.c +++ b/arch/x86/boot/prepare_uboot.c @@ -1,12 +1,6 @@ -/* -*- linux-c -*- ------------------------------------------------------- * - * - * Copyright (C) 1991, 1992 Linus Torvalds - * Copyright 2007 rPath, Inc. - All Rights Reserved - * - * This file is part of the Linux kernel, and is made available under - * the terms of the GNU General Public License version 2. - * - * ----------------------------------------------------------------------- */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 1991,1992 Linus Torvalds +// SPDX-FileCopyrightText: 2007 rPath, Inc. /* * Prepare the machine for transition to protected mode. diff --git a/arch/x86/boot/regs.c b/arch/x86/boot/regs.c index ddc515518c..318b662175 100644 --- a/arch/x86/boot/regs.c +++ b/arch/x86/boot/regs.c @@ -1,12 +1,7 @@ -/* ----------------------------------------------------------------------- - * - * Copyright 2009 Intel Corporation; author H. Peter Anvin - * - * This file is part of the Linux kernel, and is made available under - * the terms of the GNU General Public License version 2 or (at your - * option) any later version; incorporated herein by reference. - * - * ----------------------------------------------------------------------- */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Intel Corporation + +/* Author: H. Peter Anvin */ /** * @file diff --git a/arch/x86/boot/tty.c b/arch/x86/boot/tty.c index a81671be3b..620197c677 100644 --- a/arch/x86/boot/tty.c +++ b/arch/x86/boot/tty.c @@ -1,13 +1,9 @@ -/* -*- linux-c -*- ------------------------------------------------------- * - * - * Copyright (C) 1991, 1992 Linus Torvalds - * Copyright 2007 rPath, Inc. - All Rights Reserved - * Copyright 2009 Intel Corporation; author H. Peter Anvin - * - * This file is part of the Linux kernel, and is made available under - * the terms of the GNU General Public License version 2. - * - * ----------------------------------------------------------------------- */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 1991,1992 Linus Torvalds +// SPDX-FileCopyrightText: 2007 rPath, Inc. +// SPDX-FileCopyrightText: 2009 Intel Corporation + +/* Author: H. Peter Anvin and others */ /** * @file diff --git a/arch/x86/configs/efi_defconfig b/arch/x86/configs/efi_defconfig index 47842d10af..83794d7a07 100644 --- a/arch/x86/configs/efi_defconfig +++ b/arch/x86/configs/efi_defconfig @@ -14,7 +14,6 @@ CONFIG_BLSPEC=y CONFIG_CONSOLE_ACTIVATE_ALL=y CONFIG_PARTITION_DISK_EFI=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_POLLER=y CONFIG_STATE=y CONFIG_DEBUG_LL=y CONFIG_LONGHELP=y @@ -66,7 +65,6 @@ CONFIG_NET=y CONFIG_NET_NFS=y CONFIG_NET_NETCONSOLE=y CONFIG_DRIVER_SERIAL_EFI_STDIO=y -CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_DRIVER_NET_EFI_SNP=y # CONFIG_SPI is not set CONFIG_DISK=y diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index e77ab83202..e2bdf98e95 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -1,16 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _ASM_BITOPS_H_ #define _ASM_BITOPS_H_ diff --git a/arch/x86/include/asm/byteorder.h b/arch/x86/include/asm/byteorder.h index 3cfd850568..878b7eaa3c 100644 --- a/arch/x86/include/asm/byteorder.h +++ b/arch/x86/include/asm/byteorder.h @@ -1,16 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /** * @file diff --git a/arch/x86/include/asm/common.h b/arch/x86/include/asm/common.h index 174363b58b..1376b76ffe 100644 --- a/arch/x86/include/asm/common.h +++ b/arch/x86/include/asm/common.h @@ -1,16 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /** * @file diff --git a/arch/x86/include/asm/dma.h b/arch/x86/include/asm/dma.h index 27d269f491..3dab2b688d 100644 --- a/arch/x86/include/asm/dma.h +++ b/arch/x86/include/asm/dma.h @@ -1,9 +1,5 @@ -/* - * Copyright (C) 2012 by Marc Kleine-Budde <mkl@pengutronix.de> - * - * This file is released under the GPLv2 - * - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2012 Marc Kleine-Budde <mkl@pengutronix.de> */ #ifndef __ASM_DMA_H #define __ASM_DMA_H diff --git a/arch/x86/include/asm/modes.h b/arch/x86/include/asm/modes.h index bd454c7c95..b33df85892 100644 --- a/arch/x86/include/asm/modes.h +++ b/arch/x86/include/asm/modes.h @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix */ /** * @file diff --git a/arch/x86/include/asm/module.h b/arch/x86/include/asm/module.h index 05fbb81d2b..3fd2ce27f4 100644 --- a/arch/x86/include/asm/module.h +++ b/arch/x86/include/asm/module.h @@ -1,16 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /** * @file diff --git a/arch/x86/include/asm/segment.h b/arch/x86/include/asm/segment.h index 88d908a2fc..9e1d897b03 100644 --- a/arch/x86/include/asm/segment.h +++ b/arch/x86/include/asm/segment.h @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix */ #ifndef _ASM_X86_SEGMENT_H #define _ASM_X86_SEGMENT_H diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h index 5994b51d70..f72d8a3d1d 100644 --- a/arch/x86/include/asm/string.h +++ b/arch/x86/include/asm/string.h @@ -1,16 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /** * @file diff --git a/arch/x86/include/asm/syslib.h b/arch/x86/include/asm/syslib.h index 14e373a5af..7e08cfd44e 100644 --- a/arch/x86/include/asm/syslib.h +++ b/arch/x86/include/asm/syslib.h @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix */ #ifdef CONFIG_X86_BIOS_BRINGUP diff --git a/arch/x86/include/asm/types.h b/arch/x86/include/asm/types.h index e57ae2c8cf..17947b2ff3 100644 --- a/arch/x86/include/asm/types.h +++ b/arch/x86/include/asm/types.h @@ -1,6 +1,8 @@ #ifndef __ASM_I386_TYPES_H #define __ASM_I386_TYPES_H +#include <asm-generic/int-ll64.h> + #ifndef __ASSEMBLY__ #ifdef __x86_64__ @@ -18,46 +20,6 @@ #endif -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#include <asm/bitsperlong.h> - -#endif /* __KERNEL__ */ - #endif #endif diff --git a/arch/x86/lib/barebox.lds.S b/arch/x86/lib/barebox.lds.S index bf52ba9a18..b24c4807b5 100644 --- a/arch/x86/lib/barebox.lds.S +++ b/arch/x86/lib/barebox.lds.S @@ -1,16 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #undef i386 #include <asm-generic/barebox.lds.h> diff --git a/arch/x86/lib/gdt.c b/arch/x86/lib/gdt.c index 447e81942e..4cd1622b6b 100644 --- a/arch/x86/lib/gdt.c +++ b/arch/x86/lib/gdt.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix /** * @file diff --git a/arch/x86/lib/linux_start.S b/arch/x86/lib/linux_start.S index b9489b8e50..07be37fed4 100644 --- a/arch/x86/lib/linux_start.S +++ b/arch/x86/lib/linux_start.S @@ -1,21 +1,8 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * Mostly stolen from the GRUB2 project - * Copyright (C) 1999,2000,2001,2002,2003,2004,2005,2006,2007,2008 Free Software Foundation, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix */ +/* SPDX-FileCopyrightText: 1999-2008 Free Software Foundation, Inc. */ + +/* Mostly stolen from the GRUB2 project */ /** * @file diff --git a/arch/x86/lib/memory.c b/arch/x86/lib/memory.c index de0e5d907f..64fbbb9300 100644 --- a/arch/x86/lib/memory.c +++ b/arch/x86/lib/memory.c @@ -1,20 +1,7 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This code was inspired by the GRUB2 project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix + +/* This code was inspired by the GRUB2 project. */ /** * @file diff --git a/arch/x86/mach-i386/include/mach/barebox.lds.h b/arch/x86/mach-i386/include/mach/barebox.lds.h index f6f6346398..50f17340e4 100644 --- a/arch/x86/mach-i386/include/mach/barebox.lds.h +++ b/arch/x86/mach-i386/include/mach/barebox.lds.h @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix */ /** * @file diff --git a/arch/x86/mach-i386/pit_timer.c b/arch/x86/mach-i386/pit_timer.c index 857ba3136c..d2da3b60d4 100644 --- a/arch/x86/mach-i386/pit_timer.c +++ b/arch/x86/mach-i386/pit_timer.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix */ /** * @file |