diff options
Diffstat (limited to 'arch')
46 files changed, 936 insertions, 764 deletions
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg index 0773f4d276..47b572db46 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg @@ -4,7 +4,6 @@ dcdofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> -#include <mach/imx6-ccm-regs.h> #include "ram-base.imxcfg" #include "800mhz_4x128mx16.imxcfg" diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg index 6622c517fa..cf3716dbaa 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg @@ -4,7 +4,6 @@ dcdofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> -#include <mach/imx6-ccm-regs.h> #include "ram-base.imxcfg" #include "800mhz_4x256mx16.imxcfg" diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg index bd4134f8a9..8ed987daa8 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg @@ -4,7 +4,6 @@ dcdofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> -#include <mach/imx6-ccm-regs.h> #include "ram-base.imxcfg" #include "1066mhz_4x128mx16.imxcfg" diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg index 89aa21c300..e6d97d11c1 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg @@ -4,7 +4,6 @@ dcdofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> -#include <mach/imx6-ccm-regs.h> #include "ram-base.imxcfg" #include "1066mhz_4x256mx16.imxcfg" diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg index 66f0e1a860..50bbfc5bdd 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg @@ -4,7 +4,6 @@ dcdofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> -#include <mach/imx6-ccm-regs.h> #include "ram-base.imxcfg" #include "1066mhz_4x512mx16-qp.imxcfg" diff --git a/arch/arm/boards/freescale-mx51-babbage/board.c b/arch/arm/boards/freescale-mx51-babbage/board.c index 74ad7fa51f..4839aa5683 100644 --- a/arch/arm/boards/freescale-mx51-babbage/board.c +++ b/arch/arm/boards/freescale-mx51-babbage/board.c @@ -43,80 +43,55 @@ #define MX51_CCM_CACRR 0x10 -static int imx51_babbage_init(void) +#define USBH1_STP IMX_GPIO_NR(1, 27) +#define USBH1_PHY_RESET IMX_GPIO_NR(2, 5) +#define USBH1_HUB_RESET IMX_GPIO_NR(1, 7) + +static int imx51_babbage_reset_usbh1(void) { + void __iomem *iomuxbase = IOMEM(MX51_IOMUXC_BASE_ADDR); + if (!of_machine_is_compatible("fsl,imx51-babbage")) return 0; - imx51_babbage_power_init(); + imx_setup_pad(iomuxbase, MX51_PAD_EIM_D21__GPIO2_5); + imx_setup_pad(iomuxbase, MX51_PAD_GPIO1_7__GPIO1_7); - barebox_set_hostname("babbage"); + gpio_direction_output(USBH1_PHY_RESET, 0); + gpio_direction_output(USBH1_HUB_RESET, 0); - armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE); + mdelay(10); - imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0", - BBU_HANDLER_FLAG_DEFAULT); - - return 0; -} -coredevice_initcall(imx51_babbage_init); + gpio_set_value(USBH1_PHY_RESET, 1); + gpio_set_value(USBH1_HUB_RESET, 1); -#ifdef CONFIG_ARCH_IMX_XLOAD + imx_setup_pad(iomuxbase, MX51_PAD_USBH1_STP__GPIO1_27); + gpio_direction_output(USBH1_STP, 1); -static int imx51_babbage_xload_init_pinmux(void) -{ - static const iomux_v3_cfg_t pinmux[] = { - /* (e)CSPI */ - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, - MX51_PAD_CSPI1_MISO__ECSPI1_MISO, - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, + mdelay(1); - /* (e)CSPI chip select lines */ - MX51_PAD_CSPI1_SS1__GPIO4_25, + imx_setup_pad(iomuxbase, MX51_PAD_USBH1_STP__USBH1_STP); - - /* eSDHC 1 */ - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - }; - - mxc_iomux_v3_setup_multiple_pads(ARRAY_AND_SIZE(pinmux)); + gpio_free(USBH1_PHY_RESET); return 0; } -coredevice_initcall(imx51_babbage_xload_init_pinmux); +console_initcall(imx51_babbage_reset_usbh1); -static int imx51_babbage_xload_init_devices(void) +static int imx51_babbage_init(void) { - static int spi0_chipselects[] = { - IMX_GPIO_NR(4, 25), - }; + if (!of_machine_is_compatible("fsl,imx51-babbage")) + return 0; - static struct spi_imx_master spi0_pdata = { - .chipselect = spi0_chipselects, - .num_chipselect = ARRAY_SIZE(spi0_chipselects), - }; + imx51_babbage_power_init(); - static const struct spi_board_info spi0_devices[] = { - { - .name = "mtd_dataflash", - .chip_select = 0, - .max_speed_hz = 25 * 1000 * 1000, - .bus_num = 0, - }, - }; + barebox_set_hostname("babbage"); - imx51_add_mmc0(NULL); + armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE); - spi_register_board_info(ARRAY_AND_SIZE(spi0_devices)); - imx51_add_spi0(&spi0_pdata); + imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0", + BBU_HANDLER_FLAG_DEFAULT); return 0; } -device_initcall(imx51_babbage_xload_init_devices); - -#endif +coredevice_initcall(imx51_babbage_init); diff --git a/arch/arm/boards/freescale-mx51-babbage/flash-header-common.imxcfg b/arch/arm/boards/freescale-mx51-babbage/flash-header-common.imxcfg deleted file mode 100644 index 1332b74707..0000000000 --- a/arch/arm/boards/freescale-mx51-babbage/flash-header-common.imxcfg +++ /dev/null @@ -1,58 +0,0 @@ -soc imx51 -dcdofs 0x400 -wm 32 0x73fa88a0 0x00000200 -wm 32 0x73fa850c 0x000020c5 -wm 32 0x73fa8510 0x000020c5 -wm 32 0x73fa883c 0x00000002 -wm 32 0x73fa8848 0x00000002 -wm 32 0x73fa84b8 0x000000e7 -wm 32 0x73fa84bc 0x00000045 -wm 32 0x73fa84c0 0x00000045 -wm 32 0x73fa84c4 0x00000045 -wm 32 0x73fa84c8 0x00000045 -wm 32 0x73fa8820 0x00000000 -wm 32 0x73fa84a4 0x00000003 -wm 32 0x73fa84a8 0x00000003 -wm 32 0x73fa84ac 0x000000e3 -wm 32 0x73fa84b0 0x000000e3 -wm 32 0x73fa84b4 0x000000e3 -wm 32 0x73fa84cc 0x000000e3 -wm 32 0x73fa84d0 0x000000e2 -wm 32 0x73fa882c 0x00000004 -wm 32 0x73fa88a4 0x00000004 -wm 32 0x73fa88ac 0x00000004 -wm 32 0x73fa88b8 0x00000004 -wm 32 0x83fd9000 0x82a20000 -wm 32 0x83fd9008 0x82a20000 -wm 32 0x83fd9010 0x000ad0d0 -wm 32 0x83fd9004 0x3f3584ab -wm 32 0x83fd900c 0x3f3584ab -wm 32 0x83fd9014 0x04008008 -wm 32 0x83fd9014 0x0000801a -wm 32 0x83fd9014 0x0000801b -wm 32 0x83fd9014 0x00448019 -wm 32 0x83fd9014 0x07328018 -wm 32 0x83fd9014 0x04008008 -wm 32 0x83fd9014 0x00008010 -wm 32 0x83fd9014 0x00008010 -wm 32 0x83fd9014 0x06328018 -wm 32 0x83fd9014 0x03808019 -wm 32 0x83fd9014 0x00408019 -wm 32 0x83fd9014 0x00008000 -wm 32 0x83fd9014 0x0400800c -wm 32 0x83fd9014 0x0000801e -wm 32 0x83fd9014 0x0000801f -wm 32 0x83fd9014 0x0000801d -wm 32 0x83fd9014 0x0732801c -wm 32 0x83fd9014 0x0400800c -wm 32 0x83fd9014 0x00008014 -wm 32 0x83fd9014 0x00008014 -wm 32 0x83fd9014 0x0632801c -wm 32 0x83fd9014 0x0380801d -wm 32 0x83fd9014 0x0040801d -wm 32 0x83fd9014 0x00008004 -wm 32 0x83fd9000 0xb2a20000 -wm 32 0x83fd9008 0xb2a20000 -wm 32 0x83fd9010 0x000ad6d0 -wm 32 0x83fd9034 0x90000000 -wm 32 0x83fd9014 0x00000000 diff --git a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg deleted file mode 100644 index b249a7d4bc..0000000000 --- a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg +++ /dev/null @@ -1,3 +0,0 @@ -loadaddr CONFIG_ARCH_IMX_UNUSED_IRAM_BASE - -#include "flash-header-common.imxcfg"
\ No newline at end of file diff --git a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg index cb60e4752a..bac6816fee 100644 --- a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg +++ b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg @@ -1,3 +1,59 @@ loadaddr 0x90000000 - -#include "flash-header-common.imxcfg"
\ No newline at end of file +soc imx51 +dcdofs 0x400 +wm 32 0x73fa88a0 0x00000200 +wm 32 0x73fa850c 0x000020c5 +wm 32 0x73fa8510 0x000020c5 +wm 32 0x73fa883c 0x00000002 +wm 32 0x73fa8848 0x00000002 +wm 32 0x73fa84b8 0x000000e7 +wm 32 0x73fa84bc 0x00000045 +wm 32 0x73fa84c0 0x00000045 +wm 32 0x73fa84c4 0x00000045 +wm 32 0x73fa84c8 0x00000045 +wm 32 0x73fa8820 0x00000000 +wm 32 0x73fa84a4 0x00000003 +wm 32 0x73fa84a8 0x00000003 +wm 32 0x73fa84ac 0x000000e3 +wm 32 0x73fa84b0 0x000000e3 +wm 32 0x73fa84b4 0x000000e3 +wm 32 0x73fa84cc 0x000000e3 +wm 32 0x73fa84d0 0x000000e2 +wm 32 0x73fa882c 0x00000004 +wm 32 0x73fa88a4 0x00000004 +wm 32 0x73fa88ac 0x00000004 +wm 32 0x73fa88b8 0x00000004 +wm 32 0x83fd9000 0x82a20000 +wm 32 0x83fd9008 0x82a20000 +wm 32 0x83fd9010 0x000ad0d0 +wm 32 0x83fd9004 0x3f3584ab +wm 32 0x83fd900c 0x3f3584ab +wm 32 0x83fd9014 0x04008008 +wm 32 0x83fd9014 0x0000801a +wm 32 0x83fd9014 0x0000801b +wm 32 0x83fd9014 0x00448019 +wm 32 0x83fd9014 0x07328018 +wm 32 0x83fd9014 0x04008008 +wm 32 0x83fd9014 0x00008010 +wm 32 0x83fd9014 0x00008010 +wm 32 0x83fd9014 0x06328018 +wm 32 0x83fd9014 0x03808019 +wm 32 0x83fd9014 0x00408019 +wm 32 0x83fd9014 0x00008000 +wm 32 0x83fd9014 0x0400800c +wm 32 0x83fd9014 0x0000801e +wm 32 0x83fd9014 0x0000801f +wm 32 0x83fd9014 0x0000801d +wm 32 0x83fd9014 0x0732801c +wm 32 0x83fd9014 0x0400800c +wm 32 0x83fd9014 0x00008014 +wm 32 0x83fd9014 0x00008014 +wm 32 0x83fd9014 0x0632801c +wm 32 0x83fd9014 0x0380801d +wm 32 0x83fd9014 0x0040801d +wm 32 0x83fd9014 0x00008004 +wm 32 0x83fd9000 0xb2a20000 +wm 32 0x83fd9008 0xb2a20000 +wm 32 0x83fd9010 0x000ad6d0 +wm 32 0x83fd9034 0x90000000 +wm 32 0x83fd9014 0x00000000 diff --git a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c index 216576ca27..f254db7b7b 100644 --- a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c +++ b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c @@ -4,7 +4,6 @@ #include <common.h> #include <mach/esdctl.h> #include <mach/generic.h> -#include <asm/cache.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> @@ -47,27 +46,3 @@ ENTRY_FUNCTION(start_imx51_babbage, r0, r1, r2) imx51_barebox_entry(fdt); } - -static noinline void babbage_entry(void) -{ - arm_early_mmu_cache_invalidate(); - - relocate_to_current_adr(); - setup_c(); - - puts_ll("lowlevel init done\n"); - - imx51_barebox_entry(NULL); -} - -ENTRY_FUNCTION(start_imx51_babbage_xload, r0, r1, r2) -{ - imx5_cpu_lowlevel_init(); - - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); - - arm_setup_stack(0x20000000 - 16); - - babbage_entry(); -} diff --git a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg index f4506f1da5..b9a6fc12ff 100644 --- a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg +++ b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg @@ -4,7 +4,6 @@ dcdofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> -#include <mach/imx6-ccm-regs.h> #include "ram-base.imxcfg" #include "quad_128x64.imxcfg" diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg index 2a1c42aeed..b7a914fba5 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg @@ -4,7 +4,6 @@ dcdofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> -#include <mach/imx6-ccm-regs.h> #include "ram-base.imxcfg" #include "1600mhz_4x128mx16.imxcfg" diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c index d93e21da17..868c25ebb2 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/board.c +++ b/arch/arm/boards/nxp-imx8mq-evk/board.c @@ -21,6 +21,7 @@ #include <init.h> #include <asm/memory.h> #include <linux/sizes.h> +#include <mach/bbu.h> static int imx8mq_evk_mem_init(void) { @@ -39,6 +40,8 @@ static int nxp_imx8mq_evk_init(void) barebox_set_hostname("imx8mq-evk"); + imx8mq_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc0", 0); + return 0; } device_initcall(nxp_imx8mq_evk_init); diff --git a/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/emmc b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/emmc index b1792a6ff0..47dc9516e6 100644 --- a/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/emmc +++ b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/emmc @@ -1,5 +1,5 @@ #!/bin/sh -global.bootm.image=/mnt/mmc1.0/linuximage +global.bootm.image=/mnt/mmc1.0/zImage global.bootm.oftree=/mnt/mmc1.0/oftree global.linux.bootargs.dyn.root="root=/dev/mmcblk1p2 rootflags='data=journal'" diff --git a/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/mmc b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/mmc index 77a076df58..b025a578d0 100644 --- a/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/mmc +++ b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/mmc @@ -1,5 +1,5 @@ #!/bin/sh -global.bootm.image=/mnt/mmc0.0/linuximage +global.bootm.image=/mnt/mmc0.0/zImage global.bootm.oftree=/mnt/mmc0.0/oftree global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootflags='data=journal'" diff --git a/arch/arm/boards/zii-vf610-dev/board.c b/arch/arm/boards/zii-vf610-dev/board.c index c90644b048..91c653804e 100644 --- a/arch/arm/boards/zii-vf610-dev/board.c +++ b/arch/arm/boards/zii-vf610-dev/board.c @@ -149,6 +149,25 @@ static int zii_vf610_dev_set_hostname(void) } late_initcall(zii_vf610_dev_set_hostname); +static int zii_vf610_dev_register_bbu(void) +{ + int ret; + if (!of_machine_is_compatible("zii,vf610dev-c") && + !of_machine_is_compatible("zii,vf610dev-b")) + return 0; + + ret = vf610_bbu_internal_spi_i2c_register_handler("SPI", + "/dev/m25p0.bootloader", + 0); + if (ret) { + pr_err("Failed to register SPI BBU handler"); + return ret; + } + + return 0; +} +late_initcall(zii_vf610_dev_register_bbu); + static int zii_vf610_spu3_register_bbu(void) { int ret; diff --git a/arch/arm/configs/imx_v7-xload_defconfig b/arch/arm/configs/imx_v7-xload_defconfig deleted file mode 100644 index dcf100d440..0000000000 --- a/arch/arm/configs/imx_v7-xload_defconfig +++ /dev/null @@ -1,31 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_ARCH_IMX_XLOAD=y -CONFIG_IMX_MULTI_BOARDS=y -CONFIG_MACH_FREESCALE_MX51_PDK=y -CONFIG_THUMB2_BAREBOX=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_MMU=y -CONFIG_TEXT_BASE=0x0 -CONFIG_MALLOC_SIZE=0x0 -CONFIG_MALLOC_DUMMY=y -CONFIG_RELOCATABLE=y -CONFIG_SHELL_NONE=y -# CONFIG_ERRNO_MESSAGES is not set -# CONFIG_TIMESTAMP is not set -CONFIG_DEBUG_LL=y -CONFIG_MTD=y -# CONFIG_MTD_WRITE is not set -CONFIG_MTD_DATAFLASH=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -# CONFIG_MCI_WRITE is not set -CONFIG_MCI_IMX_ESDHC=y -CONFIG_EEPROM_AT25=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_IMX=y -# CONFIG_FS_RAMFS is not set -# CONFIG_FS_DEVFS is not set -CONFIG_FS_FAT=y -CONFIG_BOOTSTRAP=y -CONFIG_BOOTSTRAP_DEVFS=y -CONFIG_BOOTSTRAP_DISK=y diff --git a/arch/arm/configs/kindle-mx50_defconfig b/arch/arm/configs/kindle-mx50_defconfig new file mode 100644 index 0000000000..31bfc9c06b --- /dev/null +++ b/arch/arm/configs/kindle-mx50_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARCH_IMX=y +CONFIG_IMX_MULTI_BOARDS=y +CONFIG_MACH_KINDLE_MX50=y +CONFIG_THUMB2_BAREBOX=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_MMU_EARLY=y +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_RELOCATABLE=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_FLEXIBLE_BOOTARGS=y +CONFIG_BOOTM_SHOW_TYPE=y +CONFIG_BOOTM_VERBOSE=y +CONFIG_BOOTM_INITRD=y +CONFIG_BOOTM_OFTREE=y +CONFIG_CONSOLE_ACTIVATE_ALL=y +CONFIG_CONSOLE_ALLOW_COLOR=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_BOOT=y +CONFIG_CMD_RESET=y +CONFIG_CMD_AUTOMOUNT=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_GLOBAL=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USBGADGET=y +CONFIG_CMD_OF_DUMP=y +CONFIG_CMD_OFTREE=y +CONFIG_OFDEVICE=y +CONFIG_OF_GPIO=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_MTD=y +CONFIG_MTD_WRITE=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SPI_NOR=y +CONFIG_USB=y +CONFIG_USB_HOST=y +CONFIG_USB_IMX_CHIPIDEA=y +CONFIG_USB_EHCI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DRIVER_ARC=y +CONFIG_USB_GADGET_SERIAL=y +CONFIG_USB_GADGET_FASTBOOT=y +CONFIG_MCI=y +CONFIG_MCI_INFO=y +CONFIG_MCI_WRITE=y +CONFIG_MCI_MMC_BOOT_PARTITIONS=y +CONFIG_MCI_IMX_ESDHC=y +CONFIG_PINCTRL=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED=y +CONFIG_GENERIC_PHY=y +CONFIG_USB_NOP_XCEIV=y +CONFIG_FS_AUTOMOUNT=y +CONFIG_IMAGE_COMPRESSION_XZKERN=y diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c index 8e0fff66d5..e975ecffc7 100644 --- a/arch/arm/cpu/cache-l2x0.c +++ b/arch/arm/cpu/cache-l2x0.c @@ -60,14 +60,14 @@ static inline void l2x0_inv_all(void) static void l2x0_inv_range(unsigned long start, unsigned long end) { - if (start & (CACHE_LINE_SIZE - 1)) { - start &= ~(CACHE_LINE_SIZE - 1); + if (!IS_ALIGNED(start, CACHE_LINE_SIZE)) { + start = ALIGN_DOWN(start, CACHE_LINE_SIZE); l2x0_flush_line(start); start += CACHE_LINE_SIZE; } - if (end & (CACHE_LINE_SIZE - 1)) { - end &= ~(CACHE_LINE_SIZE - 1); + if (!IS_ALIGNED(end, CACHE_LINE_SIZE)) { + end = ALIGN_DOWN(end, CACHE_LINE_SIZE); l2x0_flush_line(end); } @@ -87,7 +87,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end) { void __iomem *base = l2x0_base; - start &= ~(CACHE_LINE_SIZE - 1); + start = ALIGN_DOWN(start, CACHE_LINE_SIZE); while (start < end) { unsigned long blk_end = start + min(end - start, 4096UL); @@ -102,7 +102,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end) static void l2x0_flush_range(unsigned long start, unsigned long end) { - start &= ~(CACHE_LINE_SIZE - 1); + start = ALIGN_DOWN(start, CACHE_LINE_SIZE); while (start < end) { unsigned long blk_end = start + min(end - start, 4096UL); diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c index 88ee11cb48..f6c44e3e25 100644 --- a/arch/arm/cpu/mmu.c +++ b/arch/arm/cpu/mmu.c @@ -151,7 +151,7 @@ static u32 *arm_create_pte(unsigned long virt, uint32_t flags) dma_flush_range(table, PTRS_PER_PTE * sizeof(u32)); ttb[ttb_idx] = (unsigned long)table | PMD_TYPE_TABLE; - dma_flush_range(ttb, sizeof(u32)); + dma_flush_range(&ttb[ttb_idx], sizeof(u32)); return table; } diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c index b6287aec89..69d1b20718 100644 --- a/arch/arm/cpu/mmu_64.c +++ b/arch/arm/cpu/mmu_64.c @@ -297,7 +297,8 @@ void dma_sync_single_for_device(dma_addr_t address, size_t size, { if (dir == DMA_FROM_DEVICE) v8_inv_dcache_range(address, address + size - 1); - v8_flush_dcache_range(address, address + size - 1); + else + v8_flush_dcache_range(address, address + size - 1); } dma_addr_t dma_map_single(struct device_d *dev, void *ptr, size_t size, diff --git a/arch/arm/dts/am335x-bone-common-strip.dtsi b/arch/arm/dts/am335x-bone-common-strip.dtsi new file mode 100644 index 0000000000..e03ae2a8d3 --- /dev/null +++ b/arch/arm/dts/am335x-bone-common-strip.dtsi @@ -0,0 +1,297 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + chosen { + stdout-path = &uart0; + }; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + led@2 { + label = "beaglebone:green:heartbeat"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@3 { + label = "beaglebone:green:mmc0"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@4 { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led@5 { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + }; + + vmmcsd_fixed: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin>; + + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ + 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ + 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ + 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ + 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ + 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ + 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ + 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ + >; + }; + + emmc_pins: pinmux_emmc_pins { + pinctrl-single,pins = < + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + +}; + +/include/ "tps65217.dtsi" + +&tps { + regulators { + dcdc1_reg: regulator@0 { + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-always-on; + }; + }; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "mii"; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "mii"; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&mmc1 { + status = "okay"; + bus-width = <0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + cd-inverted; +}; diff --git a/arch/arm/dts/am335x-bone-common.dts b/arch/arm/dts/am335x-bone-common.dts index 0488cbe1fc..26896b4c7c 100644 --- a/arch/arm/dts/am335x-bone-common.dts +++ b/arch/arm/dts/am335x-bone-common.dts @@ -10,7 +10,7 @@ #include "am33xx.dtsi" #include "am33xx-strip.dtsi" #include "am33xx-clocks-strip.dtsi" -#include "am335x-bone-common.dtsi" +#include "am335x-bone-common-strip.dtsi" / { model = "TI AM335x BeagleBone"; diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi index e03ae2a8d3..8711802f57 100644 --- a/arch/arm/dts/am335x-bone-common.dtsi +++ b/arch/arm/dts/am335x-bone-common.dtsi @@ -6,292 +6,4 @@ * published by the Free Software Foundation. */ -/ { - chosen { - stdout-path = &uart0; - }; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led@2 { - label = "beaglebone:green:heartbeat"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led@3 { - label = "beaglebone:green:mmc0"; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led@4 { - label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led@5 { - label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - }; - - vmmcsd_fixed: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin>; - - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ - 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ - 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ - 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ - 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ - 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ - 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ - 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ - 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ - 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ - 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ - >; - }; - - emmc_pins: pinmux_emmc_pins { - pinctrl-single,pins = < - 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "peripheral"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - -}; - -/include/ "tps65217.dtsi" - -&tps { - regulators { - dcdc1_reg: regulator@0 { - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1325000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - regulator-always-on; - }; - }; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "mii"; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "mii"; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; -}; - -&mmc1 { - status = "okay"; - bus-width = <0x4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - cd-inverted; -}; +#include <arm/am335x-bone-common.dtsi> diff --git a/arch/arm/dts/am33xx-strip.dtsi b/arch/arm/dts/am33xx-strip.dtsi index 83d23a88e8..0c9d852630 100644 --- a/arch/arm/dts/am33xx-strip.dtsi +++ b/arch/arm/dts/am33xx-strip.dtsi @@ -12,8 +12,8 @@ /delete-property/ i2c1; /delete-property/ i2c2; /delete-property/ mmc2; - /delete-property/ d_can0; - /delete-property/ d_can1; + /delete-property/ d-can0; + /delete-property/ d-can1; /delete-property/ spi1; }; }; diff --git a/arch/arm/dts/imx51-babbage.dts b/arch/arm/dts/imx51-babbage.dts index 5147195617..f85415f6db 100644 --- a/arch/arm/dts/imx51-babbage.dts +++ b/arch/arm/dts/imx51-babbage.dts @@ -67,5 +67,25 @@ MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ >; }; + + pinctrl_usbh1: usbh1grp { + /* + * Ditto for USBH1 iomux settings. + */ + fsl,pins = < + MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 + MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 + >; + }; }; }; diff --git a/arch/arm/dts/imx51-zii-rdu1.dts b/arch/arm/dts/imx51-zii-rdu1.dts index 979c4c9de6..bde565fe08 100644 --- a/arch/arm/dts/imx51-zii-rdu1.dts +++ b/arch/arm/dts/imx51-zii-rdu1.dts @@ -86,3 +86,45 @@ }; }; }; + +&iomuxc { + pinctrl_usbh1: usbh1grp { + + /* + * Overwrite upstream USBH1,2 iomux settings to match + * the setting U-Boot would set these to. Remove this + * once this is fixed upstream. + */ + fsl,pins = < + MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 + MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX51_PAD_EIM_A26__USBH2_STP 0x1e5 + MX51_PAD_EIM_A24__USBH2_CLK 0x1e5 + MX51_PAD_EIM_A25__USBH2_DIR 0x1e5 + MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 + MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5 + MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5 + MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5 + MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5 + MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5 + MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5 + MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5 + MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5 + >; + }; +}; diff --git a/arch/arm/dts/tegra20-colibri.dtsi b/arch/arm/dts/tegra20-colibri.dtsi index e931c07406..4f6dc9daf2 100644 --- a/arch/arm/dts/tegra20-colibri.dtsi +++ b/arch/arm/dts/tegra20-colibri.dtsi @@ -1,2 +1,2 @@ -#include <arm/tegra20-colibri-512.dtsi> +#include <arm/tegra20-colibri.dtsi> #include "tegra20.dtsi" diff --git a/arch/arm/dts/vf610-zii-dev-rev-b.dts b/arch/arm/dts/vf610-zii-dev-rev-b.dts index 1eb01f44a7..ac0807c49e 100644 --- a/arch/arm/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/dts/vf610-zii-dev-rev-b.dts @@ -45,3 +45,14 @@ #include <arm/vf610-zii-dev-rev-b.dts> #include "vf610-zii-dev.dtsi" + +/ { + spi0 { + m25p128@0 { + partition@0 { + label = "bootloader"; + reg = <0x0 0x100000>; + }; + }; + }; +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 7cb9138d24..1d6b4e1701 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -53,21 +53,6 @@ config ARCH_IMX_IMXIMAGE_SSL_SUPPORT This enables SSL support for the imx-image tool. This is required for created images for HABv3. This adds openssl to the build dependencies -config ARCH_IMX_XLOAD - bool - depends on ARCH_IMX51 - prompt "Build preloader image" - -config ARCH_IMX_UNUSED_IRAM_BASE - hex - depends on ARCH_IMX_XLOAD - default 0x1ffe2000 if ARCH_IMX51 - -config ARCH_IMX_UNUSED_IRAM_SIZE - hex - depends on ARCH_IMX_XLOAD - default 0x16000 if ARCH_IMX51 - config ARCH_IMX_EXTERNAL_BOOT_NAND bool depends on ARCH_IMX25 || ARCH_IMX27 || ARCH_IMX31 || ARCH_IMX35 @@ -242,6 +227,7 @@ config MACH_KINDLE_MX50 select MFD_MC13XXX select ARM_BOARD_APPEND_ATAG select ARM_LINUX + select OFTREE help Say Y here if you are using the fourth or fifth generation Amazon Kindle Model No. D01100 (Kindle Wi-Fi), D01200 (Kindle Touch) or @@ -433,7 +419,7 @@ config MACH_ZII_RDU2 select ARCH_IMX6 config MACH_ZII_VF610_DEV - bool "Zodiac VF610 Dev Family" + bool "ZII VF610 Dev Family" select ARCH_VF610 select CLKDEV_LOOKUP @@ -767,7 +753,29 @@ config HABV4 help High Assurance Boot, as found on i.MX28/i.MX6. -if HABV4 +config HAB_CERTS_ENV + depends on HAB + bool "Specify certificates in environment" + help + If this option is enabled the pathes to the HAB certificates are + taken from environment variables which allows for better integration + with build systems. With this option disabled the pathes can be + specified below. + + The environment variables have the same name as the corresponding + Kconfig variables. For HABv3 these are: + + CONFIG_HABV3_SRK_PEM + CONFIG_HABV3_CSF_CRT_DER + CONFIG_HABV3_IMG_CRT_DER + + For HABv4: + + CONFIG_HABV4_TABLE_BIN + CONFIG_HABV4_CSF_CRT_PEM + CONFIG_HABV4_IMG_CRT_PEM + +if HABV4 && !HAB_CERTS_ENV config HABV4_TABLE_BIN string "Path to SRK table" @@ -791,7 +799,7 @@ config HABV4_CSF_CRT_PEM config HABV4_IMG_CRT_PEM string "Path to IMG certificate" - default "../crts/IMG_1_sha256_4096_65537_v3_usr_crt.pem" + default "../crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem" help Path to the Image certificate, produced by the Freescale Public Key Infrastructure (PKI) script. @@ -810,7 +818,7 @@ config HABV3 help High Assurance Boot, as found on i.MX25. -if HABV3 +if HABV3 && !HAB_CERTS_ENV config HABV3_SRK_PEM string "Path to SRK Certificate (PEM)" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 595a7512ce..5a01dd57e8 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -18,7 +18,6 @@ obj-$(CONFIG_ARCH_IMX7) += imx7.o obj-$(CONFIG_ARCH_VF610) += vf610.o obj-$(CONFIG_ARCH_IMX8MQ) += imx8mq.o lwl-$(CONFIG_ARCH_IMX8MQ) += imx8-ddrc.o atf.o -obj-$(CONFIG_ARCH_IMX_XLOAD) += xload.o obj-$(CONFIG_IMX_IIM) += iim.o obj-$(CONFIG_NAND_IMX) += nand.o lwl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o diff --git a/arch/arm/mach-imx/imx-bbu-external-nand.c b/arch/arm/mach-imx/imx-bbu-external-nand.c index 0f1a028f98..52622ac4cb 100644 --- a/arch/arm/mach-imx/imx-bbu-external-nand.c +++ b/arch/arm/mach-imx/imx-bbu-external-nand.c @@ -190,7 +190,7 @@ out: * each bit represents a single block. With 2k NAND flashes this is enough for * 4MiB size including bad blocks. */ -int imx_bbu_external_nand_register_handler(const char *name, char *devicefile, +int imx_bbu_external_nand_register_handler(const char *name, const char *devicefile, unsigned long flags) { struct bbu_handler *handler; diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c index 55e344cff2..504e359bc3 100644 --- a/arch/arm/mach-imx/imx-bbu-internal.c +++ b/arch/arm/mach-imx/imx-bbu-internal.c @@ -16,8 +16,6 @@ * GNU General Public License for more details. */ -#define IMX_INTERNAL_NAND_BBU - #include <common.h> #include <malloc.h> #include <bbu.h> @@ -31,18 +29,55 @@ #include <ioctl.h> #include <environment.h> #include <mach/bbu.h> +#include <mach/generic.h> +#include <libfile.h> -#define FLASH_HEADER_OFFSET_MMC 0x400 - -#define IMX_INTERNAL_FLAG_NAND BIT(31) #define IMX_INTERNAL_FLAG_ERASE BIT(30) struct imx_internal_bbu_handler { struct bbu_handler handler; + int (*write_device)(struct imx_internal_bbu_handler *, + struct bbu_data *); unsigned long flash_header_offset; size_t device_size; + enum filetype expected_type; }; +static bool +imx_bbu_erase_required(struct imx_internal_bbu_handler *imx_handler) +{ + return imx_handler->handler.flags & IMX_INTERNAL_FLAG_ERASE; +} + +static int imx_bbu_protect(int fd, struct imx_internal_bbu_handler *imx_handler, + const char *devicefile, int offset, int image_len, + int prot) +{ + const char *prefix = prot ? "" : "un"; + int ret; + + if (!imx_bbu_erase_required(imx_handler)) + return 0; + + pr_debug("%s: %sprotecting %s from 0x%08x to 0x%08x\n", __func__, + prefix, devicefile, offset, image_len); + + ret = protect(fd, image_len, offset, prot); + if (ret) { + /* + * If protect() is not implemented for this device, + * just report success + */ + if (ret == -ENOSYS) + return 0; + + pr_err("%sprotecting %s failed with %s\n", prefix, devicefile, + strerror(-ret)); + } + + return ret; +} + /* * Actually write an image to the target device, eventually keeping a * DOS partition table on the device @@ -66,16 +101,12 @@ static int imx_bbu_write_device(struct imx_internal_bbu_handler *imx_handler, if (imx_handler->handler.flags & IMX_BBU_FLAG_KEEP_HEAD) offset += imx_handler->flash_header_offset; - if (imx_handler->handler.flags & IMX_INTERNAL_FLAG_ERASE) { - pr_debug("%s: unprotecting %s from 0x%08x to 0x%08x\n", __func__, - devicefile, offset, image_len); - ret = protect(fd, image_len, offset, 0); - if (ret && ret != -ENOSYS) { - pr_err("unprotecting %s failed with %s\n", devicefile, - strerror(-ret)); - goto err_close; - } + ret = imx_bbu_protect(fd, imx_handler, devicefile, offset, + image_len, 0); + if (ret) + goto err_close; + if (imx_bbu_erase_required(imx_handler)) { pr_debug("%s: erasing %s from 0x%08x to 0x%08x\n", __func__, devicefile, offset, image_len); ret = erase(fd, image_len, offset); @@ -86,33 +117,66 @@ static int imx_bbu_write_device(struct imx_internal_bbu_handler *imx_handler, } } - ret = pwrite(fd, buf, image_len, offset); - if (ret < 0) + ret = pwrite_full(fd, buf, image_len, offset); + if (ret < 0) { + pr_err("writing to %s failed with %s\n", devicefile, + strerror(-ret)); goto err_close; - - if (imx_handler->handler.flags & IMX_INTERNAL_FLAG_ERASE) { - pr_debug("%s: protecting %s from 0x%08x to 0x%08x\n", __func__, - devicefile, offset, image_len); - ret = protect(fd, image_len, offset, 1); - if (ret && ret != -ENOSYS) { - pr_err("protecting %s failed with %s\n", devicefile, - strerror(-ret)); - } } - ret = 0; + imx_bbu_protect(fd, imx_handler, devicefile, offset, + image_len, 1); err_close: close(fd); - return ret; + return ret < 0 ? ret : 0; } -static int imx_bbu_check_prereq(const char *devicefile, struct bbu_data *data) +static int __imx_bbu_write_device(struct imx_internal_bbu_handler *imx_handler, + struct bbu_data *data) { - int ret; + return imx_bbu_write_device(imx_handler, data->devicefile, data, + data->image, data->len); +} - if (file_detect_type(data->image, data->len) != filetype_arm_barebox) { +static int imx_bbu_check_prereq(struct imx_internal_bbu_handler *imx_handler, + const char *devicefile, struct bbu_data *data, + enum filetype expected_type) +{ + int ret; + const void *blob; + size_t len; + enum filetype type; + + type = file_detect_type(data->image, data->len); + + switch (type) { + case filetype_arm_barebox: + /* + * Specifying expected_type as unknown will disable the + * inner image type check. + * + * The only user of this code is + * imx_bbu_external_nor_register_handler() used by + * i.MX27. + */ + if (expected_type == filetype_unknown) + break; + + blob = data->image + imx_handler->flash_header_offset; + len = data->len - imx_handler->flash_header_offset; + type = file_detect_type(blob, len); + + if (type != expected_type) { + pr_err("Expected image type: %s, " + "detected image type: %s\n", + file_type_to_string(expected_type), + file_type_to_string(type)); + return -EINVAL; + } + break; + default: if (!bbu_force(data, "Not an ARM barebox image")) return -EINVAL; } @@ -126,30 +190,6 @@ static int imx_bbu_check_prereq(const char *devicefile, struct bbu_data *data) return 0; } -/* - * Update barebox on a v1 type internal boot (i.MX25, i.MX35, i.MX51) - * - * This constructs a DCD header, adds the specific DCD data and writes - * the resulting image to the device. Currently this handles MMC/SD - * devices. - */ -static int imx_bbu_internal_v1_update(struct bbu_handler *handler, struct bbu_data *data) -{ - struct imx_internal_bbu_handler *imx_handler = - container_of(handler, struct imx_internal_bbu_handler, handler); - int ret; - - ret = imx_bbu_check_prereq(data->devicefile, data); - if (ret) - return ret; - - pr_info("updating to %s\n", data->devicefile); - - ret = imx_bbu_write_device(imx_handler, data->devicefile, data, data->image, data->len); - - return ret; -} - #define DBBT_MAGIC 0x44424254 #define FCB_MAGIC 0x20424346 @@ -321,40 +361,44 @@ out: return ret; } -#define IVT_BARKER 0x402000d1 +static enum filetype imx_bbu_expected_filetype(void) +{ + if (cpu_is_mx8mq() || + cpu_is_mx7() || + cpu_is_mx6() || + cpu_is_vf610() || + cpu_is_mx53()) + return filetype_imx_image_v2; + + return filetype_imx_image_v1; +} -/* - * Update barebox on a v2 type internal boot (i.MX53) - * - * This constructs a DCD header, adds the specific DCD data and writes - * the resulting image to the device. Currently this handles MMC/SD - * and NAND devices. - */ -static int imx_bbu_internal_v2_update(struct bbu_handler *handler, struct bbu_data *data) +static unsigned long imx_bbu_flash_header_offset_mmc(void) +{ + unsigned long offset = SZ_1K; + + /* + * i.MX8MQ moved the header by 32K to accomodate for GPT + * partition tables + */ + if (cpu_is_mx8mq()) + offset += SZ_32K; + + return offset; +} + +static int imx_bbu_update(struct bbu_handler *handler, struct bbu_data *data) { struct imx_internal_bbu_handler *imx_handler = container_of(handler, struct imx_internal_bbu_handler, handler); int ret; - const uint32_t *barker; - ret = imx_bbu_check_prereq(data->devicefile, data); + ret = imx_bbu_check_prereq(imx_handler, data->devicefile, data, + imx_handler->expected_type); if (ret) return ret; - barker = data->image + imx_handler->flash_header_offset; - - if (*barker != IVT_BARKER) { - pr_err("Board does not provide DCD data and this image is no imximage\n"); - return -EINVAL; - } - - if (imx_handler->handler.flags & IMX_INTERNAL_FLAG_NAND) - ret = imx_bbu_internal_v2_write_nand_dbbt(imx_handler, data); - else - ret = imx_bbu_write_device(imx_handler, data->devicefile, data, - data->image, data->len); - - return ret; + return imx_handler->write_device(imx_handler, data); } static int imx_bbu_internal_v2_mmcboot_update(struct bbu_handler *handler, @@ -363,18 +407,10 @@ static int imx_bbu_internal_v2_mmcboot_update(struct bbu_handler *handler, struct imx_internal_bbu_handler *imx_handler = container_of(handler, struct imx_internal_bbu_handler, handler); int ret; - const uint32_t *barker; char *bootpartvar; const char *bootpart; char *devicefile; - barker = data->image + imx_handler->flash_header_offset; - - if (*barker != IVT_BARKER) { - pr_err("Board does not provide DCD data and this image is no imximage\n"); - return -EINVAL; - } - ret = asprintf(&bootpartvar, "%s.boot", data->devicefile); if (ret < 0) return ret; @@ -391,7 +427,8 @@ static int imx_bbu_internal_v2_mmcboot_update(struct bbu_handler *handler, if (ret < 0) goto free_bootpartvar; - ret = imx_bbu_check_prereq(devicefile, data); + ret = imx_bbu_check_prereq(imx_handler, devicefile, data, + filetype_imx_image_v2); if (ret) goto free_devicefile; @@ -410,22 +447,9 @@ free_bootpartvar: return ret; } -static int imx_bbu_external_update(struct bbu_handler *handler, struct bbu_data *data) -{ - struct imx_internal_bbu_handler *imx_handler = - container_of(handler, struct imx_internal_bbu_handler, handler); - int ret; - - ret = imx_bbu_check_prereq(data->devicefile, data); - if (ret) - return ret; - - return imx_bbu_write_device(imx_handler, data->devicefile, data, - data->image, data->len); -} - -static struct imx_internal_bbu_handler *__init_handler(const char *name, char *devicefile, - unsigned long flags) +static struct imx_internal_bbu_handler *__init_handler(const char *name, + const char *devicefile, + unsigned long flags) { struct imx_internal_bbu_handler *imx_handler; struct bbu_handler *handler; @@ -435,6 +459,10 @@ static struct imx_internal_bbu_handler *__init_handler(const char *name, char *d handler->devicefile = devicefile; handler->name = name; handler->flags = flags; + handler->handler = imx_bbu_update; + + imx_handler->expected_type = imx_bbu_expected_filetype(); + imx_handler->write_device = __imx_bbu_write_device; return imx_handler; } @@ -451,73 +479,62 @@ static int __register_handler(struct imx_internal_bbu_handler *imx_handler) } static int -imx_bbu_internal_mmc_register_handler(const char *name, char *devicefile, - unsigned long flags, void *handler) +imx_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, + unsigned long flags) { struct imx_internal_bbu_handler *imx_handler; imx_handler = __init_handler(name, devicefile, flags | IMX_BBU_FLAG_KEEP_HEAD); - imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC; - - imx_handler->handler.handler = handler; + imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc(); return __register_handler(imx_handler); } -int imx51_bbu_internal_spi_i2c_register_handler(const char *name, - char *devicefile, unsigned long flags) +static int +imx_bbu_internal_spi_i2c_register_handler(const char *name, + const char *devicefile, + unsigned long flags) { struct imx_internal_bbu_handler *imx_handler; imx_handler = __init_handler(name, devicefile, flags | IMX_INTERNAL_FLAG_ERASE); - imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC; - - imx_handler->handler.handler = imx_bbu_internal_v1_update; + imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc(); return __register_handler(imx_handler); } +int imx51_bbu_internal_spi_i2c_register_handler(const char *name, + const char *devicefile, + unsigned long flags) + __alias(imx_bbu_internal_spi_i2c_register_handler); + /* * Register an i.MX51 internal boot update handler for MMC/SD */ -int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile, - unsigned long flags) -{ - - return imx_bbu_internal_mmc_register_handler(name, devicefile, flags, - imx_bbu_internal_v1_update); -} +int imx51_bbu_internal_mmc_register_handler(const char *name, + const char *devicefile, + unsigned long flags) + __alias(imx_bbu_internal_mmc_register_handler); /* * Register an i.MX53 internal boot update handler for MMC/SD */ -int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile, - unsigned long flags) -{ - return imx_bbu_internal_mmc_register_handler(name, devicefile, flags, - imx_bbu_internal_v2_update); -} +int imx53_bbu_internal_mmc_register_handler(const char *name, + const char *devicefile, + unsigned long flags) + __alias(imx_bbu_internal_mmc_register_handler); /* * Register an i.MX6 internal boot update handler for i2c/spi * EEPROMs / flashes. Nearly the same as MMC/SD, but we do not need to * keep a partition table. We have to erase the device beforehand though. */ -int imx53_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile, - unsigned long flags) -{ - struct imx_internal_bbu_handler *imx_handler; - - imx_handler = __init_handler(name, devicefile, flags | - IMX_INTERNAL_FLAG_ERASE); - imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC; - - imx_handler->handler.handler = imx_bbu_internal_v2_update; - - return __register_handler(imx_handler); -} +int imx53_bbu_internal_spi_i2c_register_handler(const char *name, + const char *devicefile, + unsigned long flags) + __alias(imx_bbu_internal_spi_i2c_register_handler); /* * Register an i.MX53 internal boot update handler for NAND @@ -527,13 +544,11 @@ int imx53_bbu_internal_nand_register_handler(const char *name, { struct imx_internal_bbu_handler *imx_handler; - imx_handler = __init_handler(name, NULL, flags | - IMX_INTERNAL_FLAG_NAND); - imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC; + imx_handler = __init_handler(name, "/dev/nand0", flags); + imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc(); - imx_handler->handler.handler = imx_bbu_internal_v2_update; - imx_handler->handler.devicefile = "/dev/nand0"; imx_handler->device_size = partition_size; + imx_handler->write_device = imx_bbu_internal_v2_write_nand_dbbt; return __register_handler(imx_handler); } @@ -541,18 +556,28 @@ int imx53_bbu_internal_nand_register_handler(const char *name, /* * Register an i.MX6 internal boot update handler for MMC/SD */ -int imx6_bbu_internal_mmc_register_handler(const char *name, char *devicefile, +int imx6_bbu_internal_mmc_register_handler(const char *name, + const char *devicefile, unsigned long flags) __alias(imx53_bbu_internal_mmc_register_handler); /* * Register an VF610 internal boot update handler for MMC/SD */ -int vf610_bbu_internal_mmc_register_handler(const char *name, char *devicefile, +int vf610_bbu_internal_mmc_register_handler(const char *name, + const char *devicefile, unsigned long flags) __alias(imx6_bbu_internal_mmc_register_handler); /* + * Register an i.MX8MQ internal boot update handler for MMC/SD + */ +int imx8mq_bbu_internal_mmc_register_handler(const char *name, + const char *devicefile, + unsigned long flags) + __alias(imx6_bbu_internal_mmc_register_handler); + +/* * Register a handler that writes to the non-active boot partition of an mmc * medium and on success activates the written-to partition. So the machine can * still boot even after a failed try to write a boot image. @@ -561,13 +586,14 @@ int vf610_bbu_internal_mmc_register_handler(const char *name, char *devicefile, * Note that no further partitioning of the boot partition is supported up to * now. */ -int imx6_bbu_internal_mmcboot_register_handler(const char *name, char *devicefile, +int imx6_bbu_internal_mmcboot_register_handler(const char *name, + const char *devicefile, unsigned long flags) { struct imx_internal_bbu_handler *imx_handler; imx_handler = __init_handler(name, devicefile, flags); - imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC; + imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc(); imx_handler->handler.handler = imx_bbu_internal_v2_mmcboot_update; @@ -580,18 +606,30 @@ int imx6_bbu_internal_mmcboot_register_handler(const char *name, char *devicefil * keep a partition table. We have to erase the device beforehand though. */ int imx6_bbu_internal_spi_i2c_register_handler(const char *name, - char *devicefile, + const char *devicefile, unsigned long flags) __alias(imx53_bbu_internal_spi_i2c_register_handler); -int imx_bbu_external_nor_register_handler(const char *name, char *devicefile, - unsigned long flags) +/* + * Register an VFxxx internal boot update handler for i2c/spi + * EEPROMs / flashes. Nearly the same as MMC/SD, but we do not need to + * keep a partition table. We have to erase the device beforehand though. + */ +int vf610_bbu_internal_spi_i2c_register_handler(const char *name, + const char *devicefile, + unsigned long flags) + __alias(imx6_bbu_internal_spi_i2c_register_handler); + +int imx_bbu_external_nor_register_handler(const char *name, + const char *devicefile, + unsigned long flags) { struct imx_internal_bbu_handler *imx_handler; imx_handler = __init_handler(name, devicefile, flags | IMX_INTERNAL_FLAG_ERASE); - imx_handler->handler.handler = imx_bbu_external_update; + + imx_handler->expected_type = filetype_unknown; return __register_handler(imx_handler); } diff --git a/arch/arm/mach-imx/imx50.c b/arch/arm/mach-imx/imx50.c index f7cbc9d4ba..4fd5481670 100644 --- a/arch/arm/mach-imx/imx50.c +++ b/arch/arm/mach-imx/imx50.c @@ -22,6 +22,7 @@ #include <mach/clock-imx51_53.h> #include <mach/generic.h> #include <mach/reset-reason.h> +#include <mach/usb.h> #define SI_REV 0x48 @@ -90,6 +91,9 @@ void imx50_init_lowlevel_early(unsigned int cpufreq_mhz) void __iomem *ccm = IOMEM(MX50_CCM_BASE_ADDR); u32 r; + if ((readl(ccm + MX5_CCM_CCGR2) & MX5_CCM_CCGRx_CG13_MASK)) + imx_reset_otg_controller(IOMEM(MX50_OTG_BASE_ADDR)); + imx5_init_lowlevel(); /* diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c index ec8cdd868b..7404254bee 100644 --- a/arch/arm/mach-imx/imx51.c +++ b/arch/arm/mach-imx/imx51.c @@ -22,6 +22,7 @@ #include <mach/clock-imx51_53.h> #include <mach/generic.h> #include <mach/reset-reason.h> +#include <mach/usb.h> #define IIM_SREV 0x24 @@ -140,6 +141,9 @@ void imx51_init_lowlevel(unsigned int cpufreq_mhz) u32 r; int rev = imx51_silicon_revision(); + if ((readl(ccm + MX5_CCM_CCGR2) & MX5_CCM_CCGRx_CG13_MASK)) + imx_reset_otg_controller(IOMEM(MX51_OTG_BASE_ADDR)); + imx5_init_lowlevel(); /* disable write combine for TO 2 and lower revs */ diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c index b22929f749..f8e34a39da 100644 --- a/arch/arm/mach-imx/imx53.c +++ b/arch/arm/mach-imx/imx53.c @@ -22,6 +22,7 @@ #include <mach/clock-imx51_53.h> #include <mach/generic.h> #include <mach/reset-reason.h> +#include <mach/usb.h> #define SI_REV 0x48 @@ -88,6 +89,9 @@ void imx53_init_lowlevel_early(unsigned int cpufreq_mhz) void __iomem *ccm = (void __iomem *)MX53_CCM_BASE_ADDR; u32 r, cbcdr, cbcmr; + if ((readl(ccm + MX5_CCM_CCGR2) & MX5_CCM_CCGRx_CG13_MASK)) + imx_reset_otg_controller(IOMEM(MX53_OTG_BASE_ADDR)); + imx5_init_lowlevel(); /* diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index 3d95c9e374..cc368c5820 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -24,11 +24,13 @@ #include <mach/imx6-anadig.h> #include <mach/imx6-regs.h> #include <mach/generic.h> +#include <mach/usb.h> #include <asm/mmu.h> #include <asm/cache-l2x0.h> #include <poweroff.h> #include <mach/imx6-regs.h> +#include <mach/clock-imx6.h> #include <io.h> #define CLPCR 0x54 @@ -52,6 +54,9 @@ static void imx6_init_lowlevel(void) uint32_t periph_sel_2; uint32_t reg; + if ((readl(MXC_CCM_CCGR6) & 0x3)) + imx_reset_otg_controller(IOMEM(MX6_OTG_BASE_ADDR)); + /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h index b9b2c5bcba..b64c8d1180 100644 --- a/arch/arm/mach-imx/include/mach/bbu.h +++ b/arch/arm/mach-imx/include/mach/bbu.h @@ -32,57 +32,63 @@ struct imx_dcd_v2_entry; #ifdef CONFIG_BAREBOX_UPDATE -int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile, +int imx51_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, unsigned long flags); int imx51_bbu_internal_spi_i2c_register_handler(const char *name, - char *devicefile, unsigned long flags); + const char *devicefile, unsigned long flags); -int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile, +int imx53_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, unsigned long flags); -int imx53_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile, +int imx53_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, unsigned long flags); int imx53_bbu_internal_nand_register_handler(const char *name, unsigned long flags, int partition_size); -int imx6_bbu_internal_mmc_register_handler(const char *name, char *devicefile, +int imx6_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, unsigned long flags); -int imx6_bbu_internal_mmcboot_register_handler(const char *name, char *devicefile, +int imx6_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile, unsigned long flags); -int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile, +int imx6_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, unsigned long flags); -int vf610_bbu_internal_mmc_register_handler(const char *name, char *devicefile, +int vf610_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, unsigned long flags); -int imx_bbu_external_nor_register_handler(const char *name, char *devicefile, +int vf610_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, + unsigned long flags); + +int imx8mq_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, + unsigned long flags); + +int imx_bbu_external_nor_register_handler(const char *name, const char *devicefile, unsigned long flags); #else -static inline int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile, +static inline int imx51_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, unsigned long flags) { return -ENOSYS; } static inline int imx51_bbu_internal_spi_i2c_register_handler(const char *name, - char *devicefile, unsigned long flags) + const char *devicefile, unsigned long flags) { return -ENOSYS; } -static inline int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile, +static inline int imx53_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, unsigned long flags) { return -ENOSYS; } -static inline int imx53_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile, +static inline int imx53_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, unsigned long flags) { return -ENOSYS; @@ -94,43 +100,57 @@ static inline int imx53_bbu_internal_nand_register_handler(const char *name, return -ENOSYS; } -static inline int imx6_bbu_internal_mmc_register_handler(const char *name, char *devicefile, +static inline int imx6_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, unsigned long flags) { return -ENOSYS; } static inline int imx6_bbu_internal_mmcboot_register_handler(const char *name, - char *devicefile, + const char *devicefile, unsigned long flags) { return -ENOSYS; } -static inline int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile, +static inline int imx6_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, unsigned long flags) { return -ENOSYS; } -static inline int vf610_bbu_internal_mmc_register_handler(const char *name, char *devicefile, +static inline int vf610_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, unsigned long flags) { return -ENOSYS; } -static inline int imx_bbu_external_nor_register_handler(const char *name, char *devicefile, +static inline int imx8mq_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, + unsigned long flags) +{ + return -ENOSYS; +} + +static inline int imx_bbu_external_nor_register_handler(const char *name, const char *devicefile, unsigned long flags) { return -ENOSYS; } + +static inline int +vf610_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile, + unsigned long flags) +{ + return -ENOSYS; +} + #endif #if defined(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) -int imx_bbu_external_nand_register_handler(const char *name, char *devicefile, +int imx_bbu_external_nand_register_handler(const char *name, const char *devicefile, unsigned long flags); #else -static inline int imx_bbu_external_nand_register_handler(const char *name, char *devicefile, +static inline int imx_bbu_external_nand_register_handler(const char *name, const char *devicefile, unsigned long flags) { return -ENOSYS; diff --git a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h index 0649caa0cb..5818879609 100644 --- a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h +++ b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h @@ -43,3 +43,16 @@ hab [Authenticate Data] hab Verification index = 2 hab_blocks + +hab_encrypt [Install Secret Key] +hab_encrypt Verification index = 0 +hab_encrypt Target index = 0 +hab_encrypt_key +hab_encrypt_key_length 256 +hab_encrypt_blob_address + +hab_encrypt [Decrypt Data] +hab_encrypt Verification index = 0 +hab_encrypt Mac Bytes = 16 + +hab_encrypt_blocks diff --git a/arch/arm/mach-imx/include/mach/imx-header.h b/arch/arm/mach-imx/include/mach/imx-header.h index c9b2a58819..05f1669318 100644 --- a/arch/arm/mach-imx/include/mach/imx-header.h +++ b/arch/arm/mach-imx/include/mach/imx-header.h @@ -4,6 +4,14 @@ #include <linux/types.h> #define HEADER_LEN 0x1000 /* length of the blank area + IVT + DCD */ +#define CSF_LEN 0x2000 /* length of the CSF (needed for HAB) */ + +#define DEK_BLOB_HEADER 8 /* length of DEK blob header */ +#define DEK_BLOB_KEY 32 /* length of DEK blob AES-256 key */ +#define DEK_BLOB_MAC 16 /* length of DEK blob MAC */ + +/* DEK blob length excluding DEK itself */ +#define DEK_BLOB_OVERHEAD (DEK_BLOB_HEADER + DEK_BLOB_KEY + DEK_BLOB_MAC) /* * ============================================================================ @@ -47,6 +55,14 @@ struct imx_dcd_rec_v1 { #define PARAMETER_FLAG_MASK (1 << 3) #define PARAMETER_FLAG_SET (1 << 4) +#define PLUGIN_HDMI_IMAGE 0x0002 + +/* + * As per Table 6-22 "eMMC/SD BOOT layout", in Normal Boot layout HDMI + * firmware image starts at LBA# 64 and ends at LBA# 271 + */ +#define PLUGIN_HDMI_SIZE ((271 - 64 + 1) * 512) + struct imx_ivt_header { uint8_t tag; uint16_t length; @@ -94,6 +110,9 @@ struct config_data { int (*nop)(const struct config_data *data); int csf_space; char *csf; + char *signed_hdmi_firmware_file; + int encrypt_image; + size_t dek_size; }; #define MAX_RECORDS_DCD_V2 1024 diff --git a/arch/arm/mach-imx/include/mach/imx6-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx6-ccm-regs.h deleted file mode 100644 index 099d5621de..0000000000 --- a/arch/arm/mach-imx/include/mach/imx6-ccm-regs.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define MX6_CCM_CCOSR 0x020c4060 -#define MX6_CCM_CCGR0 0x020C4068 -#define MX6_CCM_CCGR1 0x020C406c -#define MX6_CCM_CCGR2 0x020C4070 -#define MX6_CCM_CCGR3 0x020C4074 -#define MX6_CCM_CCGR4 0x020C4078 -#define MX6_CCM_CCGR5 0x020C407c -#define MX6_CCM_CCGR6 0x020C4080 - -#define MX6_PMU_MISC2 0x020C8170 diff --git a/arch/arm/mach-imx/include/mach/ocotp-fusemap.h b/arch/arm/mach-imx/include/mach/ocotp-fusemap.h index 44b58ca6e8..aec50dbf8a 100644 --- a/arch/arm/mach-imx/include/mach/ocotp-fusemap.h +++ b/arch/arm/mach-imx/include/mach/ocotp-fusemap.h @@ -23,7 +23,11 @@ #define OCOTP_BOOT_CFG2 (OCOTP_WORD(0x450) | OCOTP_BIT(8) | OCOTP_WIDTH(8)) #define OCOTP_BOOT_CFG3 (OCOTP_WORD(0x450) | OCOTP_BIT(16) | OCOTP_WIDTH(8)) #define OCOTP_BOOT_CFG4 (OCOTP_WORD(0x450) | OCOTP_BIT(24) | OCOTP_WIDTH(8)) +/* available on i.MX6SDL silicon revision >=1.4, "reserved" elsewhere */ +#define OCOTP_SDP_DISABLE (OCOTP_WORD(0x460) | OCOTP_BIT(0) | OCOTP_WIDTH(1)) #define OCOTP_SEC_CONFIG_1 (OCOTP_WORD(0x460) | OCOTP_BIT(1) | OCOTP_WIDTH(1)) +/* available on i.MX6SDL silicon revision >=1.4, "reserved" elsewhere */ +#define OCOTP_SDP_READ_DISABLE (OCOTP_WORD(0x460) | OCOTP_BIT(2) | OCOTP_WIDTH(1)) #define OCOTP_DIR_BT_DIS (OCOTP_WORD(0x460) | OCOTP_BIT(3) | OCOTP_WIDTH(1)) #define OCOTP_BT_FUSE_SEL (OCOTP_WORD(0x460) | OCOTP_BIT(4) | OCOTP_WIDTH(1)) #define OCOTP_SJC_DISABLE (OCOTP_WORD(0x460) | OCOTP_BIT(20) | OCOTP_WIDTH(1)) @@ -31,6 +35,8 @@ #define OCOTP_JTAG_SMODE (OCOTP_WORD(0x460) | OCOTP_BIT(22) | OCOTP_WIDTH(2)) #define OCOTP_KTE (OCOTP_WORD(0x460) | OCOTP_BIT(26) | OCOTP_WIDTH(1)) #define OCOTP_JTAG_HEO (OCOTP_WORD(0x460) | OCOTP_BIT(27) | OCOTP_WIDTH(1)) +/* available on i.MX6SDL silicon revision >=1.4, "reserved" elsewhere */ +#define OCOTP_FORCE_INTERNAL_BOOT (OCOTP_WORD(0x460) | OCOTP_BIT(31) | OCOTP_WIDTH(1)) #define OCOTP_NAND_READ_CMD_CODE1 (OCOTP_WORD(0x470) | OCOTP_BIT(0) | OCOTP_WIDTH(8)) #define OCOTP_NAND_READ_CMD_CODE2 (OCOTP_WORD(0x470) | OCOTP_BIT(8) | OCOTP_WIDTH(8)) #define OCOTP_TEMP_SENSE (OCOTP_WORD(0x4e0) | OCOTP_BIT(0) | OCOTP_WIDTH(32)) diff --git a/arch/arm/mach-imx/include/mach/usb.h b/arch/arm/mach-imx/include/mach/usb.h index 85528d77e6..3b5e24d1cc 100644 --- a/arch/arm/mach-imx/include/mach/usb.h +++ b/arch/arm/mach-imx/include/mach/usb.h @@ -14,4 +14,27 @@ int imx6_usb_phy2_disable_oc(void); int imx6_usb_phy2_enable(void); +#define USBCMD 0x140 +#define USB_CMD_RESET 0x00000002 + +/* + * imx_reset_otg_controller - reset the USB OTG controller + * @base: The base address of the controller + * + * When booting from USB the ROM just leaves the controller enabled. This can + * have bad side effects when for example we change PLL frequencies. In this + * case it is seen that the hub the board is connected to gets confused and USB + * is no longer working properly on the remote host. This function resets the + * OTG controller. It should be called before the clocks the controller hangs on + * is fiddled with. + */ +static inline void imx_reset_otg_controller(void __iomem *base) +{ + u32 r; + + r = readl(base + USBCMD); + r |= USB_CMD_RESET; + writel(r, base + USBCMD); +} + #endif /* __MACH_USB_H_*/ diff --git a/arch/arm/mach-imx/xload-esdhc.c b/arch/arm/mach-imx/xload-esdhc.c index 55d6c69299..6455cabf98 100644 --- a/arch/arm/mach-imx/xload-esdhc.c +++ b/arch/arm/mach-imx/xload-esdhc.c @@ -224,24 +224,47 @@ esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, ptrdiff_t entry, u32 o { void *buf = (void *)address; - struct imx_flash_header_v2 *hdr = buf + offset + SZ_1K; + struct imx_flash_header_v2 *hdr; int ret, len; void __noreturn (*bb)(void); unsigned int ofs; + int i, header_count = 1; len = imx_image_size(); len = ALIGN(len, SECTOR_SIZE); - ret = esdhc_read_blocks(esdhc, buf, offset + SZ_1K + SECTOR_SIZE); - if (ret) - return ret; + for (i = 0; i < header_count; i++) { + ret = esdhc_read_blocks(esdhc, buf, + offset + SZ_1K + SECTOR_SIZE); + if (ret) + return ret; - if (!is_imx_flash_header_v2(hdr)) { - pr_debug("IVT header not found on SD card. " - "Found tag: 0x%02x length: 0x%04x version: %02x\n", - hdr->header.tag, hdr->header.length, - hdr->header.version); - return -EINVAL; + hdr = buf + offset + SZ_1K; + + if (!is_imx_flash_header_v2(hdr)) { + pr_debug("IVT header not found on SD card. " + "Found tag: 0x%02x length: 0x%04x " + "version: %02x\n", + hdr->header.tag, hdr->header.length, + hdr->header.version); + return -EINVAL; + } + + if (IS_ENABLED(CONFIG_ARCH_IMX8MQ) && + hdr->boot_data.plugin & PLUGIN_HDMI_IMAGE) { + /* + * In images that include signed HDMI + * firmware, first v2 header would be + * dedicated to that and would not contain any + * useful for us information. In order for us + * to pull the rest of the bootloader image + * in, we need to re-read header from SD/MMC, + * this time skipping anything HDMI firmware + * related. + */ + offset += hdr->boot_data.size + hdr->header.length; + header_count++; + } } pr_debug("Check ok, loading image\n"); diff --git a/arch/arm/mach-imx/xload.c b/arch/arm/mach-imx/xload.c deleted file mode 100644 index 921e9ade20..0000000000 --- a/arch/arm/mach-imx/xload.c +++ /dev/null @@ -1,52 +0,0 @@ -#include <bootsource.h> -#include <bootstrap.h> -#include <common.h> -#include <malloc.h> -#include <init.h> -#include <envfs.h> -#include <linux/sizes.h> -#include <fs.h> -#include <io.h> - -#include <linux/clkdev.h> -#include <linux/stat.h> -#include <linux/clk.h> - -#include <mach/devices-imx51.h> - -static __noreturn int imx_xload(void) -{ - enum bootsource bootsource = bootsource_get(); - void *buf; - - switch (bootsource) { - case BOOTSOURCE_MMC: - pr_info("booting from MMC\n"); - buf = bootstrap_read_disk("disk0.0", "fat"); - break; - case BOOTSOURCE_SPI_NOR: - pr_info("booting from SPI\n"); - buf = bootstrap_read_devfs("dataflash0", false, - SZ_256K, SZ_1M, SZ_1M); - break; - default: - pr_err("unknown bootsource %d\n", bootsource); - hang(); - } - - if (!buf) { - pr_err("failed to load barebox.bin\n"); - hang(); - } - - bootstrap_boot(buf, 0); - - hang(); -} - -static int imx_devices_init(void) -{ - barebox_main = imx_xload; - return 0; -} -coredevice_initcall(imx_devices_init); diff --git a/arch/arm/mach-omap/am33xx_bbu_emmc.c b/arch/arm/mach-omap/am33xx_bbu_emmc.c index d3adb3744c..1fd7222ddc 100644 --- a/arch/arm/mach-omap/am33xx_bbu_emmc.c +++ b/arch/arm/mach-omap/am33xx_bbu_emmc.c @@ -73,7 +73,7 @@ error_save_part_table: error: close(fd); - return ret; + return (ret > 0) ? 0 : ret; } int am33xx_bbu_emmc_mlo_register_handler(const char *name, char *devicefile) |