4 files changed, 230 insertions, 0 deletions
diff --git a/board/pcm038/Makefile b/board/pcm038/Makefile
new file mode 100644
index 0000000000..6082b2d657
--- /dev/null
+++ b/board/pcm038/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += lowlevel_init.o
+obj-y += pcm038.o
diff --git a/board/pcm038/lowlevel_init.S b/board/pcm038/lowlevel_init.S
new file mode 100644
index 0000000000..fc65b902b6
--- /dev/null
+++ b/board/pcm038/lowlevel_init.S
@@ -0,0 +1,98 @@
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+
+#define writel(val, reg) \
+	ldr		r0,	=reg;	\
+	ldr		r1,	=val;	\
+	str		r1,   [r0];
+
+#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn)  (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0))
+
+.globl board_init_lowlevel
+board_init_lowlevel:
+
+	mov	r10, lr
+
+	/*
+	 * AHB-Lite IP Interface
+	 */
+	writel(0x20040304, AIPI1_PSR0)
+	writel(0xDFFBFCFB, AIPI1_PSR1)
+	writel(0x00000000, AIPI2_PSR0)
+	writel(0xFFFFFFFF, AIPI2_PSR1)
+
+	ldr r0, =CSCR
+	ldr r1, [r0]
+	bic r1, r1, #0x3
+	str r1, [r0] 
+
+	writel(0x00041c02, MPCTL0)
+	writel(0x04082008, SPCTL0)
+
+	writel(0x33f00304, CSCR)
+	writel(0x33f00300 | CSCR_FPM_EN | CSCR_MPEN | CSCR_SPEN | CSCR_MCU_SEL |
+			CSCR_SP_SEL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART |
+			0 ,
+			CSCR)
+
+	/* add some delay here */
+	mov r1, #0x1000
+1:	subs r1, r1, #0x1
+	bne 1b
+
+	writel(0x33f00300 | CSCR_FPM_EN | CSCR_MPEN | CSCR_SPEN | CSCR_MCU_SEL |
+			CSCR_SP_SEL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART |
+			CSCR_ARM_SRC_MPLL,
+			CSCR)
+
+	writel(0x00070f08, GPCR)
+
+	writel(0x130410c3, PCDR0)
+	writel(0x09030913, PCDR1)
+
+	/* skip sdram setup for debugging */
+	mov	pc,r10
+
+	/* Skip SDRAM initialization if we run from RAM */
+	cmp	pc, #0xa0000000
+	bls	1f
+	cmp	pc, #0xc0000000
+	bhi	1f
+
+	mov	pc,r10
+
+1:
+	/*
+	 * DDR on CSD0
+	 */
+	writel(0x00000008, 0xD8001010)
+	writel(0x55555555, 0x10027828)
+	writel(0x55555555, 0x10027830)
+	writel(0x55555555, 0x10027834)
+	writel(0x00005005, 0x10027838)
+	writel(0x15555555, 0x1002783C)
+	writel(0x00000004, 0xD8001010)
+	writel(0x006ac73a, 0xD8001004)
+	writel(0x92100000, 0xD8001000)
+	writel(0x00000000, 0xA0000F00)
+	writel(0xA2100000, 0xD8001000)
+	writel(0x00000000, 0xA0000F00)
+	writel(0x00000000, 0xA0000F00)
+	writel(0x00000000, 0xA0000F00)
+	writel(0x00000000, 0xA0000F00)
+	writel(0xA2200000, 0xD8001000)
+	writel(0x00000000, 0xA0000F00)
+	writel(0x00000000, 0xA0000F00)
+	writel(0x00000000, 0xA0000F00)
+	writel(0x00000000, 0xA0000F00)
+	writel(0xb2100000, 0xD8001000)
+	ldr		r0, =0xA0000033
+	mov		r1, #0xda
+	strb		r1, [r0]
+	ldr		r0, =0xA1000000
+	mov		r1, #0xff
+	strb		r1, [r0]
+	writel(0x82226080, 0xD8001000)
+
+	mov	pc,r10
+
diff --git a/board/pcm038/pcm038.c b/board/pcm038/pcm038.c
new file mode 100644
index 0000000000..99cbc5eec4
--- /dev/null
+++ b/board/pcm038/pcm038.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <net.h>
+#include <cfi_flash.h>
+#include <init.h>
+#include <environment.h>
+#include <asm/arch/imx-regs.h>
+#include <fec.h>
+#include <asm/arch/gpio.h>
+#include <partition.h>
+#include <fs.h>
+#include <fcntl.h>
+
+static struct device_d cfi_dev = {
+	.name     = "cfi_flash",
+	.id       = "nor0",
+
+	.map_base = 0xC0000000,
+	.size     = 32 * 1024 * 1024,
+};
+
+static struct device_d sdram_dev = {
+	.name     = "ram",
+	.id       = "ram0",
+
+	.map_base = 0xa0000000,
+	.size     = 128 * 1024 * 1024,
+
+	.type     = DEVICE_TYPE_DRAM,
+};
+
+static struct fec_platform_data fec_info = {
+	.xcv_type = MII100,
+};
+
+static struct device_d fec_dev = {
+	.name     = "fec_imx27",
+	.id       = "eth0",
+	.map_base = 0x1002b000,
+	.platform_data	= &fec_info,
+	.type     = DEVICE_TYPE_ETHER,
+};
+
+static int pcm038_devices_init(void)
+{
+	int i;
+	unsigned int mode[] = {
+		PD0_AIN_FEC_TXD0,
+		PD1_AIN_FEC_TXD1,
+		PD2_AIN_FEC_TXD2,
+		PD3_AIN_FEC_TXD3,
+		PD4_AOUT_FEC_RX_ER,
+		PD5_AOUT_FEC_RXD1,
+		PD6_AOUT_FEC_RXD2,
+		PD7_AOUT_FEC_RXD3,
+		PD8_AF_FEC_MDIO,
+		PD9_AIN_FEC_MDC | GPIO_PUEN,
+		PD10_AOUT_FEC_CRS,
+		PD11_AOUT_FEC_TX_CLK,
+		PD12_AOUT_FEC_RXD0,
+		PD13_AOUT_FEC_RX_DV,
+		PD14_AOUT_FEC_CLR,
+		PD15_AOUT_FEC_COL,
+		PD16_AIN_FEC_TX_ER,
+		PF23_AIN_FEC_TX_EN,
+		PE12_PF_UART1_TXD,
+		PE13_PF_UART1_RXD,
+		PE14_PF_UART1_CTS,
+		PE15_PF_UART1_RTS };
+
+	for (i = 0; i < sizeof(mode) / sizeof(int); i++)
+		imx_gpio_mode(mode[i]);
+
+	register_device(&cfi_dev);
+	register_device(&sdram_dev);
+	register_device(&fec_dev);
+
+	dev_add_partition(&cfi_dev, 0x00000, 0x20000, PARTITION_FIXED, "self");
+	dev_add_partition(&cfi_dev, 0x40000, 0x20000, PARTITION_FIXED, "env");
+	dev_protect(&cfi_dev, 0x20000, 0, 1);
+
+	return 0;
+}
+
+device_initcall(pcm038_devices_init);
+
+static struct device_d pcm038_serial_device = {
+	.name     = "imx_serial",
+	.id       = "cs0",
+	.map_base = IMX_UART1_BASE,
+	.size     = 4096,
+	.type     = DEVICE_TYPE_CONSOLE,
+};
+
+static int pcm038_console_init(void)
+{
+	register_device(&pcm038_serial_device);
+	return 0;
+}
+
+console_initcall(pcm038_console_init);
+
diff --git a/board/pcm038/pcm038.dox b/board/pcm038/pcm038.dox
new file mode 100644
index 0000000000..9b17674a21
--- /dev/null
+++ b/board/pcm038/pcm038.dox
@@ -0,0 +1,8 @@
+/** @page pcm038 Phytec's phyCORE-i.MX27
+
+This CPU card is based on a Freescale i.MX27 CPU. The card is shipped with:
+
+- up to 32MiB NOR type Flash Memory
+- 32MiB synchronous dynamic RAM
+
+*/