diff options
Diffstat (limited to 'drivers/clk/clk-divider.c')
-rw-r--r-- | drivers/clk/clk-divider.c | 176 |
1 files changed, 131 insertions, 45 deletions
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 78b4153171..ccab70aecc 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -1,26 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * clk-divider.c - generic barebox clock support. Based on Linux clk support * * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> #include <io.h> #include <malloc.h> -#include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/err.h> #include <linux/log2.h> -#include <asm-generic/div64.h> +#include <linux/math64.h> static unsigned int _get_table_maxdiv(const struct clk_div_table *table) { @@ -98,14 +88,21 @@ unsigned long divider_recalc_rate(struct clk *clk, unsigned long parent_rate, unsigned int div; div = _get_div(table, val, flags, width); + if (!div) { + WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO), + "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", + clk->name); + return parent_rate; + } return DIV_ROUND_UP_ULL((u64)parent_rate, div); } -static unsigned long clk_divider_recalc_rate(struct clk *clk, +static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_divider *divider = container_of(clk, struct clk_divider, clk); + struct clk *clk = clk_hw_to_clk(hw); + struct clk_divider *divider = container_of(hw, struct clk_divider, hw); unsigned int val; val = readl(divider->reg) >> divider->shift; @@ -243,13 +240,47 @@ long divider_round_rate(struct clk *clk, unsigned long rate, return DIV_ROUND_UP(*prate, div); } -static long clk_divider_round_rate(struct clk *clk, unsigned long rate, +long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, + unsigned long rate, unsigned long *prate, + const struct clk_div_table *table, + u8 width, unsigned long flags) +{ + int div; + + div = clk_divider_bestdiv(&hw->clk, rate, prate, table, width, flags); + + return DIV_ROUND_UP_ULL((u64)*prate, div); +} +EXPORT_SYMBOL_GPL(divider_round_rate_parent); + +long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, + unsigned long rate, unsigned long *prate, + const struct clk_div_table *table, u8 width, + unsigned long flags, unsigned int val) +{ + int div; + + div = _get_div(table, val, flags, width); + + /* Even a read-only clock can propagate a rate change */ + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { + if (!*prate) + return -EINVAL; + + *prate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * div); + } + + return DIV_ROUND_UP_ULL((u64)*prate, div); +} + +static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { - struct clk_divider *divider = container_of(clk, struct clk_divider, clk); + struct clk *clk = clk_hw_to_clk(hw); + struct clk_divider *divider = to_clk_divider(hw); if (divider->flags & CLK_DIVIDER_READ_ONLY) - return clk_divider_recalc_rate(clk, *prate); + return clk_divider_recalc_rate(hw, *prate); return divider_round_rate(clk, rate, prate, divider->table, divider->width, divider->flags); @@ -271,23 +302,22 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate, return min_t(unsigned int, value, clk_div_mask(width)); } -static int clk_divider_set_rate(struct clk *clk, unsigned long rate, +static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_divider *divider = container_of(clk, struct clk_divider, clk); - unsigned int div, value; + struct clk *clk = clk_hw_to_clk(hw); + struct clk_divider *divider = to_clk_divider(hw); + unsigned int value; u32 val; if (divider->flags & CLK_DIVIDER_READ_ONLY) return 0; if (clk->flags & CLK_SET_RATE_PARENT) { - unsigned long best_parent_rate = parent_rate; - div = clk_divider_bestdiv(clk, rate, &best_parent_rate, - divider->table, divider->width, divider->flags); - clk_set_rate(clk_get_parent(clk), best_parent_rate); - } else { - div = DIV_ROUND_UP(parent_rate, rate); + clk_divider_bestdiv(clk, rate, &parent_rate, + divider->table, divider->width, + divider->flags); + clk_set_rate(clk_get_parent(clk), parent_rate); } value = divider_get_val(rate, parent_rate, divider->table, @@ -297,7 +327,7 @@ static int clk_divider_set_rate(struct clk *clk, unsigned long rate, val &= ~(clk_div_mask(divider->width) << divider->shift); val |= value << divider->shift; - if (clk->flags & CLK_DIVIDER_HIWORD_MASK) + if (divider->flags & CLK_DIVIDER_HIWORD_MASK) val |= clk_div_mask(divider->width) << (divider->shift + 16); writel(val, divider->reg); @@ -305,12 +335,16 @@ static int clk_divider_set_rate(struct clk *clk, unsigned long rate, return 0; } -struct clk_ops clk_divider_ops = { +const struct clk_ops clk_divider_ops = { .set_rate = clk_divider_set_rate, .recalc_rate = clk_divider_recalc_rate, .round_rate = clk_divider_round_rate, }; +const struct clk_ops clk_divider_ro_ops = { + .recalc_rate = clk_divider_recalc_rate, +}; + struct clk *clk_divider_alloc(const char *name, const char *parent, unsigned clk_flags, void __iomem *reg, u8 shift, u8 width, unsigned div_flags) @@ -322,18 +356,19 @@ struct clk *clk_divider_alloc(const char *name, const char *parent, div->width = width; div->parent = parent; div->flags = div_flags; - div->clk.ops = &clk_divider_ops; - div->clk.name = name; - div->clk.flags = clk_flags; - div->clk.parent_names = &div->parent; - div->clk.num_parents = 1; + div->hw.clk.ops = &clk_divider_ops; + div->hw.clk.name = name; + div->hw.clk.flags = clk_flags; + div->hw.clk.parent_names = &div->parent; + div->hw.clk.num_parents = 1; - return &div->clk; + return &div->hw.clk; } void clk_divider_free(struct clk *clk) { - struct clk_divider *d = container_of(clk, struct clk_divider, clk); + struct clk_hw *hw = clk_to_clk_hw(clk); + struct clk_divider *d = to_clk_divider(hw); free(d); } @@ -347,7 +382,7 @@ struct clk *clk_divider(const char *name, const char *parent, unsigned clk_flags d = clk_divider_alloc(name , parent, clk_flags, reg, shift, width, div_flags); - ret = clk_register(d); + ret = bclk_register(d); if (ret) { clk_divider_free(d); return ERR_PTR(ret); @@ -362,12 +397,15 @@ struct clk *clk_divider_one_based(const char *name, const char *parent, { struct clk_divider *div; struct clk *clk; + struct clk_hw *hw; clk = clk_divider(name, parent, clk_flags, reg, shift, width, div_flags); if (IS_ERR(clk)) return clk; - div = container_of(clk, struct clk_divider, clk); + hw = clk_to_clk_hw(clk); + div = to_clk_divider(hw); + div->flags |= CLK_DIVIDER_ONE_BASED; return clk; @@ -387,11 +425,11 @@ struct clk *clk_divider_table(const char *name, const char *parent, div->width = width; div->parent = parent; div->flags = div_flags; - div->clk.ops = &clk_divider_ops; - div->clk.name = name; - div->clk.flags = clk_flags; - div->clk.parent_names = &div->parent; - div->clk.num_parents = 1; + div->hw.clk.ops = &clk_divider_ops; + div->hw.clk.name = name; + div->hw.clk.flags = clk_flags; + div->hw.clk.parent_names = &div->parent; + div->hw.clk.num_parents = 1; div->table = table; for (clkt = div->table; clkt->div; clkt++) { @@ -402,11 +440,59 @@ struct clk *clk_divider_table(const char *name, const char *parent, div->table_size++; } - ret = clk_register(&div->clk); + ret = bclk_register(&div->hw.clk); if (ret) { free(div); return ERR_PTR(ret); } - return &div->clk; + return &div->hw.clk; +} + +struct clk *clk_register_divider_table(struct device *dev, const char *name, + const char *parent_name, + unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, + const struct clk_div_table *table, + spinlock_t *lock) +{ + return clk_divider_table(name, parent_name, flags, reg, shift, width, + table, clk_divider_flags); +} + +struct clk *clk_register_divider(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, spinlock_t *lock) +{ + return clk_divider(name, parent_name, flags, reg, shift, width, + clk_divider_flags); +} + +struct clk_hw *clk_hw_register_divider_table(struct device *dev, + const char *name, + const char *parent_name, + unsigned long flags, + void __iomem *reg, u8 shift, + u8 width, + u8 clk_divider_flags, + const struct clk_div_table *table, + spinlock_t *lock) +{ + return clk_to_clk_hw(clk_register_divider_table(dev, xstrdup(name), + xstrdup(parent_name), flags, reg, shift, width, + clk_divider_flags, table, lock)); +} + +struct clk_hw *clk_hw_register_divider(struct device *dev, + const char *name, + const char *parent_name, + unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, spinlock_t *lock) +{ + return clk_to_clk_hw(clk_register_divider(dev, xstrdup(name), + xstrdup(parent_name), flags, reg, shift, width, + clk_divider_flags, lock)); } |