diff options
Diffstat (limited to 'drivers/clk/imx/clk-composite-8m.c')
| -rw-r--r-- | drivers/clk/imx/clk-composite-8m.c | 87 |
1 files changed, 69 insertions, 18 deletions
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index 0cd52b5b46..04d83d208b 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright 2018 NXP */ @@ -15,6 +15,7 @@ #define PCG_PREDIV_MAX 8 #define PCG_DIV_SHIFT 0 +#define PCG_CORE_DIV_WIDTH 3 #define PCG_DIV_WIDTH 6 #define PCG_DIV_MAX 64 @@ -25,10 +26,11 @@ #define clk_div_mask(width) ((1 << (width)) - 1) -static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk *clk, +static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_divider *divider = container_of(clk, struct clk_divider, clk); + struct clk_divider *divider = container_of(hw, struct clk_divider, hw); + struct clk *clk = clk_hw_to_clk(hw); unsigned long prediv_rate; unsigned int prediv_value; unsigned int div_value; @@ -73,7 +75,7 @@ static int imx8m_clk_composite_compute_dividers(unsigned long rate, return ret; } -static long imx8m_clk_composite_divider_round_rate(struct clk *clk, +static long imx8m_clk_composite_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { @@ -88,11 +90,11 @@ static long imx8m_clk_composite_divider_round_rate(struct clk *clk, } -static int imx8m_clk_composite_divider_set_rate(struct clk *clk, +static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_divider *divider = container_of(clk, struct clk_divider, clk); + struct clk_divider *divider = container_of(hw, struct clk_divider, hw); int prediv_value; int div_value; int ret; @@ -113,6 +115,29 @@ static int imx8m_clk_composite_divider_set_rate(struct clk *clk, return ret; } +static int imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) +{ + return clk_mux_ops.get_parent(hw); +} + +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_mux *m = container_of(hw, struct clk_mux, hw); + u32 val; + + val = readl(m->reg); + val &= ~(((1 << m->width) - 1) << m->shift); + val |= index << m->shift; + + /* + * write twice to make sure non-target interface + * SEL_A/B point the same clk input. + */ + writel(val, m->reg); + writel(val, m->reg); + + return 0; +} static const struct clk_ops imx8m_clk_composite_divider_ops = { .recalc_rate = imx8m_clk_composite_divider_recalc_rate, @@ -120,52 +145,78 @@ static const struct clk_ops imx8m_clk_composite_divider_ops = { .set_rate = imx8m_clk_composite_divider_set_rate, }; +static const struct clk_ops imx8m_clk_composite_mux_ops = { + .get_parent = imx8m_clk_composite_mux_get_parent, + .set_parent = imx8m_clk_composite_mux_set_parent, + .set_rate = clk_parent_set_rate, + .round_rate = clk_parent_round_rate, +}; + struct clk *imx8m_clk_composite_flags(const char *name, - const char **parent_names, + const char * const *parent_names, int num_parents, void __iomem *reg, + u32 composite_flags, unsigned long flags) { - struct clk *comp = ERR_PTR(-ENOMEM); + struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw; + struct clk_hw *div_hw, *gate_hw = NULL; struct clk_divider *div = NULL; struct clk_gate *gate = NULL; struct clk_mux *mux = NULL; + const struct clk_ops *divider_ops; + const struct clk_ops *mux_ops; mux = kzalloc(sizeof(*mux), GFP_KERNEL); if (!mux) goto fail; + mux_hw = &mux->hw; mux->reg = reg; mux->shift = PCG_PCS_SHIFT; mux->width = PCG_PCS_WIDTH; - mux->clk.ops = &clk_mux_ops; div = kzalloc(sizeof(*div), GFP_KERNEL); if (!div) goto fail; + div_hw = &div->hw; div->reg = reg; - div->shift = PCG_PREDIV_SHIFT; - div->width = PCG_PREDIV_WIDTH; - div->clk.ops = &imx8m_clk_composite_divider_ops; + if (composite_flags & IMX_COMPOSITE_CORE) { + div->shift = PCG_DIV_SHIFT; + div->width = PCG_CORE_DIV_WIDTH; + divider_ops = &clk_divider_ops; + mux_ops = &imx8m_clk_composite_mux_ops; + } else if (composite_flags & IMX_COMPOSITE_BUS) { + div->shift = PCG_PREDIV_SHIFT; + div->width = PCG_PREDIV_WIDTH; + divider_ops = &imx8m_clk_composite_divider_ops; + mux_ops = &imx8m_clk_composite_mux_ops; + } else { + div->shift = PCG_PREDIV_SHIFT; + div->width = PCG_PREDIV_WIDTH; + divider_ops = &imx8m_clk_composite_divider_ops; + mux_ops = &clk_mux_ops; + } gate = kzalloc(sizeof(*gate), GFP_KERNEL); if (!gate) goto fail; + gate_hw = &gate->hw; gate->reg = reg; gate->shift = PCG_CGC_SHIFT; - gate->clk.ops = &clk_gate_ops; - comp = clk_register_composite(name, parent_names, num_parents, - &mux->clk, &div->clk, &gate->clk, flags); - if (IS_ERR(comp)) + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, + mux_hw, mux_ops, div_hw, + divider_ops, gate_hw, &clk_gate_ops, flags); + if (IS_ERR(hw)) goto fail; - return comp; + return clk_hw_to_clk(hw); fail: kfree(gate); kfree(div); kfree(mux); - return ERR_CAST(comp); + return ERR_CAST(hw); } |