diff options
Diffstat (limited to 'drivers/clk/imx/clk.h')
| -rw-r--r-- | drivers/clk/imx/clk.h | 167 |
1 files changed, 148 insertions, 19 deletions
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 04286f03f7..32e4903837 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __IMX_CLK_H #define __IMX_CLK_H @@ -39,11 +40,19 @@ static inline struct clk *imx_clk_divider_table(const char *name, width, table, 0); } +static inline struct clk *__imx_clk_mux(const char *name, void __iomem *reg, + u8 shift, u8 width, const char * const *parents, + u8 num_parents, unsigned flags, unsigned long clk_mux_flags) +{ + return clk_mux(name, CLK_SET_RATE_NO_REPARENT | flags, reg, + shift, width, parents, num_parents, clk_mux_flags); +} + static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg, - u8 shift, u8 width, const char **parents, int num_parents) + u8 shift, u8 width, const char * const *parents, int num_parents) { - return clk_mux(name, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg, - shift, width, parents, num_parents, CLK_MUX_READ_ONLY); + return __imx_clk_mux(name, reg, shift, width, parents, num_parents, + CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY); } @@ -55,39 +64,39 @@ static inline struct clk *imx_clk_fixed_factor(const char *name, static inline struct clk *imx_clk_mux_flags(const char *name, void __iomem *reg, u8 shift, u8 width, - const char **parents, u8 num_parents, + const char * const *parents, u8 num_parents, unsigned long clk_flags) { - return clk_mux(name, clk_flags, reg, shift, width, parents, num_parents, - 0); + return __imx_clk_mux(name, reg, shift, width, parents, num_parents, + clk_flags, 0); } static inline struct clk *imx_clk_mux2_flags(const char *name, - void __iomem *reg, u8 shift, u8 width, const char **parents, + void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, unsigned long clk_flags) { - return clk_mux(name, clk_flags | CLK_OPS_PARENT_ENABLE, reg, shift, - width, parents, num_parents, 0); + return __imx_clk_mux(name,reg, shift, width, parents, num_parents, + clk_flags | CLK_OPS_PARENT_ENABLE, 0); } static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, - u8 shift, u8 width, const char **parents, u8 num_parents) + u8 shift, u8 width, const char * const *parents, u8 num_parents) { - return clk_mux(name, 0, reg, shift, width, parents, num_parents, 0); + return __imx_clk_mux(name, reg, shift, width, parents, num_parents, 0, 0); } static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, - u8 shift, u8 width, const char **parents, u8 num_parents) + u8 shift, u8 width, const char * const *parents, u8 num_parents) { - return clk_mux(name, CLK_OPS_PARENT_ENABLE, reg, shift, width, parents, - num_parents, 0); + return __imx_clk_mux(name, reg, shift, width, parents, + num_parents, CLK_OPS_PARENT_ENABLE, 0); } static inline struct clk *imx_clk_mux_p(const char *name, void __iomem *reg, - u8 shift, u8 width, const char **parents, u8 num_parents) + u8 shift, u8 width, const char * const *parents, u8 num_parents) { - return clk_mux(name, CLK_SET_RATE_PARENT, reg, shift, width, parents, - num_parents, 0); + return __imx_clk_mux(name, reg, shift, width, parents, num_parents, + CLK_SET_RATE_PARENT, 0); } static inline struct clk *imx_clk_gate(const char *name, const char *parent, @@ -140,6 +149,12 @@ static inline struct clk *imx_clk_gate4(const char *name, const char *parent, return clk_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE); } +static inline struct clk *imx_clk_gate4_flags(const char *name, const char *parent, + void __iomem *reg, u8 shift, unsigned long flags) +{ + return clk_gate2(name, parent, reg, shift, 0x3, flags | CLK_OPS_PARENT_ENABLE); +} + static inline struct clk *imx_clk_gate_shared(const char *name, const char *parent, const char *shared) { @@ -168,6 +183,50 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent, void __iomem *base, u32 div_mask); +enum imx_pll14xx_type { + PLL_1416X, + PLL_1443X, +}; + +/* NOTE: Rate table should be kept sorted in descending order. */ +struct imx_pll14xx_rate_table { + unsigned int rate; + unsigned int pdiv; + unsigned int mdiv; + unsigned int sdiv; + unsigned int kdiv; +}; + +#define PLL_1416X_RATE(_rate, _m, _p, _s) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + } + +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + .kdiv = (_k), \ + } + +struct imx_pll14xx_clk { + enum imx_pll14xx_type type; + const struct imx_pll14xx_rate_table *rate_table; + int rate_count; + int flags; +}; + +extern struct imx_pll14xx_clk imx_1443x_pll; +extern struct imx_pll14xx_clk imx_1416x_pll; + +struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, + void __iomem *base, const struct imx_pll14xx_clk *pll_clk); + struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, void __iomem *base); @@ -214,16 +273,86 @@ struct clk *imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); +#define IMX_COMPOSITE_CORE BIT(0) +#define IMX_COMPOSITE_BUS BIT(1) + +#define IMX_COMPOSITE_CLK_FLAGS_DEFAULT \ + (CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) +#define IMX_COMPOSITE_CLK_FLAGS_CRITICAL \ + (IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_IS_CRITICAL) + struct clk *imx8m_clk_composite_flags(const char *name, - const char **parent_names, int num_parents, void __iomem *reg, + const char * const *parent_names, int num_parents, void __iomem *reg, + u32 composite_flags, unsigned long flags); +#define imx8m_clk_hw_composite_core(name, parent_names, reg) \ + imx8m_clk_hw_composite_flags(name, parent_names, \ + ARRAY_SIZE(parent_names), reg, \ + IMX_COMPOSITE_CORE, \ + IMX_COMPOSITE_CLK_FLAGS_DEFAULT) + +#define imx8m_clk_hw_composite_bus(name, parent_names, reg) \ + imx8m_clk_hw_composite_flags(name, parent_names, \ + ARRAY_SIZE(parent_names), reg, \ + IMX_COMPOSITE_BUS, \ + IMX_COMPOSITE_CLK_FLAGS_DEFAULT) + +#define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \ + imx8m_clk_hw_composite_flags(name, parent_names, \ + ARRAY_SIZE(parent_names), reg, \ + IMX_COMPOSITE_BUS, \ + IMX_COMPOSITE_CLK_FLAGS_CRITICAL) + #define __imx8m_clk_composite(name, parent_names, reg, flags) \ imx8m_clk_composite_flags(name, parent_names, \ - ARRAY_SIZE(parent_names), reg, \ + ARRAY_SIZE(parent_names), reg, 0, \ flags | CLK_OPS_PARENT_ENABLE) #define imx8m_clk_composite(name, parent_names, reg) \ __imx8m_clk_composite(name, parent_names, reg, 0) +#define imx8m_clk_composite_critical(name, parent_names, reg) \ + __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL) + +#include <soc/imx/clk-fracn-gppll.h> + +struct clk *imx93_clk_composite_flags(const char *name, + const char * const *parent_names, + int num_parents, + void __iomem *reg, + u32 domain_id, + unsigned long flags); +#define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \ + imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \ + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) + +struct clk *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name, + unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val, + u32 mask, u32 domain_id, unsigned int *share_count); + +/* + * Names of the above functions used in the Linux Kernel. Added here + * to be able to use the same names in barebox to reduce the diffs + * between barebox and Linux clk drivers. + */ +#define imx_clk_hw_mux imx_clk_mux +#define imx_clk_hw_pll14xx imx_clk_pll14xx +#define imx_clk_hw_gate imx_clk_gate +#define imx_clk_hw_fixed_factor imx_clk_fixed_factor +#define imx_clk_hw_mux_flags imx_clk_mux_flags +#define imx_clk_hw_divider imx_clk_divider +#define imx_clk_hw_divider2 imx_clk_divider2 +#define imx_clk_hw_mux2_flags imx_clk_mux2_flags +#define imx_clk_hw_gate4_flags imx_clk_gate4_flags +#define imx_clk_hw_gate4 imx_clk_gate4 +#define imx_clk_hw_cpu imx_clk_cpu +#define imx_clk_hw_gate2 imx_clk_gate2 +#define imx8m_clk_hw_composite_flags imx8m_clk_composite_flags +#define imx8m_clk_hw_composite imx8m_clk_composite +#define imx8m_clk_hw_composite_critical imx8m_clk_composite_critical +#define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \ + ({ (void)shared_count; imx_clk_gate2_shared2(name, parent, reg, shift); }) +#define imx_clk_hw_mux2 imx_clk_mux2 + #endif /* __IMX_CLK_H */ |