1 files changed, 17 insertions, 23 deletions

diff --git a/drivers/clk/mxs/clk-pll.c b/drivers/clk/mxs/clk-pll.c
index 1b1c9b3543..2c55ab7d8b 100644
--- a/drivers/clk/mxs/clk-pll.c
+++ b/drivers/clk/mxs/clk-pll.c
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
 /*
  * Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
  */
 
 #include <common.h>
@@ -30,18 +24,18 @@
  * and the shift of gate bit is always 31.
  */
 struct clk_pll {
-	struct clk clk;
+	struct clk_hw hw;
 	const char *parent;
 	void __iomem *base;
 	u8 power;
 	unsigned long rate;
 };
 
-#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, clk)
+#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
 
-static int clk_pll_enable(struct clk *clk)
+static int clk_pll_enable(struct clk_hw *hw)
 {
-	struct clk_pll *pll = to_clk_pll(clk);
+	struct clk_pll *pll = to_clk_pll(hw);
 
 	writel(1 << pll->power, pll->base + SET);
 
@@ -52,18 +46,18 @@ static int clk_pll_enable(struct clk *clk)
 	return 0;
 }
 
-static void clk_pll_disable(struct clk *clk)
+static void clk_pll_disable(struct clk_hw *hw)
 {
-	struct clk_pll *pll = to_clk_pll(clk);
+	struct clk_pll *pll = to_clk_pll(hw);
 
 	writel(1 << 31, pll->base + SET);
 
 	writel(1 << pll->power, pll->base + CLR);
 }
 
-static int clk_pll_is_enabled(struct clk *clk)
+static int clk_pll_is_enabled(struct clk_hw *hw)
 {
-	struct clk_pll *pll = to_clk_pll(clk);
+	struct clk_pll *pll = to_clk_pll(hw);
 	u32 val;
 
 	val = readl(pll->base);
@@ -74,10 +68,10 @@ static int clk_pll_is_enabled(struct clk *clk)
 		return 1;
 }
 
-static unsigned long clk_pll_recalc_rate(struct clk *clk,
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 					 unsigned long parent_rate)
 {
-	struct clk_pll *pll = to_clk_pll(clk);
+	struct clk_pll *pll = to_clk_pll(hw);
 
 	return pll->rate;
 }
@@ -98,18 +92,18 @@ struct clk *mxs_clk_pll(const char *name, const char *parent_name,
 	pll = xzalloc(sizeof(*pll));
 
 	pll->parent = parent_name;
-	pll->clk.name = name;
-	pll->clk.ops = &clk_pll_ops;
-	pll->clk.parent_names = &pll->parent;
-	pll->clk.num_parents = 1;
+	pll->hw.clk.name = name;
+	pll->hw.clk.ops = &clk_pll_ops;
+	pll->hw.clk.parent_names = &pll->parent;
+	pll->hw.clk.num_parents = 1;
 
 	pll->base = base;
 	pll->rate = rate;
 	pll->power = power;
 
-	ret = clk_register(&pll->clk);
+	ret = bclk_register(&pll->hw.clk);
 	if (ret)
 		ERR_PTR(ret);
 
-	return &pll->clk;
+	return &pll->hw.clk;
 }