diff options
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/Makefile | 7 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk-cpu.c | 87 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk-inverter.c | 107 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk-mmc-phase.c | 192 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk-muxgrf.c | 95 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk-pll.c | 1084 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3188.c | 374 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3288.c | 320 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3399.c | 1654 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3568.c | 1751 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3588.c | 2533 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk.c | 548 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 641 | ||||
| -rw-r--r-- | drivers/clk/rockchip/rst-rk3588.c | 855 | ||||
| -rw-r--r-- | drivers/clk/rockchip/softrst.c | 126 |
15 files changed, 9728 insertions, 646 deletions
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index e43f57304c..f01014da0c 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -1,3 +1,8 @@ -obj-y += clk-cpu.o clk-pll.o clk.o +# SPDX-License-Identifier: GPL-2.0-only +obj-y += clk-cpu.o clk-pll.o clk.o clk-muxgrf.o clk-mmc-phase.o clk-inverter.o +obj-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-$(CONFIG_ARCH_RK3188) += clk-rk3188.o obj-$(CONFIG_ARCH_RK3288) += clk-rk3288.o +obj-$(CONFIG_ARCH_RK3399) += clk-rk3399.o +obj-$(CONFIG_ARCH_RK3568) += clk-rk3568.o +obj-$(CONFIG_ARCH_RK3588) += clk-rk3588.o rst-rk3588.o diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 226b819242..8b5d4a0330 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> @@ -6,10 +7,6 @@ * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Author: Thomas Abraham <thomas.ab@samsung.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * A CPU clock is defined as a clock supplied to a CPU or a group of CPUs. * The CPU clock is typically derived from a hierarchy of clock * blocks which includes mux and divider blocks. There are a number of other @@ -37,8 +34,10 @@ #include <malloc.h> #include <io.h> #include <xfuncs.h> -#include "clk.h" #include <linux/barebox-wrapper.h> +#include <linux/clk.h> +#include <linux/spinlock.h> +#include "clk.h" /** * struct rockchip_cpuclk: information about clock supplied to a CPU core. @@ -46,31 +45,34 @@ * @alt_parent: alternate parent clock to use when switching the speed * of the primary parent clock. * @reg_base: base register for cpu-clock values. + * @clk_nb: clock notifier registered for changes in clock speed of the + * primary parent clock. * @rate_count: number of rates in the rate_table * @rate_table: pll-rates and their associated dividers * @reg_data: cpu-specific register settings + * @lock: clock lock */ struct rockchip_cpuclk { - struct clk hw; - + struct clk_hw hw; struct clk *alt_parent; void __iomem *reg_base; unsigned int rate_count; struct rockchip_cpuclk_rate_table *rate_table; const struct rockchip_cpuclk_reg_data *reg_data; + spinlock_t *lock; }; #define to_rockchip_cpuclk_hw(hw) container_of(hw, struct rockchip_cpuclk, hw) -static unsigned long rockchip_cpuclk_recalc_rate(struct clk *hw, +static unsigned long rockchip_cpuclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw); const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; - u32 clksel0 = readl(cpuclk->reg_base + reg_data->core_reg); + u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]); - clksel0 >>= reg_data->div_core_shift; - clksel0 &= reg_data->div_core_mask; + clksel0 >>= reg_data->div_core_shift[0]; + clksel0 &= reg_data->div_core_mask[0]; return parent_rate / (clksel0 + 1); } @@ -79,17 +81,18 @@ static const struct clk_ops rockchip_cpuclk_ops = { }; struct clk *rockchip_clk_register_cpuclk(const char *name, - const char **parent_names, u8 num_parents, + const char *const *parent_names, u8 num_parents, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, - int nrates, void __iomem *reg_base) + int nrates, void __iomem *reg_base, spinlock_t *lock) { struct rockchip_cpuclk *cpuclk; - struct clk *clk; + struct clk_init_data init; + struct clk *clk, *cclk; int ret; - if (num_parents != 2) { - pr_err("%s: needs two parent clocks\n", __func__); + if (num_parents < 2) { + pr_err("%s: needs at least two parent clocks\n", __func__); return ERR_PTR(-EINVAL); } @@ -97,21 +100,28 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, if (!cpuclk) return ERR_PTR(-ENOMEM); - cpuclk->hw.name = name; - cpuclk->hw.parent_names = &parent_names[0]; - cpuclk->hw.num_parents = 1; - cpuclk->hw.ops = &rockchip_cpuclk_ops; + init.name = name; + init.parent_names = &parent_names[reg_data->mux_core_main]; + init.num_parents = 1; + init.ops = &rockchip_cpuclk_ops; /* only allow rate changes when we have a rate table */ - cpuclk->hw.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0; + init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0; + + /* disallow automatic parent changes by ccf */ + init.flags |= CLK_SET_RATE_NO_REPARENT; + + init.flags |= CLK_GET_RATE_NOCACHE; cpuclk->reg_base = reg_base; + cpuclk->lock = lock; cpuclk->reg_data = reg_data; + cpuclk->hw.init = &init; - cpuclk->alt_parent = __clk_lookup(parent_names[1]); + cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]); if (!cpuclk->alt_parent) { - pr_err("%s: could not lookup alternate parent\n", - __func__); + pr_err("%s: could not lookup alternate parent: (%d)\n", + __func__, reg_data->mux_core_alt); ret = -EINVAL; goto free_cpuclk; } @@ -123,37 +133,40 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, goto free_cpuclk; } - clk = __clk_lookup(parent_names[0]); + clk = __clk_lookup(parent_names[reg_data->mux_core_main]); if (!clk) { - pr_err("%s: could not lookup parent clock %s\n", - __func__, parent_names[0]); + pr_err("%s: could not lookup parent clock: (%d) %s\n", + __func__, reg_data->mux_core_main, + parent_names[reg_data->mux_core_main]); ret = -EINVAL; - goto free_cpuclk; + goto free_alt_parent; } if (nrates > 0) { cpuclk->rate_count = nrates; - cpuclk->rate_table = xmemdup(rates, - sizeof(*rates) * nrates - ); + cpuclk->rate_table = kmemdup(rates, + sizeof(*rates) * nrates, + GFP_KERNEL); if (!cpuclk->rate_table) { - pr_err("%s: could not allocate memory for cpuclk rates\n", - __func__); ret = -ENOMEM; - goto free_cpuclk; + goto unregister_notifier; } } - ret = clk_register(&cpuclk->hw); - if (ret) { + cclk = clk_register(NULL, &cpuclk->hw); + if (IS_ERR(cclk)) { pr_err("%s: could not register cpuclk %s\n", __func__, name); + ret = PTR_ERR(cclk); goto free_rate_table; } - return &cpuclk->hw; + return cclk; free_rate_table: kfree(cpuclk->rate_table); +unregister_notifier: +free_alt_parent: + clk_disable(cpuclk->alt_parent); free_cpuclk: kfree(cpuclk); return ERR_PTR(ret); diff --git a/drivers/clk/rockchip/clk-inverter.c b/drivers/clk/rockchip/clk-inverter.c new file mode 100644 index 0000000000..ea72d8c6b2 --- /dev/null +++ b/drivers/clk/rockchip/clk-inverter.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015 Heiko Stuebner <heiko@sntech.de> + */ + +#include <common.h> +#include <of.h> +#include <malloc.h> +#include <io.h> +#include <xfuncs.h> +#include <linux/barebox-wrapper.h> +#include <linux/clk.h> +#include <linux/regmap.h> +#include <linux/spinlock.h> +#include "clk.h" + +struct rockchip_inv_clock { + struct clk_hw hw; + void __iomem *reg; + int shift; + int flags; + spinlock_t *lock; +}; + +#define to_inv_clock(_hw) container_of(_hw, struct rockchip_inv_clock, hw) + +#define INVERTER_MASK 0x1 + +static int rockchip_inv_get_phase(struct clk_hw *hw) +{ + struct rockchip_inv_clock *inv_clock = to_inv_clock(hw); + u32 val; + + val = readl(inv_clock->reg) >> inv_clock->shift; + val &= INVERTER_MASK; + return val ? 180 : 0; +} + +static int rockchip_inv_set_phase(struct clk_hw *hw, int degrees) +{ + struct rockchip_inv_clock *inv_clock = to_inv_clock(hw); + u32 val; + + if (degrees % 180 == 0) { + val = !!degrees; + } else { + pr_err("%s: unsupported phase %d for %s\n", + __func__, degrees, clk_hw_get_name(hw)); + return -EINVAL; + } + + if (inv_clock->flags & ROCKCHIP_INVERTER_HIWORD_MASK) { + writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), + inv_clock->reg); + } else { + unsigned long flags; + u32 reg; + + spin_lock_irqsave(inv_clock->lock, flags); + + reg = readl(inv_clock->reg); + reg &= ~BIT(inv_clock->shift); + reg |= val; + writel(reg, inv_clock->reg); + + spin_unlock_irqrestore(inv_clock->lock, flags); + } + + return 0; +} + +static const struct clk_ops rockchip_inv_clk_ops = { + .get_phase = rockchip_inv_get_phase, + .set_phase = rockchip_inv_set_phase, +}; + +struct clk *rockchip_clk_register_inverter(const char *name, + const char *const *parent_names, u8 num_parents, + void __iomem *reg, int shift, int flags, + spinlock_t *lock) +{ + struct clk_init_data init; + struct rockchip_inv_clock *inv_clock; + struct clk *clk; + + inv_clock = kzalloc(sizeof(*inv_clock), GFP_KERNEL); + if (!inv_clock) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.num_parents = num_parents; + init.flags = CLK_SET_RATE_PARENT; + init.parent_names = parent_names; + init.ops = &rockchip_inv_clk_ops; + + inv_clock->hw.init = &init; + inv_clock->reg = reg; + inv_clock->shift = shift; + inv_clock->flags = flags; + inv_clock->lock = lock; + + clk = clk_register(NULL, &inv_clock->hw); + if (IS_ERR(clk)) + kfree(inv_clock); + + return clk; +} diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c new file mode 100644 index 0000000000..822189a2fd --- /dev/null +++ b/drivers/clk/rockchip/clk-mmc-phase.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2014 Google, Inc + * Author: Alexandru M Stan <amstan@chromium.org> + */ + +#include <common.h> +#include <of.h> +#include <malloc.h> +#include <io.h> +#include <xfuncs.h> +#include <linux/barebox-wrapper.h> +#include <linux/clk.h> +#include <linux/spinlock.h> +#include "clk.h" + +struct rockchip_mmc_clock { + struct clk_hw hw; + void __iomem *reg; + int id; + int shift; + int cached_phase; +}; + +#define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw) + +#define RK3288_MMC_CLKGEN_DIV 2 + +static unsigned long rockchip_mmc_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate / RK3288_MMC_CLKGEN_DIV; +} + +#define ROCKCHIP_MMC_DELAY_SEL BIT(10) +#define ROCKCHIP_MMC_DEGREE_MASK 0x3 +#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 +#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) + +#define PSECS_PER_SEC 1000000000000LL + +/* + * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to + * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. + */ +#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 + +static int rockchip_mmc_get_phase(struct clk_hw *hw) +{ + struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw); + unsigned long rate = clk_hw_get_rate(hw); + u32 raw_value; + u16 degrees; + u32 delay_num = 0; + + /* Constant signal, no measurable phase shift */ + if (!rate) + return 0; + + raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); + + degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; + + if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { + /* degrees/delaynum * 1000000 */ + unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * + 36 * (rate / 10000); + + delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); + delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; + degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000); + } + + return degrees % 360; +} + +static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees) +{ + struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw); + unsigned long rate = clk_hw_get_rate(hw); + u8 nineties, remainder; + u8 delay_num; + u32 raw_value; + u32 delay; + + /* + * The below calculation is based on the output clock from + * MMC host to the card, which expects the phase clock inherits + * the clock rate from its parent, namely the output clock + * provider of MMC host. However, things may go wrong if + * (1) It is orphan. + * (2) It is assigned to the wrong parent. + * + * This check help debug the case (1), which seems to be the + * most likely problem we often face and which makes it difficult + * for people to debug unstable mmc tuning results. + */ + if (!rate) { + pr_err("%s: invalid clk rate\n", __func__); + return -EINVAL; + } + + nineties = degrees / 90; + remainder = (degrees % 90); + + /* + * Due to the inexact nature of the "fine" delay, we might + * actually go non-monotonic. We don't go _too_ monotonic + * though, so we should be OK. Here are options of how we may + * work: + * + * Ideally we end up with: + * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0 + * + * On one extreme (if delay is actually 44ps): + * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0 + * The other (if delay is actually 77ps): + * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90 + * + * It's possible we might make a delay that is up to 25 + * degrees off from what we think we're making. That's OK + * though because we should be REALLY far from any bad range. + */ + + /* + * Convert to delay; do a little extra work to make sure we + * don't overflow 32-bit / 64-bit numbers. + */ + delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ + delay *= remainder; + delay = DIV_ROUND_CLOSEST(delay, + (rate / 1000) * 36 * + (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); + + delay_num = (u8) min_t(u32, delay, 255); + + raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; + raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; + raw_value |= nineties; + writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), + mmc_clock->reg); + + pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n", + clk_hw_get_name(hw), degrees, delay_num, + mmc_clock->reg, raw_value>>(mmc_clock->shift), + rockchip_mmc_get_phase(hw) + ); + + return 0; +} + +static const struct clk_ops rockchip_mmc_clk_ops = { + .recalc_rate = rockchip_mmc_recalc, + .get_phase = rockchip_mmc_get_phase, + .set_phase = rockchip_mmc_set_phase, +}; + +struct clk *rockchip_clk_register_mmc(const char *name, + const char *const *parent_names, u8 num_parents, + void __iomem *reg, int shift) +{ + struct clk_init_data init; + struct rockchip_mmc_clock *mmc_clock; + struct clk *clk; + int ret; + + mmc_clock = kzalloc(sizeof(*mmc_clock), GFP_KERNEL); + if (!mmc_clock) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = 0; + init.num_parents = num_parents; + init.parent_names = parent_names; + init.ops = &rockchip_mmc_clk_ops; + + mmc_clock->hw.init = &init; + mmc_clock->reg = reg; + mmc_clock->shift = shift; + + clk = clk_register(NULL, &mmc_clock->hw); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto err_register; + } + + return clk; + +err_register: + kfree(mmc_clock); + return ERR_PTR(ret); +} diff --git a/drivers/clk/rockchip/clk-muxgrf.c b/drivers/clk/rockchip/clk-muxgrf.c new file mode 100644 index 0000000000..e81761422f --- /dev/null +++ b/drivers/clk/rockchip/clk-muxgrf.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <of.h> +#include <malloc.h> +#include <io.h> +#include <xfuncs.h> +#include <linux/barebox-wrapper.h> +#include <linux/clk.h> +#include <linux/regmap.h> +#include <linux/spinlock.h> +#include "clk.h" + +struct rockchip_muxgrf_clock { + struct clk_hw hw; + struct regmap *regmap; + u32 reg; + u32 shift; + u32 width; + int flags; +}; + +#define to_muxgrf_clock(_hw) container_of(_hw, struct rockchip_muxgrf_clock, hw) + +static int rockchip_muxgrf_get_parent(struct clk_hw *hw) +{ + struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw); + unsigned int mask = GENMASK(mux->width - 1, 0); + unsigned int val; + + regmap_read(mux->regmap, mux->reg, &val); + + val >>= mux->shift; + val &= mask; + + return val; +} + +static int rockchip_muxgrf_set_parent(struct clk_hw *hw, u8 index) +{ + struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw); + unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); + unsigned int val; + + val = index; + val <<= mux->shift; + + if (mux->flags & CLK_MUX_HIWORD_MASK) + return regmap_write(mux->regmap, mux->reg, val | (mask << 16)); + else + return regmap_update_bits(mux->regmap, mux->reg, mask, val); +} + +static const struct clk_ops rockchip_muxgrf_clk_ops = { + .get_parent = rockchip_muxgrf_get_parent, + .set_parent = rockchip_muxgrf_set_parent, +}; + +struct clk *rockchip_clk_register_muxgrf(const char *name, + const char *const *parent_names, u8 num_parents, + int flags, struct regmap *regmap, int reg, + int shift, int width, int mux_flags) +{ + struct rockchip_muxgrf_clock *muxgrf_clock; + struct clk_init_data init; + struct clk *clk; + + if (IS_ERR(regmap)) { + pr_err("%s: regmap not available\n", __func__); + return ERR_PTR(-ENOTSUPP); + } + + muxgrf_clock = kzalloc(sizeof(*muxgrf_clock), GFP_KERNEL); + if (!muxgrf_clock) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.num_parents = num_parents; + init.parent_names = parent_names; + init.ops = &rockchip_muxgrf_clk_ops; + + muxgrf_clock->hw.init = &init; + muxgrf_clock->regmap = regmap; + muxgrf_clock->reg = reg; + muxgrf_clock->shift = shift; + muxgrf_clock->width = width; + muxgrf_clock->flags = mux_flags; + + clk = clk_register(NULL, &muxgrf_clock->hw); + if (IS_ERR(clk)) + kfree(muxgrf_clock); + + return clk; +} diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 39ccf0a226..b4152b03b1 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1,19 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> */ -#include <asm-generic/div64.h> +#include <linux/math64.h> #include <common.h> #include <io.h> #include <linux/list.h> @@ -23,16 +17,19 @@ #include <linux/barebox-wrapper.h> #include "clk.h" #include <xfuncs.h> +#include <linux/regmap.h> +#include <linux/iopoll.h> -#define PLL_MODE_MASK 0x3 +#define PLL_MODE_WIDTH 2 #define PLL_MODE_SLOW 0x0 #define PLL_MODE_NORM 0x1 #define PLL_MODE_DEEP 0x2 +#define PLL_RK3328_MODE_WIDTH 1 struct rockchip_clk_pll { - struct clk hw; + struct clk_hw hw; - struct clk pll_mux; + struct clk_mux pll_mux; const struct clk_ops *pll_mux_ops; void __iomem *reg_base; @@ -42,7 +39,9 @@ struct rockchip_clk_pll { u8 flags; const struct rockchip_pll_rate_table *rate_table; unsigned int rate_count; - char pll_name[20]; + spinlock_t *lock; + + struct rockchip_clk_provider *ctx; }; #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw) @@ -61,7 +60,7 @@ static const struct rockchip_pll_rate_table *rockchip_get_pll_settings( return NULL; } -static long rockchip_pll_round_rate(struct clk *hw, +static long rockchip_pll_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); @@ -83,26 +82,282 @@ static long rockchip_pll_round_rate(struct clk *hw, * The calling set_rate function is responsible for making sure the * grf regmap is available. */ -#define RK3188_PLL_LOCK_REG 0x200080ac - static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) { - int delay = 24000000; - int val; + struct regmap *grf = pll->ctx->grf; + unsigned int val; + int ret; + + ret = regmap_read_poll_timeout(grf, pll->lock_offset, val, + val & BIT(pll->lock_shift), 1000); + if (ret) + pr_err("%s: timeout waiting for pll to lock\n", __func__); + + return ret; +} + +/* + * PLL used in RK3036 + */ + +#define RK3036_PLLCON(i) (i * 0x4) +#define RK3036_PLLCON0_FBDIV_MASK 0xfff +#define RK3036_PLLCON0_FBDIV_SHIFT 0 +#define RK3036_PLLCON0_POSTDIV1_MASK 0x7 +#define RK3036_PLLCON0_POSTDIV1_SHIFT 12 +#define RK3036_PLLCON1_REFDIV_MASK 0x3f +#define RK3036_PLLCON1_REFDIV_SHIFT 0 +#define RK3036_PLLCON1_POSTDIV2_MASK 0x7 +#define RK3036_PLLCON1_POSTDIV2_SHIFT 6 +#define RK3036_PLLCON1_LOCK_STATUS BIT(10) +#define RK3036_PLLCON1_DSMPD_MASK 0x1 +#define RK3036_PLLCON1_DSMPD_SHIFT 12 +#define RK3036_PLLCON1_PWRDOWN BIT(13) +#define RK3036_PLLCON2_FRAC_MASK 0xffffff +#define RK3036_PLLCON2_FRAC_SHIFT 0 + +static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll) +{ + u32 pllcon; + int ret; + + /* + * Lock time typical 250, max 500 input clock cycles @24MHz + * So define a very safe maximum of 1000us, meaning 24000 cycles. + */ + ret = readl_poll_timeout(pll->reg_base + RK3036_PLLCON(1), + pllcon, + pllcon & RK3036_PLLCON1_LOCK_STATUS, + 1000); + if (ret) + pr_err("%s: timeout waiting for pll to lock\n", __func__); + + return ret; +} + +static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll, + struct rockchip_pll_rate_table *rate) +{ + u32 pllcon; + + pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); + rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) + & RK3036_PLLCON0_FBDIV_MASK); + rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) + & RK3036_PLLCON0_POSTDIV1_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); + rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) + & RK3036_PLLCON1_REFDIV_MASK); + rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) + & RK3036_PLLCON1_POSTDIV2_MASK); + rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT) + & RK3036_PLLCON1_DSMPD_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); + rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) + & RK3036_PLLCON2_FRAC_MASK); +} + +static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + struct rockchip_pll_rate_table cur; + u64 rate64 = prate; + + rockchip_rk3036_pll_get_params(pll, &cur); + + rate64 *= cur.fbdiv; + do_div(rate64, cur.refdiv); + + if (cur.dsmpd == 0) { + /* fractional mode */ + u64 frac_rate64 = prate * cur.frac; + + do_div(frac_rate64, cur.refdiv); + rate64 += frac_rate64 >> 24; + } + + do_div(rate64, cur.postdiv1); + do_div(rate64, cur.postdiv2); + + return (unsigned long)rate64; +} + +static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, + const struct rockchip_pll_rate_table *rate) +{ + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; + struct clk_mux *pll_mux = &pll->pll_mux; + struct rockchip_pll_rate_table cur; + u32 pllcon; + int rate_change_remuxed = 0; + int cur_parent; + int ret; + + pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", + __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, + rate->postdiv2, rate->dsmpd, rate->frac); + + rockchip_rk3036_pll_get_params(pll, &cur); + cur.rate = 0; + + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); + if (cur_parent == PLL_MODE_NORM) { + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); + rate_change_remuxed = 1; + } + + /* update pll values */ + writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, + RK3036_PLLCON0_FBDIV_SHIFT) | + HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, + RK3036_PLLCON0_POSTDIV1_SHIFT), + pll->reg_base + RK3036_PLLCON(0)); + + writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, + RK3036_PLLCON1_REFDIV_SHIFT) | + HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, + RK3036_PLLCON1_POSTDIV2_SHIFT) | + HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, + RK3036_PLLCON1_DSMPD_SHIFT), + pll->reg_base + RK3036_PLLCON(1)); + + /* GPLL CON2 is not HIWORD_MASK */ + pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); + pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT); + pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; + writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); /* wait for the pll to lock */ - while (delay > 0) { - val = readl(RK3188_PLL_LOCK_REG); - if (val & BIT(pll->lock_shift)) + ret = rockchip_rk3036_pll_wait_lock(pll); + if (ret) { + pr_warn("%s: pll update unsuccessful, trying to restore old params\n", + __func__); + rockchip_rk3036_pll_set_params(pll, &cur); + } + + if (rate_change_remuxed) + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); + + return ret; +} + +static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + + pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", + __func__, clk_hw_get_name(hw), drate, prate); + + /* Get required rate settings from table */ + rate = rockchip_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, clk_hw_get_name(hw)); + return -EINVAL; + } + + return rockchip_rk3036_pll_set_params(pll, rate); +} + +static int rockchip_rk3036_pll_enable(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3036_PLLCON(1)); + rockchip_rk3036_pll_wait_lock(pll); + + return 0; +} + +static void rockchip_rk3036_pll_disable(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, + RK3036_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3036_PLLCON(1)); +} + +static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1)); + + return !(pllcon & RK3036_PLLCON1_PWRDOWN); +} + +static int rockchip_rk3036_pll_init(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + struct rockchip_pll_rate_table cur; + unsigned long drate; + + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) + return 0; + + drate = clk_hw_get_rate(hw); + rate = rockchip_get_pll_settings(pll, drate); + + /* when no rate setting for the current rate, rely on clk_set_rate */ + if (!rate) + return 0; + + rockchip_rk3036_pll_get_params(pll, &cur); + + pr_debug("%s: pll %s@%lu: Hz\n", __func__, clk_hw_get_name(hw), + drate); + pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", + cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, + cur.dsmpd, cur.frac); + pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", + rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, + rate->dsmpd, rate->frac); + + if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || + rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || + rate->dsmpd != cur.dsmpd || + (!cur.dsmpd && (rate->frac != cur.frac))) { + struct clk *parent = clk_get_parent(clk_hw_to_clk(hw)); + + if (!parent) { + pr_warn("%s: parent of %s not available\n", + __func__, clk_hw_get_name(hw)); return 0; - delay--; + } + + pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", + __func__, clk_hw_get_name(hw)); + rockchip_rk3036_pll_set_params(pll, rate); } - pr_err("%s: timeout waiting for pll to lock\n", __func__); - return -ETIMEDOUT; + return 0; } -/** +static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = { + .recalc_rate = rockchip_rk3036_pll_recalc_rate, + .enable = rockchip_rk3036_pll_enable, + .disable = rockchip_rk3036_pll_disable, + .is_enabled = rockchip_rk3036_pll_is_enabled, +}; + +static const struct clk_ops rockchip_rk3036_pll_clk_ops = { + .recalc_rate = rockchip_rk3036_pll_recalc_rate, + .round_rate = rockchip_pll_round_rate, + .set_rate = rockchip_rk3036_pll_set_rate, + .enable = rockchip_rk3036_pll_enable, + .disable = rockchip_rk3036_pll_disable, + .is_enabled = rockchip_rk3036_pll_is_enabled, + .init = rockchip_rk3036_pll_init, +}; + +/* * PLL used in RK3066, RK3188 and RK3288 */ @@ -115,75 +370,75 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) #define RK3066_PLLCON0_NR_SHIFT 8 #define RK3066_PLLCON1_NF_MASK 0x1fff #define RK3066_PLLCON1_NF_SHIFT 0 -#define RK3066_PLLCON2_BWADJ_MASK 0xfff -#define RK3066_PLLCON2_BWADJ_SHIFT 0 +#define RK3066_PLLCON2_NB_MASK 0xfff +#define RK3066_PLLCON2_NB_SHIFT 0 #define RK3066_PLLCON3_RESET (1 << 5) #define RK3066_PLLCON3_PWRDOWN (1 << 1) #define RK3066_PLLCON3_BYPASS (1 << 0) -static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk *hw, +static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, + struct rockchip_pll_rate_table *rate) +{ + u32 pllcon; + + pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); + rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) + & RK3066_PLLCON0_NR_MASK) + 1; + rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) + & RK3066_PLLCON0_OD_MASK) + 1; + + pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); + rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) + & RK3066_PLLCON1_NF_MASK) + 1; + + pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); + rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) + & RK3066_PLLCON2_NB_MASK) + 1; +} + +static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); - u64 nf, nr, no, rate64 = prate; + struct rockchip_pll_rate_table cur; + u64 rate64 = prate; u32 pllcon; - pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); + pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); if (pllcon & RK3066_PLLCON3_BYPASS) { pr_debug("%s: pll %s is bypassed\n", __func__, - __clk_get_name(hw)); + clk_hw_get_name(hw)); return prate; } - pllcon = readl(pll->reg_base + RK3066_PLLCON(1)); - nf = (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK; + rockchip_rk3066_pll_get_params(pll, &cur); - pllcon = readl(pll->reg_base + RK3066_PLLCON(0)); - nr = (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK; - no = (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK; - - rate64 *= (nf + 1); - do_div(rate64, nr + 1); - do_div(rate64, no + 1); - - pr_debug("%s: %s rate=%lu\n", - __func__, hw->name, (unsigned long)rate64); + rate64 *= cur.nf; + do_div(rate64, cur.nr); + do_div(rate64, cur.no); return (unsigned long)rate64; } -static int rockchip_rk3066_pll_set_rate(struct clk *hw, unsigned long drate, - unsigned long prate) +static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, + const struct rockchip_pll_rate_table *rate) { - struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); - const struct rockchip_pll_rate_table *rate; - unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate); - struct clk *pll_mux = &pll->pll_mux; const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; + struct clk_mux *pll_mux = &pll->pll_mux; + struct rockchip_pll_rate_table cur; int rate_change_remuxed = 0; int cur_parent; int ret; - if (old_rate == drate) - return 0; - - pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", - __func__, __clk_get_name(hw), old_rate, drate, prate); - - /* Get required rate settings from table */ - rate = rockchip_get_pll_settings(pll, drate); - if (!rate) { - pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, __clk_get_name(hw)); - return -EINVAL; - } - pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n", __func__, rate->rate, rate->nr, rate->no, rate->nf); - cur_parent = pll_mux_ops->get_parent(pll_mux); + rockchip_rk3066_pll_get_params(pll, &cur); + cur.rate = 0; + + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); if (cur_parent == PLL_MODE_NORM) { - pll_mux_ops->set_parent(pll_mux, PLL_MODE_SLOW); + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); rate_change_remuxed = 1; } @@ -198,11 +453,11 @@ static int rockchip_rk3066_pll_set_rate(struct clk *hw, unsigned long drate, RK3066_PLLCON0_OD_SHIFT), pll->reg_base + RK3066_PLLCON(0)); - writel(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, + writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, RK3066_PLLCON1_NF_SHIFT), pll->reg_base + RK3066_PLLCON(1)); - writel(HIWORD_UPDATE(rate->bwadj, RK3066_PLLCON2_BWADJ_MASK, - RK3066_PLLCON2_BWADJ_SHIFT), + writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK, + RK3066_PLLCON2_NB_SHIFT), pll->reg_base + RK3066_PLLCON(2)); /* leave reset and wait the reset_delay */ @@ -213,28 +468,49 @@ static int rockchip_rk3066_pll_set_rate(struct clk *hw, unsigned long drate, /* wait for the pll to lock */ ret = rockchip_pll_wait_lock(pll); if (ret) { - pr_warn("%s: pll did not lock, trying to restore old rate %lu\n", - __func__, old_rate); - rockchip_rk3066_pll_set_rate(hw, old_rate, prate); + pr_warn("%s: pll update unsuccessful, trying to restore old params\n", + __func__); + rockchip_rk3066_pll_set_params(pll, &cur); } if (rate_change_remuxed) - pll_mux_ops->set_parent(pll_mux, PLL_MODE_NORM); + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); return ret; } -static int rockchip_rk3066_pll_enable(struct clk *hw) +static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + + pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", + __func__, clk_hw_get_name(hw), drate, prate); + + /* Get required rate settings from table */ + rate = rockchip_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, clk_hw_get_name(hw)); + return -EINVAL; + } + + return rockchip_rk3066_pll_set_params(pll, rate); +} + +static int rockchip_rk3066_pll_enable(struct clk_hw *hw) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), pll->reg_base + RK3066_PLLCON(3)); + rockchip_pll_wait_lock(pll); return 0; } -static void rockchip_rk3066_pll_disable(struct clk *hw) +static void rockchip_rk3066_pll_disable(struct clk_hw *hw) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); @@ -243,7 +519,7 @@ static void rockchip_rk3066_pll_disable(struct clk *hw) pll->reg_base + RK3066_PLLCON(3)); } -static int rockchip_rk3066_pll_is_enabled(struct clk *hw) +static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); @@ -251,6 +527,38 @@ static int rockchip_rk3066_pll_is_enabled(struct clk *hw) return !(pllcon & RK3066_PLLCON3_PWRDOWN); } +static int rockchip_rk3066_pll_init(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + struct rockchip_pll_rate_table cur; + unsigned long drate; + + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) + return 0; + + drate = clk_hw_get_rate(hw); + rate = rockchip_get_pll_settings(pll, drate); + + /* when no rate setting for the current rate, rely on clk_set_rate */ + if (!rate) + return 0; + + rockchip_rk3066_pll_get_params(pll, &cur); + + pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n", + __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, + rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); + if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf + || rate->nb != cur.nb) { + pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", + __func__, clk_hw_get_name(hw)); + rockchip_rk3066_pll_set_params(pll, rate); + } + + return 0; +} + static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = { .recalc_rate = rockchip_rk3066_pll_recalc_rate, .enable = rockchip_rk3066_pll_enable, @@ -265,44 +573,562 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = { .enable = rockchip_rk3066_pll_enable, .disable = rockchip_rk3066_pll_disable, .is_enabled = rockchip_rk3066_pll_is_enabled, + .init = rockchip_rk3066_pll_init, +}; + +/* + * PLL used in RK3399 + */ + +#define RK3399_PLLCON(i) (i * 0x4) +#define RK3399_PLLCON0_FBDIV_MASK 0xfff +#define RK3399_PLLCON0_FBDIV_SHIFT 0 +#define RK3399_PLLCON1_REFDIV_MASK 0x3f +#define RK3399_PLLCON1_REFDIV_SHIFT 0 +#define RK3399_PLLCON1_POSTDIV1_MASK 0x7 +#define RK3399_PLLCON1_POSTDIV1_SHIFT 8 +#define RK3399_PLLCON1_POSTDIV2_MASK 0x7 +#define RK3399_PLLCON1_POSTDIV2_SHIFT 12 +#define RK3399_PLLCON2_FRAC_MASK 0xffffff +#define RK3399_PLLCON2_FRAC_SHIFT 0 +#define RK3399_PLLCON2_LOCK_STATUS BIT(31) +#define RK3399_PLLCON3_PWRDOWN BIT(0) +#define RK3399_PLLCON3_DSMPD_MASK 0x1 +#define RK3399_PLLCON3_DSMPD_SHIFT 3 + +static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll) +{ + u32 pllcon; + int ret; + + /* + * Lock time typical 250, max 500 input clock cycles @24MHz + * So define a very safe maximum of 1000us, meaning 24000 cycles. + */ + ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2), + pllcon, + pllcon & RK3399_PLLCON2_LOCK_STATUS, + 1000); + if (ret) + pr_err("%s: timeout waiting for pll to lock\n", __func__); + + return ret; +} + +static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll, + struct rockchip_pll_rate_table *rate) +{ + u32 pllcon; + + pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0)); + rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT) + & RK3399_PLLCON0_FBDIV_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1)); + rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT) + & RK3399_PLLCON1_REFDIV_MASK); + rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT) + & RK3399_PLLCON1_POSTDIV1_MASK); + rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT) + & RK3399_PLLCON1_POSTDIV2_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); + rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT) + & RK3399_PLLCON2_FRAC_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3)); + rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT) + & RK3399_PLLCON3_DSMPD_MASK); +} + +static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + struct rockchip_pll_rate_table cur; + u64 rate64 = prate; + + rockchip_rk3399_pll_get_params(pll, &cur); + + rate64 *= cur.fbdiv; + do_div(rate64, cur.refdiv); + + if (cur.dsmpd == 0) { + /* fractional mode */ + u64 frac_rate64 = prate * cur.frac; + + do_div(frac_rate64, cur.refdiv); + rate64 += frac_rate64 >> 24; + } + + do_div(rate64, cur.postdiv1); + do_div(rate64, cur.postdiv2); + + return (unsigned long)rate64; +} + +static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, + const struct rockchip_pll_rate_table *rate) +{ + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; + struct clk_mux *pll_mux = &pll->pll_mux; + struct rockchip_pll_rate_table cur; + u32 pllcon; + int rate_change_remuxed = 0; + int cur_parent; + int ret; + + pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", + __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, + rate->postdiv2, rate->dsmpd, rate->frac); + + rockchip_rk3399_pll_get_params(pll, &cur); + cur.rate = 0; + + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); + if (cur_parent == PLL_MODE_NORM) { + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); + rate_change_remuxed = 1; + } + + /* update pll values */ + writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, + RK3399_PLLCON0_FBDIV_SHIFT), + pll->reg_base + RK3399_PLLCON(0)); + + writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK, + RK3399_PLLCON1_REFDIV_SHIFT) | + HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK, + RK3399_PLLCON1_POSTDIV1_SHIFT) | + HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK, + RK3399_PLLCON1_POSTDIV2_SHIFT), + pll->reg_base + RK3399_PLLCON(1)); + + /* xPLL CON2 is not HIWORD_MASK */ + pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); + pllcon &= ~(RK3399_PLLCON2_FRAC_MASK << RK3399_PLLCON2_FRAC_SHIFT); + pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT; + writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2)); + + writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK, + RK3399_PLLCON3_DSMPD_SHIFT), + pll->reg_base + RK3399_PLLCON(3)); + + /* wait for the pll to lock */ + ret = rockchip_rk3399_pll_wait_lock(pll); + if (ret) { + pr_warn("%s: pll update unsuccessful, trying to restore old params\n", + __func__); + rockchip_rk3399_pll_set_params(pll, &cur); + } + + if (rate_change_remuxed) + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); + + return ret; +} + +static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + + pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", + __func__, clk_hw_get_name(hw), drate, prate); + + /* Get required rate settings from table */ + rate = rockchip_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, clk_hw_get_name(hw)); + return -EINVAL; + } + + return rockchip_rk3399_pll_set_params(pll, rate); +} + +static int rockchip_rk3399_pll_enable(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0), + pll->reg_base + RK3399_PLLCON(3)); + rockchip_rk3399_pll_wait_lock(pll); + + return 0; +} + +static void rockchip_rk3399_pll_disable(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN, + RK3399_PLLCON3_PWRDOWN, 0), + pll->reg_base + RK3399_PLLCON(3)); +} + +static int rockchip_rk3399_pll_is_enabled(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3)); + + return !(pllcon & RK3399_PLLCON3_PWRDOWN); +} + +static int rockchip_rk3399_pll_init(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + struct rockchip_pll_rate_table cur; + unsigned long drate; + + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) + return 0; + + drate = clk_hw_get_rate(hw); + rate = rockchip_get_pll_settings(pll, drate); + + /* when no rate setting for the current rate, rely on clk_set_rate */ + if (!rate) + return 0; + + rockchip_rk3399_pll_get_params(pll, &cur); + + pr_debug("%s: pll %s@%lu: Hz\n", __func__, clk_hw_get_name(hw), + drate); + pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", + cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, + cur.dsmpd, cur.frac); + pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", + rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, + rate->dsmpd, rate->frac); + + if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || + rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || + rate->dsmpd != cur.dsmpd || + (!cur.dsmpd && (rate->frac != cur.frac))) { + struct clk *parent = clk_get_parent(clk_hw_to_clk(hw)); + + if (!parent) { + pr_warn("%s: parent of %s not available\n", + __func__, clk_hw_get_name(hw)); + return 0; + } + + pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", + __func__, clk_hw_get_name(hw)); + rockchip_rk3399_pll_set_params(pll, rate); + } + + return 0; +} + +static const struct clk_ops rockchip_rk3399_pll_clk_norate_ops = { + .recalc_rate = rockchip_rk3399_pll_recalc_rate, + .enable = rockchip_rk3399_pll_enable, + .disable = rockchip_rk3399_pll_disable, + .is_enabled = rockchip_rk3399_pll_is_enabled, +}; + +static const struct clk_ops rockchip_rk3399_pll_clk_ops = { + .recalc_rate = rockchip_rk3399_pll_recalc_rate, + .round_rate = rockchip_pll_round_rate, + .set_rate = rockchip_rk3399_pll_set_rate, + .enable = rockchip_rk3399_pll_enable, + .disable = rockchip_rk3399_pll_disable, + .is_enabled = rockchip_rk3399_pll_is_enabled, + .init = rockchip_rk3399_pll_init, +}; + +/* + * PLL used in RK3588 + */ + +#define RK3588_PLLCON(i) (i * 0x4) +#define RK3588_PLLCON0_M_MASK 0x3ff +#define RK3588_PLLCON0_M_SHIFT 0 +#define RK3588_PLLCON1_P_MASK 0x3f +#define RK3588_PLLCON1_P_SHIFT 0 +#define RK3588_PLLCON1_S_MASK 0x7 +#define RK3588_PLLCON1_S_SHIFT 6 +#define RK3588_PLLCON2_K_MASK 0xffff +#define RK3588_PLLCON2_K_SHIFT 0 +#define RK3588_PLLCON1_PWRDOWN BIT(13) +#define RK3588_PLLCON6_LOCK_STATUS BIT(15) + +static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll) +{ + u32 pllcon; + int ret; + + /* + * Lock time typical 250, max 500 input clock cycles @24MHz + * So define a very safe maximum of 1000us, meaning 24000 cycles. + */ + ret = readl_poll_timeout(pll->reg_base + RK3588_PLLCON(6), + pllcon, + pllcon & RK3588_PLLCON6_LOCK_STATUS, + 1000); + if (ret) + pr_err("%s: timeout waiting for pll to lock\n", __func__); + + return ret; +} + +static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll, + struct rockchip_pll_rate_table *rate) +{ + u32 pllcon; + + pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0)); + rate->m = ((pllcon >> RK3588_PLLCON0_M_SHIFT) & RK3588_PLLCON0_M_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1)); + rate->p = ((pllcon >> RK3588_PLLCON1_P_SHIFT) & RK3588_PLLCON1_P_MASK); + rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) & RK3588_PLLCON1_S_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2)); + rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK); +} + +static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + struct rockchip_pll_rate_table cur; + u64 rate64 = prate, postdiv; + + rockchip_rk3588_pll_get_params(pll, &cur); + + rate64 *= cur.m; + do_div(rate64, cur.p); + + if (cur.k) { + /* fractional mode */ + u64 frac_rate64 = prate * cur.k; + + postdiv = cur.p * 65535; + do_div(frac_rate64, postdiv); + rate64 += frac_rate64; + } + rate64 = rate64 >> cur.s; + + return (unsigned long)rate64; +} + +static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, + const struct rockchip_pll_rate_table *rate) +{ + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; + struct clk_mux *pll_mux = &pll->pll_mux; + struct rockchip_pll_rate_table cur; + int rate_change_remuxed = 0; + int cur_parent; + int ret; + + pr_debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n", + __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); + + rockchip_rk3588_pll_get_params(pll, &cur); + cur.rate = 0; + + if (pll->type == pll_rk3588) { + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); + if (cur_parent == PLL_MODE_NORM) { + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); + rate_change_remuxed = 1; + } + } + + /* set pll power down */ + writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, + RK3588_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3399_PLLCON(1)); + + /* update pll values */ + writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT), + pll->reg_base + RK3399_PLLCON(0)); + + writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) | + HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT), + pll->reg_base + RK3399_PLLCON(1)); + + writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT), + pll->reg_base + RK3399_PLLCON(2)); + + /* set pll power up */ + writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3588_PLLCON(1)); + + /* wait for the pll to lock */ + ret = rockchip_rk3588_pll_wait_lock(pll); + if (ret) { + pr_warn("%s: pll update unsuccessful, trying to restore old params\n", + __func__); + rockchip_rk3588_pll_set_params(pll, &cur); + } + + if ((pll->type == pll_rk3588) && rate_change_remuxed) + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); + + return ret; +} + +static int rockchip_rk3588_pll_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + + pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", + __func__, clk_hw_get_name(hw), drate, prate); + + /* Get required rate settings from table */ + rate = rockchip_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, clk_hw_get_name(hw)); + return -EINVAL; + } + + return rockchip_rk3588_pll_set_params(pll, rate); +} + +static int rockchip_rk3588_pll_enable(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3588_PLLCON(1)); + rockchip_rk3588_pll_wait_lock(pll); + + return 0; +} + +static void rockchip_rk3588_pll_disable(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, RK3588_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3588_PLLCON(1)); +} + +static int rockchip_rk3588_pll_is_enabled(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1)); + + return !(pllcon & RK3588_PLLCON1_PWRDOWN); +} + +static int rockchip_rk3588_pll_init(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) + return 0; + + return 0; +} + +static const struct clk_ops rockchip_rk3588_pll_clk_norate_ops = { + .recalc_rate = rockchip_rk3588_pll_recalc_rate, + .enable = rockchip_rk3588_pll_enable, + .disable = rockchip_rk3588_pll_disable, + .is_enabled = rockchip_rk3588_pll_is_enabled, +}; + +static const struct clk_ops rockchip_rk3588_pll_clk_ops = { + .recalc_rate = rockchip_rk3588_pll_recalc_rate, + .round_rate = rockchip_pll_round_rate, + .set_rate = rockchip_rk3588_pll_set_rate, + .enable = rockchip_rk3588_pll_enable, + .disable = rockchip_rk3588_pll_disable, + .is_enabled = rockchip_rk3588_pll_is_enabled, + .init = rockchip_rk3588_pll_init, }; /* * Common registering of pll clocks */ -struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, - const char *name, const char **parent_names, u8 num_parents, - void __iomem *base, int con_offset, int grf_lock_offset, +struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, + enum rockchip_pll_type pll_type, + const char *name, const char *const *parent_names, + u8 num_parents, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, - u8 clk_pll_flags) + unsigned long flags, u8 clk_pll_flags) { - const char **pll_parents; + const char *pll_parents[3]; + struct clk_init_data init; struct rockchip_clk_pll *pll; - struct clk *pll_mux; - struct clk *mux_clk; - int ret; + struct clk_mux *pll_mux; + struct clk *pll_clk, *mux_clk; + char pll_name[20]; - if (num_parents != 2) { + if ((pll_type != pll_rk3328 && num_parents != 2) || + (pll_type == pll_rk3328 && num_parents != 1)) { pr_err("%s: needs two parent clocks\n", __func__); return ERR_PTR(-EINVAL); } + /* name the actual pll */ + snprintf(pll_name, sizeof(pll_name), "pll_%s", name); + pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) return ERR_PTR(-ENOMEM); - pll_parents = kzalloc(sizeof(char *)*3, GFP_KERNEL); - if (!pll_parents) - return ERR_PTR(-ENOMEM); + /* create the mux on top of the real pll */ + pll->pll_mux_ops = &clk_mux_ops; + pll_mux = &pll->pll_mux; + pll_mux->reg = ctx->reg_base + mode_offset; + pll_mux->shift = mode_shift; + if (pll_type == pll_rk3328) + pll_mux->width = PLL_RK3328_MODE_WIDTH; + else + pll_mux->width = PLL_MODE_WIDTH; + pll_mux->flags = 0; + pll_mux->lock = &ctx->lock; + pll_mux->hw.init = &init; + + if (pll_type == pll_rk3036 || + pll_type == pll_rk3066 || + pll_type == pll_rk3328 || + pll_type == pll_rk3399 || + pll_type == pll_rk3588 || + pll_type == pll_rk3588_core) + pll_mux->flags |= CLK_MUX_HIWORD_MASK; - /* name the actual pll */ - snprintf(pll->pll_name, sizeof(pll->pll_name), "pll_%s", name); - pll->hw.name = pll->pll_name; + init.name = name; + init.flags = CLK_SET_RATE_PARENT; + init.ops = pll->pll_mux_ops; + init.parent_names = pll_parents; + + /* the actual muxing is xin24m, pll-output, xin32k */ + pll_parents[0] = parent_names[0]; + pll_parents[1] = pll_name; + + if (pll_type == pll_rk3328) { + init.num_parents = 2; + } else { + pll_parents[2] = parent_names[1]; + init.num_parents = ARRAY_SIZE(pll_parents); + } + + mux_clk = clk_register(NULL, &pll_mux->hw); + if (IS_ERR(mux_clk)) + goto err_mux; + + /* now create the actual pll */ + init.name = pll_name; + + /* keep all plls untouched for now */ + init.flags = flags | CLK_IGNORE_UNUSED; - pll->hw.parent_names = &parent_names[0]; - pll->hw.num_parents = 1; + init.parent_names = &parent_names[0]; + init.num_parents = 1; if (rate_table) { int len; @@ -312,61 +1138,71 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, len++; pll->rate_count = len; - pll->rate_table = xmemdup(rate_table, + pll->rate_table = kmemdup(rate_table, pll->rate_count * - sizeof(struct rockchip_pll_rate_table) - ); + sizeof(struct rockchip_pll_rate_table), + GFP_KERNEL); WARN(!pll->rate_table, "%s: could not allocate rate table for %s\n", __func__, name); } switch (pll_type) { + case pll_rk3036: + case pll_rk3328: + if (!pll->rate_table) + init.ops = &rockchip_rk3036_pll_clk_norate_ops; + else + init.ops = &rockchip_rk3036_pll_clk_ops; + break; case pll_rk3066: + if (!pll->rate_table || IS_ERR(ctx->grf)) + init.ops = &rockchip_rk3066_pll_clk_norate_ops; + else + init.ops = &rockchip_rk3066_pll_clk_ops; + break; + case pll_rk3399: if (!pll->rate_table) - pll->hw.ops = &rockchip_rk3066_pll_clk_norate_ops; + init.ops = &rockchip_rk3399_pll_clk_norate_ops; else - pll->hw.ops = &rockchip_rk3066_pll_clk_ops; + init.ops = &rockchip_rk3399_pll_clk_ops; + break; + case pll_rk3588: + case pll_rk3588_core: + if (!pll->rate_table) + init.ops = &rockchip_rk3588_pll_clk_norate_ops; + else + init.ops = &rockchip_rk3588_pll_clk_ops; + init.flags = flags; break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, name); } + pll->hw.init = &init; pll->type = pll_type; - pll->reg_base = base + con_offset; + pll->reg_base = ctx->reg_base + con_offset; pll->lock_offset = grf_lock_offset; pll->lock_shift = lock_shift; pll->flags = clk_pll_flags; - - ret = clk_register(&pll->hw); - if (ret) { - pr_err("%s: failed to register pll clock %s : %d\n", - __func__, name, ret); - mux_clk = &pll->hw; - goto err_exit; + pll->lock = &ctx->lock; + pll->ctx = ctx; + + pll_clk = clk_register(NULL, &pll->hw); + if (IS_ERR(pll_clk)) { + pr_err("%s: failed to register pll clock %s : %ld\n", + __func__, name, PTR_ERR(pll_clk)); + goto err_pll; } - /* the actual muxing is xin24m, pll-output, xin32k */ - pll_parents[0] = parent_names[0]; - pll_parents[1] = pll->pll_name; - pll_parents[2] = parent_names[1]; - - pll_mux = clk_mux_alloc(name, CLK_SET_RATE_PARENT, base + mode_offset, mode_shift, - PLL_MODE_MASK, pll_parents, 3, 0); - pll->pll_mux_ops = pll_mux->ops; - mux_clk = pll_mux; - - if (pll_type == pll_rk3066) - pll_mux->flags |= CLK_MUX_HIWORD_MASK; - - ret = clk_register(pll_mux); - if (ret) - goto err_exit; - return mux_clk; -err_exit: +err_pll: + kfree(pll->rate_table); + clk_unregister(mux_clk); + mux_clk = pll_clk; +err_mux: kfree(pll); return mux_clk; } diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index 9340739945..8597a9d229 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -1,16 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> @@ -29,7 +20,7 @@ enum rk3188_plls { apll, cpll, dpll, gpll, }; -struct rockchip_pll_rate_table rk3188_pll_rates[] = { +static struct rockchip_pll_rate_table rk3188_pll_rates[] = { RK3066_PLL_RATE(2208000000, 1, 92, 1), RK3066_PLL_RATE(2184000000, 1, 91, 1), RK3066_PLL_RATE(2160000000, 1, 90, 1), @@ -91,6 +82,7 @@ struct rockchip_pll_rate_table rk3188_pll_rates[] = { RK3066_PLL_RATE( 504000000, 1, 84, 4), RK3066_PLL_RATE( 456000000, 1, 76, 4), RK3066_PLL_RATE( 408000000, 1, 68, 4), + RK3066_PLL_RATE( 400000000, 3, 100, 2), RK3066_PLL_RATE( 384000000, 2, 128, 4), RK3066_PLL_RATE( 360000000, 1, 60, 4), RK3066_PLL_RATE( 312000000, 1, 52, 4), @@ -154,10 +146,14 @@ static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = { }; static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = { - .core_reg = RK2928_CLKSEL_CON(0), - .div_core_shift = 0, - .div_core_mask = 0x1f, + .core_reg[0] = RK2928_CLKSEL_CON(0), + .div_core_shift[0] = 0, + .div_core_mask[0] = 0x1f, + .num_cores = 1, + .mux_core_alt = 1, + .mux_core_main = 0, .mux_core_shift = 8, + .mux_core_mask = 0x1, }; #define RK3188_DIV_ACLK_CORE_MASK 0x7 @@ -190,10 +186,14 @@ static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = { }; static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = { - .core_reg = RK2928_CLKSEL_CON(0), - .div_core_shift = 9, - .div_core_mask = 0x1f, + .core_reg[0] = RK2928_CLKSEL_CON(0), + .div_core_shift[0] = 9, + .div_core_mask[0] = 0x1f, + .num_cores = 1, + .mux_core_alt = 1, + .mux_core_main = 0, .mux_core_shift = 8, + .mux_core_mask = 0x1, }; PNAME(mux_pll_p) = { "xin24m", "xin32k" }; @@ -204,7 +204,7 @@ PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; PNAME(mux_aclk_cpu_p) = { "apll", "gpll" }; PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" }; PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" }; -PNAME(mux_sclk_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" }; +PNAME(mux_sclk_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" }; PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" }; PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" }; PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" }; @@ -238,6 +238,7 @@ static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = { #define MFLAGS CLK_MUX_HIWORD_MASK #define DFLAGS CLK_DIVIDER_HIWORD_MASK #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) +#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK /* 2 ^ (val + 1) */ static struct clk_div_table div_core_peri_t[] = { @@ -248,6 +249,30 @@ static struct clk_div_table div_core_peri_t[] = { { /* sentinel */ }, }; +static struct rockchip_clk_branch common_hsadc_out_fracmux __initdata = + MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0, + RK2928_CLKSEL_CON(22), 4, 2, MFLAGS); + +static struct rockchip_clk_branch common_spdif_fracmux __initdata = + MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(5), 8, 2, MFLAGS); + +static struct rockchip_clk_branch common_uart0_fracmux __initdata = + MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(13), 8, 2, MFLAGS); + +static struct rockchip_clk_branch common_uart1_fracmux __initdata = + MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(14), 8, 2, MFLAGS); + +static struct rockchip_clk_branch common_uart2_fracmux __initdata = + MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); + +static struct rockchip_clk_branch common_uart3_fracmux __initdata = + MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(16), 8, 2, MFLAGS); + static struct rockchip_clk_branch common_clk_branches[] __initdata = { /* * Clock-Architecture Diagram 2 @@ -260,15 +285,15 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY, div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS), - COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0, + COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 9, GFLAGS), - GATE(0, "hclk_vepu", "aclk_vepu", 0, + GATE(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0, RK2928_CLKGATE_CON(3), 10, GFLAGS), - COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0, + COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(3), 11, GFLAGS), - GATE(0, "hclk_vdpu", "aclk_vdpu", 0, + GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0, RK2928_CLKGATE_CON(3), 12, GFLAGS), GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, @@ -277,14 +302,14 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(0), 2, GFLAGS), - GATE(0, "aclk_cpu", "aclk_cpu_pre", 0, + GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, RK2928_CLKGATE_CON(0), 3, GFLAGS), GATE(0, "atclk_cpu", "pclk_cpu_pre", 0, RK2928_CLKGATE_CON(0), 6, GFLAGS), - GATE(0, "pclk_cpu", "pclk_cpu_pre", 0, + GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", 0, RK2928_CLKGATE_CON(0), 5, GFLAGS), - GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED, + GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 4, GFLAGS), COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, @@ -294,12 +319,12 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 4, GFLAGS), - GATE(0, "aclk_peri", "aclk_peri_pre", 0, + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0, RK2928_CLKGATE_CON(2), 1, GFLAGS), - COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_pre", 0, + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", 0, RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(2), 2, GFLAGS), - COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_pre", 0, + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", 0, RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(2), 3, GFLAGS), @@ -313,14 +338,18 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { GATE(0, "pclkin_cif0", "ext_cif0", 0, RK2928_CLKGATE_CON(3), 3, GFLAGS), + INVERTER(0, "pclk_cif0", "pclkin_cif0", + RK2928_CLKSEL_CON(30), 8, IFLAGS), + + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), /* * the 480m are generated inside the usb block from these clocks, * but they are also a source for the hsicphy clock. */ - GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED, + GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(1), 5, GFLAGS), - GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED, + GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(1), 6, GFLAGS), COMPOSITE(0, "mac_src", mux_mac_p, 0, @@ -328,17 +357,18 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKGATE_CON(2), 5, GFLAGS), MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(21), 4, 1, MFLAGS), - GATE(0, "sclk_mac_lbtest", "sclk_macref", - RK2928_CLKGATE_CON(2), 12, 0, GFLAGS), + GATE(0, "sclk_mac_lbtest", "sclk_macref", 0, + RK2928_CLKGATE_CON(2), 12, GFLAGS), COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0, RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS, RK2928_CLKGATE_CON(2), 6, GFLAGS), - COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", 0, + COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0, RK2928_CLKSEL_CON(23), 0, - RK2928_CLKGATE_CON(2), 7, GFLAGS), - MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0, - RK2928_CLKSEL_CON(22), 4, 2, MFLAGS), + RK2928_CLKGATE_CON(2), 7, GFLAGS, + &common_hsadc_out_fracmux), + INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out", + RK2928_CLKSEL_CON(22), 7, IFLAGS), COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, RK2928_CLKSEL_CON(24), 8, 8, DFLAGS, @@ -347,18 +377,17 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0, RK2928_CLKSEL_CON(5), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 13, GFLAGS), - COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0, + COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(9), 0, - RK2928_CLKGATE_CON(0), 14, GFLAGS), - MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, - RK2928_CLKSEL_CON(5), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(0), 14, GFLAGS, + &common_spdif_fracmux), /* * Clock-Architecture Diagram 4 */ - GATE(SCLK_SMC, "sclk_smc", "hclk_peri", - RK2928_CLKGATE_CON(2), 4, 0, GFLAGS), + GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0, + RK2928_CLKGATE_CON(2), 4, GFLAGS), COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0, RK2928_CLKSEL_CON(25), 0, 7, DFLAGS, @@ -382,35 +411,31 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0, RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 8, GFLAGS), - COMPOSITE_FRAC(0, "uart0_frac", "uart0_pre", 0, + COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(17), 0, - RK2928_CLKGATE_CON(1), 9, GFLAGS), - MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0, - RK2928_CLKSEL_CON(13), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(1), 9, GFLAGS, + &common_uart0_fracmux), COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0, RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 10, GFLAGS), - COMPOSITE_FRAC(0, "uart1_frac", "uart1_pre", 0, + COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(18), 0, - RK2928_CLKGATE_CON(1), 11, GFLAGS), - MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0, - RK2928_CLKSEL_CON(14), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(1), 11, GFLAGS, + &common_uart1_fracmux), COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0, RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), - COMPOSITE_FRAC(0, "uart2_frac", "uart2_pre", 0, + COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(19), 0, - RK2928_CLKGATE_CON(1), 13, GFLAGS), - MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0, - RK2928_CLKSEL_CON(15), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(1), 13, GFLAGS, + &common_uart2_fracmux), COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0, RK2928_CLKSEL_CON(16), 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 14, GFLAGS), - COMPOSITE_FRAC(0, "uart3_frac", "uart3_pre", 0, + COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(20), 0, - RK2928_CLKGATE_CON(1), 15, GFLAGS), - MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0, - RK2928_CLKSEL_CON(16), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(1), 15, GFLAGS, + &common_uart3_fracmux), GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS), @@ -427,7 +452,6 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { /* hclk_cpu gates */ GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS), - GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS), GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS), /* hclk_ahb2apb is part of a clk branch */ @@ -477,8 +501,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS), GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS), - GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS), - GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), + GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS), + GATE(PCLK_PUBL, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS), GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS), @@ -520,6 +544,18 @@ static struct clk_div_table div_aclk_cpu_t[] = { { /* sentinel */ }, }; +static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata = + MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(2), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata = + MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata = + MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(4), 8, 2, MFLAGS); + static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { DIVTBL(0, "aclk_cpu_pre", "armclk", 0, RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t), @@ -544,12 +580,12 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS, RK2928_CLKGATE_CON(3), 1, GFLAGS), - MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0, + MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(27), 4, 1, MFLAGS), COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS, RK2928_CLKGATE_CON(3), 2, GFLAGS), - MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0, + MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(28), 4, 1, MFLAGS), COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0, @@ -560,6 +596,8 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { GATE(0, "pclkin_cif1", "ext_cif1", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS), + INVERTER(0, "pclk_cif1", "pclkin_cif1", + RK2928_CLKSEL_CON(30), 12, IFLAGS), COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS, @@ -570,7 +608,7 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 2, GFLAGS), - COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0, + COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0, RK2928_CLKSEL_CON(34), 0, 16, DFLAGS, RK2928_CLKGATE_CON(2), 15, GFLAGS), @@ -579,37 +617,35 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, RK2928_CLKSEL_CON(2), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 7, GFLAGS), - COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0, + COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(6), 0, - RK2928_CLKGATE_CON(0), 8, GFLAGS), - MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0, - RK2928_CLKSEL_CON(2), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(0), 8, GFLAGS, + &rk3066a_i2s0_fracmux), COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0, RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 9, GFLAGS), - COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_pre", 0, + COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(7), 0, - RK2928_CLKGATE_CON(0), 10, GFLAGS), - MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0, - RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(0), 10, GFLAGS, + &rk3066a_i2s1_fracmux), COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0, RK2928_CLKSEL_CON(4), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 11, GFLAGS), - COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_pre", 0, + COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(8), 0, - RK2928_CLKGATE_CON(0), 12, GFLAGS), - MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0, - RK2928_CLKSEL_CON(4), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(0), 12, GFLAGS, + &rk3066a_i2s2_fracmux), - GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), - GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), - GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS), - GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), + GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), + GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), + GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), + GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS), + GATE(HCLK_HDMI, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 14, GFLAGS), - GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS), + GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS), GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS), GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), @@ -630,9 +666,13 @@ static struct clk_div_table div_rk3188_aclk_core_t[] = { { /* sentinel */ }, }; -PNAME(mux_hsicphy_p) = { "sclk_otgphy0", "sclk_otgphy1", +PNAME(mux_hsicphy_p) = { "sclk_otgphy0_480m", "sclk_otgphy1_480m", "gpll", "cpll" }; +static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata = + MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); + static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, @@ -686,12 +726,12 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 9, GFLAGS), - COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0, + COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(7), 0, - RK2928_CLKGATE_CON(0), 10, GFLAGS), - MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0, - RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(0), 10, GFLAGS, + &rk3188_i2s0_fracmux), + GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS), @@ -707,142 +747,104 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), }; -static const char *rk3188_critical_clocks[] __initconst = { +static const char *const rk3188_critical_clocks[] __initconst = { "aclk_cpu", "aclk_peri", "hclk_peri", + "pclk_cpu", + "pclk_peri", + "hclk_cpubus", + "hclk_vio_bus", + "sclk_mac_lbtest", }; - -static void __init rockchip_reparent_clk(char *clock, char *new_parent) -{ - struct clk *clk1, *clk2; - unsigned long rate; - int ret; - - clk1 = __clk_lookup(clock); - clk2 = __clk_lookup(new_parent); - if (!IS_ERR(clk1) && !IS_ERR(clk2)) { - rate = clk_get_rate(clk1); - - ret = clk_set_parent(clk1, clk2); - if (ret < 0) - pr_err("%s: could not reparent %s to %s, ret=%d\n", - __func__, clock, new_parent, ret); - - clk_set_rate(clk1, rate); - } else { - pr_err("%s: missing clocks to reparent %s to %s\n", - __func__, clock, new_parent); - } -} - -static void __init rockchip_clk_set_rate(char *clock, unsigned long rate) -{ - struct clk *clk; - - clk = __clk_lookup(clock); - if(clk && !IS_ERR(clk)) { - clk_set_rate(clk, rate); - return; - } - pr_err("%s: missing clock %s when setting initial rate to %lu\n", - __func__, clock, rate); -} - -static void __init rockchip_clk_set_defaults(void) -{ - struct rockchip_initial_rate { - char *name; - unsigned long rate; - }; - int i; - - struct rockchip_initial_rate rates[] = { - {"gpll", 891000000}, - {"cpll", 600000000}, - {"aclk_cpu", 300000000}, - {"hclk_cpu", 150000000}, - {"pclk_cpu", 75000000}, - {"hclk_ahb2apb", 75000000}, - {"aclk_peri_pre", 150000000}, - {"hclk_peri", 150000000}, - {"pclk_peri", 75000000}, - }; - - rockchip_reparent_clk("aclk_cpu_pre", "gpll"); - rockchip_reparent_clk("mac_src", "dpll"); - rockchip_reparent_clk("aclk_peri_pre", "cpll"); - - for(i = 0; i < ARRAY_SIZE(rates); i++) - rockchip_clk_set_rate(rates[i].name, rates[i].rate); -} - -static void __init rk3188_common_clk_init(struct device_node *np) +static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np) { + struct rockchip_clk_provider *ctx; void __iomem *reg_base; - struct clk *clk; reg_base = of_iomap(np, 0); if (!reg_base) { pr_err("%s: could not map cru region\n", __func__); - return; + return ERR_PTR(-ENOMEM); } - rockchip_clk_init(np, reg_base, CLK_NR_CLKS); - - /* Fixed-clock should be registered before all others */ - clk=clk_fixed("xin24m",24000000); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock xin24m: %ld\n", - __func__, PTR_ERR(clk)); - - /* xin12m is created by an cru-internal divider */ - clk = clk_fixed_factor("xin12m", "xin24m", 1, 2, 0); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock xin12m: %ld\n", - __func__, PTR_ERR(clk)); - - clk = clk_fixed_factor("usb480m", "xin24m", 20, 1, 0); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock usb480m: %ld\n", - __func__, PTR_ERR(clk)); + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + return ERR_PTR(-ENOMEM); + } - rockchip_clk_register_branches(common_clk_branches, + rockchip_clk_register_branches(ctx, common_clk_branches, ARRAY_SIZE(common_clk_branches)); - rockchip_clk_protect_critical(rk3188_critical_clocks, - ARRAY_SIZE(rk3188_critical_clocks)); + + return ctx; } static void __init rk3066a_clk_init(struct device_node *np) { - rk3188_common_clk_init(np); - rockchip_clk_register_plls(rk3066_pll_clks, + struct rockchip_clk_provider *ctx; + + ctx = rk3188_common_clk_init(np); + if (IS_ERR(ctx)) + return; + + rockchip_clk_register_plls(ctx, rk3066_pll_clks, ARRAY_SIZE(rk3066_pll_clks), RK3066_GRF_SOC_STATUS); - rockchip_clk_register_branches(rk3066a_clk_branches, + rockchip_clk_register_branches(ctx, rk3066a_clk_branches, ARRAY_SIZE(rk3066a_clk_branches)); - rockchip_clk_register_armclk(ARMCLK, "armclk", + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", mux_armclk_p, ARRAY_SIZE(mux_armclk_p), &rk3066_cpuclk_data, rk3066_cpuclk_rates, ARRAY_SIZE(rk3066_cpuclk_rates)); + rockchip_clk_protect_critical(rk3188_critical_clocks, + ARRAY_SIZE(rk3188_critical_clocks)); + rockchip_clk_of_add_provider(np, ctx); } CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init); static void __init rk3188a_clk_init(struct device_node *np) { - rk3188_common_clk_init(np); - rockchip_clk_register_plls(rk3188_pll_clks, + struct rockchip_clk_provider *ctx; + struct clk *clk1, *clk2; + unsigned long rate; + int ret; + + ctx = rk3188_common_clk_init(np); + if (IS_ERR(ctx)) + return; + + rockchip_clk_register_plls(ctx, rk3188_pll_clks, ARRAY_SIZE(rk3188_pll_clks), RK3188_GRF_SOC_STATUS); - rockchip_clk_register_branches(rk3188_clk_branches, + rockchip_clk_register_branches(ctx, rk3188_clk_branches, ARRAY_SIZE(rk3188_clk_branches)); - rockchip_clk_register_armclk(ARMCLK, "armclk", + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", mux_armclk_p, ARRAY_SIZE(mux_armclk_p), &rk3188_cpuclk_data, rk3188_cpuclk_rates, ARRAY_SIZE(rk3188_cpuclk_rates)); - rockchip_clk_set_defaults(); + /* reparent aclk_cpu_pre from apll */ + clk1 = __clk_lookup("aclk_cpu_pre"); + clk2 = __clk_lookup("gpll"); + if (clk1 && clk2) { + rate = clk_get_rate(clk1); + + ret = clk_set_parent(clk1, clk2); + if (ret < 0) + pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n", + __func__); + + clk_set_rate(clk1, rate); + } else { + pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n", + __func__); + } + + rockchip_clk_protect_critical(rk3188_critical_clocks, + ARRAY_SIZE(rk3188_critical_clocks)); + rockchip_clk_of_add_provider(np, ctx); } CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init); @@ -859,7 +861,7 @@ static void __init rk3188_clk_init(struct device_node *np) rate = pll->rate_table; while (rate->rate > 0) { - rate->bwadj = 0; + rate->nb = 1; rate++; } } diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index dcfaae2407..fc9554e0f3 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -1,16 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> @@ -25,6 +16,11 @@ #define RK3288_GRF_SOC_CON(x) (0x244 + x * 4) #define RK3288_GRF_SOC_STATUS1 0x284 +enum rk3288_variant { + RK3288_CRU, + RK3288W_CRU, +}; + enum rk3288_plls { apll, dpll, cpll, gpll, npll, }; @@ -85,24 +81,44 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { RK3066_PLL_RATE( 768000000, 1, 64, 2), RK3066_PLL_RATE( 742500000, 8, 495, 2), RK3066_PLL_RATE( 696000000, 1, 58, 2), + RK3066_PLL_RATE_NB(621000000, 1, 207, 8, 1), RK3066_PLL_RATE( 600000000, 1, 50, 2), - RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1), + RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1), RK3066_PLL_RATE( 552000000, 1, 46, 2), RK3066_PLL_RATE( 504000000, 1, 84, 4), RK3066_PLL_RATE( 500000000, 3, 125, 2), RK3066_PLL_RATE( 456000000, 1, 76, 4), + RK3066_PLL_RATE( 428000000, 1, 107, 6), RK3066_PLL_RATE( 408000000, 1, 68, 4), RK3066_PLL_RATE( 400000000, 3, 100, 2), + RK3066_PLL_RATE_NB( 394000000, 1, 197, 12, 1), RK3066_PLL_RATE( 384000000, 2, 128, 4), RK3066_PLL_RATE( 360000000, 1, 60, 4), + RK3066_PLL_RATE_NB( 356000000, 1, 178, 12, 1), + RK3066_PLL_RATE_NB( 324000000, 1, 189, 14, 1), RK3066_PLL_RATE( 312000000, 1, 52, 4), - RK3066_PLL_RATE( 300000000, 1, 50, 4), - RK3066_PLL_RATE( 297000000, 2, 198, 8), + RK3066_PLL_RATE_NB( 308000000, 1, 154, 12, 1), + RK3066_PLL_RATE_NB( 303000000, 1, 202, 16, 1), + RK3066_PLL_RATE( 300000000, 1, 75, 6), + RK3066_PLL_RATE_NB( 297750000, 2, 397, 16, 1), + RK3066_PLL_RATE_NB( 293250000, 2, 391, 16, 1), + RK3066_PLL_RATE_NB( 292500000, 1, 195, 16, 1), + RK3066_PLL_RATE( 273600000, 1, 114, 10), + RK3066_PLL_RATE_NB( 273000000, 1, 182, 16, 1), + RK3066_PLL_RATE_NB( 270000000, 1, 180, 16, 1), + RK3066_PLL_RATE_NB( 266250000, 2, 355, 16, 1), + RK3066_PLL_RATE_NB( 256500000, 1, 171, 16, 1), RK3066_PLL_RATE( 252000000, 1, 84, 8), - RK3066_PLL_RATE( 216000000, 1, 72, 8), - RK3066_PLL_RATE( 148500000, 2, 99, 8), + RK3066_PLL_RATE_NB( 250500000, 1, 167, 16, 1), + RK3066_PLL_RATE_NB( 243428571, 1, 142, 14, 1), + RK3066_PLL_RATE( 238000000, 1, 119, 12), + RK3066_PLL_RATE_NB( 219750000, 2, 293, 16, 1), + RK3066_PLL_RATE_NB( 216000000, 1, 144, 16, 1), + RK3066_PLL_RATE_NB( 213000000, 1, 142, 16, 1), + RK3066_PLL_RATE( 195428571, 1, 114, 14), + RK3066_PLL_RATE( 160000000, 1, 80, 12), + RK3066_PLL_RATE( 157500000, 1, 105, 16), RK3066_PLL_RATE( 126000000, 1, 84, 16), - RK3066_PLL_RATE( 48000000, 1, 64, 32), { /* sentinel */ }, }; @@ -164,10 +180,14 @@ static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = { }; static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = { - .core_reg = RK3288_CLKSEL_CON(0), - .div_core_shift = 8, - .div_core_mask = 0x1f, + .core_reg[0] = RK3288_CLKSEL_CON(0), + .div_core_shift[0] = 8, + .div_core_mask[0] = 0x1f, + .num_cores = 1, + .mux_core_alt = 1, + .mux_core_main = 0, .mux_core_shift = 15, + .mux_core_mask = 0x1, }; PNAME(mux_pll_p) = { "xin24m", "xin32k" }; @@ -178,8 +198,8 @@ PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" }; PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; -PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usbphy480m_src" }; -PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "usbphy480m_src", "npll" }; +PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" }; +PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" }; PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" }; PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" }; @@ -197,8 +217,9 @@ PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" }; PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" }; PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" }; -PNAME(mux_usbphy480m_p) = { "sclk_otgphy1", "sclk_otgphy2", - "sclk_otgphy0" }; +PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vdpu", "aclk_vepu" }; +PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m", + "sclk_otgphy0_480m" }; PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" }; PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" }; @@ -225,6 +246,39 @@ static struct clk_div_table div_hclk_cpu_t[] = { #define MFLAGS CLK_MUX_HIWORD_MASK #define DFLAGS CLK_DIVIDER_HIWORD_MASK #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) +#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK + +static struct rockchip_clk_branch rk3288_i2s_fracmux __initdata = + MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(4), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3288_spdif_fracmux __initdata = + MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(5), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3288_spdif_8ch_fracmux __initdata = + MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(40), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3288_uart0_fracmux __initdata = + MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(13), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3288_uart1_fracmux __initdata = + MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(14), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3288_uart2_fracmux __initdata = + MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(15), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3288_uart3_fracmux __initdata = + MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(16), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3288_uart4_fracmux __initdata = + MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(3), 8, 2, MFLAGS); static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { /* @@ -296,20 +350,21 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKGATE_CON(0), 4, GFLAGS), GATE(0, "c2c_host", "aclk_cpu_src", 0, RK3288_CLKGATE_CON(13), 8, GFLAGS), - COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0, + COMPOSITE_NOMUX(SCLK_CRYPTO, "crypto", "aclk_cpu_pre", 0, RK3288_CLKSEL_CON(26), 6, 2, DFLAGS, RK3288_CLKGATE_CON(5), 4, GFLAGS), GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(0), 7, GFLAGS), + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), + COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS, RK3288_CLKGATE_CON(4), 1, GFLAGS), - COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(8), 0, - RK3288_CLKGATE_CON(4), 2, GFLAGS), - MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(4), 8, 2, MFLAGS), + RK3288_CLKGATE_CON(4), 2, GFLAGS, + &rk3288_i2s_fracmux), COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0, RK3288_CLKSEL_CON(4), 12, 1, MFLAGS, RK3288_CLKGATE_CON(4), 0, GFLAGS), @@ -318,27 +373,28 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(5), 15, 1, MFLAGS), - COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", 0, + COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(5), 0, 7, DFLAGS, RK3288_CLKGATE_CON(4), 4, GFLAGS), - COMPOSITE_FRAC(0, "spdif_frac", "spdif_src", 0, + COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(9), 0, - RK3288_CLKGATE_CON(4), 5, GFLAGS), - COMPOSITE_NODIV(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0, - RK3288_CLKSEL_CON(5), 8, 2, MFLAGS, + RK3288_CLKGATE_CON(4), 5, GFLAGS, + &rk3288_spdif_fracmux), + GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT, RK3288_CLKGATE_CON(4), 6, GFLAGS), - COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0, + COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(40), 0, 7, DFLAGS, RK3288_CLKGATE_CON(4), 7, GFLAGS), - COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_pre", 0, + COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(41), 0, - RK3288_CLKGATE_CON(4), 8, GFLAGS), - COMPOSITE_NODIV(SCLK_SPDIF8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0, - RK3288_CLKSEL_CON(40), 8, 2, MFLAGS, + RK3288_CLKGATE_CON(4), 8, GFLAGS, + &rk3288_spdif_8ch_fracmux), + GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT, RK3288_CLKGATE_CON(4), 9, GFLAGS), GATE(0, "sclk_acc_efuse", "xin24m", 0, RK3288_CLKGATE_CON(0), 12, GFLAGS), + GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, RK3288_CLKGATE_CON(1), 0, GFLAGS), GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, @@ -351,6 +407,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKGATE_CON(1), 4, GFLAGS), GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, RK3288_CLKGATE_CON(1), 5, GFLAGS), + /* * Clock-Architecture Diagram 2 */ @@ -361,26 +418,20 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 11, GFLAGS), - /* - * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system, - * so we ignore the mux and make clocks nodes as following, - */ - GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0, + MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT, + RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS), + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0, RK3288_CLKGATE_CON(9), 0, GFLAGS), - /* - * We introduce a virtul node of hclk_vodec_pre_v to split one clock - * struct with a gate and a fix divider into two node in software. - */ - GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0, + + FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, 1, 4, RK3288_CLKGATE_CON(3), 10, GFLAGS), + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, RK3288_CLKGATE_CON(9), 1, GFLAGS), COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3288_CLKGATE_CON(3), 0, GFLAGS), - DIV(0, "hclk_vio", "aclk_vio0", 0, - RK3288_CLKSEL_CON(28), 8, 5, DFLAGS), COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 2, GFLAGS), @@ -434,7 +485,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(26), 8, 1, MFLAGS, RK3288_CLKGATE_CON(3), 7, GFLAGS), - COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0, + COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0, RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS), DIV(0, "pclk_pd_alive", "gpll", 0, @@ -505,11 +556,11 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3288_CLKGATE_CON(4), 10, GFLAGS), - GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED, + GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(13), 4, GFLAGS), - GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED, + GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(13), 5, GFLAGS), - GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", CLK_IGNORE_UNUSED, + GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(13), 6, GFLAGS), GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(13), 7, GFLAGS), @@ -535,45 +586,40 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0, RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS, RK3288_CLKGATE_CON(1), 8, GFLAGS), - COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(17), 0, - RK3288_CLKGATE_CON(1), 9, GFLAGS), - MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(13), 8, 2, MFLAGS), + RK3288_CLKGATE_CON(1), 9, GFLAGS, + &rk3288_uart0_fracmux), MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(13), 15, 1, MFLAGS), COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0, RK3288_CLKSEL_CON(14), 0, 7, DFLAGS, RK3288_CLKGATE_CON(1), 10, GFLAGS), - COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(18), 0, - RK3288_CLKGATE_CON(1), 11, GFLAGS), - MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(14), 8, 2, MFLAGS), + RK3288_CLKGATE_CON(1), 11, GFLAGS, + &rk3288_uart1_fracmux), COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0, RK3288_CLKSEL_CON(15), 0, 7, DFLAGS, RK3288_CLKGATE_CON(1), 12, GFLAGS), - COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(19), 0, - RK3288_CLKGATE_CON(1), 13, GFLAGS), - MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(15), 8, 2, MFLAGS), + RK3288_CLKGATE_CON(1), 13, GFLAGS, + &rk3288_uart2_fracmux), COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0, RK3288_CLKSEL_CON(16), 0, 7, DFLAGS, RK3288_CLKGATE_CON(1), 14, GFLAGS), - COMPOSITE_FRAC(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(20), 0, - RK3288_CLKGATE_CON(1), 15, GFLAGS), - MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(16), 8, 2, MFLAGS), + RK3288_CLKGATE_CON(1), 15, GFLAGS, + &rk3288_uart3_fracmux), COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0, RK3288_CLKSEL_CON(3), 0, 7, DFLAGS, RK3288_CLKGATE_CON(2), 12, GFLAGS), - COMPOSITE_FRAC(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(7), 0, - RK3288_CLKGATE_CON(2), 13, GFLAGS), - MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(3), 8, 2, MFLAGS), + RK3288_CLKGATE_CON(2), 13, GFLAGS, + &rk3288_uart4_fracmux), COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0, RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS, @@ -594,6 +640,8 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKGATE_CON(2), 6, GFLAGS), MUX(0, "sclk_hsadc_out", mux_hsadcout_p, 0, RK3288_CLKSEL_CON(22), 4, 1, MFLAGS), + INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out", + RK3288_CLKSEL_CON(22), 7, IFLAGS), GATE(0, "jtag", "ext_jtag", 0, RK3288_CLKGATE_CON(4), 14, GFLAGS), @@ -641,11 +689,11 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS), GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS), GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS), - GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS), + GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS), GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), - GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS), - GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS), + GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS), + GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS), /* ddrctrl [DDR Controller PHY clock] gates */ GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS), @@ -658,7 +706,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { /* aclk_peri gates */ GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS), GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS), - GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 11, GFLAGS), + GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS), GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS), GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS), GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS), @@ -706,7 +754,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS), GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS), GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS), - GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS), + GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS), /* sclk_gpu gates */ GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS), @@ -721,12 +769,15 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS), GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS), GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS), - GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 12, GFLAGS), + GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS), + + /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */ + SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"), /* pclk_pd_pmu gates */ GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS), GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS), - GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 2, GFLAGS), + GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS), GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS), GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS), @@ -735,7 +786,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS), GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS), GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS), - GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 10, GFLAGS), + GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS), GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS), GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS), GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS), @@ -751,83 +802,106 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { /* aclk_vio0 gates */ GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS), GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS), - GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 11, GFLAGS), + GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS), GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS), /* aclk_vio1 gates */ GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS), GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS), - GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 12, GFLAGS), + GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS), /* aclk_rga_pre gates */ GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS), - GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 13, GFLAGS), + GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS), /* * Other ungrouped clocks. */ GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS), - GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS), + INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS), + GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS), + INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS), +}; + +static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = { + DIV(0, "hclk_vio", "aclk_vio1", 0, + RK3288_CLKSEL_CON(28), 8, 5, DFLAGS), }; -static const char *rk3288_critical_clocks[] __initconst = { +static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = { + DIV(0, "hclk_vio", "aclk_vio0", 0, + RK3288_CLKSEL_CON(28), 8, 5, DFLAGS), +}; + +static const char *const rk3288_critical_clocks[] __initconst = { "aclk_cpu", "aclk_peri", + "aclk_peri_niu", + "aclk_vio0_niu", + "aclk_vio1_niu", + "aclk_rga_niu", "hclk_peri", + "hclk_vio_niu", + "pclk_alive_niu", "pclk_pd_pmu", + "pclk_pmu_niu", + "pmu_hclk_otg0", + /* pwm-regulators on some boards, so handoff-critical later */ + "pclk_rkpwm", }; -static int __init rk3288_clk_init(struct device_node *np) +static void __iomem *rk3288_cru_base; + +static void __init rk3288_common_init(struct device_node *np, + enum rk3288_variant soc) { - void __iomem *reg_base; - struct clk *clk; + struct rockchip_clk_provider *ctx; - reg_base = of_iomap(np, 0); - if (!reg_base) { + rk3288_cru_base = of_iomap(np, 0); + if (!rk3288_cru_base) { pr_err("%s: could not map cru region\n", __func__); - return -ENOMEM; + return; } - rockchip_clk_init(np, reg_base, CLK_NR_CLKS); - - /* xin12m is created by an cru-internal divider */ - clk = clk_fixed_factor("xin12m", "xin24m", 1, 2, 0); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock xin12m: %ld\n", - __func__, PTR_ERR(clk)); - - clk = clk_fixed_factor("usb480m", "xin24m", 20, 1, 0); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock usb480m: %ld\n", - __func__, PTR_ERR(clk)); - - clk = clk_fixed_factor("hclk_vcodec_pre", - "hclk_vcodec_pre_v", 1, 4, 0); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", - __func__, PTR_ERR(clk)); - - /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */ - clk = clk_fixed_factor("pclk_wdt", "pclk_pd_alive", 1, 1, 0); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock pclk_wdt: %ld\n", - __func__, PTR_ERR(clk)); - else - rockchip_clk_add_lookup(clk, PCLK_WDT); + ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + return; + } - rockchip_clk_register_plls(rk3288_pll_clks, + rockchip_clk_register_plls(ctx, rk3288_pll_clks, ARRAY_SIZE(rk3288_pll_clks), RK3288_GRF_SOC_STATUS1); - rockchip_clk_register_branches(rk3288_clk_branches, + rockchip_clk_register_branches(ctx, rk3288_clk_branches, ARRAY_SIZE(rk3288_clk_branches)); + + if (soc == RK3288W_CRU) + rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch, + ARRAY_SIZE(rk3288w_hclkvio_branch)); + else + rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch, + ARRAY_SIZE(rk3288_hclkvio_branch)); + rockchip_clk_protect_critical(rk3288_critical_clocks, ARRAY_SIZE(rk3288_critical_clocks)); - rockchip_clk_register_armclk(ARMCLK, "armclk", + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", mux_armclk_p, ARRAY_SIZE(mux_armclk_p), &rk3288_cpuclk_data, rk3288_cpuclk_rates, ARRAY_SIZE(rk3288_cpuclk_rates)); - return 0; + + rockchip_clk_of_add_provider(np, ctx); +} + +static void __init rk3288_clk_init(struct device_node *np) +{ + rk3288_common_init(np, RK3288_CRU); } CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init); + +static void __init rk3288w_clk_init(struct device_node *np) +{ + rk3288_common_init(np, RK3288W_CRU); +} +CLK_OF_DECLARE(rk3288w_cru, "rockchip,rk3288w-cru", rk3288w_clk_init); diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c new file mode 100644 index 0000000000..d6c2a04711 --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -0,0 +1,1654 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> + */ + +#include <common.h> +#include <linux/clk.h> +#include <of.h> +#include <of_address.h> +#include <linux/barebox-wrapper.h> +#include <init.h> +#include <linux/spinlock.h> +#include <of_device.h> +#include <dt-bindings/clock/rk3399-cru.h> +#include "clk.h" + +enum rk3399_plls { + lpll, bpll, dpll, cpll, gpll, npll, vpll, +}; + +enum rk3399_pmu_plls { + ppll, +}; + +static struct rockchip_pll_rate_table rk3399_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), + RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), + RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), + RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0), + RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0), + RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), + RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), + RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), + RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), + RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), + RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0), + RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0), + RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), + RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), + RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0), + RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0), + RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0), + RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), + RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0), + RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0), + RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0), + RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), + RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0), + RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0), + RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0), + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), + RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), + RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), + RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), + RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), + RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), + RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), + RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), + RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), + RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), + RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), + RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), + RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), + RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), + RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), + RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), + RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), + RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), + RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), + RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), + RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), + RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), + RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0), + RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), + RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), + RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), + RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), + RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0), + RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0), + RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), + RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), + RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), + RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0), + RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0), + RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0), + RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), + RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0), + RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0), + RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0), + RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0), + { /* sentinel */ }, +}; + +/* CRU parents */ +PNAME(mux_pll_p) = { "xin24m", "xin32k" }; + +PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src", + "clk_core_l_bpll_src", + "clk_core_l_dpll_src", + "clk_core_l_gpll_src" }; +PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src", + "clk_core_b_bpll_src", + "clk_core_b_dpll_src", + "clk_core_b_gpll_src" }; +PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", + "clk_ddrc_bpll_src", + "clk_ddrc_dpll_src", + "clk_ddrc_gpll_src" }; +PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", + "gpll_aclk_cci_src", + "npll_aclk_cci_src", + "vpll_aclk_cci_src" }; +PNAME(mux_cci_trace_p) = { "cpll_cci_trace", + "gpll_cci_trace" }; +PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", + "npll_cs"}; +PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src", + "gpll_aclk_perihp_src" }; + +PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; +PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; +PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" }; +PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" }; +PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; +PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll", + "ppll" }; +PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll", + "xin24m" }; +PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll", + "clk_usbphy_480m" }; +PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll", + "npll", "upll" }; +PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", + "upll", "xin24m" }; +PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", + "ppll", "upll", "xin24m" }; + +PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; +PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", + "npll" }; +PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", + "xin24m" }; + +PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", + "dclk_vop0_frac" }; +PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", + "dclk_vop1_frac" }; + +PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" }; + +PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" }; +PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" }; +PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k", + "cpll", "gpll" }; +PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru", + "clk_pcie_core_phy" }; + +PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src", + "gpll_aclk_emmc_src" }; + +PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src", + "gpll_aclk_perilp0_src" }; + +PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src", + "gpll_fclk_cm0s_src" }; + +PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src", + "gpll_hclk_perilp1_src" }; + +PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" }; +PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" }; + +PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src", + "clk_usbphy1_480m_src" }; +PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src", + "gpll_aclk_gmac_src" }; +PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" }; +PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac", + "clkin_i2s", "xin12m" }; +PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", + "clkin_i2s", "xin12m" }; +PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", + "clkin_i2s", "xin12m" }; +PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", + "clkin_i2s", "xin12m" }; +PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1", + "clk_i2s2" }; +PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" }; + +PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; +PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; +PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; +PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; + +/* PMU CRU parents */ +PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" }; +PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; +PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" }; +PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" }; +PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac", + "xin24m" }; +PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" }; + +static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { + [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0), + RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates), + [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8), + RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates), + [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16), + RK3399_PLL_CON(19), 8, 31, 0, NULL), + [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24), + RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), + [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32), + RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), + [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40), + RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), + [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48), + RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), +}; + +static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = { + [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0), + RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), +}; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) +#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK + +static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata = + MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(32), 13, 2, MFLAGS); + +static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata = + MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(28), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata = + MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(29), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata = + MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(30), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata = + MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(33), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata = + MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(34), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata = + MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(35), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata = + MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(36), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata = + MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT, + RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata = + MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(49), 11, 1, MFLAGS); + +static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata = + MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(50), 11, 1, MFLAGS); + +static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata = + MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT, + RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS); + +static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = { + .core_reg[0] = RK3399_CLKSEL_CON(0), + .div_core_shift[0] = 0, + .div_core_mask[0] = 0x1f, + .num_cores = 1, + .mux_core_alt = 3, + .mux_core_main = 0, + .mux_core_shift = 6, + .mux_core_mask = 0x3, +}; + +static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = { + .core_reg[0] = RK3399_CLKSEL_CON(2), + .div_core_shift[0] = 0, + .div_core_mask[0] = 0x1f, + .num_cores = 1, + .mux_core_alt = 3, + .mux_core_main = 1, + .mux_core_shift = 6, + .mux_core_mask = 0x3, +}; + +#define RK3399_DIV_ACLKM_MASK 0x1f +#define RK3399_DIV_ACLKM_SHIFT 8 +#define RK3399_DIV_ATCLK_MASK 0x1f +#define RK3399_DIV_ATCLK_SHIFT 0 +#define RK3399_DIV_PCLK_DBG_MASK 0x1f +#define RK3399_DIV_PCLK_DBG_SHIFT 8 + +#define RK3399_CLKSEL0(_offs, _aclkm) \ + { \ + .reg = RK3399_CLKSEL_CON(0 + _offs), \ + .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \ + RK3399_DIV_ACLKM_SHIFT), \ + } +#define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \ + { \ + .reg = RK3399_CLKSEL_CON(1 + _offs), \ + .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \ + RK3399_DIV_ATCLK_SHIFT) | \ + HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \ + RK3399_DIV_PCLK_DBG_SHIFT), \ + } + +/* cluster_l: aclkm in clksel0, rest in clksel1 */ +#define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \ + { \ + .prate = _prate##U, \ + .divs = { \ + RK3399_CLKSEL0(0, _aclkm), \ + RK3399_CLKSEL1(0, _atclk, _pdbg), \ + }, \ + } + +/* cluster_b: aclkm in clksel2, rest in clksel3 */ +#define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \ + { \ + .prate = _prate##U, \ + .divs = { \ + RK3399_CLKSEL0(2, _aclkm), \ + RK3399_CLKSEL1(2, _atclk, _pdbg), \ + }, \ + } + +static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = { + RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8), + RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8), + RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7), + RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7), + RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6), + RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6), + RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5), + RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5), + RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4), + RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3), + RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3), + RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2), + RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1), + RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1), + RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1), +}; + +static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = { + RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11), + RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11), + RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10), + RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10), + RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9), + RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9), + RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9), + RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8), + RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8), + RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7), + RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7), + RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6), + RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6), + RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5), + RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5), + RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4), + RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3), + RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3), + RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2), + RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1), + RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1), + RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1), +}; + +static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { + /* + * CRU Clock-Architecture + */ + + /* usbphy */ + GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(6), 5, GFLAGS), + GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(6), 6, GFLAGS), + + GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0, + RK3399_CLKGATE_CON(13), 12, GFLAGS), + GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0, + RK3399_CLKGATE_CON(13), 12, GFLAGS), + MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0, + RK3399_CLKSEL_CON(14), 6, 1, MFLAGS), + + MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0, + RK3399_CLKSEL_CON(14), 15, 1, MFLAGS), + + COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0, + RK3399_CLKSEL_CON(19), 0, 2, MFLAGS, + RK3399_CLKGATE_CON(6), 4, GFLAGS), + + COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0, + RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(12), 0, GFLAGS), + GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(30), 0, GFLAGS), + GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0, + RK3399_CLKGATE_CON(30), 1, GFLAGS), + GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0, + RK3399_CLKGATE_CON(30), 2, GFLAGS), + GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0, + RK3399_CLKGATE_CON(30), 3, GFLAGS), + GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0, + RK3399_CLKGATE_CON(30), 4, GFLAGS), + + GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0, + RK3399_CLKGATE_CON(12), 1, GFLAGS), + GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0, + RK3399_CLKGATE_CON(12), 2, GFLAGS), + + COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0, + RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS, + RK3399_CLKGATE_CON(12), 3, GFLAGS), + + COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0, + RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS, + RK3399_CLKGATE_CON(12), 4, GFLAGS), + + COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0, + RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKGATE_CON(13), 4, GFLAGS), + + COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(13), 5, GFLAGS), + + COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0, + RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKGATE_CON(13), 6, GFLAGS), + + COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(13), 7, GFLAGS), + + /* little core */ + GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(0), 0, GFLAGS), + GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(0), 1, GFLAGS), + GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(0), 2, GFLAGS), + GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(0), 3, GFLAGS), + + COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3399_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3399_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE_NOMUX(PCLK_COREDBG_L, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3399_CLKGATE_CON(0), 6, GFLAGS), + + GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(14), 12, GFLAGS), + GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(14), 13, GFLAGS), + + GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(14), 9, GFLAGS), + GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(14), 10, GFLAGS), + GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(14), 11, GFLAGS), + GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, + RK3399_CLKGATE_CON(0), 7, GFLAGS), + + /* big core */ + GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(1), 0, GFLAGS), + GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(1), 1, GFLAGS), + GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(1), 2, GFLAGS), + GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(1), 3, GFLAGS), + + COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3399_CLKGATE_CON(1), 4, GFLAGS), + COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3399_CLKGATE_CON(1), 5, GFLAGS), + COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3399_CLKGATE_CON(1), 6, GFLAGS), + + GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(14), 5, GFLAGS), + GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(14), 6, GFLAGS), + + GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(14), 1, GFLAGS), + GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(14), 3, GFLAGS), + GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(14), 4, GFLAGS), + + DIV(PCLK_COREDBG_B, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY), + + GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(14), 2, GFLAGS), + + GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 0, + RK3399_CLKGATE_CON(1), 7, GFLAGS), + + /* gmac */ + GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(6), 9, GFLAGS), + GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(6), 8, GFLAGS), + COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0, + RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(6), 10, GFLAGS), + + GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0, + RK3399_CLKGATE_CON(32), 0, GFLAGS), + GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(32), 1, GFLAGS), + GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0, + RK3399_CLKGATE_CON(32), 4, GFLAGS), + + COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0, + RK3399_CLKSEL_CON(19), 8, 3, DFLAGS, + RK3399_CLKGATE_CON(6), 11, GFLAGS), + GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0, + RK3399_CLKGATE_CON(32), 2, GFLAGS), + GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(32), 3, GFLAGS), + + COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0, + RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKGATE_CON(5), 5, GFLAGS), + + MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(19), 4, 1, MFLAGS), + GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0, + RK3399_CLKGATE_CON(5), 6, GFLAGS), + GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0, + RK3399_CLKGATE_CON(5), 7, GFLAGS), + GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0, + RK3399_CLKGATE_CON(5), 8, GFLAGS), + GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0, + RK3399_CLKGATE_CON(5), 9, GFLAGS), + + /* spdif */ + COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3399_CLKGATE_CON(8), 13, GFLAGS), + COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0, + RK3399_CLKSEL_CON(99), 0, + RK3399_CLKGATE_CON(8), 14, GFLAGS, + &rk3399_spdif_fracmux), + GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT, + RK3399_CLKGATE_CON(8), 15, GFLAGS), + + COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKGATE_CON(10), 6, GFLAGS), + /* i2s */ + COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3399_CLKGATE_CON(8), 3, GFLAGS), + COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0, + RK3399_CLKSEL_CON(96), 0, + RK3399_CLKGATE_CON(8), 4, GFLAGS, + &rk3399_i2s0_fracmux), + GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT, + RK3399_CLKGATE_CON(8), 5, GFLAGS), + + COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3399_CLKGATE_CON(8), 6, GFLAGS), + COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0, + RK3399_CLKSEL_CON(97), 0, + RK3399_CLKGATE_CON(8), 7, GFLAGS, + &rk3399_i2s1_fracmux), + GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT, + RK3399_CLKGATE_CON(8), 8, GFLAGS), + + COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3399_CLKGATE_CON(8), 9, GFLAGS), + COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0, + RK3399_CLKSEL_CON(98), 0, + RK3399_CLKGATE_CON(8), 10, GFLAGS, + &rk3399_i2s2_fracmux), + GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, + RK3399_CLKGATE_CON(8), 11, GFLAGS), + + MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(31), 0, 2, MFLAGS), + COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(31), 2, 1, MFLAGS, + RK3399_CLKGATE_CON(8), 12, GFLAGS), + + /* uart */ + MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0, + RK3399_CLKSEL_CON(33), 12, 2, MFLAGS), + COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0, + RK3399_CLKSEL_CON(33), 0, 7, DFLAGS, + RK3399_CLKGATE_CON(9), 0, GFLAGS), + COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0, + RK3399_CLKSEL_CON(100), 0, + RK3399_CLKGATE_CON(9), 1, GFLAGS, + &rk3399_uart0_fracmux), + + MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(33), 15, 1, MFLAGS), + COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0, + RK3399_CLKSEL_CON(34), 0, 7, DFLAGS, + RK3399_CLKGATE_CON(9), 2, GFLAGS), + COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0, + RK3399_CLKSEL_CON(101), 0, + RK3399_CLKGATE_CON(9), 3, GFLAGS, + &rk3399_uart1_fracmux), + + COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0, + RK3399_CLKSEL_CON(35), 0, 7, DFLAGS, + RK3399_CLKGATE_CON(9), 4, GFLAGS), + COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0, + RK3399_CLKSEL_CON(102), 0, + RK3399_CLKGATE_CON(9), 5, GFLAGS, + &rk3399_uart2_fracmux), + + COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0, + RK3399_CLKSEL_CON(36), 0, 7, DFLAGS, + RK3399_CLKGATE_CON(9), 6, GFLAGS), + COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", 0, + RK3399_CLKSEL_CON(103), 0, + RK3399_CLKGATE_CON(9), 7, GFLAGS, + &rk3399_uart3_fracmux), + + COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKGATE_CON(3), 4, GFLAGS), + + GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(18), 10, GFLAGS), + GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0, + RK3399_CLKGATE_CON(18), 12, GFLAGS), + GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(18), 15, GFLAGS), + GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(19), 2, GFLAGS), + + GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0, + RK3399_CLKGATE_CON(4), 11, GFLAGS), + GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", 0, + RK3399_CLKGATE_CON(3), 5, GFLAGS), + GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", 0, + RK3399_CLKGATE_CON(3), 6, GFLAGS), + + /* cci */ + GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(2), 0, GFLAGS), + GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(2), 1, GFLAGS), + GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(2), 2, GFLAGS), + GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(2), 3, GFLAGS), + + COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(2), 4, GFLAGS), + + GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(15), 0, GFLAGS), + GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(15), 1, GFLAGS), + GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(15), 2, GFLAGS), + GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(15), 3, GFLAGS), + GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(15), 4, GFLAGS), + GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(15), 7, GFLAGS), + + GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(2), 5, GFLAGS), + GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(2), 6, GFLAGS), + COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKGATE_CON(2), 7, GFLAGS), + + GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(2), 8, GFLAGS), + GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(2), 9, GFLAGS), + GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(2), 10, GFLAGS), + COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS), + GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(15), 5, GFLAGS), + GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(15), 6, GFLAGS), + + /* vcodec */ + COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, + RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(4), 0, GFLAGS), + COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, + RK3399_CLKSEL_CON(7), 8, 5, DFLAGS, + RK3399_CLKGATE_CON(4), 1, GFLAGS), + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, + RK3399_CLKGATE_CON(17), 2, GFLAGS), + GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(17), 3, GFLAGS), + + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0, + RK3399_CLKGATE_CON(17), 0, GFLAGS), + GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(17), 1, GFLAGS), + + /* vdu */ + COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0, + RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(4), 4, GFLAGS), + COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0, + RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKGATE_CON(4), 5, GFLAGS), + + COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, + RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(4), 2, GFLAGS), + COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0, + RK3399_CLKSEL_CON(8), 8, 5, DFLAGS, + RK3399_CLKGATE_CON(4), 3, GFLAGS), + GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0, + RK3399_CLKGATE_CON(17), 10, GFLAGS), + GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(17), 11, GFLAGS), + + GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0, + RK3399_CLKGATE_CON(17), 8, GFLAGS), + GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(17), 9, GFLAGS), + + /* iep */ + COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, + RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(4), 6, GFLAGS), + COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0, + RK3399_CLKSEL_CON(10), 8, 5, DFLAGS, + RK3399_CLKGATE_CON(4), 7, GFLAGS), + GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0, + RK3399_CLKGATE_CON(16), 2, GFLAGS), + GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(16), 3, GFLAGS), + + GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, + RK3399_CLKGATE_CON(16), 0, GFLAGS), + GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(16), 1, GFLAGS), + + /* rga */ + COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0, + RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(4), 10, GFLAGS), + + COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, + RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(4), 8, GFLAGS), + COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0, + RK3399_CLKSEL_CON(11), 8, 5, DFLAGS, + RK3399_CLKGATE_CON(4), 9, GFLAGS), + GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, + RK3399_CLKGATE_CON(16), 10, GFLAGS), + GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(16), 11, GFLAGS), + + GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, + RK3399_CLKGATE_CON(16), 8, GFLAGS), + GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(16), 9, GFLAGS), + + /* center */ + COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKGATE_CON(3), 7, GFLAGS), + GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(19), 0, GFLAGS), + GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(19), 1, GFLAGS), + + /* gpu */ + COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(13), 0, GFLAGS), + GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, + RK3399_CLKGATE_CON(30), 8, GFLAGS), + GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0, + RK3399_CLKGATE_CON(30), 10, GFLAGS), + GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0, + RK3399_CLKGATE_CON(30), 11, GFLAGS), + GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0, + RK3399_CLKGATE_CON(13), 1, GFLAGS), + + /* perihp */ + GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(5), 1, GFLAGS), + GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(5), 0, GFLAGS), + COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(5), 2, GFLAGS), + COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(14), 8, 2, DFLAGS, + RK3399_CLKGATE_CON(5), 3, GFLAGS), + COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(14), 12, 2, DFLAGS, + RK3399_CLKGATE_CON(5), 4, GFLAGS), + + GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0, + RK3399_CLKGATE_CON(20), 2, GFLAGS), + GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0, + RK3399_CLKGATE_CON(20), 10, GFLAGS), + GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(20), 12, GFLAGS), + + GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0, + RK3399_CLKGATE_CON(20), 5, GFLAGS), + GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0, + RK3399_CLKGATE_CON(20), 6, GFLAGS), + GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0, + RK3399_CLKGATE_CON(20), 7, GFLAGS), + GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0, + RK3399_CLKGATE_CON(20), 8, GFLAGS), + GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0, + RK3399_CLKGATE_CON(20), 9, GFLAGS), + GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(20), 13, GFLAGS), + GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(20), 15, GFLAGS), + + GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(20), 4, GFLAGS), + GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0, + RK3399_CLKGATE_CON(20), 11, GFLAGS), + GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(20), 14, GFLAGS), + GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0, + RK3399_CLKGATE_CON(31), 8, GFLAGS), + + /* sdio & sdmmc */ + COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKGATE_CON(12), 13, GFLAGS), + GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0, + RK3399_CLKGATE_CON(33), 8, GFLAGS), + GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(33), 9, GFLAGS), + + COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, + RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS, + RK3399_CLKGATE_CON(6), 0, GFLAGS), + + COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, + RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS, + RK3399_CLKGATE_CON(6), 1, GFLAGS), + + MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1), + MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1), + + MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1), + MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1), + + /* pcie */ + COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0, + RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS, + RK3399_CLKGATE_CON(6), 2, GFLAGS), + + COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0, + RK3399_CLKSEL_CON(18), 11, 5, DFLAGS, + RK3399_CLKGATE_CON(12), 6, GFLAGS), + MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(18), 10, 1, MFLAGS), + + COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0, + RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3399_CLKGATE_CON(6), 3, GFLAGS), + MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(18), 7, 1, MFLAGS), + + /* emmc */ + COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0, + RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS, + RK3399_CLKGATE_CON(6), 14, GFLAGS), + + GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(6), 13, GFLAGS), + GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(6), 12, GFLAGS), + COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS), + GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(32), 8, GFLAGS), + GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(32), 9, GFLAGS), + GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(32), 10, GFLAGS), + + /* perilp0 */ + GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(7), 1, GFLAGS), + GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(7), 0, GFLAGS), + COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(7), 2, GFLAGS), + COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(23), 8, 2, DFLAGS, + RK3399_CLKGATE_CON(7), 3, GFLAGS), + COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0, + RK3399_CLKSEL_CON(23), 12, 3, DFLAGS, + RK3399_CLKGATE_CON(7), 4, GFLAGS), + + /* aclk_perilp0 gates */ + GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS), + GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS), + GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS), + GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS), + GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS), + GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS), + GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS), + GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS), + GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS), + GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS), + GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS), + GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS), + + /* hclk_perilp0 gates */ + GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS), + GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS), + GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS), + GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS), + GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS), + GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS), + + /* pclk_perilp0 gates */ + GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS), + + /* crypto */ + COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0, + RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(7), 7, GFLAGS), + + COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0, + RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(7), 8, GFLAGS), + + /* cm0s_perilp */ + GATE(0, "cpll_fclk_cm0s_src", "cpll", 0, + RK3399_CLKGATE_CON(7), 6, GFLAGS), + GATE(0, "gpll_fclk_cm0s_src", "gpll", 0, + RK3399_CLKGATE_CON(7), 5, GFLAGS), + COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0, + RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKGATE_CON(7), 9, GFLAGS), + + /* fclk_cm0s gates */ + GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS), + GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS), + GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS), + GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS), + GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS), + + /* perilp1 */ + GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(8), 1, GFLAGS), + GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(8), 0, GFLAGS), + COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS), + COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(25), 8, 3, DFLAGS, + RK3399_CLKGATE_CON(8), 2, GFLAGS), + + /* hclk_perilp1 gates */ + GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS), + GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS), + GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS), + GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS), + GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS), + GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS), + GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS), + GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS), + GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS), + + /* pclk_perilp1 gates */ + GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS), + GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS), + GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS), + GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS), + GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS), + GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS), + GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS), + GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS), + GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS), + GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS), + GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS), + GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS), + GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS), + GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS), + GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS), + + /* saradc */ + COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, + RK3399_CLKSEL_CON(26), 8, 8, DFLAGS, + RK3399_CLKGATE_CON(9), 11, GFLAGS), + + /* tsadc */ + COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0, + RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS, + RK3399_CLKGATE_CON(9), 10, GFLAGS), + + /* cif_testout */ + MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0, + RK3399_CLKSEL_CON(38), 6, 2, MFLAGS), + COMPOSITE(SCLK_TESTCLKOUT1, "clk_testout1", mux_clk_testout1_p, 0, + RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(13), 14, GFLAGS), + + MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0, + RK3399_CLKSEL_CON(38), 14, 2, MFLAGS), + COMPOSITE(SCLK_TESTCLKOUT2, "clk_testout2", mux_clk_testout2_p, 0, + RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKGATE_CON(13), 15, GFLAGS), + + /* vio */ + COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(11), 0, GFLAGS), + COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0, + RK3399_CLKSEL_CON(43), 0, 5, DFLAGS, + RK3399_CLKGATE_CON(11), 1, GFLAGS), + + GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(29), 0, GFLAGS), + + GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0, + RK3399_CLKGATE_CON(29), 1, GFLAGS), + GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0, + RK3399_CLKGATE_CON(29), 2, GFLAGS), + GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(29), 12, GFLAGS), + + /* hdcp */ + COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0, + RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKGATE_CON(11), 12, GFLAGS), + COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0, + RK3399_CLKSEL_CON(43), 5, 5, DFLAGS, + RK3399_CLKGATE_CON(11), 3, GFLAGS), + COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0, + RK3399_CLKSEL_CON(43), 10, 5, DFLAGS, + RK3399_CLKGATE_CON(11), 10, GFLAGS), + + GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(29), 4, GFLAGS), + GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0, + RK3399_CLKGATE_CON(29), 10, GFLAGS), + + GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(29), 5, GFLAGS), + GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0, + RK3399_CLKGATE_CON(29), 9, GFLAGS), + + GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(29), 3, GFLAGS), + GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0, + RK3399_CLKGATE_CON(29), 6, GFLAGS), + GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0, + RK3399_CLKGATE_CON(29), 7, GFLAGS), + GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0, + RK3399_CLKGATE_CON(29), 8, GFLAGS), + GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0, + RK3399_CLKGATE_CON(29), 11, GFLAGS), + + /* edp */ + COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(11), 8, GFLAGS), + + COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS, + RK3399_CLKGATE_CON(11), 11, GFLAGS), + GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(32), 12, GFLAGS), + GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0, + RK3399_CLKGATE_CON(32), 13, GFLAGS), + + /* hdmi */ + GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0, + RK3399_CLKGATE_CON(11), 6, GFLAGS), + + COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0, + RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS, + RK3399_CLKGATE_CON(11), 7, GFLAGS), + + /* vop0 */ + COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0, + RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(10), 8, GFLAGS), + COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0, + RK3399_CLKSEL_CON(47), 8, 5, DFLAGS, + RK3399_CLKGATE_CON(10), 9, GFLAGS), + + GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0, + RK3399_CLKGATE_CON(28), 3, GFLAGS), + GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(28), 1, GFLAGS), + + GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0, + RK3399_CLKGATE_CON(28), 2, GFLAGS), + GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(28), 0, GFLAGS), + + COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3399_CLKGATE_CON(10), 12, GFLAGS), + + COMPOSITE_FRACMUX_NOGATE(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0, + RK3399_CLKSEL_CON(106), 0, + &rk3399_dclk_vop0_fracmux), + + COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0, + RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(10), 14, GFLAGS), + + /* vop1 */ + COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0, + RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(10), 10, GFLAGS), + COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0, + RK3399_CLKSEL_CON(48), 8, 5, DFLAGS, + RK3399_CLKGATE_CON(10), 11, GFLAGS), + + GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0, + RK3399_CLKGATE_CON(28), 7, GFLAGS), + GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(28), 5, GFLAGS), + + GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0, + RK3399_CLKGATE_CON(28), 6, GFLAGS), + GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(28), 4, GFLAGS), + + COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3399_CLKGATE_CON(10), 13, GFLAGS), + + COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0, + RK3399_CLKSEL_CON(107), 0, + &rk3399_dclk_vop1_fracmux), + + COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(10), 15, GFLAGS), + + /* isp */ + COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0, + RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(12), 8, GFLAGS), + COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0, + RK3399_CLKSEL_CON(53), 8, 5, DFLAGS, + RK3399_CLKGATE_CON(12), 9, GFLAGS), + + GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(27), 1, GFLAGS), + GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0, + RK3399_CLKGATE_CON(27), 5, GFLAGS), + GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0, + RK3399_CLKGATE_CON(27), 7, GFLAGS), + + GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(27), 0, GFLAGS), + GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0, + RK3399_CLKGATE_CON(27), 4, GFLAGS), + + COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0, + RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(11), 4, GFLAGS), + + COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0, + RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKGATE_CON(12), 10, GFLAGS), + COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0, + RK3399_CLKSEL_CON(54), 8, 5, DFLAGS, + RK3399_CLKGATE_CON(12), 11, GFLAGS), + + GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(27), 3, GFLAGS), + + GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(27), 2, GFLAGS), + GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0, + RK3399_CLKGATE_CON(27), 8, GFLAGS), + + COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0, + RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKGATE_CON(11), 5, GFLAGS), + + /* + * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system, + * so we ignore the mux and make clocks nodes as following, + * + * pclkin_cifinv --|-------\ + * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper + * pclkin_cif --|-------/ + */ + GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0, + RK3399_CLKGATE_CON(27), 6, GFLAGS), + + /* cif */ + COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0, + RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, + RK3399_CLKGATE_CON(10), 7, GFLAGS), + + COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0, + RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS), + + /* gic */ + COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKGATE_CON(12), 12, GFLAGS), + + GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS), + GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS), + GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS), + GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS), + GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS), + GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS), + + /* alive */ + /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */ + DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0, + RK3399_CLKSEL_CON(57), 0, 5, DFLAGS), + + GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS), + GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS), + GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS), + GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS), + GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS), + + GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS), + GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS), + GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS), + GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS), + GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS), + GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS), + + /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */ + SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_alive"), + + GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS), + GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS), + + GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS), + GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS), + GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS), + GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS), + + /* testout */ + MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT, + RK3399_CLKSEL_CON(58), 7, 1, MFLAGS), + COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0, + RK3399_CLKSEL_CON(105), 0, + RK3399_CLKGATE_CON(13), 9, GFLAGS), + + DIV(0, "clk_test_24m", "xin24m", 0, + RK3399_CLKSEL_CON(57), 6, 10, DFLAGS), + + /* spi */ + COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3399_CLKGATE_CON(9), 12, GFLAGS), + + COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3399_CLKGATE_CON(9), 13, GFLAGS), + + COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3399_CLKGATE_CON(9), 14, GFLAGS), + + COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3399_CLKGATE_CON(9), 15, GFLAGS), + + COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3399_CLKGATE_CON(13), 13, GFLAGS), + + /* i2c */ + COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3399_CLKGATE_CON(10), 0, GFLAGS), + + COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3399_CLKGATE_CON(10), 2, GFLAGS), + + COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3399_CLKGATE_CON(10), 4, GFLAGS), + + COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3399_CLKGATE_CON(10), 1, GFLAGS), + + COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3399_CLKGATE_CON(10), 3, GFLAGS), + + COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0, + RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3399_CLKGATE_CON(10), 5, GFLAGS), + + /* timer */ + GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS), + GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS), + GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS), + GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS), + GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS), + GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS), + GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS), + GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS), + GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS), + GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS), + GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS), + GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS), + + /* clk_test */ + /* clk_test_pre is controlled by CRU_MISC_CON[3] */ + COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(58), 0, 5, DFLAGS, + RK3399_CLKGATE_CON(13), 11, GFLAGS), + + /* ddrc */ + GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3), + 0, GFLAGS), + GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3), + 1, GFLAGS), + GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3), + 2, GFLAGS), + GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3), + 3, GFLAGS), + COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc", mux_ddrclk_p, 0, + RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP), +}; + +static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { + /* + * PMU CRU Clock-Architecture + */ + + GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0, + RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS), + + COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0, + RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS), + + COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0, + RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS), + + COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED, + RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS, + RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS), + + COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", 0, + RK3399_PMU_CLKSEL_CON(7), 0, + &rk3399_pmuclk_wifi_fracmux), + + MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED, + RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS), + + COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0, + RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS, + RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS), + + COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0, + RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS, + RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS), + + COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0, + RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS, + RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS), + + DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED, + RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS), + MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED, + RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS), + + COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0, + RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS, + RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS), + + COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0, + RK3399_PMU_CLKSEL_CON(6), 0, + RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS, + &rk3399_uart4_pmu_fracmux), + + DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED, + RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS), + + /* pmu clock gates */ + GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS), + GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS), + + GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS), + + GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS), + GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS), + GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS), + GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS), + GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS), + GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS), + GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS), + GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS), + GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS), + GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS), + GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS), + GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS), + GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS), + GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS), + GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS), + GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS), + + GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS), + GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS), + GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS), + GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS), + GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS), +}; + +static const char *const rk3399_cru_critical_clocks[] __initconst = { + "aclk_cci_pre", + "aclk_gic", + "aclk_gic_noc", + "aclk_hdcp_noc", + "hclk_hdcp_noc", + "pclk_hdcp_noc", + "pclk_perilp0", + "pclk_perilp0", + "hclk_perilp0", + "hclk_perilp0_noc", + "pclk_perilp1", + "pclk_perilp1_noc", + "pclk_perihp", + "pclk_perihp_noc", + "hclk_perihp", + "aclk_perihp", + "aclk_perihp_noc", + "aclk_perilp0", + "aclk_perilp0_noc", + "hclk_perilp1", + "hclk_perilp1_noc", + "aclk_dmac0_perilp", + "aclk_emmc_noc", + "gpll_hclk_perilp1_src", + "gpll_aclk_perilp0_src", + "gpll_aclk_perihp_src", + "aclk_vio_noc", + + /* ddrc */ + "sclk_ddrc", + + "armclkl", + "armclkb", +}; + +static const char *const rk3399_pmucru_critical_clocks[] __initconst = { + "ppll", + "pclk_pmu_src", + "fclk_cm0s_src_pmu", + "clk_timer_src_pmu", + "pclk_rkpwm_pmu", +}; + +static void __init rk3399_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + void __iomem *reg_base; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + return; + } + + rockchip_clk_register_plls(ctx, rk3399_pll_clks, + ARRAY_SIZE(rk3399_pll_clks), -1); + + rockchip_clk_register_branches(ctx, rk3399_clk_branches, + ARRAY_SIZE(rk3399_clk_branches)); + + rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl", + mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), + &rk3399_cpuclkl_data, rk3399_cpuclkl_rates, + ARRAY_SIZE(rk3399_cpuclkl_rates)); + + rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb", + mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p), + &rk3399_cpuclkb_data, rk3399_cpuclkb_rates, + ARRAY_SIZE(rk3399_cpuclkb_rates)); + + rockchip_clk_protect_critical(rk3399_cru_critical_clocks, + ARRAY_SIZE(rk3399_cru_critical_clocks)); + + rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); + + rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST); + + rockchip_clk_of_add_provider(np, ctx); +} + +static void __init rk3399_pmu_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + void __iomem *reg_base; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru pmu region\n", __func__); + return; + } + + ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip pmu clk init failed\n", __func__); + return; + } + + rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks, + ARRAY_SIZE(rk3399_pmu_pll_clks), -1); + + rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches, + ARRAY_SIZE(rk3399_clk_pmu_branches)); + + rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks, + ARRAY_SIZE(rk3399_pmucru_critical_clocks)); + + rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); + + rockchip_clk_of_add_provider(np, ctx); +} + +struct clk_rk3399_inits { + void (*inits)(struct device_node *np); +}; + +static const struct clk_rk3399_inits clk_rk3399_pmucru_init = { + .inits = rk3399_pmu_clk_init, +}; + +static const struct clk_rk3399_inits clk_rk3399_cru_init = { + .inits = rk3399_clk_init, +}; + +static const struct of_device_id clk_rk3399_match_table[] = { + { + .compatible = "rockchip,rk3399-cru", + .data = &clk_rk3399_cru_init, + }, { + .compatible = "rockchip,rk3399-pmucru", + .data = &clk_rk3399_pmucru_init, + }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_rk3399_match_table); + +static int __init clk_rk3399_probe(struct device *dev) +{ + struct device_node *np = dev->of_node; + const struct of_device_id *match; + const struct clk_rk3399_inits *init_data; + + match = of_match_device(clk_rk3399_match_table, dev); + if (!match || !match->data) + return -EINVAL; + + init_data = match->data; + if (init_data->inits) + init_data->inits(np); + + return 0; +} + +static struct driver clk_rk3399_driver = { + .probe = clk_rk3399_probe, + .name = "clk-rk3399", + .of_compatible = DRV_OF_COMPAT(clk_rk3399_match_table), +}; + +core_platform_driver(clk_rk3399_driver); diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c new file mode 100644 index 0000000000..50fbf66d23 --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -0,0 +1,1751 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#include <common.h> +#include <linux/clk.h> +#include <of.h> +#include <of_address.h> +#include <linux/barebox-wrapper.h> +#include <init.h> +#include <linux/spinlock.h> +#include <of_device.h> +#include <dt-bindings/clock/rk3568-cru.h> +#include "clk.h" + +#define RK3568_GRF_SOC_STATUS0 0x580 + +enum rk3568_pmu_plls { + ppll, hpll, +}; + +enum rk3568_plls { + apll, dpll, gpll, cpll, npll, vpll, +}; + +static struct rockchip_pll_rate_table rk3568_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), + RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), + RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), + RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), + RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), + RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), + RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), + RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), + RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), + RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), + RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), + RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), + RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0), + RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0), + RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0), + RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0), + RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0), + RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0), + RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0), + RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0), + RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0), + RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0), + RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0), + RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0), + RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0), + RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), + RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), + RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0), + RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), + RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), + RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), + RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0), + RK3036_PLL_RATE(292500000, 1, 195, 4, 4, 1, 0), + RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0), + RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), + RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), + RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), + RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0), + RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), + RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0), + RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), + RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0), + RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), + RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), + RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0), + RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), + { /* sentinel */ }, +}; + +#define RK3568_DIV_ATCLK_CORE_MASK 0x1f +#define RK3568_DIV_ATCLK_CORE_SHIFT 0 +#define RK3568_DIV_GICCLK_CORE_MASK 0x1f +#define RK3568_DIV_GICCLK_CORE_SHIFT 8 +#define RK3568_DIV_PCLK_CORE_MASK 0x1f +#define RK3568_DIV_PCLK_CORE_SHIFT 0 +#define RK3568_DIV_PERIPHCLK_CORE_MASK 0x1f +#define RK3568_DIV_PERIPHCLK_CORE_SHIFT 8 +#define RK3568_DIV_ACLK_CORE_MASK 0x1f +#define RK3568_DIV_ACLK_CORE_SHIFT 8 + +#define RK3568_DIV_SCLK_CORE_MASK 0xf +#define RK3568_DIV_SCLK_CORE_SHIFT 0 +#define RK3568_MUX_SCLK_CORE_MASK 0x3 +#define RK3568_MUX_SCLK_CORE_SHIFT 8 +#define RK3568_MUX_SCLK_CORE_NPLL_MASK 0x1 +#define RK3568_MUX_SCLK_CORE_NPLL_SHIFT 15 +#define RK3568_MUX_CLK_CORE_APLL_MASK 0x1 +#define RK3568_MUX_CLK_CORE_APLL_SHIFT 7 +#define RK3568_MUX_CLK_PVTPLL_MASK 0x1 +#define RK3568_MUX_CLK_PVTPLL_SHIFT 15 + +#define RK3568_CLKSEL1(_sclk_core) \ +{ \ + .reg = RK3568_CLKSEL_CON(2), \ + .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \ + RK3568_MUX_SCLK_CORE_NPLL_SHIFT) | \ + HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \ + RK3568_MUX_SCLK_CORE_SHIFT) | \ + HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \ + RK3568_DIV_SCLK_CORE_SHIFT), \ +} + +#define RK3568_CLKSEL2(_aclk_core) \ +{ \ + .reg = RK3568_CLKSEL_CON(5), \ + .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \ + RK3568_DIV_ACLK_CORE_SHIFT), \ +} + +#define RK3568_CLKSEL3(_atclk_core, _gic_core) \ +{ \ + .reg = RK3568_CLKSEL_CON(3), \ + .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \ + RK3568_DIV_ATCLK_CORE_SHIFT) | \ + HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \ + RK3568_DIV_GICCLK_CORE_SHIFT), \ +} + +#define RK3568_CLKSEL4(_pclk_core, _periph_core) \ +{ \ + .reg = RK3568_CLKSEL_CON(4), \ + .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \ + RK3568_DIV_PCLK_CORE_SHIFT) | \ + HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \ + RK3568_DIV_PERIPHCLK_CORE_SHIFT), \ +} + +#define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \ +{ \ + .prate = _prate##U, \ + .divs = { \ + RK3568_CLKSEL1(_sclk), \ + RK3568_CLKSEL2(_acore), \ + RK3568_CLKSEL3(_atcore, _gicclk), \ + RK3568_CLKSEL4(_pclk, _periph), \ + }, \ +} + +static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = { + RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7), + RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7), + RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3), +}; + +static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = { + .core_reg[0] = RK3568_CLKSEL_CON(0), + .div_core_shift[0] = 0, + .div_core_mask[0] = 0x1f, + .core_reg[1] = RK3568_CLKSEL_CON(0), + .div_core_shift[1] = 8, + .div_core_mask[1] = 0x1f, + .core_reg[2] = RK3568_CLKSEL_CON(1), + .div_core_shift[2] = 0, + .div_core_mask[2] = 0x1f, + .core_reg[3] = RK3568_CLKSEL_CON(1), + .div_core_shift[3] = 8, + .div_core_mask[3] = 0x1f, + .num_cores = 4, + .mux_core_alt = 1, + .mux_core_main = 0, + .mux_core_shift = 6, + .mux_core_mask = 0x1, +}; + +PNAME(mux_pll_p) = { "xin24m" }; +PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" }; +PNAME(mux_armclk_p) = { "apll", "gpll" }; +PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half "}; +PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half" }; +PNAME(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" }; +PNAME(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" }; +PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; +PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; +PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; +PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; +PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; +PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; +PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; +PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; +PNAME(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; +PNAME(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" }; +PNAME(clk_rtc32k_pmu_p) = { "clk_32k_pvtm", "xin32k", "clk_rtc32k_frac" }; +PNAME(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" }; +PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" }; +PNAME(npll_gpll_p) = { "npll", "gpll" }; +PNAME(cpll_gpll_p) = { "cpll", "gpll" }; +PNAME(gpll_cpll_p) = { "gpll", "cpll" }; +PNAME(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" }; +PNAME(apll_gpll_npll_p) = { "apll", "gpll", "npll" }; +PNAME(sclk_core_pre_p) = { "sclk_core_src", "npll" }; +PNAME(gpll150_gpll100_gpll75_xin24m_p) = { "gpll_150m", "gpll_100m", "gpll_75m", "xin24m" }; +PNAME(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" }; +PNAME(clk_npu_pre_ndft_p) = { "clk_npu_src", "dummy"}; +PNAME(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" }; +PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" }; +PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" }; +PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" }; +PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" }; +PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" }; +PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" }; +PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" }; +PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" }; +PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" }; +PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" }; +PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" }; +PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" }; +PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" }; +PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" }; +PNAME(gpll300_gpll200_gpll100_p) = { "gpll_300m", "gpll_200m", "gpll_100m" }; +PNAME(clk_nandc_p) = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" }; +PNAME(sclk_sfc_p) = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", "gpll_150m" }; +PNAME(gpll200_gpll150_cpll125_p) = { "gpll_200m", "gpll_150m", "cpll_125m" }; +PNAME(cclk_emmc_p) = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", "cpll_50m", "clk_osc0_div_375k" }; +PNAME(aclk_pipe_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; +PNAME(gpll200_cpll125_p) = { "gpll_200m", "cpll_125m" }; +PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", "gpll_100m", "xin24m" }; +PNAME(clk_sdmmc_p) = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", "cpll_50m", "clk_osc0_div_750k" }; +PNAME(cpll125_cpll50_cpll25_xin24m_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "xin24m" }; +PNAME(clk_gmac_ptp_p) = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" }; +PNAME(cpll333_gpll300_gpll200_p) = { "cpll_333m", "gpll_300m", "gpll_200m" }; +PNAME(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" }; +PNAME(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" }; +PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", "gpll_100m", "xin24m" }; +PNAME(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" }; +PNAME(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" }; +PNAME(gpll400_cpll333_gpll200_p) = { "gpll_400m", "cpll_333m", "gpll_200m" }; +PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", "xin24m" }; +PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" }; +PNAME(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" }; +PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" }; +PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" }; +PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; +PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", "gpll_300m", "xin24m" }; +PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; +PNAME(xin24m_cpll100_p) = { "xin24m", "cpll_100m" }; +PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"}; +PNAME(clk_usbphy0_ref_p) = { "clk_ref24m", "xin_osc0_usbphy0_g" }; +PNAME(clk_usbphy1_ref_p) = { "clk_ref24m", "xin_osc0_usbphy1_g" }; +PNAME(clk_mipidsiphy0_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" }; +PNAME(clk_mipidsiphy1_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" }; +PNAME(clk_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" }; +PNAME(clk_pciephy0_ref_p) = { "clk_pciephy0_osc0", "clk_pciephy0_div" }; +PNAME(clk_pciephy1_ref_p) = { "clk_pciephy1_osc0", "clk_pciephy1_div" }; +PNAME(clk_pciephy2_ref_p) = { "clk_pciephy2_osc0", "clk_pciephy2_div" }; +PNAME(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" }; +PNAME(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" }; +PNAME(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" }; +PNAME(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", "clk_gmac0_xpcs_mii" }; +PNAME(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" }; +PNAME(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" }; +PNAME(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" }; +PNAME(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii" }; +PNAME(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" }; +PNAME(clk_pdpmu_p) = { "ppll", "gpll" }; +PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" }; +PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" }; +PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" }; +PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "dummy_npll", "dummy_vpll" }; + +static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = { + [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p, + 0, RK3568_PMU_PLL_CON(0), + RK3568_PMU_MODE_CON0, 0, 4, 0, rk3568_pll_rates), + [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p, + 0, RK3568_PMU_PLL_CON(16), + RK3568_PMU_MODE_CON0, 2, 7, 0, rk3568_pll_rates), +}; + +static struct rockchip_pll_clock rk3568_pll_clks[] __initdata = { + [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, + 0, RK3568_PLL_CON(0), + RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates), + [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, + 0, RK3568_PLL_CON(8), + RK3568_MODE_CON0, 2, 1, 0, NULL), + [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, + 0, RK3568_PLL_CON(24), + RK3568_MODE_CON0, 4, 2, 0, rk3568_pll_rates), + [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, + 0, RK3568_PLL_CON(16), + RK3568_MODE_CON0, 6, 3, 0, rk3568_pll_rates), + [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, + 0, RK3568_PLL_CON(32), + RK3568_MODE_CON0, 10, 5, 0, rk3568_pll_rates), + [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p, + 0, RK3568_PLL_CON(40), + RK3568_MODE_CON0, 12, 6, 0, rk3568_pll_rates), +}; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata = + MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(11), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata = + MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(13), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata = + MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(15), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata = + MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(17), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_i2s2_2ch_fracmux __initdata = + MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(19), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata = + MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(21), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata = + MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(83), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_spdif_8ch_fracmux __initdata = + MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(23), 15, 1, MFLAGS); + +static struct rockchip_clk_branch rk3568_audpwm_fracmux __initdata = + MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(25), 15, 1, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart1_fracmux __initdata = + MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(52), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart2_fracmux __initdata = + MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(54), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart3_fracmux __initdata = + MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(56), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart4_fracmux __initdata = + MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(58), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart5_fracmux __initdata = + MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(60), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart6_fracmux __initdata = + MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(62), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart7_fracmux __initdata = + MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(64), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart8_fracmux __initdata = + MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(66), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart9_fracmux __initdata = + MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(68), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart0_fracmux __initdata = + MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT, + RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_rtc32k_pmu_fracmux __initdata = + MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { + /* + * Clock-Architecture Diagram 1 + */ + /* SRC_CLK */ + COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(75), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 0, GFLAGS), + COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(75), 8, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 1, GFLAGS), + COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(76), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 2, GFLAGS), + COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(76), 8, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 3, GFLAGS), + COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(77), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 4, GFLAGS), + COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(77), 8, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 5, GFLAGS), + COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(78), 0, 6, DFLAGS, + RK3568_CLKGATE_CON(35), 6, GFLAGS), + COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(78), 8, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 7, GFLAGS), + COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(79), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 8, GFLAGS), + COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(79), 8, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 9, GFLAGS), + COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(80), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 10, GFLAGS), + COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 11, GFLAGS), + COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(80), 8, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 12, GFLAGS), + COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(81), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 13, GFLAGS), + COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(81), 8, 6, DFLAGS, + RK3568_CLKGATE_CON(35), 14, GFLAGS), + COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(82), 8, 6, DFLAGS, + RK3568_CLKGATE_CON(35), 15, GFLAGS), + FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 0, 1, 2), + FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2), + MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, + RK3568_MODE_CON0, 14, 2, MFLAGS), + + /* PD_CORE */ + COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(2), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(0), 7, GFLAGS), + + COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(0), 9, GFLAGS), + COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(4), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(0), 10, GFLAGS), + COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(4), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(0), 11, GFLAGS), + COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(5), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(0), 14, GFLAGS), + COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(5), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(5), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(1), 0, GFLAGS), + + COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(5), 14, 2, MFLAGS, + RK3568_CLKGATE_CON(1), 2, GFLAGS), + + GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0, + RK3568_CLKGATE_CON(1), 10, GFLAGS), + GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0, + RK3568_CLKGATE_CON(1), 11, GFLAGS), + GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(1), 12, GFLAGS), + GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0, + RK3568_CLKGATE_CON(1), 9, GFLAGS), + + /* PD_GPU */ + COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(2), 0, GFLAGS), + MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY), + DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0, + RK3568_CLKSEL_CON(6), 8, 2, DFLAGS), + DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0, + RK3568_CLKSEL_CON(6), 12, 4, DFLAGS), + GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0, + RK3568_CLKGATE_CON(2), 3, GFLAGS), + + GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0, + RK3568_CLKGATE_CON(2), 6, GFLAGS), + GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, + RK3568_CLKGATE_CON(2), 7, GFLAGS), + GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0, + RK3568_CLKGATE_CON(2), 8, GFLAGS), + GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(2), 9, GFLAGS), + + /* PD_NPU */ + COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0, + RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS, + RK3568_CLKGATE_CON(3), 0, GFLAGS), + MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + RK3568_CLKSEL_CON(7), 8, 1, MFLAGS), + MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(7), 15, 1, MFLAGS), + COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 0, + RK3568_CLKSEL_CON(8), 0, 4, DFLAGS, + RK3568_CLKGATE_CON(3), 2, GFLAGS), + COMPOSITE_NOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 0, + RK3568_CLKSEL_CON(8), 4, 4, DFLAGS, + RK3568_CLKGATE_CON(3), 3, GFLAGS), + GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0, + RK3568_CLKGATE_CON(3), 4, GFLAGS), + GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0, + RK3568_CLKGATE_CON(3), 7, GFLAGS), + GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0, + RK3568_CLKGATE_CON(3), 8, GFLAGS), + + GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0, + RK3568_CLKGATE_CON(3), 9, GFLAGS), + GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, + RK3568_CLKGATE_CON(3), 10, GFLAGS), + GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0, + RK3568_CLKGATE_CON(3), 11, GFLAGS), + GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(3), 12, GFLAGS), + + /* PD_DDR */ + COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(4), 0, GFLAGS), + MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(9), 15, 1, MFLAGS), + + COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(10), 0, 2, DFLAGS, + RK3568_CLKGATE_CON(4), 2, GFLAGS), + GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(4), 15, GFLAGS), + + /* PD_GIC_AUDIO */ + COMPOSITE_NODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", gpll200_gpll150_gpll100_xin24m_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(10), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(5), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(10), 10, 2, MFLAGS, + RK3568_CLKGATE_CON(5), 1, GFLAGS), + GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(5), 8, GFLAGS), + COMPOSITE_NODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", gpll100_gpll75_gpll50_p, 0, + RK3568_CLKSEL_CON(10), 12, 2, MFLAGS, + RK3568_CLKGATE_CON(5), 9, GFLAGS), + GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(5), 4, GFLAGS), + GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(5), 7, GFLAGS), + GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(5), 10, GFLAGS), + GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(5), 11, GFLAGS), + GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(5), 12, GFLAGS), + GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(5), 13, GFLAGS), + + COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(6), 0, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(12), 0, + RK3568_CLKGATE_CON(6), 1, GFLAGS, + &rk3568_i2s0_8ch_tx_fracmux), + GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, + RK3568_CLKGATE_CON(6), 2, GFLAGS), + COMPOSITE_NODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(11), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(6), 3, GFLAGS), + + COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(13), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(6), 4, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(14), 0, + RK3568_CLKGATE_CON(6), 5, GFLAGS, + &rk3568_i2s0_8ch_rx_fracmux), + GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, + RK3568_CLKGATE_CON(6), 6, GFLAGS), + COMPOSITE_NODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(13), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(6), 7, GFLAGS), + + COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(15), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(6), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(16), 0, + RK3568_CLKGATE_CON(6), 9, GFLAGS, + &rk3568_i2s1_8ch_tx_fracmux), + GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, + RK3568_CLKGATE_CON(6), 10, GFLAGS), + COMPOSITE_NODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(15), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(6), 11, GFLAGS), + + COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(6), 12, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(18), 0, + RK3568_CLKGATE_CON(6), 13, GFLAGS, + &rk3568_i2s1_8ch_rx_fracmux), + GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, + RK3568_CLKGATE_CON(6), 14, GFLAGS), + COMPOSITE_NODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(17), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(6), 15, GFLAGS), + + COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(7), 0, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(20), 0, + RK3568_CLKGATE_CON(7), 1, GFLAGS, + &rk3568_i2s2_2ch_fracmux), + GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, + RK3568_CLKGATE_CON(7), 2, GFLAGS), + COMPOSITE_NODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(19), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(7), 3, GFLAGS), + + COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(7), 4, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(22), 0, + RK3568_CLKGATE_CON(7), 5, GFLAGS, + &rk3568_i2s3_2ch_tx_fracmux), + GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0, + RK3568_CLKGATE_CON(7), 6, GFLAGS), + COMPOSITE_NODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(21), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(7), 7, GFLAGS), + + COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(83), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(7), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(84), 0, + RK3568_CLKGATE_CON(7), 9, GFLAGS, + &rk3568_i2s3_2ch_rx_fracmux), + GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0, + RK3568_CLKGATE_CON(7), 10, GFLAGS), + COMPOSITE_NODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(83), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(7), 11, GFLAGS), + + GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(5), 14, GFLAGS), + COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0, + RK3568_CLKSEL_CON(23), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(5), 15, GFLAGS), + GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(7), 12, GFLAGS), + GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(7), 13, GFLAGS), + + COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 0, + RK3568_CLKSEL_CON(23), 14, 1, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(7), 14, GFLAGS), + COMPOSITE_FRACMUX(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(24), 0, + RK3568_CLKGATE_CON(7), 15, GFLAGS, + &rk3568_spdif_8ch_fracmux), + + GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(8), 0, GFLAGS), + COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0, + RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS, + RK3568_CLKGATE_CON(8), 1, GFLAGS), + COMPOSITE_FRACMUX(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(26), 0, + RK3568_CLKGATE_CON(8), 2, GFLAGS, + &rk3568_audpwm_fracmux), + + GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(8), 3, GFLAGS), + COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0, + RK3568_CLKSEL_CON(23), 10, 2, MFLAGS, + RK3568_CLKGATE_CON(8), 4, GFLAGS), + GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0, + RK3568_CLKGATE_CON(8), 5, GFLAGS), + GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0, + RK3568_CLKGATE_CON(8), 6, GFLAGS), + + /* PD_SECURE_FLASH */ + COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, 0, + RK3568_CLKSEL_CON(27), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(8), 7, GFLAGS), + COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, 0, + RK3568_CLKSEL_CON(27), 2, 2, MFLAGS, + RK3568_CLKGATE_CON(8), 8, GFLAGS), + GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0, + RK3568_CLKGATE_CON(8), 11, GFLAGS), + GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0, + RK3568_CLKGATE_CON(8), 12, GFLAGS), + COMPOSITE_NODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", gpll200_gpll150_gpll100_p, 0, + RK3568_CLKSEL_CON(27), 4, 2, MFLAGS, + RK3568_CLKGATE_CON(8), 13, GFLAGS), + COMPOSITE_NODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", gpll300_gpll200_gpll100_p, 0, + RK3568_CLKSEL_CON(27), 6, 2, MFLAGS, + RK3568_CLKGATE_CON(8), 14, GFLAGS), + GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0, + RK3568_CLKGATE_CON(8), 15, GFLAGS), + GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(9), 10, GFLAGS), + GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(9), 11, GFLAGS), + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0, + RK3568_CLKGATE_CON(26), 9, GFLAGS), + GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0, + RK3568_CLKGATE_CON(26), 10, GFLAGS), + GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0, + RK3568_CLKGATE_CON(26), 11, GFLAGS), + GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0, + RK3568_CLKGATE_CON(9), 0, GFLAGS), + COMPOSITE_NODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 0, + RK3568_CLKSEL_CON(28), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(9), 1, GFLAGS), + GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0, + RK3568_CLKGATE_CON(9), 2, GFLAGS), + GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0, + RK3568_CLKGATE_CON(9), 3, GFLAGS), + COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0, + RK3568_CLKSEL_CON(28), 4, 3, MFLAGS, + RK3568_CLKGATE_CON(9), 4, GFLAGS), + GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0, + RK3568_CLKGATE_CON(9), 5, GFLAGS), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0, + RK3568_CLKGATE_CON(9), 6, GFLAGS), + COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 0, + RK3568_CLKSEL_CON(28), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(9), 7, GFLAGS), + COMPOSITE_NODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 0, + RK3568_CLKSEL_CON(28), 12, 3, MFLAGS, + RK3568_CLKGATE_CON(9), 8, GFLAGS), + GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, + RK3568_CLKGATE_CON(9), 9, GFLAGS), + MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_emmc", RK3568_EMMC_CON0, 1), + MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_emmc", RK3568_EMMC_CON1, 1), + + /* PD_PIPE */ + COMPOSITE_NODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 0, + RK3568_CLKSEL_CON(29), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(10), 0, GFLAGS), + COMPOSITE_NOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 0, + RK3568_CLKSEL_CON(29), 4, 4, DFLAGS, + RK3568_CLKGATE_CON(10), 1, GFLAGS), + GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0, + RK3568_CLKGATE_CON(12), 0, GFLAGS), + GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0, + RK3568_CLKGATE_CON(12), 1, GFLAGS), + GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0, + RK3568_CLKGATE_CON(12), 2, GFLAGS), + GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0, + RK3568_CLKGATE_CON(12), 3, GFLAGS), + GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0, + RK3568_CLKGATE_CON(12), 4, GFLAGS), + GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0, + RK3568_CLKGATE_CON(12), 8, GFLAGS), + GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0, + RK3568_CLKGATE_CON(12), 9, GFLAGS), + GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0, + RK3568_CLKGATE_CON(12), 10, GFLAGS), + GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0, + RK3568_CLKGATE_CON(12), 11, GFLAGS), + GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0, + RK3568_CLKGATE_CON(12), 12, GFLAGS), + GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0, + RK3568_CLKGATE_CON(13), 0, GFLAGS), + GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0, + RK3568_CLKGATE_CON(13), 1, GFLAGS), + GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0, + RK3568_CLKGATE_CON(13), 2, GFLAGS), + GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0, + RK3568_CLKGATE_CON(13), 3, GFLAGS), + GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0, + RK3568_CLKGATE_CON(13), 4, GFLAGS), + GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0, + RK3568_CLKGATE_CON(11), 0, GFLAGS), + GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0, + RK3568_CLKGATE_CON(11), 1, GFLAGS), + GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0, + RK3568_CLKGATE_CON(11), 2, GFLAGS), + GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0, + RK3568_CLKGATE_CON(11), 4, GFLAGS), + GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0, + RK3568_CLKGATE_CON(11), 5, GFLAGS), + GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0, + RK3568_CLKGATE_CON(11), 6, GFLAGS), + GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0, + RK3568_CLKGATE_CON(11), 8, GFLAGS), + GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0, + RK3568_CLKGATE_CON(11), 9, GFLAGS), + GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0, + RK3568_CLKGATE_CON(11), 10, GFLAGS), + GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0, + RK3568_CLKGATE_CON(10), 8, GFLAGS), + GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0, + RK3568_CLKGATE_CON(10), 9, GFLAGS), + COMPOSITE_NODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 0, + RK3568_CLKSEL_CON(29), 8, 1, MFLAGS, + RK3568_CLKGATE_CON(10), 10, GFLAGS), + GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0, + RK3568_CLKGATE_CON(10), 12, GFLAGS), + GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0, + RK3568_CLKGATE_CON(10), 13, GFLAGS), + COMPOSITE_NODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 0, + RK3568_CLKSEL_CON(29), 9, 1, MFLAGS, + RK3568_CLKGATE_CON(10), 14, GFLAGS), + COMPOSITE_NODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 0, + RK3568_CLKSEL_CON(29), 13, 1, MFLAGS, + RK3568_CLKGATE_CON(10), 4, GFLAGS), + GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0, + RK3568_CLKGATE_CON(13), 6, GFLAGS), + + /* PD_PHP */ + COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0, + RK3568_CLKSEL_CON(30), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(14), 8, GFLAGS), + COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 0, + RK3568_CLKSEL_CON(30), 2, 2, MFLAGS, + RK3568_CLKGATE_CON(14), 9, GFLAGS), + COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0, + RK3568_CLKSEL_CON(30), 4, 4, DFLAGS, + RK3568_CLKGATE_CON(14), 10, GFLAGS), + GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0, + RK3568_CLKGATE_CON(15), 0, GFLAGS), + COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0, + RK3568_CLKSEL_CON(30), 8, 3, MFLAGS, + RK3568_CLKGATE_CON(15), 1, GFLAGS), + MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "clk_sdmmc0", RK3568_SDMMC0_CON0, 1), + MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "clk_sdmmc0", RK3568_SDMMC0_CON1, 1), + + GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0, + RK3568_CLKGATE_CON(15), 2, GFLAGS), + COMPOSITE_NODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 0, + RK3568_CLKSEL_CON(30), 12, 3, MFLAGS, + RK3568_CLKGATE_CON(15), 3, GFLAGS), + MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "clk_sdmmc1", RK3568_SDMMC1_CON0, 1), + MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "clk_sdmmc1", RK3568_SDMMC1_CON1, 1), + + GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 0, + RK3568_CLKGATE_CON(15), 5, GFLAGS), + GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 0, + RK3568_CLKGATE_CON(15), 6, GFLAGS), + COMPOSITE_NODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 0, + RK3568_CLKSEL_CON(31), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(15), 7, GFLAGS), + COMPOSITE_NODIV(CLK_MAC0_OUT, "clk_mac0_out", cpll125_cpll50_cpll25_xin24m_p, 0, + RK3568_CLKSEL_CON(31), 14, 2, MFLAGS, + RK3568_CLKGATE_CON(15), 8, GFLAGS), + GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0, + RK3568_CLKGATE_CON(15), 12, GFLAGS), + COMPOSITE_NODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 0, + RK3568_CLKSEL_CON(31), 12, 2, MFLAGS, + RK3568_CLKGATE_CON(15), 4, GFLAGS), + MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3568_CLKSEL_CON(31), 2, 1, MFLAGS), + FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 0, 1, 5), + FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 0, 1, 50), + FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 0, 1, 2), + FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 0, 1, 20), + MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", mux_gmac0_rgmii_speed_p, 0, + RK3568_CLKSEL_CON(31), 4, 2, MFLAGS), + MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", mux_gmac0_rmii_speed_p, 0, + RK3568_CLKSEL_CON(31), 3, 1, MFLAGS), + MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(31), 0, 2, MFLAGS), + + /* PD_USB */ + COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0, + RK3568_CLKSEL_CON(32), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(16), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 0, + RK3568_CLKSEL_CON(32), 2, 2, MFLAGS, + RK3568_CLKGATE_CON(16), 1, GFLAGS), + COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 0, + RK3568_CLKSEL_CON(32), 4, 4, DFLAGS, + RK3568_CLKGATE_CON(16), 2, GFLAGS), + GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0, + RK3568_CLKGATE_CON(16), 12, GFLAGS), + GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0, + RK3568_CLKGATE_CON(16), 13, GFLAGS), + GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0, + RK3568_CLKGATE_CON(16), 14, GFLAGS), + GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0, + RK3568_CLKGATE_CON(16), 15, GFLAGS), + GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0, + RK3568_CLKGATE_CON(17), 0, GFLAGS), + COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0, + RK3568_CLKSEL_CON(32), 8, 3, MFLAGS, + RK3568_CLKGATE_CON(17), 1, GFLAGS), + MMC(SCLK_SDMMC2_DRV, "sdmmc2_drv", "clk_sdmmc2", RK3568_SDMMC2_CON0, 1), + MMC(SCLK_SDMMC2_SAMPLE, "sdmmc2_sample", "clk_sdmmc2", RK3568_SDMMC2_CON1, 1), + + GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0, + RK3568_CLKGATE_CON(17), 3, GFLAGS), + GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0, + RK3568_CLKGATE_CON(17), 4, GFLAGS), + COMPOSITE_NODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 0, + RK3568_CLKSEL_CON(33), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(17), 5, GFLAGS), + COMPOSITE_NODIV(CLK_MAC1_OUT, "clk_mac1_out", cpll125_cpll50_cpll25_xin24m_p, 0, + RK3568_CLKSEL_CON(33), 14, 2, MFLAGS, + RK3568_CLKGATE_CON(17), 6, GFLAGS), + GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0, + RK3568_CLKGATE_CON(17), 10, GFLAGS), + COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 0, + RK3568_CLKSEL_CON(33), 12, 2, MFLAGS, + RK3568_CLKGATE_CON(17), 2, GFLAGS), + MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3568_CLKSEL_CON(33), 2, 1, MFLAGS), + FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 0, 1, 5), + FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 0, 1, 50), + FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 0, 1, 2), + FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 0, 1, 20), + MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", mux_gmac1_rgmii_speed_p, 0, + RK3568_CLKSEL_CON(33), 4, 2, MFLAGS), + MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0, + RK3568_CLKSEL_CON(33), 3, 1, MFLAGS), + MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(33), 0, 2, MFLAGS), + + /* PD_PERI */ + COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(10), 4, 2, MFLAGS, + RK3568_CLKGATE_CON(14), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(10), 6, 2, MFLAGS, + RK3568_CLKGATE_CON(14), 1, GFLAGS), + + /* PD_VI */ + COMPOSITE_NODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 0, + RK3568_CLKSEL_CON(34), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(18), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 0, + RK3568_CLKSEL_CON(34), 4, 4, DFLAGS, + RK3568_CLKGATE_CON(18), 1, GFLAGS), + COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 0, + RK3568_CLKSEL_CON(34), 8, 4, DFLAGS, + RK3568_CLKGATE_CON(18), 2, GFLAGS), + GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0, + RK3568_CLKGATE_CON(18), 9, GFLAGS), + GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0, + RK3568_CLKGATE_CON(18), 10, GFLAGS), + COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 0, + RK3568_CLKSEL_CON(34), 14, 2, MFLAGS, + RK3568_CLKGATE_CON(18), 11, GFLAGS), + GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0, + RK3568_CLKGATE_CON(18), 13, GFLAGS), + GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0, + RK3568_CLKGATE_CON(19), 0, GFLAGS), + GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0, + RK3568_CLKGATE_CON(19), 1, GFLAGS), + COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0, + RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(19), 2, GFLAGS), + GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0, + RK3568_CLKGATE_CON(19), 4, GFLAGS), + COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0, + RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3568_CLKGATE_CON(19), 8, GFLAGS), + COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0, + RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3568_CLKGATE_CON(19), 9, GFLAGS), + COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 0, + RK3568_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3568_CLKGATE_CON(19), 10, GFLAGS), + + /* PD_VO */ + COMPOSITE_NODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 0, + RK3568_CLKSEL_CON(37), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(20), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 0, + RK3568_CLKSEL_CON(37), 8, 4, DFLAGS, + RK3568_CLKGATE_CON(20), 1, GFLAGS), + COMPOSITE_NOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 0, + RK3568_CLKSEL_CON(37), 12, 4, DFLAGS, + RK3568_CLKGATE_CON(20), 2, GFLAGS), + COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0, + RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(20), 6, GFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, + RK3568_CLKGATE_CON(20), 8, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0, + RK3568_CLKGATE_CON(20), 9, GFLAGS), + COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, + RK3568_CLKGATE_CON(20), 10, GFLAGS), + COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, + RK3568_CLKGATE_CON(20), 11, GFLAGS), + COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0, + RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS, + RK3568_CLKGATE_CON(20), 12, GFLAGS), + GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0, + RK3568_CLKGATE_CON(20), 13, GFLAGS), + GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0, + RK3568_CLKGATE_CON(21), 0, GFLAGS), + GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0, + RK3568_CLKGATE_CON(21), 1, GFLAGS), + GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0, + RK3568_CLKGATE_CON(21), 2, GFLAGS), + GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0, + RK3568_CLKGATE_CON(21), 3, GFLAGS), + GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0, + RK3568_CLKGATE_CON(21), 4, GFLAGS), + GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0, + RK3568_CLKGATE_CON(21), 5, GFLAGS), + GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0, + RK3568_CLKGATE_CON(21), 6, GFLAGS), + GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0, + RK3568_CLKGATE_CON(21), 7, GFLAGS), + GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0, + RK3568_CLKGATE_CON(21), 8, GFLAGS), + COMPOSITE_NODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 0, + RK3568_CLKSEL_CON(38), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(21), 9, GFLAGS), + + /* PD_VPU */ + COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0, + RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(22), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, + RK3568_CLKSEL_CON(42), 8, 4, DFLAGS, + RK3568_CLKGATE_CON(22), 1, GFLAGS), + GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, + RK3568_CLKGATE_CON(22), 4, GFLAGS), + GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, + RK3568_CLKGATE_CON(22), 5, GFLAGS), + + /* PD_RGA */ + COMPOSITE_NODIV(ACLK_RGA_PRE, "aclk_rga_pre", gpll300_cpll250_gpll100_xin24m_p, 0, + RK3568_CLKSEL_CON(43), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(23), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 0, + RK3568_CLKSEL_CON(43), 8, 4, DFLAGS, + RK3568_CLKGATE_CON(23), 1, GFLAGS), + COMPOSITE_NOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 0, + RK3568_CLKSEL_CON(43), 12, 4, DFLAGS, + RK3568_CLKGATE_CON(22), 12, GFLAGS), + GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 4, GFLAGS), + GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 5, GFLAGS), + COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0, + RK3568_CLKSEL_CON(43), 2, 2, MFLAGS, + RK3568_CLKGATE_CON(23), 6, GFLAGS), + GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 7, GFLAGS), + GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 8, GFLAGS), + COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0, + RK3568_CLKSEL_CON(43), 4, 2, MFLAGS, + RK3568_CLKGATE_CON(23), 9, GFLAGS), + GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS), + COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0, + RK3568_CLKSEL_CON(43), 6, 2, MFLAGS, + RK3568_CLKGATE_CON(23), 11, GFLAGS), + GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 12, GFLAGS), + GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 13, GFLAGS), + GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 14, GFLAGS), + GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 15, GFLAGS), + GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0, + RK3568_CLKGATE_CON(22), 14, GFLAGS), + GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0, + RK3568_CLKGATE_CON(22), 15, GFLAGS), + + /* PD_RKVENC */ + COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(24), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, + RK3568_CLKSEL_CON(44), 8, 4, DFLAGS, + RK3568_CLKGATE_CON(24), 1, GFLAGS), + GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0, + RK3568_CLKGATE_CON(24), 6, GFLAGS), + GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0, + RK3568_CLKGATE_CON(24), 7, GFLAGS), + COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0, + RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(24), 8, GFLAGS), + COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT, + RK3568_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(25), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, + RK3568_CLKSEL_CON(47), 8, 4, DFLAGS, + RK3568_CLKGATE_CON(25), 1, GFLAGS), + GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, + RK3568_CLKGATE_CON(25), 4, GFLAGS), + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, + RK3568_CLKGATE_CON(25), 5, GFLAGS), + COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0, + RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(25), 6, GFLAGS), + COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT, + RK3568_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3568_CLKGATE_CON(25), 7, GFLAGS), + COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0, + RK3568_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(25), 8, GFLAGS), + + /* PD_BUS */ + COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 0, + RK3568_CLKSEL_CON(50), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(26), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 0, + RK3568_CLKSEL_CON(50), 4, 2, MFLAGS, + RK3568_CLKGATE_CON(26), 1, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, + RK3568_CLKGATE_CON(26), 4, GFLAGS), + COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 0, + RK3568_CLKSEL_CON(51), 4, 2, MFLAGS, 0, 3, DFLAGS, + RK3568_CLKGATE_CON(26), 5, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0, + RK3568_CLKSEL_CON(51), 8, 7, DFLAGS, + RK3568_CLKGATE_CON(26), 6, GFLAGS), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, + RK3568_CLKGATE_CON(26), 7, GFLAGS), + GATE(CLK_SARADC, "clk_saradc", "xin24m", 0, + RK3568_CLKGATE_CON(26), 8, GFLAGS), + GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(26), 12, GFLAGS), + GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0, + RK3568_CLKGATE_CON(26), 13, GFLAGS), + GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0, + RK3568_CLKGATE_CON(26), 14, GFLAGS), + GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(32), 13, GFLAGS), + GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(32), 14, GFLAGS), + GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, + RK3568_CLKGATE_CON(32), 15, GFLAGS), + + GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, + RK3568_CLKGATE_CON(27), 12, GFLAGS), + COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(27), 13, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(53), 0, + RK3568_CLKGATE_CON(27), 14, GFLAGS, + &rk3568_uart1_fracmux), + GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0, + RK3568_CLKGATE_CON(27), 15, GFLAGS), + + GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, + RK3568_CLKGATE_CON(28), 0, GFLAGS), + COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(28), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(55), 0, + RK3568_CLKGATE_CON(28), 2, GFLAGS, + &rk3568_uart2_fracmux), + GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0, + RK3568_CLKGATE_CON(28), 3, GFLAGS), + + GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, + RK3568_CLKGATE_CON(28), 4, GFLAGS), + COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(28), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(57), 0, + RK3568_CLKGATE_CON(28), 6, GFLAGS, + &rk3568_uart3_fracmux), + GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0, + RK3568_CLKGATE_CON(28), 7, GFLAGS), + + GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0, + RK3568_CLKGATE_CON(28), 8, GFLAGS), + COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(28), 9, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(59), 0, + RK3568_CLKGATE_CON(28), 10, GFLAGS, + &rk3568_uart4_fracmux), + GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0, + RK3568_CLKGATE_CON(28), 11, GFLAGS), + + GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0, + RK3568_CLKGATE_CON(28), 12, GFLAGS), + COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(28), 13, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(61), 0, + RK3568_CLKGATE_CON(28), 14, GFLAGS, + &rk3568_uart5_fracmux), + GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0, + RK3568_CLKGATE_CON(28), 15, GFLAGS), + + GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0, + RK3568_CLKGATE_CON(29), 0, GFLAGS), + COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(29), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(63), 0, + RK3568_CLKGATE_CON(29), 2, GFLAGS, + &rk3568_uart6_fracmux), + GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0, + RK3568_CLKGATE_CON(29), 3, GFLAGS), + + GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0, + RK3568_CLKGATE_CON(29), 4, GFLAGS), + COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(29), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(65), 0, + RK3568_CLKGATE_CON(29), 6, GFLAGS, + &rk3568_uart7_fracmux), + GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0, + RK3568_CLKGATE_CON(29), 7, GFLAGS), + + GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0, + RK3568_CLKGATE_CON(29), 8, GFLAGS), + COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(29), 9, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(67), 0, + RK3568_CLKGATE_CON(29), 10, GFLAGS, + &rk3568_uart8_fracmux), + GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0, + RK3568_CLKGATE_CON(29), 11, GFLAGS), + + GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0, + RK3568_CLKGATE_CON(29), 12, GFLAGS), + COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(29), 13, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(69), 0, + RK3568_CLKGATE_CON(29), 14, GFLAGS, + &rk3568_uart9_fracmux), + GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0, + RK3568_CLKGATE_CON(29), 15, GFLAGS), + + GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0, + RK3568_CLKGATE_CON(27), 5, GFLAGS), + COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, + RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(27), 6, GFLAGS), + GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0, + RK3568_CLKGATE_CON(27), 7, GFLAGS), + COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, + RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS, + RK3568_CLKGATE_CON(27), 8, GFLAGS), + GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0, + RK3568_CLKGATE_CON(27), 9, GFLAGS), + COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, + RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(27), 10, GFLAGS), + COMPOSITE_NODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 0, + RK3568_CLKSEL_CON(71), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(32), 10, GFLAGS), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 0, GFLAGS), + GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0, + RK3568_CLKGATE_CON(30), 1, GFLAGS), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 2, GFLAGS), + GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0, + RK3568_CLKGATE_CON(30), 3, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 4, GFLAGS), + GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0, + RK3568_CLKGATE_CON(30), 5, GFLAGS), + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 6, GFLAGS), + GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0, + RK3568_CLKGATE_CON(30), 7, GFLAGS), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 8, GFLAGS), + GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0, + RK3568_CLKGATE_CON(30), 9, GFLAGS), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 10, GFLAGS), + COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(72), 0, 1, MFLAGS, + RK3568_CLKGATE_CON(30), 11, GFLAGS), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 12, GFLAGS), + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(72), 2, 1, MFLAGS, + RK3568_CLKGATE_CON(30), 13, GFLAGS), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 14, GFLAGS), + COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(72), 4, 1, MFLAGS, + RK3568_CLKGATE_CON(30), 15, GFLAGS), + GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0, + RK3568_CLKGATE_CON(31), 0, GFLAGS), + COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS), + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS), + COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(72), 8, 1, MFLAGS, + RK3568_CLKGATE_CON(31), 11, GFLAGS), + GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, + RK3568_CLKGATE_CON(31), 12, GFLAGS), + GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0, + RK3568_CLKGATE_CON(31), 13, GFLAGS), + COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(72), 10, 1, MFLAGS, + RK3568_CLKGATE_CON(31), 14, GFLAGS), + GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, + RK3568_CLKGATE_CON(31), 15, GFLAGS), + GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0, + RK3568_CLKGATE_CON(32), 0, GFLAGS), + COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(72), 12, 1, MFLAGS, + RK3568_CLKGATE_CON(32), 1, GFLAGS), + GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, + RK3568_CLKGATE_CON(32), 2, GFLAGS), + COMPOSITE_NODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 0, + RK3568_CLKSEL_CON(72), 14, 1, MFLAGS, + RK3568_CLKGATE_CON(32), 11, GFLAGS), + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, + RK3568_CLKGATE_CON(31), 2, GFLAGS), + GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0, + RK3568_CLKGATE_CON(31), 3, GFLAGS), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, + RK3568_CLKGATE_CON(31), 4, GFLAGS), + GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0, + RK3568_CLKGATE_CON(31), 5, GFLAGS), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, + RK3568_CLKGATE_CON(31), 6, GFLAGS), + GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0, + RK3568_CLKGATE_CON(31), 7, GFLAGS), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0, + RK3568_CLKGATE_CON(31), 8, GFLAGS), + GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0, + RK3568_CLKGATE_CON(31), 9, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, + RK3568_CLKGATE_CON(32), 3, GFLAGS), + GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0, + RK3568_CLKGATE_CON(32), 4, GFLAGS), + GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0, + RK3568_CLKGATE_CON(32), 5, GFLAGS), + GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0, + RK3568_CLKGATE_CON(32), 6, GFLAGS), + GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0, + RK3568_CLKGATE_CON(32), 7, GFLAGS), + GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0, + RK3568_CLKGATE_CON(32), 8, GFLAGS), + GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0, + RK3568_CLKGATE_CON(32), 9, GFLAGS), + + /* PD_TOP */ + COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, 0, + RK3568_CLKSEL_CON(73), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(33), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, 0, + RK3568_CLKSEL_CON(73), 4, 2, MFLAGS, + RK3568_CLKGATE_CON(33), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 0, + RK3568_CLKSEL_CON(73), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(33), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 0, + RK3568_CLKSEL_CON(73), 12, 2, MFLAGS, + RK3568_CLKGATE_CON(33), 3, GFLAGS), + GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0, + RK3568_CLKGATE_CON(33), 8, GFLAGS), + COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(73), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(33), 9, GFLAGS), + GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0, + RK3568_CLKGATE_CON(33), 13, GFLAGS), + GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0, + RK3568_CLKGATE_CON(33), 14, GFLAGS), + GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0, + RK3568_CLKGATE_CON(33), 15, GFLAGS), + GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0, + RK3568_CLKGATE_CON(34), 4, GFLAGS), + GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0, + RK3568_CLKGATE_CON(34), 5, GFLAGS), + GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0, + RK3568_CLKGATE_CON(34), 6, GFLAGS), + GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0, + RK3568_CLKGATE_CON(34), 11, GFLAGS), + GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0, + RK3568_CLKGATE_CON(34), 12, GFLAGS), + GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0, + RK3568_CLKGATE_CON(34), 13, GFLAGS), + GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0, + RK3568_CLKGATE_CON(34), 14, GFLAGS), +}; + +static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = { + /* PD_PMU */ + FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2), + FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2), + FACTOR(0, "hpll_ph0", "hpll", 0, 1, 2), + + MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0, + RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS), + COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", 0, + RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS, + RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS), + GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0, + RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS), + GATE(CLK_PMU, "clk_pmu", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0, + RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0, + RK3568_PMU_CLKSEL_CON(3), 0, 7, DFLAGS, + RK3568_PMU_CLKGATE_CON(1), 1, GFLAGS), + GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0, + RK3568_PMU_CLKGATE_CON(1), 2, GFLAGS), + + COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED, + RK3568_PMU_CLKSEL_CON(1), 0, + RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS, + &rk3568_rtc32k_pmu_fracmux), + + COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED, + RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS, + RK3568_PMU_CLKGATE_CON(0), 0, GFLAGS), + + COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0, + RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT, + RK3568_PMU_CLKSEL_CON(5), 0, + RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS, + &rk3568_uart0_fracmux), + GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0, + RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS), + + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0, + RK3568_PMU_CLKGATE_CON(1), 9, GFLAGS), + COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", xin24m_32k_p, 0, + RK3568_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, + RK3568_PMU_CLKGATE_CON(1), 10, GFLAGS), + GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0, + RK3568_PMU_CLKGATE_CON(1), 6, GFLAGS), + COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0, + RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3568_PMU_CLKGATE_CON(1), 7, GFLAGS), + GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(1), 8, GFLAGS), + GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0, + RK3568_PMU_CLKGATE_CON(1), 11, GFLAGS), + GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(1), 12, GFLAGS), + GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(1), 13, GFLAGS), + COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 0, + RK3568_PMU_CLKSEL_CON(7), 0, 6, DFLAGS, + RK3568_PMU_CLKGATE_CON(2), 0, GFLAGS), + GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 1, GFLAGS), + MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0, + RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS), + GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 2, GFLAGS), + MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0, + RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS), + GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 3, GFLAGS), + MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0, + RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS), + GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 4, GFLAGS), + MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0, + RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS), + COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "clk_pdpmu", 0, + RK3568_PMU_CLKSEL_CON(8), 8, 6, DFLAGS, + RK3568_PMU_CLKGATE_CON(2), 5, GFLAGS), + GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS), + MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT, + RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS), + COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0, + RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS, + RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS), + GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS), + MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT, + RK3568_PMU_CLKSEL_CON(9), 3, 1, MFLAGS), + COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0, + RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS, + RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS), + GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS), + MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT, + RK3568_PMU_CLKSEL_CON(9), 7, 1, MFLAGS), + COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0, + RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS, + RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS), + GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS), + MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT, + RK3568_PMU_CLKSEL_CON(9), 11, 1, MFLAGS), + GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0, + RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS), + GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0, + RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS), + GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS), + MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, + RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS), +}; + +static const char *const rk3568_cru_critical_clocks[] __initconst = { + "armclk", + "pclk_core_pre", + "aclk_bus", + "pclk_bus", + "aclk_top_high", + "aclk_top_low", + "hclk_top", + "pclk_top", + "aclk_perimid", + "hclk_perimid", + "aclk_secure_flash", + "hclk_secure_flash", + "aclk_core_niu2bus", + "npll", + "clk_optc_arb", + "hclk_php", + "pclk_php", + "hclk_usb", +}; + +static const char *const rk3568_pmucru_critical_clocks[] __initconst = { + "pclk_pdpmu", + "pclk_pmu", + "clk_pmu", +}; + +static void __init rk3568_pmu_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + void __iomem *reg_base; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru pmu region\n", __func__); + return; + } + + ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip pmu clk init failed\n", __func__); + return; + } + + rockchip_clk_register_plls(ctx, rk3568_pmu_pll_clks, + ARRAY_SIZE(rk3568_pmu_pll_clks), + RK3568_GRF_SOC_STATUS0); + + rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches, + ARRAY_SIZE(rk3568_clk_pmu_branches)); + + rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); + + rockchip_clk_protect_critical(rk3568_pmucru_critical_clocks, + ARRAY_SIZE(rk3568_pmucru_critical_clocks)); + + rockchip_clk_of_add_provider(np, ctx); + + clk_name_set_parent("ppll", "pll_ppll"); + clk_name_set_parent("clk_rtc_32k", "clk_rtc32k_frac"); + clk_name_set_rate("clk_rtc_32k", 32768); + clk_name_set_rate("pclk_pmu", 100000000); + clk_name_set_rate("pll_ppll", 200000000); +} + +static void __init rk3568_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + void __iomem *reg_base; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + return; + } + + rockchip_clk_register_plls(ctx, rk3568_pll_clks, + ARRAY_SIZE(rk3568_pll_clks), + RK3568_GRF_SOC_STATUS0); + + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", + mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + &rk3568_cpuclk_data, rk3568_cpuclk_rates, + ARRAY_SIZE(rk3568_cpuclk_rates)); + + rockchip_clk_register_branches(ctx, rk3568_clk_branches, + ARRAY_SIZE(rk3568_clk_branches)); + + rockchip_register_softrst(np, 30, reg_base + RK3568_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); + + rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST); + + rockchip_clk_protect_critical(rk3568_cru_critical_clocks, + ARRAY_SIZE(rk3568_cru_critical_clocks)); + + rockchip_clk_of_add_provider(np, ctx); + + clk_name_set_parent("npll", "pll_npll"); + clk_name_set_parent("vpll", "pll_vpll"); + clk_name_set_parent("pclk_bus", "gpll_100m"); + clk_name_set_parent("clk_sdmmc0", "cpll_50m"); + clk_name_set_parent("cclk_emmc", "gpll_200m"); + + clk_name_set_rate("pll_cpll", 1000000000); + clk_name_set_rate("pll_gpll", 1188000000); + clk_name_set_rate("armclk", 600000000); + clk_name_set_rate("aclk_bus", 150000000); + clk_name_set_rate("pclk_bus", 100000000); + clk_name_set_rate("aclk_top_high", 300000000); + clk_name_set_rate("aclk_top_low", 200000000); + clk_name_set_rate("hclk_top", 150000000); + clk_name_set_rate("pclk_top", 100000000); + clk_name_set_rate("aclk_perimid", 300000000); + clk_name_set_rate("hclk_perimid", 150000000); + clk_name_set_rate("pll_npll", 1200000000); + clk_name_set_rate("pll_apll", 816000000); + + clk_name_set_parent("pclk_top", "gpll_100m"); +} + +struct clk_rk3568_inits { + void (*inits)(struct device_node *np); +}; + +static const struct clk_rk3568_inits clk_rk3568_pmucru_init = { + .inits = rk3568_pmu_clk_init, +}; + +static const struct clk_rk3568_inits clk_3568_cru_init = { + .inits = rk3568_clk_init, +}; + +static const struct of_device_id clk_rk3568_match_table[] = { + { + .compatible = "rockchip,rk3568-cru", + .data = &clk_3568_cru_init, + }, { + .compatible = "rockchip,rk3568-pmucru", + .data = &clk_rk3568_pmucru_init, + }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_rk3568_match_table); + +static int __init clk_rk3568_probe(struct device *dev) +{ + struct device_node *np = dev->of_node; + const struct clk_rk3568_inits *init_data; + + init_data = of_device_get_match_data(dev); + if (init_data->inits) + init_data->inits(np); + + return 0; +} + +static struct driver clk_rk3568_driver = { + .probe = clk_rk3568_probe, + .name = "clk-rk3568", + .of_compatible = DRV_OF_COMPAT(clk_rk3568_match_table), +}; + +core_platform_driver(clk_rk3568_driver); diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c new file mode 100644 index 0000000000..68565a188c --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -0,0 +1,2533 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#include <common.h> +#include <linux/clk.h> +#include <of.h> +#include <of_address.h> +#include <linux/barebox-wrapper.h> +#include <init.h> +#include <linux/spinlock.h> +#include <of_device.h> +#include <dt-bindings/clock/rockchip,rk3588-cru.h> +#include "clk.h" + +/* + * GATE with additional linked clock. Downstream enables the linked clock + * (via runtime PM) whenever the gate is enabled. The downstream implementation + * does this via separate clock nodes for each of the linked gate clocks, + * which leaks parts of the clock tree into DT. It is unclear why this is + * actually needed and things work without it for simple use cases. Thus + * the linked clock is ignored for now. + */ +#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \ + GATE(_id, cname, pname, f, o, b, gf) + + +#define RK3588_GRF_SOC_STATUS0 0x600 +#define RK3588_PHYREF_ALT_GATE 0xc38 + +enum rk3588_plls { + b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, +}; + +static struct rockchip_pll_rate_table rk3588_pll_rates[] = { + /* _mhz, _p, _m, _s, _k */ + RK3588_PLL_RATE(2520000000, 2, 210, 0, 0), + RK3588_PLL_RATE(2496000000, 2, 208, 0, 0), + RK3588_PLL_RATE(2472000000, 2, 206, 0, 0), + RK3588_PLL_RATE(2448000000, 2, 204, 0, 0), + RK3588_PLL_RATE(2424000000, 2, 202, 0, 0), + RK3588_PLL_RATE(2400000000, 2, 200, 0, 0), + RK3588_PLL_RATE(2376000000, 2, 198, 0, 0), + RK3588_PLL_RATE(2352000000, 2, 196, 0, 0), + RK3588_PLL_RATE(2328000000, 2, 194, 0, 0), + RK3588_PLL_RATE(2304000000, 2, 192, 0, 0), + RK3588_PLL_RATE(2280000000, 2, 190, 0, 0), + RK3588_PLL_RATE(2256000000, 2, 376, 1, 0), + RK3588_PLL_RATE(2232000000, 2, 372, 1, 0), + RK3588_PLL_RATE(2208000000, 2, 368, 1, 0), + RK3588_PLL_RATE(2184000000, 2, 364, 1, 0), + RK3588_PLL_RATE(2160000000, 2, 360, 1, 0), + RK3588_PLL_RATE(2136000000, 2, 356, 1, 0), + RK3588_PLL_RATE(2112000000, 2, 352, 1, 0), + RK3588_PLL_RATE(2088000000, 2, 348, 1, 0), + RK3588_PLL_RATE(2064000000, 2, 344, 1, 0), + RK3588_PLL_RATE(2040000000, 2, 340, 1, 0), + RK3588_PLL_RATE(2016000000, 2, 336, 1, 0), + RK3588_PLL_RATE(1992000000, 2, 332, 1, 0), + RK3588_PLL_RATE(1968000000, 2, 328, 1, 0), + RK3588_PLL_RATE(1944000000, 2, 324, 1, 0), + RK3588_PLL_RATE(1920000000, 2, 320, 1, 0), + RK3588_PLL_RATE(1896000000, 2, 316, 1, 0), + RK3588_PLL_RATE(1872000000, 2, 312, 1, 0), + RK3588_PLL_RATE(1848000000, 2, 308, 1, 0), + RK3588_PLL_RATE(1824000000, 2, 304, 1, 0), + RK3588_PLL_RATE(1800000000, 2, 300, 1, 0), + RK3588_PLL_RATE(1776000000, 2, 296, 1, 0), + RK3588_PLL_RATE(1752000000, 2, 292, 1, 0), + RK3588_PLL_RATE(1728000000, 2, 288, 1, 0), + RK3588_PLL_RATE(1704000000, 2, 284, 1, 0), + RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), + RK3588_PLL_RATE(1656000000, 2, 276, 1, 0), + RK3588_PLL_RATE(1632000000, 2, 272, 1, 0), + RK3588_PLL_RATE(1608000000, 2, 268, 1, 0), + RK3588_PLL_RATE(1584000000, 2, 264, 1, 0), + RK3588_PLL_RATE(1560000000, 2, 260, 1, 0), + RK3588_PLL_RATE(1536000000, 2, 256, 1, 0), + RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), + RK3588_PLL_RATE(1488000000, 2, 248, 1, 0), + RK3588_PLL_RATE(1464000000, 2, 244, 1, 0), + RK3588_PLL_RATE(1440000000, 2, 240, 1, 0), + RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), + RK3588_PLL_RATE(1392000000, 2, 232, 1, 0), + RK3588_PLL_RATE(1320000000, 2, 220, 1, 0), + RK3588_PLL_RATE(1200000000, 2, 200, 1, 0), + RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), + RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), + RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), + RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), + RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), + RK3588_PLL_RATE(955520000, 3, 477, 2, 49806), + RK3588_PLL_RATE(903168000, 6, 903, 2, 11009), + RK3588_PLL_RATE(900000000, 2, 300, 2, 0), + RK3588_PLL_RATE(850000000, 3, 425, 2, 0), + RK3588_PLL_RATE(816000000, 2, 272, 2, 0), + RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), + RK3588_PLL_RATE(786000000, 1, 131, 2, 0), + RK3588_PLL_RATE(785560000, 3, 392, 2, 51117), + RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), + RK3588_PLL_RATE(600000000, 2, 200, 2, 0), + RK3588_PLL_RATE(594000000, 2, 198, 2, 0), + RK3588_PLL_RATE(408000000, 2, 272, 3, 0), + RK3588_PLL_RATE(312000000, 2, 208, 3, 0), + RK3588_PLL_RATE(216000000, 2, 288, 4, 0), + RK3588_PLL_RATE(100000000, 3, 400, 5, 0), + RK3588_PLL_RATE(96000000, 2, 256, 5, 0), + { /* sentinel */ }, +}; + +#define RK3588_CLK_CORE_B0_SEL_CLEAN_MASK 0x3 +#define RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT 13 +#define RK3588_CLK_CORE_B1_SEL_CLEAN_MASK 0x3 +#define RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT 5 +#define RK3588_CLK_CORE_B0_GPLL_DIV_MASK 0x1f +#define RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT 1 +#define RK3588_CLK_CORE_L_SEL_CLEAN_MASK 0x3 +#define RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT 12 +#define RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT 5 +#define RK3588_CLK_DSU_SEL_DF_MASK 0x1 +#define RK3588_CLK_DSU_SEL_DF_SHIFT 15 +#define RK3588_CLK_DSU_DF_SRC_MASK 0x3 +#define RK3588_CLK_DSU_DF_SRC_SHIFT 12 +#define RK3588_CLK_DSU_DF_DIV_MASK 0x1f +#define RK3588_CLK_DSU_DF_DIV_SHIFT 7 +#define RK3588_ACLKM_DSU_DIV_MASK 0x1f +#define RK3588_ACLKM_DSU_DIV_SHIFT 1 +#define RK3588_ACLKS_DSU_DIV_MASK 0x1f +#define RK3588_ACLKS_DSU_DIV_SHIFT 6 +#define RK3588_ACLKMP_DSU_DIV_MASK 0x1f +#define RK3588_ACLKMP_DSU_DIV_SHIFT 11 +#define RK3588_PERIPH_DSU_DIV_MASK 0x1f +#define RK3588_PERIPH_DSU_DIV_SHIFT 0 +#define RK3588_ATCLK_DSU_DIV_MASK 0x1f +#define RK3588_ATCLK_DSU_DIV_SHIFT 0 +#define RK3588_GICCLK_DSU_DIV_MASK 0x1f +#define RK3588_GICCLK_DSU_DIV_SHIFT 5 + +#define RK3588_CORE_B0_SEL(_apllcore) \ +{ \ + .reg = RK3588_BIGCORE0_CLKSEL_CON(0), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \ + HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \ + RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \ +} + +#define RK3588_CORE_B1_SEL(_apllcore) \ +{ \ + .reg = RK3588_BIGCORE0_CLKSEL_CON(1), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \ +} + +#define RK3588_CORE_B2_SEL(_apllcore) \ +{ \ + .reg = RK3588_BIGCORE1_CLKSEL_CON(0), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \ + HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \ + RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \ +} + +#define RK3588_CORE_B3_SEL(_apllcore) \ +{ \ + .reg = RK3588_BIGCORE1_CLKSEL_CON(1), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \ +} + +#define RK3588_CORE_L_SEL0(_offs, _apllcore) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(6 + _offs), \ + .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT) | \ + HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ + RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT), \ +} + +#define RK3588_CORE_L_SEL1(_seldsu, _divdsu) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(0), \ + .val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \ + RK3588_CLK_DSU_DF_SRC_SHIFT) | \ + HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \ + RK3588_CLK_DSU_DF_DIV_SHIFT), \ +} + +#define RK3588_CORE_L_SEL2(_aclkm, _aclkmp, _aclks) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(1), \ + .val = HIWORD_UPDATE(_aclkm - 1, RK3588_ACLKM_DSU_DIV_MASK, \ + RK3588_ACLKM_DSU_DIV_SHIFT) | \ + HIWORD_UPDATE(_aclkmp - 1, RK3588_ACLKMP_DSU_DIV_MASK, \ + RK3588_ACLKMP_DSU_DIV_SHIFT) | \ + HIWORD_UPDATE(_aclks - 1, RK3588_ACLKS_DSU_DIV_MASK, \ + RK3588_ACLKS_DSU_DIV_SHIFT), \ +} + +#define RK3588_CORE_L_SEL3(_periph) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(2), \ + .val = HIWORD_UPDATE(_periph - 1, RK3588_PERIPH_DSU_DIV_MASK, \ + RK3588_PERIPH_DSU_DIV_SHIFT), \ +} + +#define RK3588_CORE_L_SEL4(_gicclk, _atclk) \ +{ \ + .reg = RK3588_DSU_CLKSEL_CON(3), \ + .val = HIWORD_UPDATE(_gicclk - 1, RK3588_GICCLK_DSU_DIV_MASK, \ + RK3588_GICCLK_DSU_DIV_SHIFT) | \ + HIWORD_UPDATE(_atclk - 1, RK3588_ATCLK_DSU_DIV_MASK, \ + RK3588_ATCLK_DSU_DIV_SHIFT), \ +} + +#define RK3588_CPUB01CLK_RATE(_prate, _apllcore) \ +{ \ + .prate = _prate##U, \ + .pre_muxs = { \ + RK3588_CORE_B0_SEL(0), \ + RK3588_CORE_B1_SEL(0), \ + }, \ + .post_muxs = { \ + RK3588_CORE_B0_SEL(_apllcore), \ + RK3588_CORE_B1_SEL(_apllcore), \ + }, \ +} + +#define RK3588_CPUB23CLK_RATE(_prate, _apllcore) \ +{ \ + .prate = _prate##U, \ + .pre_muxs = { \ + RK3588_CORE_B2_SEL(0), \ + RK3588_CORE_B3_SEL(0), \ + }, \ + .post_muxs = { \ + RK3588_CORE_B2_SEL(_apllcore), \ + RK3588_CORE_B3_SEL(_apllcore), \ + }, \ +} + +#define RK3588_CPULCLK_RATE(_prate, _apllcore, _seldsu, _divdsu) \ +{ \ + .prate = _prate##U, \ + .pre_muxs = { \ + RK3588_CORE_L_SEL0(0, 0), \ + RK3588_CORE_L_SEL0(1, 0), \ + RK3588_CORE_L_SEL1(3, 2), \ + RK3588_CORE_L_SEL2(2, 3, 3), \ + RK3588_CORE_L_SEL3(4), \ + RK3588_CORE_L_SEL4(4, 4), \ + }, \ + .post_muxs = { \ + RK3588_CORE_L_SEL0(0, _apllcore), \ + RK3588_CORE_L_SEL0(1, _apllcore), \ + RK3588_CORE_L_SEL1(_seldsu, _divdsu), \ + }, \ +} + +static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = { + RK3588_CPUB01CLK_RATE(2496000000, 1), + RK3588_CPUB01CLK_RATE(2400000000, 1), + RK3588_CPUB01CLK_RATE(2304000000, 1), + RK3588_CPUB01CLK_RATE(2208000000, 1), + RK3588_CPUB01CLK_RATE(2184000000, 1), + RK3588_CPUB01CLK_RATE(2088000000, 1), + RK3588_CPUB01CLK_RATE(2040000000, 1), + RK3588_CPUB01CLK_RATE(2016000000, 1), + RK3588_CPUB01CLK_RATE(1992000000, 1), + RK3588_CPUB01CLK_RATE(1896000000, 1), + RK3588_CPUB01CLK_RATE(1800000000, 1), + RK3588_CPUB01CLK_RATE(1704000000, 0), + RK3588_CPUB01CLK_RATE(1608000000, 0), + RK3588_CPUB01CLK_RATE(1584000000, 0), + RK3588_CPUB01CLK_RATE(1560000000, 0), + RK3588_CPUB01CLK_RATE(1536000000, 0), + RK3588_CPUB01CLK_RATE(1512000000, 0), + RK3588_CPUB01CLK_RATE(1488000000, 0), + RK3588_CPUB01CLK_RATE(1464000000, 0), + RK3588_CPUB01CLK_RATE(1440000000, 0), + RK3588_CPUB01CLK_RATE(1416000000, 0), + RK3588_CPUB01CLK_RATE(1392000000, 0), + RK3588_CPUB01CLK_RATE(1368000000, 0), + RK3588_CPUB01CLK_RATE(1344000000, 0), + RK3588_CPUB01CLK_RATE(1320000000, 0), + RK3588_CPUB01CLK_RATE(1296000000, 0), + RK3588_CPUB01CLK_RATE(1272000000, 0), + RK3588_CPUB01CLK_RATE(1248000000, 0), + RK3588_CPUB01CLK_RATE(1224000000, 0), + RK3588_CPUB01CLK_RATE(1200000000, 0), + RK3588_CPUB01CLK_RATE(1104000000, 0), + RK3588_CPUB01CLK_RATE(1008000000, 0), + RK3588_CPUB01CLK_RATE(912000000, 0), + RK3588_CPUB01CLK_RATE(816000000, 0), + RK3588_CPUB01CLK_RATE(696000000, 0), + RK3588_CPUB01CLK_RATE(600000000, 0), + RK3588_CPUB01CLK_RATE(408000000, 0), + RK3588_CPUB01CLK_RATE(312000000, 0), + RK3588_CPUB01CLK_RATE(216000000, 0), + RK3588_CPUB01CLK_RATE(96000000, 0), +}; + +static const struct rockchip_cpuclk_reg_data rk3588_cpub0clk_data = { + .core_reg[0] = RK3588_BIGCORE0_CLKSEL_CON(0), + .div_core_shift[0] = 8, + .div_core_mask[0] = 0x1f, + .core_reg[1] = RK3588_BIGCORE0_CLKSEL_CON(1), + .div_core_shift[1] = 0, + .div_core_mask[1] = 0x1f, + .num_cores = 2, + .mux_core_alt = 1, + .mux_core_main = 2, + .mux_core_shift = 6, + .mux_core_mask = 0x3, +}; + +static struct rockchip_cpuclk_rate_table rk3588_cpub1clk_rates[] __initdata = { + RK3588_CPUB23CLK_RATE(2496000000, 1), + RK3588_CPUB23CLK_RATE(2400000000, 1), + RK3588_CPUB23CLK_RATE(2304000000, 1), + RK3588_CPUB23CLK_RATE(2208000000, 1), + RK3588_CPUB23CLK_RATE(2184000000, 1), + RK3588_CPUB23CLK_RATE(2088000000, 1), + RK3588_CPUB23CLK_RATE(2040000000, 1), + RK3588_CPUB23CLK_RATE(2016000000, 1), + RK3588_CPUB23CLK_RATE(1992000000, 1), + RK3588_CPUB23CLK_RATE(1896000000, 1), + RK3588_CPUB23CLK_RATE(1800000000, 1), + RK3588_CPUB23CLK_RATE(1704000000, 0), + RK3588_CPUB23CLK_RATE(1608000000, 0), + RK3588_CPUB23CLK_RATE(1584000000, 0), + RK3588_CPUB23CLK_RATE(1560000000, 0), + RK3588_CPUB23CLK_RATE(1536000000, 0), + RK3588_CPUB23CLK_RATE(1512000000, 0), + RK3588_CPUB23CLK_RATE(1488000000, 0), + RK3588_CPUB23CLK_RATE(1464000000, 0), + RK3588_CPUB23CLK_RATE(1440000000, 0), + RK3588_CPUB23CLK_RATE(1416000000, 0), + RK3588_CPUB23CLK_RATE(1392000000, 0), + RK3588_CPUB23CLK_RATE(1368000000, 0), + RK3588_CPUB23CLK_RATE(1344000000, 0), + RK3588_CPUB23CLK_RATE(1320000000, 0), + RK3588_CPUB23CLK_RATE(1296000000, 0), + RK3588_CPUB23CLK_RATE(1272000000, 0), + RK3588_CPUB23CLK_RATE(1248000000, 0), + RK3588_CPUB23CLK_RATE(1224000000, 0), + RK3588_CPUB23CLK_RATE(1200000000, 0), + RK3588_CPUB23CLK_RATE(1104000000, 0), + RK3588_CPUB23CLK_RATE(1008000000, 0), + RK3588_CPUB23CLK_RATE(912000000, 0), + RK3588_CPUB23CLK_RATE(816000000, 0), + RK3588_CPUB23CLK_RATE(696000000, 0), + RK3588_CPUB23CLK_RATE(600000000, 0), + RK3588_CPUB23CLK_RATE(408000000, 0), + RK3588_CPUB23CLK_RATE(312000000, 0), + RK3588_CPUB23CLK_RATE(216000000, 0), + RK3588_CPUB23CLK_RATE(96000000, 0), +}; + +static const struct rockchip_cpuclk_reg_data rk3588_cpub1clk_data = { + .core_reg[0] = RK3588_BIGCORE1_CLKSEL_CON(0), + .div_core_shift[0] = 8, + .div_core_mask[0] = 0x1f, + .core_reg[1] = RK3588_BIGCORE1_CLKSEL_CON(1), + .div_core_shift[1] = 0, + .div_core_mask[1] = 0x1f, + .num_cores = 2, + .mux_core_alt = 1, + .mux_core_main = 2, + .mux_core_shift = 6, + .mux_core_mask = 0x3, +}; + +static struct rockchip_cpuclk_rate_table rk3588_cpulclk_rates[] __initdata = { + RK3588_CPULCLK_RATE(2208000000, 1, 3, 1), + RK3588_CPULCLK_RATE(2184000000, 1, 3, 1), + RK3588_CPULCLK_RATE(2088000000, 1, 3, 1), + RK3588_CPULCLK_RATE(2040000000, 1, 3, 1), + RK3588_CPULCLK_RATE(2016000000, 1, 3, 1), + RK3588_CPULCLK_RATE(1992000000, 1, 3, 1), + RK3588_CPULCLK_RATE(1896000000, 1, 3, 1), + RK3588_CPULCLK_RATE(1800000000, 1, 3, 1), + RK3588_CPULCLK_RATE(1704000000, 0, 3, 1), + RK3588_CPULCLK_RATE(1608000000, 0, 3, 1), + RK3588_CPULCLK_RATE(1584000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1560000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1536000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1512000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1488000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1464000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1440000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1416000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1392000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1368000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1344000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1320000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1296000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1272000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1248000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1224000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1200000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1104000000, 0, 2, 1), + RK3588_CPULCLK_RATE(1008000000, 0, 2, 1), + RK3588_CPULCLK_RATE(912000000, 0, 2, 1), + RK3588_CPULCLK_RATE(816000000, 0, 2, 1), + RK3588_CPULCLK_RATE(696000000, 0, 2, 1), + RK3588_CPULCLK_RATE(600000000, 0, 2, 1), + RK3588_CPULCLK_RATE(408000000, 0, 2, 1), + RK3588_CPULCLK_RATE(312000000, 0, 2, 1), + RK3588_CPULCLK_RATE(216000000, 0, 2, 1), + RK3588_CPULCLK_RATE(96000000, 0, 2, 1), +}; + +static const struct rockchip_cpuclk_reg_data rk3588_cpulclk_data = { + .core_reg[0] = RK3588_DSU_CLKSEL_CON(6), + .div_core_shift[0] = 0, + .div_core_mask[0] = 0x1f, + .core_reg[1] = RK3588_DSU_CLKSEL_CON(6), + .div_core_shift[1] = 7, + .div_core_mask[1] = 0x1f, + .core_reg[2] = RK3588_DSU_CLKSEL_CON(7), + .div_core_shift[2] = 0, + .div_core_mask[2] = 0x1f, + .core_reg[3] = RK3588_DSU_CLKSEL_CON(7), + .div_core_shift[3] = 7, + .div_core_mask[3] = 0x1f, + .num_cores = 4, + .mux_core_reg = RK3588_DSU_CLKSEL_CON(5), + .mux_core_alt = 1, + .mux_core_main = 2, + .mux_core_shift = 14, + .mux_core_mask = 0x3, +}; + +PNAME(mux_pll_p) = { "xin24m", "xin32k" }; +PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" }; +PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",}; +PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",}; +PNAME(b0pll_b1pll_lpll_gpll_p) = { "b0pll", "b1pll", "lpll", "gpll" }; +PNAME(gpll_24m_p) = { "gpll", "xin24m" }; +PNAME(gpll_aupll_p) = { "gpll", "aupll" }; +PNAME(gpll_lpll_p) = { "gpll", "lpll" }; +PNAME(gpll_cpll_p) = { "gpll", "cpll" }; +PNAME(gpll_spll_p) = { "gpll", "spll" }; +PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m"}; +PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll"}; +PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll"}; +PNAME(gpll_cpll_npll_v0pll_p) = { "gpll", "cpll", "npll", "v0pll"}; +PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" }; +PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" }; +PNAME(gpll_cpll_aupll_npll_p) = { "gpll", "cpll", "aupll", "npll" }; +PNAME(gpll_cpll_v0pll_aupll_p) = { "gpll", "cpll", "v0pll", "aupll" }; +PNAME(gpll_cpll_v0pll_spll_p) = { "gpll", "cpll", "v0pll", "spll" }; +PNAME(gpll_cpll_aupll_npll_spll_p) = { "gpll", "cpll", "aupll", "npll", "spll" }; +PNAME(gpll_cpll_dmyaupll_npll_spll_p) = { "gpll", "cpll", "dummy_aupll", "npll", "spll" }; +PNAME(gpll_cpll_npll_aupll_spll_p) = { "gpll", "cpll", "npll", "aupll", "spll" }; +PNAME(gpll_cpll_npll_1000m_p) = { "gpll", "cpll", "npll", "clk_1000m_src" }; +PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" }; +PNAME(mux_24m_32k_p) = { "xin24m", "xin32k" }; +PNAME(mux_24m_100m_p) = { "xin24m", "clk_100m_src" }; +PNAME(mux_200m_100m_p) = { "clk_200m_src", "clk_100m_src" }; +PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" }; +PNAME(mux_150m_50m_24m_p) = { "clk_150m_src", "clk_50m_src", "xin24m" }; +PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" }; +PNAME(mux_200m_150m_24m_p) = { "clk_200m_src", "clk_150m_src", "xin24m" }; +PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; +PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; +PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; +PNAME(mux_700m_400m_200m_24m_p) = { "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin24m" }; +PNAME(mux_500m_250m_100m_24m_p) = { "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin24m" }; +PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" }; +PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; +PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin12m" }; +PNAME(i2s2_2ch_mclkout_p) = { "mclk_i2s2_2ch", "xin12m" }; +PNAME(clk_i2s3_2ch_p) = { "clk_i2s3_2ch_src", "clk_i2s3_2ch_frac", "i2s3_mclkin", "xin12m" }; +PNAME(i2s3_2ch_mclkout_p) = { "mclk_i2s3_2ch", "xin12m" }; +PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" }; +PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" }; +PNAME(i2s0_8ch_mclkout_p) = { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin12m" }; +PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin12m" }; +PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin12m" }; +PNAME(i2s1_8ch_mclkout_p) = { "mclk_i2s1_8ch_tx", "mclk_i2s1_8ch_rx", "xin12m" }; +PNAME(clk_i2s4_8ch_tx_p) = { "clk_i2s4_8ch_tx_src", "clk_i2s4_8ch_tx_frac", "i2s4_mclkin", "xin12m" }; +PNAME(clk_i2s5_8ch_tx_p) = { "clk_i2s5_8ch_tx_src", "clk_i2s5_8ch_tx_frac", "i2s5_mclkin", "xin12m" }; +PNAME(clk_i2s6_8ch_tx_p) = { "clk_i2s6_8ch_tx_src", "clk_i2s6_8ch_tx_frac", "i2s6_mclkin", "xin12m" }; +PNAME(clk_i2s6_8ch_rx_p) = { "clk_i2s6_8ch_rx_src", "clk_i2s6_8ch_rx_frac", "i2s6_mclkin", "xin12m" }; +PNAME(i2s6_8ch_mclkout_p) = { "mclk_i2s6_8ch_tx", "mclk_i2s6_8ch_rx", "xin12m" }; +PNAME(clk_i2s7_8ch_rx_p) = { "clk_i2s7_8ch_rx_src", "clk_i2s7_8ch_rx_frac", "i2s7_mclkin", "xin12m" }; +PNAME(clk_i2s8_8ch_tx_p) = { "clk_i2s8_8ch_tx_src", "clk_i2s8_8ch_tx_frac", "i2s8_mclkin", "xin12m" }; +PNAME(clk_i2s9_8ch_rx_p) = { "clk_i2s9_8ch_rx_src", "clk_i2s9_8ch_rx_frac", "i2s9_mclkin", "xin12m" }; +PNAME(clk_i2s10_8ch_rx_p) = { "clk_i2s10_8ch_rx_src", "clk_i2s10_8ch_rx_frac", "i2s10_mclkin", "xin12m" }; +PNAME(clk_spdif0_p) = { "clk_spdif0_src", "clk_spdif0_frac", "xin12m" }; +PNAME(clk_spdif1_p) = { "clk_spdif1_src", "clk_spdif1_frac", "xin12m" }; +PNAME(clk_spdif2_dp0_p) = { "clk_spdif2_dp0_src", "clk_spdif2_dp0_frac", "xin12m" }; +PNAME(clk_spdif3_p) = { "clk_spdif3_src", "clk_spdif3_frac", "xin12m" }; +PNAME(clk_spdif4_p) = { "clk_spdif4_src", "clk_spdif4_frac", "xin12m" }; +PNAME(clk_spdif5_dp1_p) = { "clk_spdif5_dp1_src", "clk_spdif5_dp1_frac", "xin12m" }; +PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" }; +PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; +PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; +PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; +PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; +PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; +PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; +PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; +PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; +PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; +PNAME(clk_gmac0_ptp_ref_p) = { "cpll", "clk_gmac0_ptpref_io" }; +PNAME(clk_gmac1_ptp_ref_p) = { "cpll", "clk_gmac1_ptpref_io" }; +PNAME(clk_hdmirx_aud_p) = { "clk_hdmirx_aud_src", "clk_hdmirx_aud_frac" }; +PNAME(aclk_hdcp1_root_p) = { "gpll", "cpll", "clk_hdmitrx_refsrc" }; +PNAME(aclk_vop_sub_src_p) = { "aclk_vop_root", "aclk_vop_div2_src" }; +PNAME(dclk_vop0_p) = { "dclk_vop0_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; +PNAME(dclk_vop1_p) = { "dclk_vop1_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; +PNAME(dclk_vop2_p) = { "dclk_vop2_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; +PNAME(pmu_200m_100m_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src" }; +PNAME(pmu_300m_24m_p) = { "clk_300m_src", "xin24m" }; +PNAME(pmu_400m_24m_p) = { "clk_400m_src", "xin24m" }; +PNAME(pmu_100m_50m_24m_src_p) = { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; +PNAME(pmu_24m_32k_100m_src_p) = { "xin24m", "32k", "clk_pmu1_100m_src" }; +PNAME(hclk_pmu1_root_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; +PNAME(hclk_pmu_cm0_root_p) = { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" }; +PNAME(mclk_pdm0_p) = { "clk_pmu1_300m_src", "clk_pmu1_200m_src" }; +PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" }; +PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; +PNAME(clk_ref_pipe_phy0_p) = { "clk_ref_pipe_phy0_osc_src", "clk_ref_pipe_phy0_pll_src" }; +PNAME(clk_ref_pipe_phy1_p) = { "clk_ref_pipe_phy1_osc_src", "clk_ref_pipe_phy1_pll_src" }; +PNAME(clk_ref_pipe_phy2_p) = { "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_pll_src" }; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_clk_branch rk3588_i2s0_8ch_tx_fracmux __initdata = + MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(26), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s0_8ch_rx_fracmux __initdata = + MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(28), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s1_8ch_tx_fracmux __initdata = + MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(7), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s1_8ch_rx_fracmux __initdata = + MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(9), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s2_2ch_fracmux __initdata = + MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(30), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s3_2ch_fracmux __initdata = + MUX(CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(32), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s4_8ch_tx_fracmux __initdata = + MUX(CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx", clk_i2s4_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(120), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s5_8ch_tx_fracmux __initdata = + MUX(CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx", clk_i2s5_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(142), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s6_8ch_tx_fracmux __initdata = + MUX(CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx", clk_i2s6_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(146), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s6_8ch_rx_fracmux __initdata = + MUX(CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx", clk_i2s6_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(148), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s7_8ch_rx_fracmux __initdata = + MUX(CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx", clk_i2s7_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(131), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s8_8ch_tx_fracmux __initdata = + MUX(CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx", clk_i2s8_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(122), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s9_8ch_rx_fracmux __initdata = + MUX(CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx", clk_i2s9_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(155), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_i2s10_8ch_rx_fracmux __initdata = + MUX(CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx", clk_i2s10_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(157), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif0_fracmux __initdata = + MUX(CLK_SPDIF0, "clk_spdif0", clk_spdif0_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(34), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif1_fracmux __initdata = + MUX(CLK_SPDIF1, "clk_spdif1", clk_spdif1_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(36), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif2_dp0_fracmux __initdata = + MUX(CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(124), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif3_fracmux __initdata = + MUX(CLK_SPDIF3, "clk_spdif3", clk_spdif3_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(150), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif4_fracmux __initdata = + MUX(CLK_SPDIF4, "clk_spdif4", clk_spdif4_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(152), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_spdif5_dp1_fracmux __initdata = + MUX(CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(126), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart0_fracmux __initdata = + MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(5), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart1_fracmux __initdata = + MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(43), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart2_fracmux __initdata = + MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(45), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart3_fracmux __initdata = + MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(47), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart4_fracmux __initdata = + MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(49), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart5_fracmux __initdata = + MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(51), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart6_fracmux __initdata = + MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(53), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart7_fracmux __initdata = + MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(55), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart8_fracmux __initdata = + MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(57), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_uart9_fracmux __initdata = + MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(59), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3588_hdmirx_aud_fracmux __initdata = + MUX(CLK_HDMIRX_AUD_P_MUX, "clk_hdmirx_aud_mux", clk_hdmirx_aud_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(140), 0, 1, MFLAGS); + +static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = { + [b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_B0_PLL_CON(0), + RK3588_B0_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), + [b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_B1_PLL_CON(8), + RK3588_B1_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), + [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_LPLL_CON(16), + RK3588_LPLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), + [v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p, + 0, RK3588_PLL_CON(88), + RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates), + [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p, + 0, RK3588_PLL_CON(96), + RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates), + [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_PLL_CON(104), + RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates), + [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_PLL_CON(112), + RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates), + [npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p, + 0, RK3588_PLL_CON(120), + RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates), + [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3588_PMU_PLL_CON(128), + RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates), +}; + +static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { + /* + * CRU Clock-Architecture + */ + /* fixed */ + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), + + /* top */ + COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 0, GFLAGS), + COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 9, GFLAGS), + COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 10, GFLAGS), + COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, 0, + RK3588_CLKSEL_CON(5), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 11, GFLAGS), + COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(6), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 12, GFLAGS), + COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(6), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 13, GFLAGS), + COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(7), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 14, GFLAGS), + COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(7), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_M300_ROOT, "aclk_top_m300_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 10, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_M500_ROOT, "aclk_top_m500_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 11, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_M400_ROOT, "aclk_top_m400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 4, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 12, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_S200_ROOT, "aclk_top_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 13, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_S400_ROOT, "aclk_top_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(9), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 14, GFLAGS), + COMPOSITE(ACLK_TOP_ROOT, "aclk_top_root", gpll_cpll_aupll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(8), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(8), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE(ACLK_LOW_TOP_ROOT, "aclk_low_top_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(8), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(1), 2, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 9, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 10, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 11, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 12, GFLAGS), + COMPOSITE(CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4", mux_24m_spll_gpll_cpll_p, 0, + RK3588_CLKSEL_CON(22), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 13, GFLAGS), + COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(5), 3, GFLAGS), + COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3588_CLKGATE_CON(5), 4, GFLAGS), + COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(5), 5, GFLAGS), + COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0, + RK3588_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(5), 6, GFLAGS), + GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(3), 14, GFLAGS), + GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(4), 3, GFLAGS), + GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(1), 6, GFLAGS), + GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(1), 8, GFLAGS), + GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(5), 0, GFLAGS), + + /* bigcore0 */ + COMPOSITE_NODIV(PCLK_BIGCORE0_ROOT, "pclk_bigcore0_root", mux_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3588_BIGCORE0_CLKSEL_CON(2), 0, 2, MFLAGS, + RK3588_BIGCORE0_CLKGATE_CON(0), 14, GFLAGS), + GATE(PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", "pclk_bigcore0_root", 0, + RK3588_BIGCORE0_CLKGATE_CON(1), 0, GFLAGS), + GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0, + RK3588_BIGCORE0_CLKGATE_CON(0), 12, GFLAGS), + GATE(CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", "armclk_b01", 0, + RK3588_BIGCORE0_CLKGATE_CON(0), 13, GFLAGS), + + /* bigcore1 */ + COMPOSITE_NODIV(PCLK_BIGCORE1_ROOT, "pclk_bigcore1_root", mux_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3588_BIGCORE1_CLKSEL_CON(2), 0, 2, MFLAGS, + RK3588_BIGCORE1_CLKGATE_CON(0), 14, GFLAGS), + GATE(PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", "pclk_bigcore1_root", 0, + RK3588_BIGCORE1_CLKGATE_CON(1), 0, GFLAGS), + GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0, + RK3588_BIGCORE1_CLKGATE_CON(0), 12, GFLAGS), + GATE(CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm", "armclk_b23", 0, + RK3588_BIGCORE1_CLKGATE_CON(0), 13, GFLAGS), + + /* dsu */ + COMPOSITE(0, "sclk_dsu", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(0), 12, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_DSU_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NOMUX(0, "atclk_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE_NOMUX(0, "gicclk_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(3), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE_NOMUX(0, "aclkmp_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(1), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 12, GFLAGS), + COMPOSITE_NOMUX(0, "aclkm_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(1), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_NOMUX(0, "aclks_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(1), 6, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 9, GFLAGS), + COMPOSITE_NOMUX(0, "periph_dsu", "sclk_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(2), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 13, GFLAGS), + COMPOSITE_NOMUX(0, "cntclk_dsu", "periph_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(2), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 14, GFLAGS), + COMPOSITE_NOMUX(0, "tsclk_dsu", "periph_dsu", CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(2), 10, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3588_DSU_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_NODIV(PCLK_DSU_S_ROOT, "pclk_dsu_s_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(4), 11, 2, MFLAGS, + RK3588_DSU_CLKGATE_CON(2), 2, GFLAGS), + COMPOSITE(PCLK_DSU_ROOT, "pclk_dsu_root", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_DSU_CLKGATE_CON(1), 3, GFLAGS), + COMPOSITE_NODIV(PCLK_DSU_NS_ROOT, "pclk_dsu_ns_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_DSU_CLKSEL_CON(4), 7, 2, MFLAGS, + RK3588_DSU_CLKGATE_CON(1), 4, GFLAGS), + GATE(PCLK_LITCORE_PVTM, "pclk_litcore_pvtm", "pclk_dsu_ns_root", 0, + RK3588_DSU_CLKGATE_CON(2), 6, GFLAGS), + GATE(PCLK_DBG, "pclk_dbg", "pclk_dsu_root", CLK_IS_CRITICAL, + RK3588_DSU_CLKGATE_CON(1), 7, GFLAGS), + GATE(PCLK_DSU, "pclk_dsu", "pclk_dsu_root", CLK_IS_CRITICAL, + RK3588_DSU_CLKGATE_CON(1), 6, GFLAGS), + GATE(PCLK_S_DAPLITE, "pclk_s_daplite", "pclk_dsu_ns_root", CLK_IGNORE_UNUSED, + RK3588_DSU_CLKGATE_CON(1), 8, GFLAGS), + GATE(PCLK_M_DAPLITE, "pclk_m_daplite", "pclk_dsu_root", CLK_IGNORE_UNUSED, + RK3588_DSU_CLKGATE_CON(1), 9, GFLAGS), + GATE(CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 0, + RK3588_DSU_CLKGATE_CON(2), 0, GFLAGS), + GATE(CLK_CORE_LITCORE_PVTM, "clk_core_litcore_pvtm", "armclk_l", 0, + RK3588_DSU_CLKGATE_CON(2), 1, GFLAGS), + + /* audio */ + COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(24), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(7), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_AUDIO_ROOT, "pclk_audio_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(24), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(7), 1, GFLAGS), + GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(7), 12, GFLAGS), + GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(7), 13, GFLAGS), + COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(28), 9, 1, MFLAGS, 4, 5, DFLAGS, + RK3588_CLKGATE_CON(7), 14, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(29), 0, + RK3588_CLKGATE_CON(7), 15, GFLAGS, + &rk3588_i2s2_2ch_fracmux), + GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, + RK3588_CLKGATE_CON(8), 0, GFLAGS), + MUX(I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", i2s2_2ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(30), 2, 1, MFLAGS), + + COMPOSITE(CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(8), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S3_2CH_FRAC, "clk_i2s3_2ch_frac", "clk_i2s3_2ch_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(31), 0, + RK3588_CLKGATE_CON(8), 2, GFLAGS, + &rk3588_i2s3_2ch_fracmux), + GATE(MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch", 0, + RK3588_CLKGATE_CON(8), 3, GFLAGS), + GATE(CLK_DAC_ACDCDIG, "clk_dac_acdcdig", "mclk_i2s3_2ch", 0, + RK3588_CLKGATE_CON(8), 4, GFLAGS), + MUX(I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", i2s3_2ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(32), 2, 1, MFLAGS), + GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0, + RK3588_CLKGATE_CON(7), 11, GFLAGS), + GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(7), 4, GFLAGS), + + COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(24), 9, 1, MFLAGS, 4, 5, DFLAGS, + RK3588_CLKGATE_CON(7), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(25), 0, + RK3588_CLKGATE_CON(7), 6, GFLAGS, + &rk3588_i2s0_8ch_tx_fracmux), + GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, + RK3588_CLKGATE_CON(7), 7, GFLAGS), + + COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(26), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(7), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(27), 0, + RK3588_CLKGATE_CON(7), 9, GFLAGS, + &rk3588_i2s0_8ch_rx_fracmux), + GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, + RK3588_CLKGATE_CON(7), 10, GFLAGS), + MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(28), 2, 2, MFLAGS), + + GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(9), 6, GFLAGS), + COMPOSITE(MCLK_PDM1, "mclk_pdm1", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(36), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(9), 7, GFLAGS), + + GATE(HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(8), 14, GFLAGS), + COMPOSITE(CLK_SPDIF0_SRC, "clk_spdif0_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(32), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(8), 15, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF0_FRAC, "clk_spdif0_frac", "clk_spdif0_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(33), 0, + RK3588_CLKGATE_CON(9), 0, GFLAGS, + &rk3588_spdif0_fracmux), + GATE(MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0", 0, + RK3588_CLKGATE_CON(9), 1, GFLAGS), + + GATE(HCLK_SPDIF1, "hclk_spdif1", "hclk_audio_root", 0, + RK3588_CLKGATE_CON(9), 2, GFLAGS), + COMPOSITE(CLK_SPDIF1_SRC, "clk_spdif1_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(34), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(9), 3, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF1_FRAC, "clk_spdif1_frac", "clk_spdif1_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(35), 0, + RK3588_CLKGATE_CON(9), 4, GFLAGS, + &rk3588_spdif1_fracmux), + GATE(MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1", 0, + RK3588_CLKGATE_CON(9), 5, GFLAGS), + + COMPOSITE(ACLK_AV1_ROOT, "aclk_av1_root", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(163), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(68), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_AV1_ROOT, "pclk_av1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(163), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(68), 3, GFLAGS), + + /* bus */ + COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(10), 0, GFLAGS), + + GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(16), 11, GFLAGS), + GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(16), 12, GFLAGS), + GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(16), 13, GFLAGS), + GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(19), 3, GFLAGS), + GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(19), 4, GFLAGS), + GATE(PCLK_DDRCM0_INTMUX, "pclk_ddrcm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(19), 5, GFLAGS), + + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 3, GFLAGS), + COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(59), 12, 2, MFLAGS, + RK3588_CLKGATE_CON(15), 4, GFLAGS), + GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, + RK3588_CLKGATE_CON(15), 5, GFLAGS), + GATE(PCLK_PWM2, "pclk_pwm2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 6, GFLAGS), + COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(59), 14, 2, MFLAGS, + RK3588_CLKGATE_CON(15), 7, GFLAGS), + GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, + RK3588_CLKGATE_CON(15), 8, GFLAGS), + GATE(PCLK_PWM3, "pclk_pwm3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 9, GFLAGS), + COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(60), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(15), 10, GFLAGS), + GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, + RK3588_CLKGATE_CON(15), 11, GFLAGS), + + GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 12, GFLAGS), + GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 13, GFLAGS), + COMPOSITE_NODIV(CLK_BUS_TIMER_ROOT, "clk_bus_timer_root", mux_24m_100m_p, 0, + RK3588_CLKSEL_CON(60), 2, 1, MFLAGS, + RK3588_CLKGATE_CON(15), 14, GFLAGS), + GATE(CLK_BUSTIMER0, "clk_bustimer0", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(15), 15, GFLAGS), + GATE(CLK_BUSTIMER1, "clk_bustimer1", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 0, GFLAGS), + GATE(CLK_BUSTIMER2, "clk_bustimer2", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 1, GFLAGS), + GATE(CLK_BUSTIMER3, "clk_bustimer3", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 2, GFLAGS), + GATE(CLK_BUSTIMER4, "clk_bustimer4", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 3, GFLAGS), + GATE(CLK_BUSTIMER5, "clk_bustimer5", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 4, GFLAGS), + GATE(CLK_BUSTIMER6, "clk_bustimer6", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 5, GFLAGS), + GATE(CLK_BUSTIMER7, "clk_bustimer7", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 6, GFLAGS), + GATE(CLK_BUSTIMER8, "clk_bustimer8", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 7, GFLAGS), + GATE(CLK_BUSTIMER9, "clk_bustimer9", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 8, GFLAGS), + GATE(CLK_BUSTIMER10, "clk_bustimer10", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 9, GFLAGS), + GATE(CLK_BUSTIMER11, "clk_bustimer11", "clk_bus_timer_root", 0, + RK3588_CLKGATE_CON(16), 10, GFLAGS), + + GATE(PCLK_WDT0, "pclk_wdt0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(15), 0, GFLAGS), + GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0, + RK3588_CLKGATE_CON(15), 1, GFLAGS), + + GATE(PCLK_CAN0, "pclk_can0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(11), 8, GFLAGS), + COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(39), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(11), 9, GFLAGS), + GATE(PCLK_CAN1, "pclk_can1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(11), 10, GFLAGS), + COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(39), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(11), 11, GFLAGS), + GATE(PCLK_CAN2, "pclk_can2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(11), 12, GFLAGS), + COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(40), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(11), 13, GFLAGS), + + GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0, + RK3588_CLKGATE_CON(17), 6, GFLAGS), + GATE(PCLK_DECOM, "pclk_decom", "pclk_top_root", 0, + RK3588_CLKGATE_CON(17), 7, GFLAGS), + COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0, + RK3588_CLKSEL_CON(62), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(17), 8, GFLAGS), + GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0, + RK3588_CLKGATE_CON(10), 5, GFLAGS), + GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0, + RK3588_CLKGATE_CON(10), 6, GFLAGS), + GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0, + RK3588_CLKGATE_CON(10), 7, GFLAGS), + GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(10), 3, GFLAGS), + + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(16), 14, GFLAGS), + COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(60), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(16), 15, GFLAGS), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(17), 0, GFLAGS), + COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(60), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(17), 1, GFLAGS), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(17), 2, GFLAGS), + COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(61), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(17), 3, GFLAGS), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_top_root", 0, + RK3588_CLKGATE_CON(17), 4, GFLAGS), + COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(61), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(17), 5, GFLAGS), + + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 8, GFLAGS), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 9, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 10, GFLAGS), + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 11, GFLAGS), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 12, GFLAGS), + GATE(PCLK_I2C6, "pclk_i2c6", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 13, GFLAGS), + GATE(PCLK_I2C7, "pclk_i2c7", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 14, GFLAGS), + GATE(PCLK_I2C8, "pclk_i2c8", "pclk_top_root", 0, + RK3588_CLKGATE_CON(10), 15, GFLAGS), + COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 6, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 0, GFLAGS), + COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 7, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 1, GFLAGS), + COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 8, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 2, GFLAGS), + COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 9, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 3, GFLAGS), + COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 10, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 4, GFLAGS), + COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 11, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 5, GFLAGS), + COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 12, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 6, GFLAGS), + COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_p, 0, + RK3588_CLKSEL_CON(38), 13, 1, MFLAGS, + RK3588_CLKGATE_CON(11), 7, GFLAGS), + + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_top_root", 0, + RK3588_CLKGATE_CON(18), 9, GFLAGS), + GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0, + RK3588_CLKGATE_CON(18), 10, GFLAGS), + GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0, + RK3588_CLKGATE_CON(18), 11, GFLAGS), + GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0, + RK3588_CLKGATE_CON(18), 13, GFLAGS), + GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0, + RK3588_CLKGATE_CON(18), 12, GFLAGS), + + GATE(PCLK_SARADC, "pclk_saradc", "pclk_top_root", 0, + RK3588_CLKGATE_CON(11), 14, GFLAGS), + COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0, + RK3588_CLKSEL_CON(40), 14, 1, MFLAGS, 6, 8, DFLAGS, + RK3588_CLKGATE_CON(11), 15, GFLAGS), + + GATE(PCLK_SPI0, "pclk_spi0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 6, GFLAGS), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 7, GFLAGS), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 8, GFLAGS), + GATE(PCLK_SPI3, "pclk_spi3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 9, GFLAGS), + GATE(PCLK_SPI4, "pclk_spi4", "pclk_top_root", 0, + RK3588_CLKGATE_CON(14), 10, GFLAGS), + COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 11, GFLAGS), + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 4, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 12, GFLAGS), + COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 13, GFLAGS), + COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 14, GFLAGS), + COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_150m_24m_p, 0, + RK3588_CLKSEL_CON(59), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(14), 15, GFLAGS), + + GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(18), 6, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 0, GFLAGS), + COMPOSITE(CLK_TSADC, "clk_tsadc", gpll_24m_p, 0, + RK3588_CLKSEL_CON(41), 8, 1, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(12), 1, GFLAGS), + + GATE(PCLK_UART1, "pclk_uart1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 2, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 3, GFLAGS), + GATE(PCLK_UART3, "pclk_uart3", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 4, GFLAGS), + GATE(PCLK_UART4, "pclk_uart4", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 5, GFLAGS), + GATE(PCLK_UART5, "pclk_uart5", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 6, GFLAGS), + GATE(PCLK_UART6, "pclk_uart6", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 7, GFLAGS), + GATE(PCLK_UART7, "pclk_uart7", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 8, GFLAGS), + GATE(PCLK_UART8, "pclk_uart8", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 9, GFLAGS), + GATE(PCLK_UART9, "pclk_uart9", "pclk_top_root", 0, + RK3588_CLKGATE_CON(12), 10, GFLAGS), + + COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(41), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(12), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(42), 0, + RK3588_CLKGATE_CON(12), 12, GFLAGS, + &rk3588_uart1_fracmux), + GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, + RK3588_CLKGATE_CON(12), 13, GFLAGS), + COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(43), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(12), 14, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(44), 0, + RK3588_CLKGATE_CON(12), 15, GFLAGS, + &rk3588_uart2_fracmux), + GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, + RK3588_CLKGATE_CON(13), 0, GFLAGS), + COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(45), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(46), 0, + RK3588_CLKGATE_CON(13), 2, GFLAGS, + &rk3588_uart3_fracmux), + GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, + RK3588_CLKGATE_CON(13), 3, GFLAGS), + COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(47), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 4, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(48), 0, + RK3588_CLKGATE_CON(13), 5, GFLAGS, + &rk3588_uart4_fracmux), + GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, + RK3588_CLKGATE_CON(13), 6, GFLAGS), + COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(49), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 7, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(50), 0, + RK3588_CLKGATE_CON(13), 8, GFLAGS, + &rk3588_uart5_fracmux), + GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, + RK3588_CLKGATE_CON(13), 9, GFLAGS), + COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(51), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 10, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(52), 0, + RK3588_CLKGATE_CON(13), 11, GFLAGS, + &rk3588_uart6_fracmux), + GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, + RK3588_CLKGATE_CON(13), 12, GFLAGS), + COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(53), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(13), 13, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(54), 0, + RK3588_CLKGATE_CON(13), 14, GFLAGS, + &rk3588_uart7_fracmux), + GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, + RK3588_CLKGATE_CON(13), 15, GFLAGS), + COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(55), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(14), 0, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(56), 0, + RK3588_CLKGATE_CON(14), 1, GFLAGS, + &rk3588_uart8_fracmux), + GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0, + RK3588_CLKGATE_CON(14), 2, GFLAGS), + COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(57), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(14), 3, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(58), 0, + RK3588_CLKGATE_CON(14), 4, GFLAGS, + &rk3588_uart9_fracmux), + GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0, + RK3588_CLKGATE_CON(14), 5, GFLAGS), + + /* center */ + COMPOSITE_NODIV(ACLK_CENTER_ROOT, "aclk_center_root", mux_700m_400m_200m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_400m_200m_100m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 4, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, + RK3588_CLKGATE_CON(69), 3, GFLAGS), + GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(69), 5, GFLAGS), + GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(69), 6, GFLAGS), + COMPOSITE_NODIV(ACLK_CENTER_S200_ROOT, "aclk_center_s200_root", mux_200m_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 8, GFLAGS), + COMPOSITE_NODIV(ACLK_CENTER_S400_ROOT, "aclk_center_s400_root", mux_400m_200m_100m_24m_p, + CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(165), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(69), 9, GFLAGS), + GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_center_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(69), 14, GFLAGS), + COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_24m_100m_p, CLK_IGNORE_UNUSED, + RK3588_CLKSEL_CON(165), 12, 1, MFLAGS, + RK3588_CLKGATE_CON(69), 15, GFLAGS), + GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0, + RK3588_CLKGATE_CON(70), 0, GFLAGS), + GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0, + RK3588_CLKGATE_CON(70), 1, GFLAGS), + GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0, + RK3588_CLKGATE_CON(70), 2, GFLAGS), + COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(166), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(70), 4, GFLAGS), + GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0, + RK3588_CLKGATE_CON(70), 7, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0, + RK3588_CLKGATE_CON(70), 8, GFLAGS), + GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(70), 9, GFLAGS), + GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(70), 10, GFLAGS), + + /* gpu */ + COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", gpll_cpll_aupll_npll_spll_p, 0, + RK3588_CLKSEL_CON(158), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(66), 1, GFLAGS), + GATE(CLK_GPU, "clk_gpu", "clk_gpu_src", 0, + RK3588_CLKGATE_CON(66), 4, GFLAGS), + GATE(CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src", 0, + RK3588_CLKGATE_CON(66), 6, GFLAGS), + COMPOSITE_NOMUX(CLK_GPU_STACKS, "clk_gpu_stacks", "clk_gpu_src", 0, + RK3588_CLKSEL_CON(159), 0, 5, DFLAGS, + RK3588_CLKGATE_CON(66), 7, GFLAGS), + GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, + RK3588_CLKGATE_CON(67), 0, GFLAGS), + GATE(CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src", 0, + RK3588_CLKGATE_CON(67), 1, GFLAGS), + + /* isp1 */ + COMPOSITE(ACLK_ISP1_ROOT, "aclk_isp1_root", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(67), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(26), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_ISP1_ROOT, "hclk_isp1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(67), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(26), 1, GFLAGS), + COMPOSITE(CLK_ISP1_CORE, "clk_isp1_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(67), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(26), 2, GFLAGS), + GATE(CLK_ISP1_CORE_MARVIN, "clk_isp1_core_marvin", "clk_isp1_core", 0, + RK3588_CLKGATE_CON(26), 3, GFLAGS), + GATE(CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", "clk_isp1_core", 0, + RK3588_CLKGATE_CON(26), 4, GFLAGS), + + /* npu */ + COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(73), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(29), 0, GFLAGS), + COMPOSITE(CLK_NPU_DSU0, "clk_npu_dsu0", gpll_cpll_aupll_npll_spll_p, 0, + RK3588_CLKSEL_CON(73), 7, 3, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(29), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(74), 1, 2, MFLAGS, + RK3588_CLKGATE_CON(29), 4, GFLAGS), + GATE(ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0", 0, + RK3588_CLKGATE_CON(27), 0, GFLAGS), + GATE(HCLK_NPU1, "hclk_npu1", "hclk_npu_root", 0, + RK3588_CLKGATE_CON(27), 2, GFLAGS), + GATE(ACLK_NPU2, "aclk_npu2", "clk_npu_dsu0", 0, + RK3588_CLKGATE_CON(28), 0, GFLAGS), + GATE(HCLK_NPU2, "hclk_npu2", "hclk_npu_root", 0, + RK3588_CLKGATE_CON(28), 2, GFLAGS), + COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(74), 5, 2, MFLAGS, + RK3588_CLKGATE_CON(30), 1, GFLAGS), + GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0, + RK3588_CLKGATE_CON(30), 3, GFLAGS), + COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0, + RK3588_CLKSEL_CON(74), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(30), 5, GFLAGS), + GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root", 0, + RK3588_CLKGATE_CON(29), 12, GFLAGS), + GATE(PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(29), 13, GFLAGS), + GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, + RK3588_CLKGATE_CON(29), 14, GFLAGS), + GATE(CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0", 0, + RK3588_CLKGATE_CON(29), 15, GFLAGS), + GATE(ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0", 0, + RK3588_CLKGATE_CON(30), 6, GFLAGS), + GATE(HCLK_NPU0, "hclk_npu0", "hclk_npu_root", 0, + RK3588_CLKGATE_CON(30), 8, GFLAGS), + GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root", 0, + RK3588_CLKGATE_CON(29), 6, GFLAGS), + COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_24m_100m_p, 0, + RK3588_CLKSEL_CON(74), 3, 1, MFLAGS, + RK3588_CLKGATE_CON(29), 7, GFLAGS), + GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0, + RK3588_CLKGATE_CON(29), 8, GFLAGS), + GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0, + RK3588_CLKGATE_CON(29), 9, GFLAGS), + GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_npu_root", 0, + RK3588_CLKGATE_CON(29), 10, GFLAGS), + GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0, + RK3588_CLKGATE_CON(29), 11, GFLAGS), + + /* nvm */ + COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(31), 0, GFLAGS), + COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(31), 1, GFLAGS), + GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, + RK3588_CLKGATE_CON(31), 5, GFLAGS), + COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_24m_p, 0, + RK3588_CLKSEL_CON(77), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3588_CLKGATE_CON(31), 6, GFLAGS), + COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(78), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(31), 7, GFLAGS), + GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0, + RK3588_CLKGATE_CON(31), 8, GFLAGS), + + COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0, + RK3588_CLKSEL_CON(78), 12, 2, MFLAGS, 6, 6, DFLAGS, + RK3588_CLKGATE_CON(31), 9, GFLAGS), + + /* php */ + COMPOSITE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac0_ptp_ref_p, 0, + RK3588_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS, + RK3588_CLKGATE_CON(34), 10, GFLAGS), + COMPOSITE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac1_ptp_ref_p, 0, + RK3588_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS, + RK3588_CLKGATE_CON(34), 11, GFLAGS), + COMPOSITE(CLK_GMAC_125M, "clk_gmac_125m", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(83), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3588_CLKGATE_CON(35), 5, GFLAGS), + COMPOSITE(CLK_GMAC_50M, "clk_gmac_50m", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(84), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(35), 6, GFLAGS), + + COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(80), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(32), 6, GFLAGS), + COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(80), 13, 1, MFLAGS, 8, 5, DFLAGS, + RK3588_CLKGATE_CON(32), 7, GFLAGS), + COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_150m_50m_24m_p, 0, + RK3588_CLKSEL_CON(80), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(32), 0, GFLAGS), + GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", CLK_IS_CRITICAL, + RK3588_CLKGATE_CON(34), 6, GFLAGS), + GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0, + RK3588_CLKGATE_CON(32), 8, GFLAGS), + GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 0, + RK3588_CLKGATE_CON(34), 7, GFLAGS), + GATE(ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 0, + RK3588_CLKGATE_CON(34), 8, GFLAGS), + GATE(ACLK_PCIE_4L_DBI, "aclk_pcie_4l_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(32), 13, GFLAGS), + GATE(ACLK_PCIE_2L_DBI, "aclk_pcie_2l_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(32), 14, GFLAGS), + GATE(ACLK_PCIE_1L0_DBI, "aclk_pcie_1l0_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(32), 15, GFLAGS), + GATE(ACLK_PCIE_1L1_DBI, "aclk_pcie_1l1_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 0, GFLAGS), + GATE(ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 1, GFLAGS), + GATE(ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 2, GFLAGS), + GATE(ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 3, GFLAGS), + GATE(ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 4, GFLAGS), + GATE(ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 5, GFLAGS), + GATE(ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", "aclk_mmu_pcie", 0, + RK3588_CLKGATE_CON(33), 6, GFLAGS), + GATE(ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 7, GFLAGS), + GATE(ACLK_PCIE_2L_SLV, "aclk_pcie_2l_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 8, GFLAGS), + GATE(ACLK_PCIE_1L0_SLV, "aclk_pcie_1l0_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 9, GFLAGS), + GATE(ACLK_PCIE_1L1_SLV, "aclk_pcie_1l1_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 10, GFLAGS), + GATE(ACLK_PCIE_1L2_SLV, "aclk_pcie_1l2_slv", "aclk_php_root", 0, + RK3588_CLKGATE_CON(33), 11, GFLAGS), + GATE(PCLK_PCIE_4L, "pclk_pcie_4l", "pclk_php_root", 0, + RK3588_CLKGATE_CON(33), 12, GFLAGS), + GATE(PCLK_PCIE_2L, "pclk_pcie_2l", "pclk_php_root", 0, + RK3588_CLKGATE_CON(33), 13, GFLAGS), + GATE(PCLK_PCIE_1L0, "pclk_pcie_1l0", "pclk_php_root", 0, + RK3588_CLKGATE_CON(33), 14, GFLAGS), + GATE(PCLK_PCIE_1L1, "pclk_pcie_1l1", "pclk_php_root", 0, + RK3588_CLKGATE_CON(33), 15, GFLAGS), + GATE(PCLK_PCIE_1L2, "pclk_pcie_1l2", "pclk_php_root", 0, + RK3588_CLKGATE_CON(34), 0, GFLAGS), + GATE(CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 0, + RK3588_CLKGATE_CON(34), 1, GFLAGS), + GATE(CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 0, + RK3588_CLKGATE_CON(34), 2, GFLAGS), + GATE(CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 0, + RK3588_CLKGATE_CON(34), 3, GFLAGS), + GATE(CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 0, + RK3588_CLKGATE_CON(34), 4, GFLAGS), + GATE(CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 0, + RK3588_CLKGATE_CON(34), 5, GFLAGS), + GATE(CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 0, + RK3588_CLKGATE_CON(37), 0, GFLAGS), + GATE(CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 0, + RK3588_CLKGATE_CON(37), 1, GFLAGS), + GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0, + RK3588_CLKGATE_CON(37), 2, GFLAGS), + GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php_root", 0, + RK3588_CLKGATE_CON(32), 3, GFLAGS), + GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 0, + RK3588_CLKGATE_CON(32), 4, GFLAGS), + GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(32), 10, GFLAGS), + GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(32), 11, GFLAGS), + GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0, + RK3588_CLKGATE_CON(37), 4, GFLAGS), + GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0, + RK3588_CLKGATE_CON(37), 5, GFLAGS), + GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0, + RK3588_CLKGATE_CON(37), 6, GFLAGS), + GATE(ACLK_SATA0, "aclk_sata0", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(37), 7, GFLAGS), + GATE(ACLK_SATA1, "aclk_sata1", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(37), 8, GFLAGS), + GATE(ACLK_SATA2, "aclk_sata2", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(37), 9, GFLAGS), + COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(82), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(37), 10, GFLAGS), + COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(82), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3588_CLKGATE_CON(37), 11, GFLAGS), + COMPOSITE(CLK_RXOOB2, "clk_rxoob2", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(83), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(37), 12, GFLAGS), + GATE(ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php", 0, + RK3588_CLKGATE_CON(35), 7, GFLAGS), + GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0, + RK3588_CLKGATE_CON(35), 8, GFLAGS), + GATE(REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 0, + RK3588_CLKGATE_CON(35), 9, GFLAGS), + COMPOSITE(CLK_UTMI_OTG2, "clk_utmi_otg2", mux_150m_50m_24m_p, 0, + RK3588_CLKSEL_CON(84), 12, 2, MFLAGS, 8, 4, DFLAGS, + RK3588_CLKGATE_CON(35), 10, GFLAGS), + GATE(PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0", "pclk_top_root", 0, + RK3588_PHP_CLKGATE_CON(0), 5, GFLAGS), + GATE(PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1", "pclk_top_root", 0, + RK3588_PHP_CLKGATE_CON(0), 6, GFLAGS), + GATE(PCLK_PCIE_COMBO_PIPE_PHY2, "pclk_pcie_combo_pipe_phy2", "pclk_top_root", 0, + RK3588_PHP_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_PCIE_COMBO_PIPE_PHY, "pclk_pcie_combo_pipe_phy", "pclk_top_root", 0, + RK3588_PHP_CLKGATE_CON(0), 8, GFLAGS), + + /* rga */ + COMPOSITE(CLK_RGA3_1_CORE, "clk_rga3_1_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(174), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(76), 6, GFLAGS), + COMPOSITE(ACLK_RGA3_ROOT, "aclk_rga3_root", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(174), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(76), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_RGA3_ROOT, "hclk_rga3_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(174), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(76), 1, GFLAGS), + GATE(HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 0, + RK3588_CLKGATE_CON(76), 4, GFLAGS), + GATE(ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 0, + RK3588_CLKGATE_CON(76), 5, GFLAGS), + + /* vdec */ + COMPOSITE_NODIV(0, "hclk_rkvdec0_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(89), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(40), 0, GFLAGS), + COMPOSITE(0, "aclk_rkvdec0_root", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(89), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 1, GFLAGS), + COMPOSITE(ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(89), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 2, GFLAGS), + COMPOSITE(CLK_RKVDEC0_CA, "clk_rkvdec0_ca", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(90), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 7, GFLAGS), + COMPOSITE(CLK_RKVDEC0_HEVC_CA, "clk_rkvdec0_hevc_ca", gpll_cpll_npll_1000m_p, 0, + RK3588_CLKSEL_CON(90), 11, 2, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 8, GFLAGS), + COMPOSITE(CLK_RKVDEC0_CORE, "clk_rkvdec0_core", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(91), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(40), 9, GFLAGS), + COMPOSITE_NODIV(0, "hclk_rkvdec1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(93), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(41), 0, GFLAGS), + COMPOSITE(0, "aclk_rkvdec1_root", gpll_cpll_aupll_npll_p, 0, + RK3588_CLKSEL_CON(93), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(41), 1, GFLAGS), + COMPOSITE(CLK_RKVDEC1_CA, "clk_rkvdec1_ca", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(93), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(41), 6, GFLAGS), + COMPOSITE(CLK_RKVDEC1_HEVC_CA, "clk_rkvdec1_hevc_ca", gpll_cpll_npll_1000m_p, 0, + RK3588_CLKSEL_CON(94), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(41), 7, GFLAGS), + COMPOSITE(CLK_RKVDEC1_CORE, "clk_rkvdec1_core", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(94), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(41), 8, GFLAGS), + + /* sdio */ + COMPOSITE_NODIV(0, "hclk_sdio_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(172), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(75), 0, GFLAGS), + COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0, + RK3588_CLKSEL_CON(172), 8, 2, MFLAGS, 2, 6, DFLAGS, + RK3588_CLKGATE_CON(75), 3, GFLAGS), + MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RK3588_SDIO_CON0, 1), + MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RK3588_SDIO_CON1, 1), + + /* usb */ + COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(96), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(42), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_USB_ROOT, "hclk_usb_root", mux_150m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(96), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(42), 1, GFLAGS), + GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0, + RK3588_CLKGATE_CON(42), 5, GFLAGS), + GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0, + RK3588_CLKGATE_CON(42), 6, GFLAGS), + GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0, + RK3588_CLKGATE_CON(42), 8, GFLAGS), + GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0, + RK3588_CLKGATE_CON(42), 9, GFLAGS), + + /* vdpu */ + COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(44), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(44), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, + RK3588_CLKGATE_CON(44), 2, GFLAGS), + COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(99), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(44), 3, GFLAGS), + GATE(HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 4, GFLAGS), + COMPOSITE(CLK_IEP2P0_CORE, "clk_iep2p0_core", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(99), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(45), 6, GFLAGS), + GATE(HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(44), 11, GFLAGS), + GATE(HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(44), 13, GFLAGS), + GATE(HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(44), 15, GFLAGS), + GATE(HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 1, GFLAGS), + GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 3, GFLAGS), + GATE(HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 7, GFLAGS), + GATE(ACLK_RGA2, "aclk_rga2", "aclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 8, GFLAGS), + COMPOSITE(CLK_RGA2_CORE, "clk_rga2_core", gpll_cpll_npll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(100), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(45), 9, GFLAGS), + GATE(HCLK_RGA3_0, "hclk_rga3_0", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 10, GFLAGS), + GATE(ACLK_RGA3_0, "aclk_rga3_0", "aclk_vdpu_root", 0, + RK3588_CLKGATE_CON(45), 11, GFLAGS), + COMPOSITE(CLK_RGA3_0_CORE, "clk_rga3_0_core", gpll_cpll_npll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(100), 13, 3, MFLAGS, 8, 5, DFLAGS, + RK3588_CLKGATE_CON(45), 12, GFLAGS), + GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0, + RK3588_CLKGATE_CON(44), 9, GFLAGS), + + /* venc */ + COMPOSITE_NODIV(HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(104), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(48), 0, GFLAGS), + COMPOSITE(ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", gpll_cpll_npll_p, 0, + RK3588_CLKSEL_CON(104), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(48), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_RKVENC0_ROOT, "hclk_rkvenc0_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(102), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(47), 0, GFLAGS), + COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, + RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(47), 1, GFLAGS), + GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0, + RK3588_CLKGATE_CON(47), 4, GFLAGS), + GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0, + RK3588_CLKGATE_CON(47), 5, GFLAGS), + COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, + RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(47), 6, GFLAGS), + COMPOSITE(CLK_RKVENC1_CORE, "clk_rkvenc1_core", gpll_cpll_aupll_npll_p, 0, + RK3588_CLKSEL_CON(104), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(48), 6, GFLAGS), + + /* vi */ + COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(49), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(49), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(106), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(49), 2, GFLAGS), + COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(108), 14, 2, MFLAGS, + RK3588_CLKGATE_CON(51), 10, GFLAGS), + GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0, + RK3588_CLKGATE_CON(51), 11, GFLAGS), + GATE(ICLK_CSIHOST1, "iclk_csihost1", "iclk_csihost01", 0, + RK3588_CLKGATE_CON(51), 12, GFLAGS), + GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 4, GFLAGS), + GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 5, GFLAGS), + GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 6, GFLAGS), + GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 7, GFLAGS), + GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 8, GFLAGS), + GATE(PCLK_CSI_HOST_5, "pclk_csi_host_5", "pclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 9, GFLAGS), + GATE(ACLK_FISHEYE0, "aclk_fisheye0", "aclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 14, GFLAGS), + GATE(HCLK_FISHEYE0, "hclk_fisheye0", "hclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 15, GFLAGS), + COMPOSITE(CLK_FISHEYE0_CORE, "clk_fisheye0_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(50), 0, GFLAGS), + GATE(ACLK_FISHEYE1, "aclk_fisheye1", "aclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 1, GFLAGS), + GATE(HCLK_FISHEYE1, "hclk_fisheye1", "hclk_vi_root", 0, + RK3588_CLKGATE_CON(50), 2, GFLAGS), + COMPOSITE(CLK_FISHEYE1_CORE, "clk_fisheye1_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(108), 12, 2, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(50), 3, GFLAGS), + COMPOSITE(CLK_ISP0_CORE, "clk_isp0_core", gpll_cpll_aupll_spll_p, 0, + RK3588_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(49), 9, GFLAGS), + GATE(CLK_ISP0_CORE_MARVIN, "clk_isp0_core_marvin", "clk_isp0_core", 0, + RK3588_CLKGATE_CON(49), 10, GFLAGS), + GATE(CLK_ISP0_CORE_VICAP, "clk_isp0_core_vicap", "clk_isp0_core", 0, + RK3588_CLKGATE_CON(49), 11, GFLAGS), + GATE(ACLK_ISP0, "aclk_isp0", "aclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 12, GFLAGS), + GATE(HCLK_ISP0, "hclk_isp0", "hclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 13, GFLAGS), + COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(49), 6, GFLAGS), + GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 7, GFLAGS), + GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0, + RK3588_CLKGATE_CON(49), 8, GFLAGS), + + /* vo0 */ + COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(116), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(55), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(116), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(55), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VO0_S_ROOT, "hclk_vo0_s_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(116), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(55), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(116), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(55), 3, GFLAGS), + COMPOSITE_NODIV(PCLK_VO0_S_ROOT, "pclk_vo0_s_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(116), 12, 2, MFLAGS, + RK3588_CLKGATE_CON(55), 4, GFLAGS), + GATE(PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 4, GFLAGS), + GATE(PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 5, GFLAGS), + GATE(PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 0, + RK3588_CLKGATE_CON(56), 6, GFLAGS), + GATE(PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 0, + RK3588_CLKGATE_CON(56), 7, GFLAGS), + GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 8, GFLAGS), + GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 9, GFLAGS), + GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0, + RK3588_CLKGATE_CON(55), 11, GFLAGS), + GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(55), 14, GFLAGS), + GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 0, GFLAGS), + GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 1, GFLAGS), + GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(55), 10, GFLAGS), + COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(56), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S4_8CH_TX_FRAC, "clk_i2s4_8ch_tx_frac", "clk_i2s4_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(119), 0, + RK3588_CLKGATE_CON(56), 12, GFLAGS, + &rk3588_i2s4_8ch_tx_fracmux), + GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0, + RK3588_CLKGATE_CON(56), 13, GFLAGS), + COMPOSITE(CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(120), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(56), 15, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S8_8CH_TX_FRAC, "clk_i2s8_8ch_tx_frac", "clk_i2s8_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(121), 0, + RK3588_CLKGATE_CON(57), 0, GFLAGS, + &rk3588_i2s8_8ch_tx_fracmux), + GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0, + RK3588_CLKGATE_CON(57), 1, GFLAGS), + COMPOSITE(CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(122), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(57), 3, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF2_DP0_FRAC, "clk_spdif2_dp0_frac", "clk_spdif2_dp0_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(123), 0, + RK3588_CLKGATE_CON(57), 4, GFLAGS, + &rk3588_spdif2_dp0_fracmux), + GATE(MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0", 0, + RK3588_CLKGATE_CON(57), 5, GFLAGS), + GATE(MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 0, + RK3588_CLKGATE_CON(57), 6, GFLAGS), + COMPOSITE(CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(57), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF5_DP1_FRAC, "clk_spdif5_dp1_frac", "clk_spdif5_dp1_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(125), 0, + RK3588_CLKGATE_CON(57), 9, GFLAGS, + &rk3588_spdif5_dp1_fracmux), + GATE(MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1", 0, + RK3588_CLKGATE_CON(57), 10, GFLAGS), + GATE(MCLK_SPDIF5, "mclk_spdif5", "clk_spdif5_dp1", 0, + RK3588_CLKGATE_CON(57), 11, GFLAGS), + COMPOSITE_NOMUX(CLK_AUX16M_0, "clk_aux16m_0", "gpll", 0, + RK3588_CLKSEL_CON(117), 0, 8, DFLAGS, + RK3588_CLKGATE_CON(56), 2, GFLAGS), + COMPOSITE_NOMUX(CLK_AUX16M_1, "clk_aux16m_1", "gpll", 0, + RK3588_CLKSEL_CON(117), 8, 8, DFLAGS, + RK3588_CLKGATE_CON(56), 3, GFLAGS), + + /* vo1 */ + COMPOSITE_HALFDIV(CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(157), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(65), 9, GFLAGS), + COMPOSITE(ACLK_HDCP1_ROOT, "aclk_hdcp1_root", aclk_hdcp1_root_p, 0, + RK3588_CLKSEL_CON(128), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(59), 0, GFLAGS), + COMPOSITE(ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(128), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(59), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(128), 13, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 2, GFLAGS), + COMPOSITE_NODIV(HCLK_VO1_S_ROOT, "hclk_vo1_s_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(129), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 3, GFLAGS), + COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_150m_100m_24m_p, 0, + RK3588_CLKSEL_CON(129), 2, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 4, GFLAGS), + COMPOSITE_NODIV(PCLK_VO1_S_ROOT, "pclk_vo1_s_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(129), 4, 2, MFLAGS, + RK3588_CLKGATE_CON(59), 5, GFLAGS), + COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, + RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(52), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(110), 12, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 3, GFLAGS), + COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(170), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(74), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3588_CLKSEL_CON(170), 6, 2, MFLAGS, + RK3588_CLKGATE_CON(74), 2, GFLAGS), + MUX(ACLK_VOP_SUB_SRC, "aclk_vop_sub_src", aclk_vop_sub_src_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(115), 9, 1, MFLAGS), + GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(62), 0, GFLAGS), + GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0, + RK3588_CLKGATE_CON(62), 1, GFLAGS), + COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(140), 1, 2, MFLAGS, + RK3588_CLKGATE_CON(62), 2, GFLAGS), + GATE(PCLK_EDP1, "pclk_edp1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(62), 3, GFLAGS), + GATE(CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 0, + RK3588_CLKGATE_CON(62), 4, GFLAGS), + COMPOSITE_NODIV(CLK_EDP1_200M, "clk_edp1_200m", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(140), 3, 2, MFLAGS, + RK3588_CLKGATE_CON(62), 5, GFLAGS), + GATE(HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(60), 4, GFLAGS), + GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(60), 7, GFLAGS), + GATE(ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root", 0, + RK3588_CLKGATE_CON(61), 9, GFLAGS), + GATE(PCLK_HDMIRX, "pclk_hdmirx", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(61), 10, GFLAGS), + GATE(CLK_HDMIRX_REF, "clk_hdmirx_ref", "aclk_hdcp1_root", 0, + RK3588_CLKGATE_CON(61), 11, GFLAGS), + COMPOSITE(CLK_HDMIRX_AUD_SRC, "clk_hdmirx_aud_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(138), 8, 1, MFLAGS, 0, 8, DFLAGS, + RK3588_CLKGATE_CON(61), 12, GFLAGS), + COMPOSITE_FRACMUX(CLK_HDMIRX_AUD_FRAC, "clk_hdmirx_aud_frac", "clk_hdmirx_aud_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(139), 0, + RK3588_CLKGATE_CON(61), 13, GFLAGS, + &rk3588_hdmirx_aud_fracmux), + GATE(CLK_HDMIRX_AUD, "clk_hdmirx_aud", "clk_hdmirx_aud_mux", 0, + RK3588_CLKGATE_CON(61), 14, GFLAGS), + GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(60), 11, GFLAGS), + COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(133), 6, 1, MFLAGS, 1, 5, DFLAGS, + RK3588_CLKGATE_CON(60), 15, GFLAGS), + GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_hdcp1_root", 0, + RK3588_CLKGATE_CON(61), 0, GFLAGS), + GATE(PCLK_HDMITX1, "pclk_hdmitx1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(61), 2, GFLAGS), + COMPOSITE(CLK_HDMITX1_EARC, "clk_hdmitx1_earc", gpll_cpll_p, 0, + RK3588_CLKSEL_CON(136), 6, 1, MFLAGS, 1, 5, DFLAGS, + RK3588_CLKGATE_CON(61), 6, GFLAGS), + GATE(CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root", 0, + RK3588_CLKGATE_CON(61), 7, GFLAGS), + GATE(ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root", 0, + RK3588_CLKGATE_CON(60), 9, GFLAGS), + GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(60), 10, GFLAGS), + GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(59), 12, GFLAGS), + GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(59), 14, GFLAGS), + GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(59), 15, GFLAGS), + GATE(PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(65), 8, GFLAGS), + COMPOSITE(CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(155), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(65), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S10_8CH_RX_FRAC, "clk_i2s10_8ch_rx_frac", "clk_i2s10_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(156), 0, + RK3588_CLKGATE_CON(65), 6, GFLAGS, + &rk3588_i2s10_8ch_rx_fracmux), + GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0, + RK3588_CLKGATE_CON(65), 7, GFLAGS), + COMPOSITE(CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(129), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3588_CLKGATE_CON(60), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S7_8CH_RX_FRAC, "clk_i2s7_8ch_rx_frac", "clk_i2s7_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(130), 0, + RK3588_CLKGATE_CON(60), 2, GFLAGS, + &rk3588_i2s7_8ch_rx_fracmux), + GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0, + RK3588_CLKGATE_CON(60), 3, GFLAGS), + COMPOSITE(CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(153), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3588_CLKGATE_CON(65), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S9_8CH_RX_FRAC, "clk_i2s9_8ch_rx_frac", "clk_i2s9_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(154), 0, + RK3588_CLKGATE_CON(65), 2, GFLAGS, + &rk3588_i2s9_8ch_rx_fracmux), + GATE(MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 0, + RK3588_CLKGATE_CON(65), 3, GFLAGS), + COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS, + RK3588_CLKGATE_CON(62), 6, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", 0, + RK3588_CLKSEL_CON(141), 0, + RK3588_CLKGATE_CON(62), 7, GFLAGS, + &rk3588_i2s5_8ch_tx_fracmux), + GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0, + RK3588_CLKGATE_CON(62), 8, GFLAGS), + COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS, + RK3588_CLKGATE_CON(62), 13, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac", "clk_i2s6_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(145), 0, + RK3588_CLKGATE_CON(62), 14, GFLAGS, + &rk3588_i2s6_8ch_tx_fracmux), + GATE(MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx", 0, + RK3588_CLKGATE_CON(62), 15, GFLAGS), + COMPOSITE(CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(146), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 0, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", 0, + RK3588_CLKSEL_CON(147), 0, + RK3588_CLKGATE_CON(63), 1, GFLAGS, + &rk3588_i2s6_8ch_rx_fracmux), + GATE(MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx", 0, + RK3588_CLKGATE_CON(63), 2, GFLAGS), + MUX(I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout", i2s6_8ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(148), 2, 2, MFLAGS), + COMPOSITE(CLK_SPDIF3_SRC, "clk_spdif3_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(148), 9, 1, MFLAGS, 4, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF3_FRAC, "clk_spdif3_frac", "clk_spdif3_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(149), 0, + RK3588_CLKGATE_CON(63), 6, GFLAGS, + &rk3588_spdif3_fracmux), + GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0, + RK3588_CLKGATE_CON(63), 7, GFLAGS), + COMPOSITE(CLK_SPDIF4_SRC, "clk_spdif4_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(150), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 9, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF4_FRAC, "clk_spdif4_frac", "clk_spdif4_src", + CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(151), 0, + RK3588_CLKGATE_CON(63), 10, GFLAGS, + &rk3588_spdif4_fracmux), + GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0, + RK3588_CLKGATE_CON(63), 11, GFLAGS), + COMPOSITE(MCLK_SPDIFRX0, "mclk_spdifrx0", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(152), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 13, GFLAGS), + COMPOSITE(MCLK_SPDIFRX1, "mclk_spdifrx1", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(152), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(63), 15, GFLAGS), + COMPOSITE(MCLK_SPDIFRX2, "mclk_spdifrx2", gpll_cpll_aupll_p, 0, + RK3588_CLKSEL_CON(153), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(64), 1, GFLAGS), + GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0, + RK3588_CLKGATE_CON(73), 12, GFLAGS), + GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0, + RK3588_CLKGATE_CON(73), 13, GFLAGS), + GATE(PCLK_HDPTX0, "pclk_hdptx0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(72), 5, GFLAGS), + GATE(PCLK_HDPTX1, "pclk_hdptx1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(72), 6, GFLAGS), + GATE(PCLK_USBDPPHY0, "pclk_usbdpphy0", "pclk_top_root", 0, + RK3588_CLKGATE_CON(72), 2, GFLAGS), + GATE(PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root", 0, + RK3588_CLKGATE_CON(72), 4, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0, + RK3588_CLKGATE_CON(52), 8, GFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_vop_sub_src", 0, + RK3588_CLKGATE_CON(52), 9, GFLAGS), + COMPOSITE(DCLK_VOP0_SRC, "dclk_vop0_src", gpll_cpll_v0pll_aupll_p, 0, + RK3588_CLKSEL_CON(111), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(52), 10, GFLAGS), + COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0, + RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3588_CLKGATE_CON(52), 11, GFLAGS), + COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(52), 12, GFLAGS), + COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3588_CLKSEL_CON(112), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 13, GFLAGS), + COMPOSITE_NODIV(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3588_CLKSEL_CON(112), 9, 2, MFLAGS, + RK3588_CLKGATE_CON(53), 0, GFLAGS), + COMPOSITE_NODIV(DCLK_VOP2, "dclk_vop2", dclk_vop2_p, + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3588_CLKSEL_CON(112), 11, 2, MFLAGS, + RK3588_CLKGATE_CON(53), 1, GFLAGS), + COMPOSITE(DCLK_VOP3, "dclk_vop3", gpll_cpll_v0pll_aupll_p, 0, + RK3588_CLKSEL_CON(113), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(53), 2, GFLAGS), + GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vop_root", 0, + RK3588_CLKGATE_CON(53), 4, GFLAGS), + GATE(PCLK_DSIHOST1, "pclk_dsihost1", "pclk_vop_root", 0, + RK3588_CLKGATE_CON(53), 5, GFLAGS), + COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_v0pll_spll_p, 0, + RK3588_CLKSEL_CON(114), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(53), 6, GFLAGS), + COMPOSITE(CLK_DSIHOST1, "clk_dsihost1", gpll_cpll_v0pll_spll_p, 0, + RK3588_CLKSEL_CON(115), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_CLKGATE_CON(53), 7, GFLAGS), + GATE(CLK_VOP_PMU, "clk_vop_pmu", "xin24m", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(53), 8, GFLAGS), + GATE(ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root", 0, + RK3588_CLKGATE_CON(53), 10, GFLAGS), + GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(2), 8, GFLAGS), + GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(2), 15, GFLAGS), + + GATE(CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", "xin24m", 0, + RK3588_CLKGATE_CON(77), 0, GFLAGS), + GATE(CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", "xin24m", 0, + RK3588_CLKGATE_CON(77), 1, GFLAGS), + GATE(CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", "xin24m", 0, + RK3588_CLKGATE_CON(77), 2, GFLAGS), + COMPOSITE_NOMUX(CLK_REF_PIPE_PHY0_PLL_SRC, "clk_ref_pipe_phy0_pll_src", "ppll", 0, + RK3588_CLKSEL_CON(176), 0, 6, DFLAGS, + RK3588_CLKGATE_CON(77), 3, GFLAGS), + COMPOSITE_NOMUX(CLK_REF_PIPE_PHY1_PLL_SRC, "clk_ref_pipe_phy1_pll_src", "ppll", 0, + RK3588_CLKSEL_CON(176), 6, 6, DFLAGS, + RK3588_CLKGATE_CON(77), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_REF_PIPE_PHY2_PLL_SRC, "clk_ref_pipe_phy2_pll_src", "ppll", 0, + RK3588_CLKSEL_CON(177), 0, 6, DFLAGS, + RK3588_CLKGATE_CON(77), 5, GFLAGS), + MUX(CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0", clk_ref_pipe_phy0_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(177), 6, 1, MFLAGS), + MUX(CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1", clk_ref_pipe_phy1_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(177), 7, 1, MFLAGS), + MUX(CLK_REF_PIPE_PHY2, "clk_ref_pipe_phy2", clk_ref_pipe_phy2_p, CLK_SET_RATE_PARENT, + RK3588_CLKSEL_CON(177), 8, 1, MFLAGS), + + /* pmu */ + COMPOSITE(CLK_PMU1_300M_SRC, "clk_pmu1_300m_src", pmu_300m_24m_p, 0, + RK3588_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 10, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE(CLK_PMU1_400M_SRC, "clk_pmu1_400m_src", pmu_400m_24m_p, 0, + RK3588_PMU_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_50M_SRC, "clk_pmu1_50m_src", "clk_pmu1_400m_src", 0, + RK3588_PMU_CLKSEL_CON(0), 0, 4, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 0, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_100M_SRC, "clk_pmu1_100m_src", "clk_pmu1_400m_src", 0, + RK3588_PMU_CLKSEL_CON(0), 4, 3, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_200M_SRC, "clk_pmu1_200m_src", "clk_pmu1_400m_src", 0, + RK3588_PMU_CLKSEL_CON(0), 7, 3, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", hclk_pmu1_root_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(1), 6, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE_NODIV(PCLK_PMU1_ROOT, "pclk_pmu1_root", pmu_100m_50m_24m_src_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(1), 8, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(5), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", hclk_pmu_cm0_root_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(1), 10, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(0), 8, GFLAGS), + GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(5), 1, GFLAGS), + GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(5), 2, GFLAGS), + GATE(PCLK_PMU0IOC, "pclk_pmu0ioc", "pclk_pmu0_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(5), 4, GFLAGS), + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(5), 5, GFLAGS), + COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, + RK3588_PMU_CLKSEL_CON(17), 0, 1, MFLAGS, + RK3588_PMU_CLKGATE_CON(5), 6, GFLAGS), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(2), 1, GFLAGS), + COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", pmu_200m_100m_p, 0, + RK3588_PMU_CLKSEL_CON(3), 6, 1, MFLAGS, + RK3588_PMU_CLKGATE_CON(2), 2, GFLAGS), + GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_pmu1_root", 0, + RK3588_PMU_CLKGATE_CON(2), 7, GFLAGS), + COMPOSITE_NOMUX(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "cpll", 0, + RK3588_PMU_CLKSEL_CON(5), 2, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(2), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", + CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(6), 0, + RK3588_PMU_CLKGATE_CON(2), 9, GFLAGS, + &rk3588_i2s1_8ch_tx_fracmux), + GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, + RK3588_PMU_CLKGATE_CON(2), 10, GFLAGS), + COMPOSITE_NOMUX(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "cpll", 0, + RK3588_PMU_CLKSEL_CON(7), 2, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(2), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", + CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(8), 0, + RK3588_PMU_CLKGATE_CON(2), 12, GFLAGS, + &rk3588_i2s1_8ch_rx_fracmux), + GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, + RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS), + MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS), + GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS), + GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED, + RK3588_PMU_CLKGATE_CON(1), 1, GFLAGS), + GATE(CLK_PMU1, "clk_pmu1", "clk_pmu0", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(1), 3, GFLAGS), + GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0, + RK3588_PMU_CLKGATE_CON(2), 14, GFLAGS), + COMPOSITE_NODIV(MCLK_PDM0, "mclk_pdm0", mclk_pdm0_p, 0, + RK3588_PMU_CLKSEL_CON(9), 4, 1, MFLAGS, + RK3588_PMU_CLKGATE_CON(2), 15, GFLAGS), + GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0, + RK3588_PMU_CLKGATE_CON(3), 0, GFLAGS), + GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", CLK_IS_CRITICAL, + RK3588_PMU_CLKGATE_CON(0), 13, GFLAGS), + COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(0), 15, GFLAGS), + GATE(PCLK_PMU1_IOC, "pclk_pmu1_ioc", "pclk_pmu0_root", CLK_IGNORE_UNUSED, + RK3588_PMU_CLKGATE_CON(1), 5, GFLAGS), + GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(1), 12, GFLAGS), + COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", pmu_100m_50m_24m_src_p, 0, + RK3588_PMU_CLKSEL_CON(2), 9, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(1), 13, GFLAGS), + GATE(CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 0, + RK3588_PMU_CLKGATE_CON(1), 14, GFLAGS), + GATE(PCLK_PMU1TIMER, "pclk_pmu1timer", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(1), 8, GFLAGS), + COMPOSITE_NODIV(CLK_PMU1TIMER_ROOT, "clk_pmu1timer_root", pmu_24m_32k_100m_src_p, 0, + RK3588_PMU_CLKSEL_CON(2), 7, 2, MFLAGS, + RK3588_PMU_CLKGATE_CON(1), 9, GFLAGS), + GATE(CLK_PMU1TIMER0, "clk_pmu1timer0", "clk_pmu1timer_root", 0, + RK3588_PMU_CLKGATE_CON(1), 10, GFLAGS), + GATE(CLK_PMU1TIMER1, "clk_pmu1timer1", "clk_pmu1timer_root", 0, + RK3588_PMU_CLKGATE_CON(1), 11, GFLAGS), + COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "cpll", 0, + RK3588_PMU_CLKSEL_CON(3), 7, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(2), 3, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT, + RK3588_PMU_CLKSEL_CON(4), 0, + RK3588_PMU_CLKGATE_CON(2), 4, GFLAGS, + &rk3588_uart0_fracmux), + GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0, + RK3588_PMU_CLKGATE_CON(2), 5, GFLAGS), + GATE(PCLK_UART0, "pclk_uart0", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(2), 6, GFLAGS), + GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu0_root", 0, + RK3588_PMU_CLKGATE_CON(1), 6, GFLAGS), + COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0, + RK3588_PMU_CLKSEL_CON(2), 6, 1, MFLAGS, + RK3588_PMU_CLKGATE_CON(1), 7, GFLAGS), + COMPOSITE(CLK_CR_PARA, "clk_cr_para", mux_24m_ppll_spll_p, 0, + RK3588_PMU_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(4), 11, GFLAGS), + COMPOSITE(CLK_USB2PHY_HDPTXRXPHY_REF, "clk_usb2phy_hdptxrxphy_ref", mux_24m_ppll_p, + CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(14), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3588_PMU_CLKGATE_CON(4), 7, GFLAGS), + COMPOSITE(CLK_USBDPPHY_MIPIDCPPHY_REF, "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_spll_p, + CLK_IS_CRITICAL, + RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS, + RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS), + + GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0, + RK3588_PHYREF_ALT_GATE, 0, GFLAGS), + GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0, + RK3588_PHYREF_ALT_GATE, 1, GFLAGS), + GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0, + RK3588_PHYREF_ALT_GATE, 2, GFLAGS), + GATE(CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 0, + RK3588_PHYREF_ALT_GATE, 3, GFLAGS), + + GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 12, GFLAGS), + GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 14, GFLAGS), + GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0, + RK3588_CLKGATE_CON(64), 0, GFLAGS), + GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 8, GFLAGS), + GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 4, GFLAGS), + GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(63), 3, GFLAGS), + GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(62), 12, GFLAGS), + GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(65), 0, GFLAGS), + GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(60), 0, GFLAGS), + GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0, + RK3588_CLKGATE_CON(65), 4, GFLAGS), + GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0, + RK3588_CLKGATE_CON(60), 5, GFLAGS), + GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0, + RK3588_CLKGATE_CON(60), 6, GFLAGS), + GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0, + RK3588_CLKGATE_CON(57), 7, GFLAGS), + GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0, + RK3588_CLKGATE_CON(57), 2, GFLAGS), + GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0, + RK3588_CLKGATE_CON(56), 14, GFLAGS), + GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0, + RK3588_CLKGATE_CON(56), 10, GFLAGS), + GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0, + RK3588_CLKGATE_CON(55), 12, GFLAGS), + GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0, + RK3588_CLKGATE_CON(55), 13, GFLAGS), + GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0, + RK3588_CLKGATE_CON(48), 4, GFLAGS), + GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0, + RK3588_CLKGATE_CON(48), 5, GFLAGS), + GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 8, GFLAGS), + GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(45), 5, GFLAGS), + GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 10, GFLAGS), + GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 12, GFLAGS), + GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(44), 14, GFLAGS), + GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0, + RK3588_CLKGATE_CON(45), 0, GFLAGS), + GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0, + RK3588_CLKGATE_CON(45), 2, GFLAGS), + GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0, + RK3588_CLKGATE_CON(42), 7, GFLAGS), + GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 10, GFLAGS), + GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 11, GFLAGS), + GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 12, GFLAGS), + GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0, + RK3588_CLKGATE_CON(42), 13, GFLAGS), + GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0, + RK3588_CLKGATE_CON(42), 4, GFLAGS), + MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0, 1), + MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1, 1), + GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0, + RK3588_CLKGATE_CON(75), 2, GFLAGS), + GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0, + RK3588_CLKGATE_CON(41), 2, GFLAGS), + GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0, + RK3588_CLKGATE_CON(41), 3, GFLAGS), + GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0, + RK3588_CLKGATE_CON(40), 3, GFLAGS), + GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0, + RK3588_CLKGATE_CON(40), 4, GFLAGS), + GATE(CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", "clk_pipe30phy_pipe0_i", 0, + RK3588_CLKGATE_CON(39), 0, GFLAGS), + GATE(CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", "clk_pipe30phy_pipe2_i", 0, + RK3588_CLKGATE_CON(39), 1, GFLAGS), + GATE(CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", "clk_pipephy0_pipe_i", 0, + RK3588_CLKGATE_CON(38), 3, GFLAGS), + GATE(CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", "clk_pipephy1_pipe_i", 0, + RK3588_CLKGATE_CON(38), 4, GFLAGS), + GATE(CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", "clk_pipephy2_pipe_i", 0, + RK3588_CLKGATE_CON(38), 5, GFLAGS), + GATE(CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", "clk_pipephy0_pipe_i", 0, + RK3588_CLKGATE_CON(38), 6, GFLAGS), + GATE(CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", "clk_pipephy1_pipe_i", 0, + RK3588_CLKGATE_CON(38), 7, GFLAGS), + GATE(CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", "clk_pipephy2_pipe_i", 0, + RK3588_CLKGATE_CON(38), 8, GFLAGS), + GATE(CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", "clk_pipephy2_pipe_i", 0, + RK3588_CLKGATE_CON(38), 9, GFLAGS), + GATE(CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", "clk_pipephy0_pipe_g", 0, + RK3588_CLKGATE_CON(38), 13, GFLAGS), + GATE(CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", "clk_pipephy1_pipe_g", 0, + RK3588_CLKGATE_CON(38), 14, GFLAGS), + GATE(CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", "clk_pipephy2_pipe_g", 0, + RK3588_CLKGATE_CON(38), 15, GFLAGS), + GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0, + RK3588_CLKGATE_CON(31), 10, GFLAGS), + GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0, + RK3588_CLKGATE_CON(31), 11, GFLAGS), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0, + RK3588_CLKGATE_CON(31), 4, GFLAGS), + GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0, + RK3588_CLKGATE_CON(26), 5, GFLAGS), + GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0, + RK3588_CLKGATE_CON(26), 7, GFLAGS), + GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0, + RK3588_CLKGATE_CON(68), 5, GFLAGS), + GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, + RK3588_CLKGATE_CON(68), 2, GFLAGS), + + GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), + GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), + GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", 0, RK3588_CLKGATE_CON(31), 2, GFLAGS), + GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), + GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), + GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), + GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS), + GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS), + GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS), + GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS), + GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS), + GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), + GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), + GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), + GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), + GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), + GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), + GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), + GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), + GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), +}; + +static void __init rk3588_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + unsigned long clk_nr_clks; + void __iomem *reg_base; + + clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches, + ARRAY_SIZE(rk3588_clk_branches)) + 1; + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + return; + } + + rockchip_clk_register_plls(ctx, rk3588_pll_clks, + ARRAY_SIZE(rk3588_pll_clks), + RK3588_GRF_SOC_STATUS0); + + rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l", + mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), + &rk3588_cpulclk_data, rk3588_cpulclk_rates, + ARRAY_SIZE(rk3588_cpulclk_rates)); + rockchip_clk_register_armclk(ctx, ARMCLK_B01, "armclk_b01", + mux_armclkb01_p, ARRAY_SIZE(mux_armclkb01_p), + &rk3588_cpub0clk_data, rk3588_cpub0clk_rates, + ARRAY_SIZE(rk3588_cpub0clk_rates)); + rockchip_clk_register_armclk(ctx, ARMCLK_B23, "armclk_b23", + mux_armclkb23_p, ARRAY_SIZE(mux_armclkb23_p), + &rk3588_cpub1clk_data, rk3588_cpub1clk_rates, + ARRAY_SIZE(rk3588_cpub1clk_rates)); + + rockchip_clk_register_branches(ctx, rk3588_clk_branches, + ARRAY_SIZE(rk3588_clk_branches)); + + rk3588_rst_init(np, reg_base); + + rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST); + + rockchip_clk_of_add_provider(np, ctx); +} + +struct clk_rk3588_inits { + void (*inits)(struct device_node *np); +}; + +static const struct clk_rk3588_inits clk_3588_cru_init = { + .inits = rk3588_clk_init, +}; + +static const struct of_device_id clk_rk3588_match_table[] = { + { + .compatible = "rockchip,rk3588-cru", + .data = &clk_3588_cru_init, + }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_rk3588_match_table); + +static int __init clk_rk3588_probe(struct device *dev) +{ + struct device_node *np = dev->of_node; + const struct clk_rk3588_inits *init_data; + + init_data = of_device_get_match_data(dev); + if (init_data->inits) + init_data->inits(np); + + return 0; +} + +static struct driver clk_rk3588_driver = { + .probe = clk_rk3588_probe, + .name = "clk-rk3588", + .of_compatible = DRV_OF_COMPAT(clk_rk3588_match_table), +}; + +core_platform_driver(clk_rk3588_driver); diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 9e0cbadd57..aedb02a8d3 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -1,32 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> * + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> + * * based on * * samsung/clk.c * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Copyright (c) 2013 Linaro Ltd. * Author: Thomas Abraham <thomas.ab@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> #include <malloc.h> #include <linux/clk.h> +#include <linux/regmap.h> +#include <mfd/syscon.h> +#include <linux/spinlock.h> +#include <linux/rational.h> +#include <restart.h> #include "clk.h" -#include <init.h> -/** +/* * Register a clock branch. * Most clock branches have a form like * @@ -37,134 +35,386 @@ * sometimes without one of those components. */ static struct clk *rockchip_clk_register_branch(const char *name, - const char **parent_names, u8 num_parents, void __iomem *base, + const char *const *parent_names, u8 num_parents, + void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, - u8 div_shift, u8 div_width, u8 div_flags, + int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, - u8 gate_shift, u8 gate_flags, unsigned long flags - ) + u8 gate_shift, u8 gate_flags, unsigned long flags, + spinlock_t *lock) { struct clk *clk; - struct clk *mux = NULL; - struct clk *gate = NULL; - struct clk *div = NULL; + struct clk_mux *mux = NULL; + struct clk_gate *gate = NULL; + struct clk_divider *div = NULL; + int ret; if (num_parents > 1) { - mux = clk_mux_alloc(name, 0, base + muxdiv_offset, mux_shift, - mux_width, parent_names, num_parents, mux_flags); + mux = kzalloc(sizeof(*mux), GFP_KERNEL); if (!mux) return ERR_PTR(-ENOMEM); + + mux->reg = base + muxdiv_offset; + mux->shift = mux_shift; + mux->width = mux_width; + mux->flags = mux_flags; + mux->lock = lock; + mux->hw.clk.name = basprintf("%s.mux", name); + mux->hw.clk.ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops + : &clk_mux_ops; } if (gate_offset >= 0) { - gate = clk_gate_alloc(name, *parent_names, base + gate_offset, - gate_shift, flags, gate_flags); - if (!gate) - return ERR_PTR(-ENOMEM); + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) { + ret = -ENOMEM; + goto err_gate; + } + + gate->flags = gate_flags; + gate->reg = base + gate_offset; + gate->shift = gate_shift; + gate->lock = lock; + gate->hw.clk.name = basprintf("%s.gate", name); + gate->hw.clk.ops = &clk_gate_ops; } if (div_width > 0) { - div = clk_divider_alloc(name, *parent_names, 0, - base + muxdiv_offset, div_shift, div_width, div_flags); - if (!div) - return ERR_PTR(-ENOMEM); + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) { + ret = -ENOMEM; + goto err_div; + } + + div->flags = div_flags; + if (div_offset) + div->reg = base + div_offset; + else + div->reg = base + muxdiv_offset; + div->shift = div_shift; + div->width = div_width; + div->lock = lock; + div->table = div_table; + div->hw.clk.name = basprintf("%s.div", name); + div->hw.clk.ops = (div_flags & CLK_DIVIDER_READ_ONLY) + ? &clk_divider_ro_ops + : &clk_divider_ops; } clk = clk_register_composite(name, parent_names, num_parents, - mux, - div, - gate, - flags); + mux ? &mux->hw.clk : NULL, + div ? &div->hw.clk : NULL, + gate ? &gate->hw.clk : NULL, + flags); + if (IS_ERR(clk)) { + kfree(div); + kfree(gate); + return ERR_CAST(clk); + } return clk; +err_div: + kfree(gate); +err_gate: + kfree(mux); + return ERR_PTR(ret); } -static struct clk *rockchip_clk_register_frac_branch(const char *name, - const char **parent_names, u8 num_parents, void __iomem *base, - int muxdiv_offset, u8 div_flags, +struct rockchip_clk_frac { + struct clk_fractional_divider div; + struct clk_gate gate; + + struct clk_mux mux; + const struct clk_ops *mux_ops; + int mux_frac_idx; + + bool rate_change_remuxed; + int rate_change_idx; +}; + +/* + * fractional divider must set that denominator is 20 times larger than + * numerator to generate precise clock frequency. + */ +static void rockchip_fractional_approximation(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate, + unsigned long *m, unsigned long *n) +{ + struct clk_fractional_divider *fd = to_clk_fd(hw); + unsigned long p_rate, p_parent_rate; + struct clk_hw *p_parent; + unsigned long scale; + + p_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); + if ((rate * 20 > p_rate) && (p_rate % rate != 0)) { + p_parent = clk_hw_get_parent(clk_hw_get_parent(hw)); + p_parent_rate = clk_hw_get_rate(p_parent); + *parent_rate = p_parent_rate; + } + + /* + * Get rate closer to *parent_rate to guarantee there is no overflow + * for m and n. In the result it will be the nearest rate left shifted + * by (scale - fd->nwidth) bits. + */ + scale = fls_long(*parent_rate / rate - 1); + if (scale > fd->nwidth) + rate <<= scale - fd->nwidth; + + rational_best_approximation(rate, *parent_rate, + GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), + m, n); +} + +static struct clk *rockchip_clk_register_frac_branch( + struct rockchip_clk_provider *ctx, const char *name, + const char *const *parent_names, u8 num_parents, + void __iomem *base, int muxdiv_offset, u8 div_flags, int gate_offset, u8 gate_shift, u8 gate_flags, - unsigned long flags) + unsigned long flags, struct rockchip_clk_branch *child, + spinlock_t *lock) { struct clk *clk; - struct clk *gate = NULL; - struct clk *div = NULL; - - if (gate_offset >= 0) { - gate = clk_gate_alloc(name, *parent_names, base + gate_offset, - gate_shift, flags, gate_flags); - if (!gate) - return ERR_PTR(-ENOMEM); - } + struct rockchip_clk_frac *frac; + struct clk_gate *gate = NULL; + struct clk_fractional_divider *div = NULL; if (muxdiv_offset < 0) return ERR_PTR(-EINVAL); - div = clk_fractional_divider_alloc(name, *parent_names, flags, - base + muxdiv_offset, 16, 16, 0, 16, div_flags); - if (!div) + if (child && child->branch_type != branch_mux) { + pr_err("%s: fractional child clock for %s can only be a mux\n", + __func__, name); + return ERR_PTR(-EINVAL); + } + + frac = kzalloc(sizeof(*frac), GFP_KERNEL); + if (!frac) return ERR_PTR(-ENOMEM); + if (gate_offset >= 0) { + gate = &frac->gate; + gate->flags = gate_flags; + gate->reg = base + gate_offset; + gate->shift = gate_shift; + gate->lock = lock; + gate->hw.clk.ops = &clk_gate_ops; + } + + div = &frac->div; + div->flags = div_flags; + div->reg = base + muxdiv_offset; + div->mshift = 16; + div->mwidth = 16; + div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift; + div->nshift = 0; + div->nwidth = 16; + div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift; + div->lock = lock; + div->approximation = rockchip_fractional_approximation; + div->hw.clk.ops = &clk_fractional_divider_ops; + clk = clk_register_composite(name, parent_names, num_parents, - NULL, - div, - gate, - flags); + NULL, + &div->hw.clk, + gate ? &gate->hw.clk : NULL, + flags | CLK_SET_RATE_UNGATE); + if (IS_ERR(clk)) { + kfree(frac); + return ERR_CAST(clk); + } + + if (child) { + struct clk_mux *frac_mux = &frac->mux; + struct clk_init_data init; + struct clk *mux_clk; + + frac->mux_frac_idx = match_string(child->parent_names, + child->num_parents, name); + frac->mux_ops = &clk_mux_ops; + + frac_mux->reg = base + child->muxdiv_offset; + frac_mux->shift = child->mux_shift; + frac_mux->width = child->mux_width; + frac_mux->flags = child->mux_flags; + frac_mux->lock = lock; + frac_mux->hw.init = &init; + + init.name = child->name; + init.flags = child->flags | CLK_SET_RATE_PARENT; + init.ops = frac->mux_ops; + init.parent_names = child->parent_names; + init.num_parents = child->num_parents; + + mux_clk = clk_register(NULL, &frac_mux->hw); + if (IS_ERR(mux_clk)) { + kfree(frac); + return mux_clk; + } + + rockchip_clk_add_lookup(ctx, mux_clk, child->id); + + /* notifier on the fraction divider to catch rate changes */ + if (frac->mux_frac_idx >= 0) { + pr_debug("%s: found fractional parent in mux at pos %d\n", + __func__, frac->mux_frac_idx); + } else { + pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n", + __func__, name, child->name); + } + } return clk; } -static struct clk **clk_table; -static void __iomem *reg_base; -static struct clk_onecell_data clk_data; -static struct device_node *cru_node; +static struct clk *rockchip_clk_register_factor_branch(const char *name, + const char *const *parent_names, u8 num_parents, + void __iomem *base, unsigned int mult, unsigned int div, + int gate_offset, u8 gate_shift, u8 gate_flags, + unsigned long flags, spinlock_t *lock) +{ + struct clk *clk; + struct clk_gate *gate = NULL; + struct clk_fixed_factor *fix = NULL; + + /* without gate, register a simple factor clock */ + if (gate_offset == 0) { + return clk_register_fixed_factor(NULL, name, + parent_names[0], flags, mult, + div); + } + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + gate->flags = gate_flags; + gate->reg = base + gate_offset; + gate->shift = gate_shift; + gate->lock = lock; + gate->hw.clk.ops = &clk_gate_ops; + + fix = kzalloc(sizeof(*fix), GFP_KERNEL); + if (!fix) { + kfree(gate); + return ERR_PTR(-ENOMEM); + } + + fix->mult = mult; + fix->div = div; + fix->hw.clk.ops = &clk_fixed_factor_ops; + + clk = clk_register_composite(name, parent_names, num_parents, + NULL, + &fix->hw.clk, + &gate->hw.clk, flags); + if (IS_ERR(clk)) { + kfree(fix); + kfree(gate); + return ERR_CAST(clk); + } -void __init rockchip_clk_init(struct device_node *np, void __iomem *base, - unsigned long nr_clks) + return clk; +} + +struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, + void __iomem *base, + unsigned long nr_clks) { - reg_base = base; - cru_node = np; + struct rockchip_clk_provider *ctx; + struct clk **clk_table; + int i; + + ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); - clk_table = calloc(nr_clks, sizeof(struct clk *)); + clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); if (!clk_table) - pr_err("%s: could not allocate clock lookup table\n", __func__); + goto err_free; - clk_data.clks = clk_table; - clk_data.clk_num = nr_clks; - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + for (i = 0; i < nr_clks; ++i) + clk_table[i] = ERR_PTR(-ENOENT); + + ctx->reg_base = base; + ctx->clk_data.clks = clk_table; + ctx->clk_data.clk_num = nr_clks; + ctx->cru_node = np; + spin_lock_init(&ctx->lock); + + ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node, + "rockchip,grf"); + + return ctx; + +err_free: + kfree(ctx); + return ERR_PTR(-ENOMEM); +} +EXPORT_SYMBOL_GPL(rockchip_clk_init); + +void rockchip_clk_of_add_provider(struct device_node *np, + struct rockchip_clk_provider *ctx) +{ + if (of_clk_add_provider(np, of_clk_src_onecell_get, + &ctx->clk_data)) + pr_err("%s: could not register clk provider\n", __func__); } +EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider); -void rockchip_clk_add_lookup(struct clk *clk, unsigned int id) +void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, + struct clk *clk, unsigned int id) { - if (clk_table && id) - clk_table[id] = clk; + if (ctx->clk_data.clks && id) + ctx->clk_data.clks[id] = clk; } +EXPORT_SYMBOL_GPL(rockchip_clk_add_lookup); -void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list, +void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, + struct rockchip_pll_clock *list, unsigned int nr_pll, int grf_lock_offset) { struct clk *clk; int idx; for (idx = 0; idx < nr_pll; idx++, list++) { - clk = rockchip_clk_register_pll(list->type, list->name, + clk = rockchip_clk_register_pll(ctx, list->type, list->name, list->parent_names, list->num_parents, - reg_base, list->con_offset, grf_lock_offset, + list->con_offset, grf_lock_offset, list->lock_shift, list->mode_offset, list->mode_shift, list->rate_table, - list->pll_flags); + list->flags, list->pll_flags); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, list->name); continue; } - rockchip_clk_add_lookup(clk, list->id); + rockchip_clk_add_lookup(ctx, clk, list->id); + } +} +EXPORT_SYMBOL_GPL(rockchip_clk_register_plls); + +unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list, + unsigned int nr_clk) +{ + unsigned long max = 0; + unsigned int idx; + + for (idx = 0; idx < nr_clk; idx++, list++) { + if (list->id > max) + max = list->id; + if (list->child && list->child->id > max) + max = list->id; } + + return max; } +EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id); -void __init rockchip_clk_register_branches( - struct rockchip_clk_branch *list, - unsigned int nr_clk) +void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *list, + unsigned int nr_clk) { struct clk *clk = NULL; unsigned int idx; @@ -176,50 +426,89 @@ void __init rockchip_clk_register_branches( /* catch simple muxes */ switch (list->branch_type) { case branch_mux: - clk = clk_mux(list->name, flags, - reg_base + list->muxdiv_offset, list->mux_shift, - list->mux_width, list->parent_names, - list->num_parents, list->mux_flags); + clk = clk_register_mux(NULL, list->name, + list->parent_names, list->num_parents, + flags, ctx->reg_base + list->muxdiv_offset, + list->mux_shift, list->mux_width, + list->mux_flags, &ctx->lock); + break; + case branch_muxgrf: + clk = rockchip_clk_register_muxgrf(list->name, + list->parent_names, list->num_parents, + flags, ctx->grf, list->muxdiv_offset, + list->mux_shift, list->mux_width, + list->mux_flags); break; case branch_divider: if (list->div_table) - clk = clk_divider_table(list->name, - list->parent_names[0], flags, - reg_base + list->muxdiv_offset, - list->div_shift, list->div_width, - list->div_table, list->div_flags); + clk = clk_register_divider_table(NULL, + list->name, list->parent_names[0], + flags, + ctx->reg_base + list->muxdiv_offset, + list->div_shift, list->div_width, + list->div_flags, list->div_table, + &ctx->lock); else - clk = clk_divider(list->name, - list->parent_names[0], flags, - reg_base + list->muxdiv_offset, - list->div_shift, list->div_width, - list->div_flags); + clk = clk_register_divider(NULL, list->name, + list->parent_names[0], flags, + ctx->reg_base + list->muxdiv_offset, + list->div_shift, list->div_width, + list->div_flags, &ctx->lock); break; case branch_fraction_divider: - clk = rockchip_clk_register_frac_branch(list->name, + clk = rockchip_clk_register_frac_branch(ctx, list->name, list->parent_names, list->num_parents, - reg_base, list->muxdiv_offset, list->div_flags, + ctx->reg_base, list->muxdiv_offset, + list->div_flags, list->gate_offset, list->gate_shift, - list->gate_flags, flags); + list->gate_flags, flags, list->child, + &ctx->lock); + break; + case branch_half_divider: break; case branch_gate: flags |= CLK_SET_RATE_PARENT; - clk = clk_gate(list->name, list->parent_names[0], - reg_base + list->gate_offset, list->gate_shift, - flags, list->gate_flags); + clk = clk_register_gate(NULL, list->name, + list->parent_names[0], flags, + ctx->reg_base + list->gate_offset, + list->gate_shift, list->gate_flags, &ctx->lock); break; case branch_composite: clk = rockchip_clk_register_branch(list->name, list->parent_names, list->num_parents, - reg_base, list->muxdiv_offset, list->mux_shift, + ctx->reg_base, list->muxdiv_offset, + list->mux_shift, list->mux_width, list->mux_flags, - list->div_shift, list->div_width, + list->div_offset, list->div_shift, list->div_width, list->div_flags, list->div_table, list->gate_offset, list->gate_shift, - list->gate_flags, flags); + list->gate_flags, flags, &ctx->lock); break; case branch_mmc: + clk = rockchip_clk_register_mmc( + list->name, + list->parent_names, list->num_parents, + ctx->reg_base + list->muxdiv_offset, + list->div_shift + ); + break; + case branch_inverter: + clk = rockchip_clk_register_inverter( + list->name, list->parent_names, + list->num_parents, + ctx->reg_base + list->muxdiv_offset, + list->div_shift, list->div_flags, &ctx->lock); + break; + case branch_factor: + clk = rockchip_clk_register_factor_branch( + list->name, list->parent_names, + list->num_parents, ctx->reg_base, + list->div_shift, list->div_width, + list->gate_offset, list->gate_shift, + list->gate_flags, flags, &ctx->lock); + break; + case branch_ddrclk: break; } @@ -236,32 +525,36 @@ void __init rockchip_clk_register_branches( continue; } - rockchip_clk_add_lookup(clk, list->id); + rockchip_clk_add_lookup(ctx, clk, list->id); } } - -void __init rockchip_clk_register_armclk(unsigned int lookup_id, - const char *name, const char **parent_names, - u8 num_parents, - const struct rockchip_cpuclk_reg_data *reg_data, - const struct rockchip_cpuclk_rate_table *rates, - int nrates) +EXPORT_SYMBOL_GPL(rockchip_clk_register_branches); + +void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, + unsigned int lookup_id, + const char *name, const char *const *parent_names, + u8 num_parents, + const struct rockchip_cpuclk_reg_data *reg_data, + const struct rockchip_cpuclk_rate_table *rates, + int nrates) { struct clk *clk; clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents, - reg_data, rates, nrates, reg_base - ); + reg_data, rates, nrates, + ctx->reg_base, &ctx->lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s: %ld\n", __func__, name, PTR_ERR(clk)); return; } - rockchip_clk_add_lookup(clk, lookup_id); + rockchip_clk_add_lookup(ctx, clk, lookup_id); } +EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk); -void __init rockchip_clk_protect_critical(const char *clocks[], int nclocks) +void rockchip_clk_protect_critical(const char *const clocks[], + int nclocks) { int i; @@ -269,7 +562,34 @@ void __init rockchip_clk_protect_critical(const char *clocks[], int nclocks) for (i = 0; i < nclocks; i++) { struct clk *clk = __clk_lookup(clocks[i]); - if (clk) - clk_enable(clk); + clk_enable(clk); } } +EXPORT_SYMBOL_GPL(rockchip_clk_protect_critical); + +static void rockchip_restart(struct restart_handler *this) +{ + struct rockchip_clk_provider *ctx = + container_of(this, struct rockchip_clk_provider, restart_handler); + + writel(0xfdb9, ctx->reg_base + ctx->reg_restart); + mdelay(1000); +} + +void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, + unsigned int reg) +{ + int ret; + + ctx->restart_handler.name = "rockchip-pmu", + ctx->restart_handler.restart = rockchip_restart, + ctx->restart_handler.priority = RESTART_DEFAULT_PRIORITY, + + ctx->reg_restart = reg; + + ret = restart_handler_register(&ctx->restart_handler); + if (ret) + pr_err("%s: cannot register restart handler, %d\n", + __func__, ret); +} +EXPORT_SYMBOL_GPL(rockchip_register_restart_notifier); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index d6798a9055..a451229326 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -1,23 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> * + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> + * * based on * * samsung/clk.h * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Copyright (c) 2013 Linaro Ltd. * Author: Thomas Abraham <thomas.ab@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef CLK_ROCKCHIP_CLK_H @@ -25,31 +19,97 @@ #include <io.h> #include <linux/clk.h> - -/* To keep changes from kernel smaller */ -#define CLK_GATE_SET_TO_DISABLE CLK_GATE_INVERTED -#define CLK_GET_RATE_NOCACHE 0 +#include <restart.h> #define HIWORD_UPDATE(val, mask, shift) \ ((val) << (shift) | (mask) << ((shift) + 16)) -/* register positions shared by RK2928, RK3066 and RK3188 */ -#define RK2928_PLL_CON(x) (x * 0x4) +/* register positions shared by PX30, RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */ +#define BOOST_PLL_H_CON(x) ((x) * 0x4) +#define BOOST_CLK_CON 0x0008 +#define BOOST_BOOST_CON 0x000c +#define BOOST_SWITCH_CNT 0x0010 +#define BOOST_HIGH_PERF_CNT0 0x0014 +#define BOOST_HIGH_PERF_CNT1 0x0018 +#define BOOST_STATIS_THRESHOLD 0x001c +#define BOOST_SHORT_SWITCH_CNT 0x0020 +#define BOOST_SWITCH_THRESHOLD 0x0024 +#define BOOST_FSM_STATUS 0x0028 +#define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c) +#define BOOST_RECOVERY_MASK 0x1 +#define BOOST_RECOVERY_SHIFT 1 +#define BOOST_SW_CTRL_MASK 0x1 +#define BOOST_SW_CTRL_SHIFT 2 +#define BOOST_LOW_FREQ_EN_MASK 0x1 +#define BOOST_LOW_FREQ_EN_SHIFT 3 +#define BOOST_BUSY_STATE BIT(8) + +#define PX30_PLL_CON(x) ((x) * 0x4) +#define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200) +#define PX30_GLB_SRST_FST 0xb8 +#define PX30_GLB_SRST_SND 0xbc +#define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300) +#define PX30_MODE_CON 0xa0 +#define PX30_MISC_CON 0xa4 +#define PX30_SDMMC_CON0 0x380 +#define PX30_SDMMC_CON1 0x384 +#define PX30_SDIO_CON0 0x388 +#define PX30_SDIO_CON1 0x38c +#define PX30_EMMC_CON0 0x390 +#define PX30_EMMC_CON1 0x394 + +#define PX30_PMU_PLL_CON(x) ((x) * 0x4) +#define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40) +#define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80) +#define PX30_PMU_MODE 0x0020 + +#define RV1108_PLL_CON(x) ((x) * 0x4) +#define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60) +#define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120) +#define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180) +#define RV1108_GLB_SRST_FST 0x1c0 +#define RV1108_GLB_SRST_SND 0x1c4 +#define RV1108_MISC_CON 0x1cc +#define RV1108_SDMMC_CON0 0x1d8 +#define RV1108_SDMMC_CON1 0x1dc +#define RV1108_SDIO_CON0 0x1e0 +#define RV1108_SDIO_CON1 0x1e4 +#define RV1108_EMMC_CON0 0x1e8 +#define RV1108_EMMC_CON1 0x1ec + +#define RK2928_PLL_CON(x) ((x) * 0x4) #define RK2928_MODE_CON 0x40 -#define RK2928_CLKSEL_CON(x) (x * 0x4 + 0x44) -#define RK2928_CLKGATE_CON(x) (x * 0x4 + 0xd0) +#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) +#define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0) #define RK2928_GLB_SRST_FST 0x100 #define RK2928_GLB_SRST_SND 0x104 -#define RK2928_SOFTRST_CON(x) (x * 0x4 + 0x110) +#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110) #define RK2928_MISC_CON 0x134 +#define RK3036_SDMMC_CON0 0x144 +#define RK3036_SDMMC_CON1 0x148 +#define RK3036_SDIO_CON0 0x14c +#define RK3036_SDIO_CON1 0x150 +#define RK3036_EMMC_CON0 0x154 +#define RK3036_EMMC_CON1 0x158 + +#define RK3228_GLB_SRST_FST 0x1f0 +#define RK3228_GLB_SRST_SND 0x1f4 +#define RK3228_SDMMC_CON0 0x1c0 +#define RK3228_SDMMC_CON1 0x1c4 +#define RK3228_SDIO_CON0 0x1c8 +#define RK3228_SDIO_CON1 0x1cc +#define RK3228_EMMC_CON0 0x1d8 +#define RK3228_EMMC_CON1 0x1dc + #define RK3288_PLL_CON(x) RK2928_PLL_CON(x) #define RK3288_MODE_CON 0x50 -#define RK3288_CLKSEL_CON(x) (x * 0x4 + 0x60) -#define RK3288_CLKGATE_CON(x) (x * 0x4 + 0x160) +#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60) +#define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160) #define RK3288_GLB_SRST_FST 0x1b0 #define RK3288_GLB_SRST_SND 0x1b4 -#define RK3288_SOFTRST_CON(x) (x * 0x4 + 0x1b8) +#define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8) #define RK3288_MISC_CON 0x1e8 #define RK3288_SDMMC_CON0 0x200 #define RK3288_SDMMC_CON1 0x204 @@ -60,41 +120,247 @@ #define RK3288_EMMC_CON0 0x218 #define RK3288_EMMC_CON1 0x21c +#define RK3308_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300) +#define RK3308_GLB_SRST_FST 0xb8 +#define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400) +#define RK3308_MODE_CON 0xa0 +#define RK3308_SDMMC_CON0 0x480 +#define RK3308_SDMMC_CON1 0x484 +#define RK3308_SDIO_CON0 0x488 +#define RK3308_SDIO_CON1 0x48c +#define RK3308_EMMC_CON0 0x490 +#define RK3308_EMMC_CON1 0x494 + +#define RK3328_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200) +#define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3328_GLB_SRST_FST 0x9c +#define RK3328_GLB_SRST_SND 0x98 +#define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300) +#define RK3328_MODE_CON 0x80 +#define RK3328_MISC_CON 0x84 +#define RK3328_SDMMC_CON0 0x380 +#define RK3328_SDMMC_CON1 0x384 +#define RK3328_SDIO_CON0 0x388 +#define RK3328_SDIO_CON1 0x38c +#define RK3328_EMMC_CON0 0x390 +#define RK3328_EMMC_CON1 0x394 +#define RK3328_SDMMC_EXT_CON0 0x398 +#define RK3328_SDMMC_EXT_CON1 0x39C + +#define RK3368_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200) +#define RK3368_GLB_SRST_FST 0x280 +#define RK3368_GLB_SRST_SND 0x284 +#define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300) +#define RK3368_MISC_CON 0x380 +#define RK3368_SDMMC_CON0 0x400 +#define RK3368_SDMMC_CON1 0x404 +#define RK3368_SDIO0_CON0 0x408 +#define RK3368_SDIO0_CON1 0x40c +#define RK3368_SDIO1_CON0 0x410 +#define RK3368_SDIO1_CON1 0x414 +#define RK3368_EMMC_CON0 0x418 +#define RK3368_EMMC_CON1 0x41c + +#define RK3399_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300) +#define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400) +#define RK3399_GLB_SRST_FST 0x500 +#define RK3399_GLB_SRST_SND 0x504 +#define RK3399_GLB_CNT_TH 0x508 +#define RK3399_MISC_CON 0x50c +#define RK3399_RST_CON 0x510 +#define RK3399_RST_ST 0x514 +#define RK3399_SDMMC_CON0 0x580 +#define RK3399_SDMMC_CON1 0x584 +#define RK3399_SDIO_CON0 0x588 +#define RK3399_SDIO_CON1 0x58c + +#define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80) +#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) +#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) + +#define RK3568_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3568_MODE_CON0 0xc0 +#define RK3568_MISC_CON0 0xc4 +#define RK3568_MISC_CON1 0xc8 +#define RK3568_MISC_CON2 0xcc +#define RK3568_GLB_CNT_TH 0xd0 +#define RK3568_GLB_SRST_FST 0xd4 +#define RK3568_GLB_SRST_SND 0xd8 +#define RK3568_GLB_RST_CON 0xdc +#define RK3568_GLB_RST_ST 0xe0 +#define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300) +#define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400) +#define RK3568_SDMMC0_CON0 0x580 +#define RK3568_SDMMC0_CON1 0x584 +#define RK3568_SDMMC1_CON0 0x588 +#define RK3568_SDMMC1_CON1 0x58c +#define RK3568_SDMMC2_CON0 0x590 +#define RK3568_SDMMC2_CON1 0x594 +#define RK3568_EMMC_CON0 0x598 +#define RK3568_EMMC_CON1 0x59c + +#define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3568_PMU_MODE_CON0 0x80 +#define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) +#define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) + +#define RK3588_PHP_CRU_BASE 0x8000 +#define RK3588_PMU_CRU_BASE 0x30000 +#define RK3588_BIGCORE0_CRU_BASE 0x50000 +#define RK3588_BIGCORE1_CRU_BASE 0x52000 +#define RK3588_DSU_CRU_BASE 0x58000 + +#define RK3588_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3588_MODE_CON0 0x280 +#define RK3588_B0_PLL_MODE_CON0 (RK3588_BIGCORE0_CRU_BASE + 0x280) +#define RK3588_B1_PLL_MODE_CON0 (RK3588_BIGCORE1_CRU_BASE + 0x280) +#define RK3588_LPLL_MODE_CON0 (RK3588_DSU_CRU_BASE + 0x280) +#define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800) +#define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) +#define RK3588_GLB_CNT_TH 0xc00 +#define RK3588_GLB_SRST_FST 0xc08 +#define RK3588_GLB_SRST_SND 0xc0c +#define RK3588_GLB_RST_CON 0xc10 +#define RK3588_GLB_RST_ST 0xc04 +#define RK3588_SDIO_CON0 0xC24 +#define RK3588_SDIO_CON1 0xC28 +#define RK3588_SDMMC_CON0 0xC30 +#define RK3588_SDMMC_CON1 0xC34 + +#define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800) +#define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00) + +#define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE) +#define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300) +#define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800) +#define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00) + +#define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE) +#define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300) +#define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800) +#define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00) +#define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE) +#define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300) +#define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800) +#define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00) +#define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE) +#define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300) +#define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800) +#define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00) + enum rockchip_pll_type { + pll_rk3036, pll_rk3066, + pll_rk3328, + pll_rk3399, + pll_rk3588, + pll_rk3588_core, }; +#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ + _postdiv2, _dsmpd, _frac) \ +{ \ + .rate = _rate##U, \ + .fbdiv = _fbdiv, \ + .postdiv1 = _postdiv1, \ + .refdiv = _refdiv, \ + .postdiv2 = _postdiv2, \ + .dsmpd = _dsmpd, \ + .frac = _frac, \ +} + #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \ { \ .rate = _rate##U, \ .nr = _nr, \ .nf = _nf, \ .no = _no, \ - .bwadj = (_nf >> 1), \ + .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \ } -#define RK3066_PLL_RATE_BWADJ(_rate, _nr, _nf, _no, _bw) \ +#define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \ { \ .rate = _rate##U, \ .nr = _nr, \ .nf = _nf, \ .no = _no, \ - .bwadj = _bw, \ + .nb = _nb, \ } +#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ +{ \ + .rate = _rate##U, \ + .p = _p, \ + .m = _m, \ + .s = _s, \ + .k = _k, \ +} + +/** + * struct rockchip_clk_provider - information about clock provider + * @reg_base: virtual address for the register base. + * @clk_data: holds clock related data like clk* and number of clocks. + * @cru_node: device-node of the clock-provider + * @grf: regmap of the general-register-files syscon + * @lock: maintains exclusion between callbacks for a given clock-provider. + */ +struct rockchip_clk_provider { + void __iomem *reg_base; + struct clk_onecell_data clk_data; + struct device_node *cru_node; + struct regmap *grf; + struct restart_handler restart_handler; + unsigned int reg_restart; + spinlock_t lock; +}; + struct rockchip_pll_rate_table { unsigned long rate; - unsigned int nr; - unsigned int nf; - unsigned int no; - unsigned int bwadj; + union { + struct { + /* for RK3066 */ + unsigned int nr; + unsigned int nf; + unsigned int no; + unsigned int nb; + }; + struct { + /* for RK3036/RK3399 */ + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; + }; + struct { + /* for RK3588 */ + unsigned int m; + unsigned int p; + unsigned int s; + unsigned int k; + }; + }; }; /** - * struct rockchip_pll_clock: information about pll clock + * struct rockchip_pll_clock - information about pll clock * @id: platform specific id of the clock. * @name: name of this pll clock. - * @parent_name: name of the parent clock. + * @parent_names: name of the parent clock. + * @num_parents: number of parents * @flags: optional flags for basic clock. * @con_offset: offset of the register for configuring the PLL. * @mode_offset: offset of the register for configuring the PLL-mode. @@ -111,7 +377,7 @@ struct rockchip_pll_rate_table { struct rockchip_pll_clock { unsigned int id; const char *name; - const char **parent_names; + const char *const *parent_names; u8 num_parents; unsigned long flags; int con_offset; @@ -142,71 +408,116 @@ struct rockchip_pll_clock { .rate_table = _rtable, \ } -struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, - const char *name, const char **parent_names, u8 num_parents, - void __iomem *base, int con_offset, int grf_lock_offset, - int lock_shift, int reg_mode, int mode_shift, +struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, + enum rockchip_pll_type pll_type, + const char *name, const char *const *parent_names, + u8 num_parents, int con_offset, int grf_lock_offset, + int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, - u8 clk_pll_flags); + unsigned long flags, u8 clk_pll_flags); struct rockchip_cpuclk_clksel { int reg; u32 val; }; -#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2 +#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 6 +#define ROCKCHIP_CPUCLK_MAX_CORES 4 struct rockchip_cpuclk_rate_table { unsigned long prate; struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; + struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; + struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; }; /** - * struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock - * @core_reg: register offset of the core settings register - * @div_core_shift: core divider offset used to divide the pll value - * @div_core_mask: core divider mask + * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock + * @core_reg[]: register offset of the cores setting register + * @div_core_shift[]: cores divider offset used to divide the pll value + * @div_core_mask[]: cores divider mask + * @num_cores: number of cpu cores + * @mux_core_reg: register offset of the cores select parent + * @mux_core_alt: mux value to select alternate parent + * @mux_core_main: mux value to select main parent of core * @mux_core_shift: offset of the core multiplexer + * @mux_core_mask: core multiplexer mask */ struct rockchip_cpuclk_reg_data { - int core_reg; - u8 div_core_shift; - u32 div_core_mask; - int mux_core_reg; - u8 mux_core_shift; + int core_reg[ROCKCHIP_CPUCLK_MAX_CORES]; + u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES]; + u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES]; + int num_cores; + int mux_core_reg; + u8 mux_core_alt; + u8 mux_core_main; + u8 mux_core_shift; + u32 mux_core_mask; }; struct clk *rockchip_clk_register_cpuclk(const char *name, - const char **parent_names, u8 num_parents, + const char *const *parent_names, u8 num_parents, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, - int nrates, void __iomem *reg_base); + int nrates, void __iomem *reg_base, spinlock_t *lock); struct clk *rockchip_clk_register_mmc(const char *name, - const char **parent_names, u8 num_parents, + const char *const *parent_names, u8 num_parents, void __iomem *reg, int shift); -#define PNAME(x) static const char *x[] __initconst +/* + * DDRCLK flags, including method of setting the rate + * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate. + */ +#define ROCKCHIP_DDRCLK_SIP BIT(0) + +struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, + const char *const *parent_names, + u8 num_parents, int mux_offset, + int mux_shift, int mux_width, + int div_shift, int div_width, + int ddr_flags, void __iomem *reg_base, + spinlock_t *lock); + +#define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0) + +struct clk *rockchip_clk_register_inverter(const char *name, + const char *const *parent_names, u8 num_parents, + void __iomem *reg, int shift, int flags, + spinlock_t *lock); + +struct clk *rockchip_clk_register_muxgrf(const char *name, + const char *const *parent_names, u8 num_parents, + int flags, struct regmap *grf, int reg, + int shift, int width, int mux_flags); + +#define PNAME(x) static const char *const x[] __initconst enum rockchip_clk_branch_type { branch_composite, branch_mux, + branch_muxgrf, branch_divider, branch_fraction_divider, branch_gate, branch_mmc, + branch_inverter, + branch_factor, + branch_ddrclk, + branch_half_divider, }; struct rockchip_clk_branch { unsigned int id; enum rockchip_clk_branch_type branch_type; const char *name; - const char **parent_names; + const char *const *parent_names; u8 num_parents; unsigned long flags; int muxdiv_offset; u8 mux_shift; u8 mux_width; u8 mux_flags; + int div_offset; u8 div_shift; u8 div_width; u8 div_flags; @@ -214,6 +525,7 @@ struct rockchip_clk_branch { int gate_offset; u8 gate_shift; u8 gate_flags; + struct rockchip_clk_branch *child; }; #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ @@ -237,6 +549,28 @@ struct rockchip_clk_branch { .gate_flags = gf, \ } +#define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \ + mf, do, ds, dw, df, go, gs, gf) \ + { \ + .id = _id, \ + .branch_type = branch_composite, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = mo, \ + .mux_shift = ms, \ + .mux_width = mw, \ + .mux_flags = mf, \ + .div_offset = do, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .gate_offset = go, \ + .gate_shift = gs, \ + .gate_flags = gf, \ + } + #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \ go, gs, gf) \ { \ @@ -311,6 +645,26 @@ struct rockchip_clk_branch { .gate_offset = -1, \ } +#define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \ + mw, mf, ds, dw, df, dt) \ + { \ + .id = _id, \ + .branch_type = branch_composite, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = mo, \ + .mux_shift = ms, \ + .mux_width = mw, \ + .mux_flags = mf, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .div_table = dt, \ + .gate_offset = -1, \ + } + #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\ { \ .id = _id, \ @@ -328,6 +682,58 @@ struct rockchip_clk_branch { .gate_flags = gf, \ } +#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \ + { \ + .id = _id, \ + .branch_type = branch_fraction_divider, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .flags = f, \ + .muxdiv_offset = mo, \ + .div_shift = 16, \ + .div_width = 16, \ + .div_flags = df, \ + .gate_offset = go, \ + .gate_shift = gs, \ + .gate_flags = gf, \ + .child = ch, \ + } + +#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \ + { \ + .id = _id, \ + .branch_type = branch_fraction_divider, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .flags = f, \ + .muxdiv_offset = mo, \ + .div_shift = 16, \ + .div_width = 16, \ + .div_flags = df, \ + .gate_offset = -1, \ + .child = ch, \ + } + +#define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \ + ds, dw, df) \ + { \ + .id = _id, \ + .branch_type = branch_ddrclk, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = mo, \ + .mux_shift = ms, \ + .mux_width = mw, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .gate_offset = -1, \ + } + #define MUX(_id, cname, pnames, f, o, s, w, mf) \ { \ .id = _id, \ @@ -343,6 +749,21 @@ struct rockchip_clk_branch { .gate_offset = -1, \ } +#define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \ + { \ + .id = _id, \ + .branch_type = branch_muxgrf, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = o, \ + .mux_shift = s, \ + .mux_width = w, \ + .mux_flags = mf, \ + .gate_offset = -1, \ + } + #define DIV(_id, cname, pname, f, o, s, w, df) \ { \ .id = _id, \ @@ -397,19 +818,117 @@ struct rockchip_clk_branch { .div_shift = shift, \ } -void rockchip_clk_init(struct device_node *np, void __iomem *base, - unsigned long nr_clks); -struct regmap *rockchip_clk_get_grf(void); -void rockchip_clk_add_lookup(struct clk *clk, unsigned int id); -void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list, +#define INVERTER(_id, cname, pname, io, is, if) \ + { \ + .id = _id, \ + .branch_type = branch_inverter, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .muxdiv_offset = io, \ + .div_shift = is, \ + .div_flags = if, \ + } + +#define FACTOR(_id, cname, pname, f, fm, fd) \ + { \ + .id = _id, \ + .branch_type = branch_factor, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .flags = f, \ + .div_shift = fm, \ + .div_width = fd, \ + } + +#define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \ + { \ + .id = _id, \ + .branch_type = branch_factor, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .flags = f, \ + .div_shift = fm, \ + .div_width = fd, \ + .gate_offset = go, \ + .gate_shift = gb, \ + .gate_flags = gf, \ + } + +#define COMPOSITE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ + df, go, gs, gf) \ + { \ + .id = _id, \ + .branch_type = branch_half_divider, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = mo, \ + .mux_shift = ms, \ + .mux_width = mw, \ + .mux_flags = mf, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .gate_offset = go, \ + .gate_shift = gs, \ + .gate_flags = gf, \ + } + +/* SGRF clocks are only accessible from secure mode, so not controllable */ +#define SGRF_GATE(_id, cname, pname) \ + FACTOR(_id, cname, pname, 0, 1, 1) + +struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, + void __iomem *base, unsigned long nr_clks); +void rockchip_clk_of_add_provider(struct device_node *np, + struct rockchip_clk_provider *ctx); +void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, + struct clk *clk, unsigned int id); +unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list, + unsigned int nr_clk); +void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *list, unsigned int nr_clk); -void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list, +void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, + struct rockchip_pll_clock *pll_list, unsigned int nr_pll, int grf_lock_offset); -void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name, - const char **parent_names, u8 num_parents, +void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, + unsigned int lookup_id, const char *name, + const char *const *parent_names, u8 num_parents, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, int nrates); -void rockchip_clk_protect_critical(const char *clocks[], int nclocks); +void rockchip_clk_protect_critical(const char *const clocks[], int nclocks); +void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, + unsigned int reg); + +#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0) + +#ifdef CONFIG_RESET_CONTROLLER +void rockchip_register_softrst_lut(struct device_node *np, + const int *lookup_table, + unsigned int num_regs, + void __iomem *base, u8 flags); +#else +static inline void rockchip_register_softrst_lut(struct device_node *np, + const int *lookup_table, + unsigned int num_regs, + void __iomem *base, u8 flags) +{ +} +#endif + +static inline void rockchip_register_softrst(struct device_node *np, + unsigned int num_regs, + void __iomem *base, u8 flags) +{ + return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); +} + +void rk3588_rst_init(struct device_node *np, void __iomem *reg_base); #endif diff --git a/drivers/clk/rockchip/rst-rk3588.c b/drivers/clk/rockchip/rst-rk3588.c new file mode 100644 index 0000000000..7501b92b45 --- /dev/null +++ b/drivers/clk/rockchip/rst-rk3588.c @@ -0,0 +1,855 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Collabora Ltd. + * Author: Sebastian Reichel <sebastian.reichel@collabora.com> + */ + +#include <dt-bindings/reset/rockchip,rk3588-cru.h> +#include "clk.h" + +/* 0xFD7C0000 + 0x0A00 */ +#define RK3588_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) + +/* 0xFD7C8000 + 0x0A00 */ +#define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit) + +/* 0xFD7D0000 + 0x0A00 */ +#define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) + +/* 0xFD7F0000 + 0x0A00 */ +#define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit) + +/* mapping table for reset ID to register offset */ +static const int rk3588_register_offset[] = { + /* SOFTRST_CON01 */ + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 1, 6), + RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 1, 8), + RK3588_CRU_RESET_OFFSET(SRST_CSIPHY1, 1, 9), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M500_BIU, 1, 15), + + /* SOFTRST_CON02 */ + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M400_BIU, 2, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S200_BIU, 2, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S400_BIU, 2, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M300_BIU, 2, 3), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_INIT, 2, 8), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_CMN, 2, 9), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LANE, 2, 10), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS, 2, 11), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_INIT, 2, 15), + + /* SOFTRST_CON03 */ + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_CMN, 3, 0), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LANE, 3, 1), + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS, 3, 2), + RK3588_CRU_RESET_OFFSET(SRST_DCPHY0, 3, 11), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0, 3, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0_GRF, 3, 15), + + /* SOFTRST_CON04 */ + RK3588_CRU_RESET_OFFSET(SRST_DCPHY1, 4, 0), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1, 4, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1_GRF, 4, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CDPHY, 4, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CSIPHY, 4, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO6, 4, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_EMMCIO, 4, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_TOP, 4, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_RIGHT, 4, 11), + + /* SOFTRST_CON05 */ + RK3588_CRU_RESET_OFFSET(SRST_P_CRU, 5, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2CENTER, 5, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2VO1USB, 5, 14), + RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2CENTER, 5, 15), + + /* SOFTRST_CON06 */ + RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2VO1USB, 6, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2CENTER, 6, 1), + + /* SOFTRST_CON07 */ + RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S0_8CH, 7, 4), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 7, 7), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S2_2CH, 7, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S3_2CH, 7, 13), + + /* SOFTRST_CON08 */ + RK3588_CRU_RESET_OFFSET(SRST_M_I2S2_2CH, 8, 0), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S3_2CH, 8, 3), + RK3588_CRU_RESET_OFFSET(SRST_DAC_ACDCDIG, 8, 4), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF0, 8, 14), + + /* SOFTRST_CON09 */ + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF0, 9, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF1, 9, 2), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF1, 9, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 6), + RK3588_CRU_RESET_OFFSET(SRST_PDM1, 9, 7), + + /* SOFTRST_CON10 */ + RK3588_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 10, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 10, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_GIC, 10, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_GIC_DBG, 10, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_DMAC0, 10, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DMAC1, 10, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_DMAC2, 10, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C1, 10, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C2, 10, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C3, 10, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C4, 10, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C5, 10, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C6, 10, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C7, 10, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_I2C8, 10, 15), + + /* SOFTRST_CON11 */ + RK3588_CRU_RESET_OFFSET(SRST_I2C1, 11, 0), + RK3588_CRU_RESET_OFFSET(SRST_I2C2, 11, 1), + RK3588_CRU_RESET_OFFSET(SRST_I2C3, 11, 2), + RK3588_CRU_RESET_OFFSET(SRST_I2C4, 11, 3), + RK3588_CRU_RESET_OFFSET(SRST_I2C5, 11, 4), + RK3588_CRU_RESET_OFFSET(SRST_I2C6, 11, 5), + RK3588_CRU_RESET_OFFSET(SRST_I2C7, 11, 6), + RK3588_CRU_RESET_OFFSET(SRST_I2C8, 11, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_CAN0, 11, 8), + RK3588_CRU_RESET_OFFSET(SRST_CAN0, 11, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_CAN1, 11, 10), + RK3588_CRU_RESET_OFFSET(SRST_CAN1, 11, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_CAN2, 11, 12), + RK3588_CRU_RESET_OFFSET(SRST_CAN2, 11, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_SARADC, 11, 14), + + /* SOFTRST_CON12 */ + RK3588_CRU_RESET_OFFSET(SRST_P_TSADC, 12, 0), + RK3588_CRU_RESET_OFFSET(SRST_TSADC, 12, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_UART1, 12, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_UART2, 12, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_UART3, 12, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_UART4, 12, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_UART5, 12, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_UART6, 12, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_UART7, 12, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_UART8, 12, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_UART9, 12, 10), + RK3588_CRU_RESET_OFFSET(SRST_S_UART1, 12, 13), + + /* SOFTRST_CON13 */ + RK3588_CRU_RESET_OFFSET(SRST_S_UART2, 13, 0), + RK3588_CRU_RESET_OFFSET(SRST_S_UART3, 13, 3), + RK3588_CRU_RESET_OFFSET(SRST_S_UART4, 13, 6), + RK3588_CRU_RESET_OFFSET(SRST_S_UART5, 13, 9), + RK3588_CRU_RESET_OFFSET(SRST_S_UART6, 13, 12), + RK3588_CRU_RESET_OFFSET(SRST_S_UART7, 13, 15), + + /* SOFTRST_CON14 */ + RK3588_CRU_RESET_OFFSET(SRST_S_UART8, 14, 2), + RK3588_CRU_RESET_OFFSET(SRST_S_UART9, 14, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI0, 14, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI1, 14, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI2, 14, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI3, 14, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_SPI4, 14, 10), + RK3588_CRU_RESET_OFFSET(SRST_SPI0, 14, 11), + RK3588_CRU_RESET_OFFSET(SRST_SPI1, 14, 12), + RK3588_CRU_RESET_OFFSET(SRST_SPI2, 14, 13), + RK3588_CRU_RESET_OFFSET(SRST_SPI3, 14, 14), + RK3588_CRU_RESET_OFFSET(SRST_SPI4, 14, 15), + + /* SOFTRST_CON15 */ + RK3588_CRU_RESET_OFFSET(SRST_P_WDT0, 15, 0), + RK3588_CRU_RESET_OFFSET(SRST_T_WDT0, 15, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 15, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_PWM1, 15, 3), + RK3588_CRU_RESET_OFFSET(SRST_PWM1, 15, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_PWM2, 15, 6), + RK3588_CRU_RESET_OFFSET(SRST_PWM2, 15, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_PWM3, 15, 9), + RK3588_CRU_RESET_OFFSET(SRST_PWM3, 15, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 15, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 15, 13), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER0, 15, 15), + + /* SOFTRST_CON16 */ + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER1, 16, 0), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER2, 16, 1), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER3, 16, 2), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER4, 16, 3), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER5, 16, 4), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER6, 16, 5), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER7, 16, 6), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER8, 16, 7), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER9, 16, 8), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER10, 16, 9), + RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER11, 16, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 16, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX1, 16, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX2, 16, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_GPIO1, 16, 14), + RK3588_CRU_RESET_OFFSET(SRST_GPIO1, 16, 15), + + /* SOFTRST_CON17 */ + RK3588_CRU_RESET_OFFSET(SRST_P_GPIO2, 17, 0), + RK3588_CRU_RESET_OFFSET(SRST_GPIO2, 17, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_GPIO3, 17, 2), + RK3588_CRU_RESET_OFFSET(SRST_GPIO3, 17, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_GPIO4, 17, 4), + RK3588_CRU_RESET_OFFSET(SRST_GPIO4, 17, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DECOM, 17, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_DECOM, 17, 7), + RK3588_CRU_RESET_OFFSET(SRST_D_DECOM, 17, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_TOP, 17, 9), + RK3588_CRU_RESET_OFFSET(SRST_A_GICADB_GIC2CORE_BUS, 17, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_DFT2APB, 17, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_TOP, 17, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CDPHY, 17, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_BOT_RIGHT, 17, 15), + + /* SOFTRST_CON18 */ + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_TOP, 18, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_RIGHT, 18, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CSIPHY, 18, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO3_5, 18, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO6, 18, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_EMMCIO, 18, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 18, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 18, 9), + RK3588_CRU_RESET_OFFSET(SRST_OTPC_NS, 18, 10), + RK3588_CRU_RESET_OFFSET(SRST_OTPC_ARB, 18, 11), + + /* SOFTRST_CON19 */ + RK3588_CRU_RESET_OFFSET(SRST_P_BUSIOC, 19, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_PMUCM0_INTMUX, 19, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_DDRCM0_INTMUX, 19, 5), + + /* SOFTRST_CON20 */ + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH0, 20, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 20, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH0, 20, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 20, 3), + RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 20, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH01, 20, 5), + RK3588_CRU_RESET_OFFSET(SRST_DFI_CH0, 20, 6), + RK3588_CRU_RESET_OFFSET(SRST_SBR_CH0, 20, 7), + RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 20, 8), + RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH0, 20, 9), + RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 20, 10), + RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH0, 20, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH0, 20, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH1, 20, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 20, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH1, 20, 15), + + /* SOFTRST_CON21 */ + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 21, 0), + RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 21, 1), + RK3588_CRU_RESET_OFFSET(SRST_DFI_CH1, 21, 2), + RK3588_CRU_RESET_OFFSET(SRST_SBR_CH1, 21, 3), + RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 21, 4), + RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH1, 21, 5), + RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 21, 6), + RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH1, 21, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH1, 21, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 21, 13), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH0, 21, 14), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH0, 21, 15), + + /* SOFTRST_CON22 */ + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE0, 22, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE0, 22, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH1, 22, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH1, 22, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE1, 22, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE1, 22, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 22, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 22, 8), + + /* SOFTRST_CON23 */ + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH2, 23, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH2, 23, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH2, 23, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH2, 23, 3), + RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH2, 23, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH23, 23, 5), + RK3588_CRU_RESET_OFFSET(SRST_DFI_CH2, 23, 6), + RK3588_CRU_RESET_OFFSET(SRST_SBR_CH2, 23, 7), + RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH2, 23, 8), + RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH2, 23, 9), + RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH2, 23, 10), + RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH2, 23, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH2, 23, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH3, 23, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH3, 23, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH3, 23, 15), + + /* SOFTRST_CON24 */ + RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH3, 24, 0), + RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH3, 24, 1), + RK3588_CRU_RESET_OFFSET(SRST_DFI_CH3, 24, 2), + RK3588_CRU_RESET_OFFSET(SRST_SBR_CH3, 24, 3), + RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH3, 24, 4), + RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH3, 24, 5), + RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH3, 24, 6), + RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH3, 24, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH3, 24, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH2, 24, 13), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH2, 24, 14), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH2, 24, 15), + + /* SOFTRST_CON25 */ + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE2, 25, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE2, 25, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH3, 25, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH3, 25, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH3, 25, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE3, 25, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE3, 25, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH2, 25, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH3, 25, 8), + + /* SOFTRST_CON26 */ + RK3588_CRU_RESET_OFFSET(SRST_ISP1, 26, 3), + RK3588_CRU_RESET_OFFSET(SRST_ISP1_VICAP, 26, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_ISP1_BIU, 26, 6), + RK3588_CRU_RESET_OFFSET(SRST_H_ISP1_BIU, 26, 8), + + /* SOFTRST_CON27 */ + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1, 27, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 27, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1, 27, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1_BIU, 27, 3), + + /* SOFTRST_CON28 */ + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2, 28, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2_BIU, 28, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2, 28, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2_BIU, 28, 3), + + /* SOFTRST_CON29 */ + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN_DSU0, 29, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 29, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 29, 6), + RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER0, 29, 8), + RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER1, 29, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 29, 10), + RK3588_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 29, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_NPU_PVTM, 29, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 29, 13), + RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTM, 29, 14), + + /* SOFTRST_CON30 */ + RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 30, 0), + RK3588_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 30, 2), + RK3588_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 30, 3), + RK3588_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 30, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0, 30, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 30, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0, 30, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0_BIU, 30, 9), + + /* SOFTRST_CON31 */ + RK3588_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 31, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 31, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_EMMC, 31, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_EMMC, 31, 5), + RK3588_CRU_RESET_OFFSET(SRST_C_EMMC, 31, 6), + RK3588_CRU_RESET_OFFSET(SRST_B_EMMC, 31, 7), + RK3588_CRU_RESET_OFFSET(SRST_T_EMMC, 31, 8), + RK3588_CRU_RESET_OFFSET(SRST_S_SFC, 31, 9), + RK3588_CRU_RESET_OFFSET(SRST_H_SFC, 31, 10), + RK3588_CRU_RESET_OFFSET(SRST_H_SFC_XIP, 31, 11), + + /* SOFTRST_CON32 */ + RK3588_CRU_RESET_OFFSET(SRST_P_GRF, 32, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_DEC_BIU, 32, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 32, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_GRIDGE, 32, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 32, 9), + RK3588_CRU_RESET_OFFSET(SRST_A_GMAC0, 32, 10), + RK3588_CRU_RESET_OFFSET(SRST_A_GMAC1, 32, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_BIU, 32, 12), + RK3588_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 32, 13), + RK3588_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 32, 14), + RK3588_CRU_RESET_OFFSET(SRST_PCIE2_POWER_UP, 32, 15), + + /* SOFTRST_CON33 */ + RK3588_CRU_RESET_OFFSET(SRST_PCIE3_POWER_UP, 33, 0), + RK3588_CRU_RESET_OFFSET(SRST_PCIE4_POWER_UP, 33, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE0, 33, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE1, 33, 13), + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE2, 33, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE3, 33, 15), + + /* SOFTRST_CON34 */ + RK3588_CRU_RESET_OFFSET(SRST_P_PCIE4, 34, 0), + RK3588_CRU_RESET_OFFSET(SRST_A_PHP_GIC_ITS, 34, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PCIE, 34, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PHP, 34, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_MMU_BIU, 34, 9), + + /* SOFTRST_CON35 */ + RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG2, 35, 7), + + /* SOFTRST_CON37 */ + RK3588_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 4), + RK3588_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 5), + RK3588_CRU_RESET_OFFSET(SRST_PMALIVE2, 37, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_SATA2, 37, 9), + RK3588_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 10), + RK3588_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 11), + RK3588_CRU_RESET_OFFSET(SRST_RXOOB2, 37, 12), + RK3588_CRU_RESET_OFFSET(SRST_ASIC0, 37, 13), + RK3588_CRU_RESET_OFFSET(SRST_ASIC1, 37, 14), + RK3588_CRU_RESET_OFFSET(SRST_ASIC2, 37, 15), + + /* SOFTRST_CON40 */ + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC_CCU, 40, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0, 40, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0, 40, 4), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0_BIU, 40, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0_BIU, 40, 6), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CA, 40, 7), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_HEVC_CA, 40, 8), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CORE, 40, 9), + + /* SOFTRST_CON41 */ + RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1, 41, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1, 41, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1_BIU, 41, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1_BIU, 41, 5), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CA, 41, 6), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_HEVC_CA, 41, 7), + RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CORE, 41, 8), + + /* SOFTRST_CON42 */ + RK3588_CRU_RESET_OFFSET(SRST_A_USB_BIU, 42, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_USB_BIU, 42, 3), + RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 42, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 42, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_HOST0, 42, 10), + RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB0, 42, 11), + RK3588_CRU_RESET_OFFSET(SRST_H_HOST1, 42, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB1, 42, 13), + RK3588_CRU_RESET_OFFSET(SRST_A_USB_GRF, 42, 14), + RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST0, 42, 15), + + /* SOFTRST_CON43 */ + RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST1, 43, 0), + RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI0, 43, 1), + RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI1, 43, 2), + + /* SOFTRST_CON44 */ + RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 44, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_LOW_BIU, 44, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 44, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER_BIU, 44, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_VPU, 44, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_VPU, 44, 9), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER0, 44, 10), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER0, 44, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER1, 44, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER1, 44, 13), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER2, 44, 14), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER2, 44, 15), + + /* SOFTRST_CON45 */ + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER3, 45, 0), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER3, 45, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 45, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 45, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_IEP2P0, 45, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_IEP2P0, 45, 5), + RK3588_CRU_RESET_OFFSET(SRST_IEP2P0_CORE, 45, 6), + RK3588_CRU_RESET_OFFSET(SRST_H_RGA2, 45, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_RGA2, 45, 8), + RK3588_CRU_RESET_OFFSET(SRST_RGA2_CORE, 45, 9), + RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_0, 45, 10), + RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_0, 45, 11), + RK3588_CRU_RESET_OFFSET(SRST_RGA3_0_CORE, 45, 12), + + /* SOFTRST_CON47 */ + RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0_BIU, 47, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0_BIU, 47, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0, 47, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0, 47, 5), + RK3588_CRU_RESET_OFFSET(SRST_RKVENC0_CORE, 47, 6), + + /* SOFTRST_CON48 */ + RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1_BIU, 48, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1_BIU, 48, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1, 48, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1, 48, 5), + RK3588_CRU_RESET_OFFSET(SRST_RKVENC1_CORE, 48, 6), + + /* SOFTRST_CON49 */ + RK3588_CRU_RESET_OFFSET(SRST_A_VI_BIU, 49, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_VI_BIU, 49, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_VI_BIU, 49, 5), + RK3588_CRU_RESET_OFFSET(SRST_D_VICAP, 49, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_VICAP, 49, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_VICAP, 49, 8), + RK3588_CRU_RESET_OFFSET(SRST_ISP0, 49, 10), + RK3588_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 49, 11), + + /* SOFTRST_CON50 */ + RK3588_CRU_RESET_OFFSET(SRST_FISHEYE0, 50, 0), + RK3588_CRU_RESET_OFFSET(SRST_FISHEYE1, 50, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 50, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 50, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 50, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 50, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 50, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_5, 50, 9), + + /* SOFTRST_CON51 */ + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST0_VICAP, 51, 4), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST1_VICAP, 51, 5), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST2_VICAP, 51, 6), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST3_VICAP, 51, 7), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST4_VICAP, 51, 8), + RK3588_CRU_RESET_OFFSET(SRST_CSIHOST5_VICAP, 51, 9), + RK3588_CRU_RESET_OFFSET(SRST_CIFIN, 51, 13), + + /* SOFTRST_CON52 */ + RK3588_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 52, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_VOP_LOW_BIU, 52, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 52, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 52, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_VOP, 52, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_VOP, 52, 9), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP0, 52, 13), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE0, 52, 14), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE1, 52, 15), + + /* SOFTRST_CON53 */ + RK3588_CRU_RESET_OFFSET(SRST_D_VOP1, 53, 0), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP2, 53, 1), + RK3588_CRU_RESET_OFFSET(SRST_D_VOP3, 53, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_VOPGRF, 53, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 53, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST1, 53, 5), + RK3588_CRU_RESET_OFFSET(SRST_DSIHOST0, 53, 6), + RK3588_CRU_RESET_OFFSET(SRST_DSIHOST1, 53, 7), + RK3588_CRU_RESET_OFFSET(SRST_VOP_PMU, 53, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_VOP_CHANNEL_BIU, 53, 9), + + /* SOFTRST_CON55 */ + RK3588_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 55, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_VO0_S_BIU, 55, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 55, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_VO0_S_BIU, 55, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 55, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_VO0GRF, 55, 10), + RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY0, 55, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0, 55, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_HDCP0, 55, 13), + RK3588_CRU_RESET_OFFSET(SRST_HDCP0, 55, 15), + + /* SOFTRST_CON56 */ + RK3588_CRU_RESET_OFFSET(SRST_P_TRNG0, 56, 1), + RK3588_CRU_RESET_OFFSET(SRST_DP0, 56, 8), + RK3588_CRU_RESET_OFFSET(SRST_DP1, 56, 9), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S4_8CH, 56, 10), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S4_8CH_TX, 56, 13), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S8_8CH, 56, 14), + + /* SOFTRST_CON57 */ + RK3588_CRU_RESET_OFFSET(SRST_M_I2S8_8CH_TX, 57, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF2_DP0, 57, 2), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF2_DP0, 57, 6), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF5_DP1, 57, 7), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF5_DP1, 57, 11), + + /* SOFTRST_CON59 */ + RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9), + RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_VOP1_BIU, 59, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_VO1GRF, 59, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_VO1_S_BIU, 59, 13), + + /* SOFTRST_CON60 */ + RK3588_CRU_RESET_OFFSET(SRST_H_I2S7_8CH, 60, 0), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S7_8CH_RX, 60, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY1, 60, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1, 60, 5), + RK3588_CRU_RESET_OFFSET(SRST_H_HDCP1, 60, 6), + RK3588_CRU_RESET_OFFSET(SRST_HDCP1, 60, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_TRNG1, 60, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX0, 60, 11), + + /* SOFTRST_CON61 */ + RK3588_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 61, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX1, 61, 2), + RK3588_CRU_RESET_OFFSET(SRST_HDMITX1_REF, 61, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX, 61, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_HDMIRX, 61, 10), + RK3588_CRU_RESET_OFFSET(SRST_HDMIRX_REF, 61, 11), + + /* SOFTRST_CON62 */ + RK3588_CRU_RESET_OFFSET(SRST_P_EDP0, 62, 0), + RK3588_CRU_RESET_OFFSET(SRST_EDP0_24M, 62, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_EDP1, 62, 3), + RK3588_CRU_RESET_OFFSET(SRST_EDP1_24M, 62, 4), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S5_8CH_TX, 62, 8), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S5_8CH, 62, 12), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_TX, 62, 15), + + /* SOFTRST_CON63 */ + RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_RX, 63, 2), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S6_8CH, 63, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF3, 63, 4), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF3, 63, 7), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF4, 63, 8), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF4, 63, 11), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX0, 63, 12), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX0, 63, 13), + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX1, 63, 14), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX1, 63, 15), + + /* SOFTRST_CON64 */ + RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX2, 64, 0), + RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX2, 64, 1), + RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 64, 12), + RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY1, 64, 13), + RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE0, 64, 14), + RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE1, 64, 15), + + /* SOFTRST_CON65 */ + RK3588_CRU_RESET_OFFSET(SRST_H_I2S9_8CH, 65, 0), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S9_8CH_RX, 65, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_I2S10_8CH, 65, 4), + RK3588_CRU_RESET_OFFSET(SRST_M_I2S10_8CH_RX, 65, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_S_HDMIRX, 65, 8), + + /* SOFTRST_CON66 */ + RK3588_CRU_RESET_OFFSET(SRST_GPU, 66, 4), + RK3588_CRU_RESET_OFFSET(SRST_SYS_GPU, 66, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 66, 8), + RK3588_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 66, 9), + RK3588_CRU_RESET_OFFSET(SRST_A_M1_GPU_BIU, 66, 10), + RK3588_CRU_RESET_OFFSET(SRST_A_M2_GPU_BIU, 66, 11), + RK3588_CRU_RESET_OFFSET(SRST_A_M3_GPU_BIU, 66, 12), + RK3588_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 66, 14), + RK3588_CRU_RESET_OFFSET(SRST_P_GPU_PVTM, 66, 15), + + /* SOFTRST_CON67 */ + RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTM, 67, 0), + RK3588_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 67, 2), + RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 67, 3), + RK3588_CRU_RESET_OFFSET(SRST_GPU_JTAG, 67, 4), + + /* SOFTRST_CON68 */ + RK3588_CRU_RESET_OFFSET(SRST_A_AV1_BIU, 68, 1), + RK3588_CRU_RESET_OFFSET(SRST_A_AV1, 68, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_AV1_BIU, 68, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_AV1, 68, 5), + + /* SOFTRST_CON69 */ + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 69, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 69, 5), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 69, 6), + RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 69, 7), + RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S200_BIU, 69, 10), + RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S400_BIU, 69, 11), + RK3588_CRU_RESET_OFFSET(SRST_H_AHB2APB, 69, 12), + RK3588_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 69, 13), + RK3588_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 69, 14), + + /* SOFTRST_CON70 */ + RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 70, 0), + RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 70, 1), + RK3588_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 70, 2), + RK3588_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 70, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 70, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_AHB2APB, 70, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_WDT, 70, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_TIMER, 70, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 70, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 70, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 70, 11), + RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_CHANNEL_BIU, 70, 12), + + /* SOFTRST_CON72 */ + RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF0, 72, 1), + RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY0, 72, 2), + RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF1, 72, 3), + RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY1, 72, 4), + RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX0, 72, 5), + RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX1, 72, 6), + RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_BOT_RIGHT, 72, 7), + RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_0_GRF0, 72, 8), + RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_1_GRF0, 72, 9), + RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_0_GRF0, 72, 10), + RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_1_GRF0, 72, 11), + RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_ROPLL, 72, 12), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_LCPLL, 72, 13), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX0, 72, 14), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_ROPLL, 72, 15), // missing in TRM + + /* SOFTRST_CON73 */ + RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_LCPLL, 73, 0), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX1, 73, 1), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_HDMIRXPHY_SET, 73, 2), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0, 73, 3), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LCPLL, 73, 4), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_ROPLL, 73, 5), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS_HS, 73, 6), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1, 73, 7), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LCPLL, 73, 8), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_ROPLL, 73, 9), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS_HS, 73, 10), // missing in TRM + RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP0, 73, 12), + RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP1, 73, 13), + + /* SOFTRST_CON74 */ + RK3588_CRU_RESET_OFFSET(SRST_A_VO1USB_TOP_BIU, 74, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_VO1USB_TOP_BIU, 74, 3), + + /* SOFTRST_CON75 */ + RK3588_CRU_RESET_OFFSET(SRST_H_SDIO_BIU, 75, 1), + RK3588_CRU_RESET_OFFSET(SRST_H_SDIO, 75, 2), + RK3588_CRU_RESET_OFFSET(SRST_SDIO, 75, 3), + + /* SOFTRST_CON76 */ + RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_BIU, 76, 2), + RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_BIU, 76, 3), + RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_1, 76, 4), + RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_1, 76, 5), + RK3588_CRU_RESET_OFFSET(SRST_RGA3_1_CORE, 76, 6), + + /* SOFTRST_CON77 */ + RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY0, 77, 6), + RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY1, 77, 7), + RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY2, 77, 8), + + /* PHPTOPCRU_SOFTRST_CON00 */ + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PHPTOP_CRU, 0, 1), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF0, 0, 2), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF1, 0, 3), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF2, 0, 4), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY0, 0, 5), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY1, 0, 6), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY2, 0, 7), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE3_PHY, 0, 8), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 9), + RK3588_PHPTOPCRU_RESET_OFFSET(SRST_PCIE30_PHY, 0, 10), + + /* PMU1CRU_SOFTRST_CON00 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 10), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 11), + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 0, 12), + RK3588_PMU1CRU_RESET_OFFSET(SRST_F_PMU_CM0_CORE, 0, 13), + RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 0, 14), + + /* PMU1CRU_SOFTRST_CON01 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 1), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 1, 2), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 1, 4), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 1, 5), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 1, 6), + RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 1, 7), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1TIMER, 1, 8), + RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER0, 1, 10), + RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER1, 1, 11), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 1, 12), + RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 1, 13), + + /* PMU1CRU_SOFTRST_CON02 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 2, 1), + RK3588_PMU1CRU_RESET_OFFSET(SRST_I2C0, 2, 2), + RK3588_PMU1CRU_RESET_OFFSET(SRST_S_UART0, 2, 5), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_UART0, 2, 6), + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_I2S1_8CH, 2, 7), + RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_TX, 2, 10), + RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_RX, 2, 13), + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 2, 14), + RK3588_PMU1CRU_RESET_OFFSET(SRST_PDM0, 2, 15), + + /* PMU1CRU_SOFTRST_CON03 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 3, 0), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_INIT, 3, 11), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_CMN, 3, 12), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_LANE, 3, 13), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_INIT, 3, 15), + + /* PMU1CRU_SOFTRST_CON04 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_CMN, 4, 0), + RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_LANE, 4, 1), + RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY0, 4, 3), + RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY0, 4, 4), + RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY1, 4, 5), + RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY1, 4, 6), + RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_0, 4, 7), + RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_1, 4, 8), + RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_0, 4, 9), + RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_1, 4, 10), + + /* PMU1CRU_SOFTRST_CON05 */ + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 5, 3), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5), + RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6), + + /* SECURECRU_SOFTRST_CON00 */ + RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11), + RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_S_BIU, 0, 12), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_S_BIU, 0, 13), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14), + RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15), + + /* SECURECRU_SOFTRST_CON01 */ + RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_PKA, 1, 0), + RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_RNG, 1, 1), + RK3588_SECURECRU_RESET_OFFSET(SRST_A_CRYPTO, 1, 2), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_CRYPTO, 1, 3), + RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9), + RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10), + RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_KEYLADDER, 1, 12), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_OTPC_S, 1, 13), + RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14), + RK3588_SECURECRU_RESET_OFFSET(SRST_WDT_S, 1, 15), + + /* SECURECRU_SOFTRST_CON02 */ + RK3588_SECURECRU_RESET_OFFSET(SRST_T_WDT_S, 2, 0), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM, 2, 1), + RK3588_SECURECRU_RESET_OFFSET(SRST_A_DCF, 2, 2), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_DCF, 2, 3), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM_NS, 2, 5), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_S, 2, 15), + + /* SECURECRU_SOFTRST_CON03 */ + RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 0), + RK3588_SECURECRU_RESET_OFFSET(SRST_D_SDMMC_BUFFER, 3, 1), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC, 3, 2), + RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC_BUFFER, 3, 3), + RK3588_SECURECRU_RESET_OFFSET(SRST_SDMMC, 3, 4), + RK3588_SECURECRU_RESET_OFFSET(SRST_P_TRNG_CHK, 3, 5), + RK3588_SECURECRU_RESET_OFFSET(SRST_TRNG_S, 3, 6), +}; + +void rk3588_rst_init(struct device_node *np, void __iomem *reg_base) +{ + rockchip_register_softrst_lut(np, + rk3588_register_offset, + ARRAY_SIZE(rk3588_register_offset), + reg_base + RK3588_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); +} diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c new file mode 100644 index 0000000000..929b227154 --- /dev/null +++ b/drivers/clk/rockchip/softrst.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + */ + +#include <common.h> +#include <io.h> +#include <linux/bitops.h> +#include <linux/reset-controller.h> +#include <linux/spinlock.h> +#include "clk.h" + +struct rockchip_softrst { + struct reset_controller_dev rcdev; + const int *lut; + void __iomem *reg_base; + int num_regs; + int num_per_reg; + u8 flags; + spinlock_t lock; +}; + +static int rockchip_softrst_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rockchip_softrst *softrst = container_of(rcdev, + struct rockchip_softrst, + rcdev); + int bank, offset; + + if (softrst->lut) + id = softrst->lut[id]; + + bank = id / softrst->num_per_reg; + offset = id % softrst->num_per_reg; + + if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) { + writel(BIT(offset) | (BIT(offset) << 16), + softrst->reg_base + (bank * 4)); + } else { + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&softrst->lock, flags); + + reg = readl(softrst->reg_base + (bank * 4)); + writel(reg | BIT(offset), softrst->reg_base + (bank * 4)); + + spin_unlock_irqrestore(&softrst->lock, flags); + } + + return 0; +} + +static int rockchip_softrst_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rockchip_softrst *softrst = container_of(rcdev, + struct rockchip_softrst, + rcdev); + int bank, offset; + + if (softrst->lut) + id = softrst->lut[id]; + + bank = id / softrst->num_per_reg; + offset = id % softrst->num_per_reg; + + if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) { + writel((BIT(offset) << 16), softrst->reg_base + (bank * 4)); + } else { + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&softrst->lock, flags); + + reg = readl(softrst->reg_base + (bank * 4)); + writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4)); + + spin_unlock_irqrestore(&softrst->lock, flags); + } + + return 0; +} + +static const struct reset_control_ops rockchip_softrst_ops = { + .assert = rockchip_softrst_assert, + .deassert = rockchip_softrst_deassert, +}; + +void rockchip_register_softrst_lut(struct device_node *np, + const int *lookup_table, + unsigned int num_regs, + void __iomem *base, u8 flags) +{ + struct rockchip_softrst *softrst; + int ret; + + softrst = kzalloc(sizeof(*softrst), GFP_KERNEL); + if (!softrst) + return; + + spin_lock_init(&softrst->lock); + + softrst->reg_base = base; + softrst->lut = lookup_table; + softrst->flags = flags; + softrst->num_regs = num_regs; + softrst->num_per_reg = (flags & ROCKCHIP_SOFTRST_HIWORD_MASK) ? 16 + : 32; + + if (lookup_table) + softrst->rcdev.nr_resets = num_regs; + else + softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg; + softrst->rcdev.ops = &rockchip_softrst_ops; + softrst->rcdev.of_node = np; + ret = reset_controller_register(&softrst->rcdev); + if (ret) { + pr_err("%s: could not register reset controller, %d\n", + __func__, ret); + kfree(softrst); + } +}; +EXPORT_SYMBOL_GPL(rockchip_register_softrst_lut); |