diff options
Diffstat (limited to 'drivers/clk/socfpga/clk-gate-a10.c')
| -rw-r--r-- | drivers/clk/socfpga/clk-gate-a10.c | 51 |
1 files changed, 20 insertions, 31 deletions
diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index 07f6026c2e..b66fbcdb8c 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -1,39 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Altera Corporation. All rights reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> #include <io.h> #include <malloc.h> -#include <regmap.h> +#include <linux/regmap.h> #include <linux/clk.h> #include <linux/clkdev.h> -#include <mach/arria10-regs.h> -#include <mach/arria10-system-manager.h> +#include <mach/socfpga/arria10-regs.h> +#include <mach/socfpga/arria10-system-manager.h> #include "clk.h" -#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, clk) +#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw) /* SDMMC Group for System Manager defines */ #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x28 -static unsigned long socfpga_gate_clk_recalc_rate(struct clk *clk, +static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(clk); + struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hw); u32 div = 1, val; if (socfpgaclk->fixed_div) @@ -47,9 +36,9 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk *clk, return parent_rate / div; } -static int socfpga_clk_prepare(struct clk *clk) +static int socfpga_clk_prepare(struct clk_hw *hw) { - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(clk); + struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hw); int i; u32 hs_timing; u32 clk_phase[2]; @@ -93,12 +82,12 @@ static int socfpga_clk_prepare(struct clk *clk) return 0; } -static int clk_socfpga_enable(struct clk *clk) +static int clk_socfpga_enable(struct clk_hw *hw) { - struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(clk); + struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(hw); u32 val; - socfpga_clk_prepare(clk); + socfpga_clk_prepare(hw); val = readl(socfpga_clk->reg); val |= 1 << socfpga_clk->bit_idx; @@ -107,9 +96,9 @@ static int clk_socfpga_enable(struct clk *clk) return 0; } -static void clk_socfpga_disable(struct clk *clk) +static void clk_socfpga_disable(struct clk_hw *hw) { - struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(clk); + struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(hw); u32 val; val = readl(socfpga_clk->reg); @@ -170,8 +159,8 @@ static struct clk *__socfpga_gate_init(struct device_node *node, of_property_read_string(node, "clock-output-names", &clk_name); - socfpga_clk->clk.name = xstrdup(clk_name); - socfpga_clk->clk.ops = ops; + socfpga_clk->hw.clk.name = xstrdup(clk_name); + socfpga_clk->hw.clk.ops = ops; for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) { socfpga_clk->parent_names[i] = of_clk_get_parent_name(node, i); @@ -179,16 +168,16 @@ static struct clk *__socfpga_gate_init(struct device_node *node, break; } - socfpga_clk->clk.num_parents = i; - socfpga_clk->clk.parent_names = socfpga_clk->parent_names; + socfpga_clk->hw.clk.num_parents = i; + socfpga_clk->hw.clk.parent_names = socfpga_clk->parent_names; - rc = clk_register(&socfpga_clk->clk); + rc = bclk_register(&socfpga_clk->hw.clk); if (rc) { free(socfpga_clk); return ERR_PTR(rc); } - return &socfpga_clk->clk; + return &socfpga_clk->hw.clk; } struct clk *socfpga_a10_gate_init(struct device_node *node) |