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-rw-r--r--drivers/clk/socfpga/Makefile1
-rw-r--r--drivers/clk/socfpga/clk-gate-a10.c51
-rw-r--r--drivers/clk/socfpga/clk-periph-a10.c41
-rw-r--r--drivers/clk/socfpga/clk-pll-a10.c45
-rw-r--r--drivers/clk/socfpga/clk.c100
-rw-r--r--drivers/clk/socfpga/clk.h17
6 files changed, 103 insertions, 152 deletions
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index 341e6433e5..0a195cbf3f 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
obj-y += clk.o
obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += clk-gate-a10.o clk-periph-a10.o clk-pll-a10.o
diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
index 07f6026c2e..b66fbcdb8c 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -1,39 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Altera Corporation. All rights reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
#include <io.h>
#include <malloc.h>
-#include <regmap.h>
+#include <linux/regmap.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
-#include <mach/arria10-regs.h>
-#include <mach/arria10-system-manager.h>
+#include <mach/socfpga/arria10-regs.h>
+#include <mach/socfpga/arria10-system-manager.h>
#include "clk.h"
-#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, clk)
+#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw)
/* SDMMC Group for System Manager defines */
#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x28
-static unsigned long socfpga_gate_clk_recalc_rate(struct clk *clk,
+static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(clk);
+ struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hw);
u32 div = 1, val;
if (socfpgaclk->fixed_div)
@@ -47,9 +36,9 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk *clk,
return parent_rate / div;
}
-static int socfpga_clk_prepare(struct clk *clk)
+static int socfpga_clk_prepare(struct clk_hw *hw)
{
- struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(clk);
+ struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hw);
int i;
u32 hs_timing;
u32 clk_phase[2];
@@ -93,12 +82,12 @@ static int socfpga_clk_prepare(struct clk *clk)
return 0;
}
-static int clk_socfpga_enable(struct clk *clk)
+static int clk_socfpga_enable(struct clk_hw *hw)
{
- struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(clk);
+ struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(hw);
u32 val;
- socfpga_clk_prepare(clk);
+ socfpga_clk_prepare(hw);
val = readl(socfpga_clk->reg);
val |= 1 << socfpga_clk->bit_idx;
@@ -107,9 +96,9 @@ static int clk_socfpga_enable(struct clk *clk)
return 0;
}
-static void clk_socfpga_disable(struct clk *clk)
+static void clk_socfpga_disable(struct clk_hw *hw)
{
- struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(clk);
+ struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(hw);
u32 val;
val = readl(socfpga_clk->reg);
@@ -170,8 +159,8 @@ static struct clk *__socfpga_gate_init(struct device_node *node,
of_property_read_string(node, "clock-output-names", &clk_name);
- socfpga_clk->clk.name = xstrdup(clk_name);
- socfpga_clk->clk.ops = ops;
+ socfpga_clk->hw.clk.name = xstrdup(clk_name);
+ socfpga_clk->hw.clk.ops = ops;
for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) {
socfpga_clk->parent_names[i] = of_clk_get_parent_name(node, i);
@@ -179,16 +168,16 @@ static struct clk *__socfpga_gate_init(struct device_node *node,
break;
}
- socfpga_clk->clk.num_parents = i;
- socfpga_clk->clk.parent_names = socfpga_clk->parent_names;
+ socfpga_clk->hw.clk.num_parents = i;
+ socfpga_clk->hw.clk.parent_names = socfpga_clk->parent_names;
- rc = clk_register(&socfpga_clk->clk);
+ rc = bclk_register(&socfpga_clk->hw.clk);
if (rc) {
free(socfpga_clk);
return ERR_PTR(rc);
}
- return &socfpga_clk->clk;
+ return &socfpga_clk->hw.clk;
}
struct clk *socfpga_a10_gate_init(struct device_node *node)
diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c
index 9dd7fc9c25..f9cf40b0aa 100644
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -1,17 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Altera Corporation. All rights reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
@@ -28,12 +17,12 @@
#define SOCFPGA_MPU_FREE_CLK "mpu_free_clk"
#define SOCFPGA_NOC_FREE_CLK "noc_free_clk"
#define SOCFPGA_SDMMC_FREE_CLK "sdmmc_free_clk"
-#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, clk)
+#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw)
-static unsigned long clk_periclk_recalc_rate(struct clk *clk,
+static unsigned long clk_periclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(clk);
+ struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hw);
u32 div;
if (socfpgaclk->fixed_div) {
@@ -49,15 +38,15 @@ static unsigned long clk_periclk_recalc_rate(struct clk *clk,
return parent_rate / div;
}
-static int clk_periclk_get_parent(struct clk *clk)
+static int clk_periclk_get_parent(struct clk_hw *hw)
{
- struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(clk);
+ struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hw);
u32 clk_src;
clk_src = readl(socfpgaclk->reg);
- if (streq(clk->name, SOCFPGA_MPU_FREE_CLK) ||
- streq(clk->name, SOCFPGA_NOC_FREE_CLK) ||
- streq(clk->name, SOCFPGA_SDMMC_FREE_CLK))
+ if (streq(clk_hw_get_name(hw), SOCFPGA_MPU_FREE_CLK) ||
+ streq(clk_hw_get_name(hw), SOCFPGA_NOC_FREE_CLK) ||
+ streq(clk_hw_get_name(hw), SOCFPGA_SDMMC_FREE_CLK))
return (clk_src >> CLK_MGR_FREE_SHIFT) &
CLK_MGR_FREE_MASK;
else
@@ -109,19 +98,19 @@ static struct clk *__socfpga_periph_init(struct device_node *node,
break;
}
- periph_clk->clk.num_parents = i;
- periph_clk->clk.parent_names = periph_clk->parent_names;
+ periph_clk->hw.clk.num_parents = i;
+ periph_clk->hw.clk.parent_names = periph_clk->parent_names;
- periph_clk->clk.name = xstrdup(clk_name);
- periph_clk->clk.ops = ops;
+ periph_clk->hw.clk.name = xstrdup(clk_name);
+ periph_clk->hw.clk.ops = ops;
- rc = clk_register(&periph_clk->clk);
+ rc = bclk_register(&periph_clk->hw.clk);
if (rc) {
free(periph_clk);
return ERR_PTR(rc);
}
- return &periph_clk->clk;
+ return &periph_clk->hw.clk;
}
struct clk *socfpga_a10_periph_init(struct device_node *node)
diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c
index 4dae3e537b..2e58a2eb5d 100644
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -1,24 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Altera Corporation. All rights reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
#include <io.h>
#include <malloc.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
-#include <asm-generic/div64.h>
+#include <linux/math64.h>
#include "clk.h"
@@ -39,12 +28,12 @@
#define SOCFPGA_MAIN_PLL_CLK "main_pll"
#define SOCFPGA_PERIP_PLL_CLK "periph_pll"
-#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, clk)
+#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw)
-static unsigned long clk_pll_recalc_rate(struct clk *clk,
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct socfpga_pll *socfpgaclk = to_socfpga_clk(clk);
+ struct socfpga_pll *socfpgaclk = to_socfpga_clk(hw);
unsigned long divf, divq, reg;
unsigned long long vco_freq;
@@ -57,9 +46,9 @@ static unsigned long clk_pll_recalc_rate(struct clk *clk,
return (unsigned long)vco_freq;
}
-static int clk_pll_get_parent(struct clk *clk)
+static int clk_pll_get_parent(struct clk_hw *hw)
{
- struct socfpga_pll *socfpgaclk = to_socfpga_clk(clk);
+ struct socfpga_pll *socfpgaclk = to_socfpga_clk(hw);
u32 pll_src;
pll_src = readl(socfpgaclk->reg);
@@ -68,9 +57,9 @@ static int clk_pll_get_parent(struct clk *clk)
CLK_MGR_PLL_CLK_SRC_MASK;
}
-static int clk_socfpga_enable(struct clk *clk)
+static int clk_socfpga_enable(struct clk_hw *hw)
{
- struct socfpga_pll *socfpga_clk = to_socfpga_clk(clk);
+ struct socfpga_pll *socfpga_clk = to_socfpga_clk(hw);
u32 val;
val = readl(socfpga_clk->reg);
@@ -80,9 +69,9 @@ static int clk_socfpga_enable(struct clk *clk)
return 0;
}
-static void clk_socfpga_disable(struct clk *clk)
+static void clk_socfpga_disable(struct clk_hw *hw)
{
- struct socfpga_pll *socfpga_clk = to_socfpga_clk(clk);
+ struct socfpga_pll *socfpga_clk = to_socfpga_clk(hw);
u32 val;
val = readl(socfpga_clk->reg);
@@ -112,8 +101,8 @@ static struct clk *__socfpga_pll_init(struct device_node *node,
of_property_read_string(node, "clock-output-names", &clk_name);
- pll_clk->clk.name = xstrdup(clk_name);
- pll_clk->clk.ops = ops;
+ pll_clk->hw.clk.name = xstrdup(clk_name);
+ pll_clk->hw.clk.ops = ops;
for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) {
pll_clk->parent_names[i] = of_clk_get_parent_name(node, i);
@@ -122,19 +111,19 @@ static struct clk *__socfpga_pll_init(struct device_node *node,
}
pll_clk->bit_idx = SOCFPGA_PLL_EXT_ENA;
- pll_clk->clk.num_parents = i;
- pll_clk->clk.parent_names = pll_clk->parent_names;
+ pll_clk->hw.clk.num_parents = i;
+ pll_clk->hw.clk.parent_names = pll_clk->parent_names;
clk_pll_ops.enable = clk_socfpga_enable;
clk_pll_ops.disable = clk_socfpga_disable;
- rc = clk_register(&pll_clk->clk);
+ rc = bclk_register(&pll_clk->hw.clk);
if (rc) {
free(pll_clk);
return NULL;
}
- return &pll_clk->clk;
+ return &pll_clk->hw.clk;
}
struct clk *socfpga_a10_pll_init(struct device_node *node)
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index ade608ffe3..35de843291 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -1,14 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <common.h>
@@ -58,15 +50,15 @@
void __iomem *clk_mgr_base_addr;
struct clk_pll {
- struct clk clk;
+ struct clk_hw hw;
const char *parent;
unsigned regofs;
};
-static unsigned long clk_pll_recalc_rate(struct clk *clk,
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct clk_pll *pll = container_of(clk, struct clk_pll, clk);
+ struct clk_pll *pll = container_of(hw, struct clk_pll, hw);
unsigned long divf, divq, vco_freq, reg;
unsigned long bypass;
@@ -98,24 +90,24 @@ static struct clk *socfpga_pll_clk(struct device_node *node)
if (!pll->parent)
return ERR_PTR(-EINVAL);
- pll->clk.parent_names = &pll->parent;
- pll->clk.num_parents = 1;
- pll->clk.name = xstrdup(node->name);
- pll->clk.ops = &clk_pll_ops;
+ pll->hw.clk.parent_names = &pll->parent;
+ pll->hw.clk.num_parents = 1;
+ pll->hw.clk.name = xstrdup(node->name);
+ pll->hw.clk.ops = &clk_pll_ops;
of_property_read_u32(node, "reg", &pll->regofs);
- ret = clk_register(&pll->clk);
+ ret = bclk_register(&pll->hw.clk);
if (ret) {
free(pll);
return ERR_PTR(ret);
}
- return &pll->clk;
+ return &pll->hw.clk;
}
struct clk_periph {
- struct clk clk;
+ struct clk_hw hw;
const char *parent;
unsigned regofs;
unsigned int fixed_div;
@@ -124,10 +116,10 @@ struct clk_periph {
unsigned int shift;
};
-static unsigned long clk_periph_recalc_rate(struct clk *clk,
+static unsigned long clk_periph_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct clk_periph *periph = container_of(clk, struct clk_periph, clk);
+ struct clk_periph *periph = container_of(hw, struct clk_periph, hw);
u32 div, val;
if (periph->fixed_div) {
@@ -160,10 +152,10 @@ static struct clk *socfpga_periph_clk(struct device_node *node)
if (!periph->parent)
return ERR_PTR(-EINVAL);
- periph->clk.parent_names = &periph->parent;
- periph->clk.num_parents = 1;
- periph->clk.name = xstrdup(node->name);
- periph->clk.ops = &clk_periph_ops;
+ periph->hw.clk.parent_names = &periph->parent;
+ periph->hw.clk.num_parents = 1;
+ periph->hw.clk.name = xstrdup(node->name);
+ periph->hw.clk.ops = &clk_periph_ops;
ret = of_property_read_u32_array(node, "div-reg", div_reg, 3);
if (!ret) {
@@ -177,17 +169,17 @@ static struct clk *socfpga_periph_clk(struct device_node *node)
of_property_read_u32(node, "reg", &periph->regofs);
of_property_read_u32(node, "fixed-divider", &periph->fixed_div);
- ret = clk_register(&periph->clk);
+ ret = bclk_register(&periph->hw.clk);
if (ret) {
free(periph);
return ERR_PTR(ret);
}
- return &periph->clk;
+ return &periph->hw.clk;
}
struct clk_socfpga {
- struct clk clk;
+ struct clk_hw hw;
const char *parent;
void __iomem *reg;
void __iomem *div_reg;
@@ -198,9 +190,9 @@ struct clk_socfpga {
const char *parent_names[SOCFGPA_MAX_PARENTS];
};
-static int clk_socfpga_enable(struct clk *clk)
+static int clk_socfpga_enable(struct clk_hw *hw)
{
- struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
+ struct clk_socfpga *cs = container_of(hw, struct clk_socfpga, hw);
u32 val;
val = readl(cs->reg);
@@ -210,9 +202,9 @@ static int clk_socfpga_enable(struct clk *clk)
return 0;
}
-static void clk_socfpga_disable(struct clk *clk)
+static void clk_socfpga_disable(struct clk_hw *hw)
{
- struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
+ struct clk_socfpga *cs = container_of(hw, struct clk_socfpga, hw);
u32 val;
val = readl(cs->reg);
@@ -220,9 +212,9 @@ static void clk_socfpga_disable(struct clk *clk)
writel(val, cs->reg);
}
-static int clk_socfpga_is_enabled(struct clk *clk)
+static int clk_socfpga_is_enabled(struct clk_hw *hw)
{
- struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
+ struct clk_socfpga *cs = container_of(hw, struct clk_socfpga, hw);
u32 val;
val = readl(cs->reg);
@@ -233,10 +225,10 @@ static int clk_socfpga_is_enabled(struct clk *clk)
return 0;
}
-static unsigned long clk_socfpga_recalc_rate(struct clk *clk,
+static unsigned long clk_socfpga_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
+ struct clk_socfpga *cs = container_of(hw, struct clk_socfpga, hw);
u32 div = 1, val;
if (cs->fixed_div) {
@@ -244,7 +236,7 @@ static unsigned long clk_socfpga_recalc_rate(struct clk *clk,
} else if (cs->div_reg) {
val = readl(cs->div_reg) >> cs->shift;
val &= div_mask(cs->width);
- if (streq(clk->name, SOCFPGA_DB_CLK))
+ if (streq(clk_hw_get_name(hw), SOCFPGA_DB_CLK))
div = val + 1;
else
div = (1 << val);
@@ -253,8 +245,9 @@ static unsigned long clk_socfpga_recalc_rate(struct clk *clk,
return parent_rate / div;
}
-static int clk_socfpga_get_parent(struct clk *clk)
+static int clk_socfpga_get_parent(struct clk_hw *hw)
{
+ struct clk *clk = clk_hw_to_clk(hw);
u32 perpll_src;
u32 l4_src;
@@ -278,8 +271,9 @@ static int clk_socfpga_get_parent(struct clk *clk)
return (perpll_src >> 4) & 3;
}
-static int clk_socfpga_set_parent(struct clk *clk, u8 parent)
+static int clk_socfpga_set_parent(struct clk_hw *hw, u8 parent)
{
+ struct clk *clk = clk_hw_to_clk(hw);
u32 src_reg;
if (streq(clk->name, SOCFPGA_L4_MP_CLK)) {
@@ -359,21 +353,22 @@ static struct clk *socfpga_gate_clk(struct device_node *node)
break;
}
- cs->clk.parent_names = cs->parent_names;
- cs->clk.num_parents = i;
- cs->clk.name = xstrdup(node->name);
- cs->clk.ops = &clk_socfpga_ops;
+ cs->hw.clk.parent_names = cs->parent_names;
+ cs->hw.clk.num_parents = i;
+ cs->hw.clk.name = xstrdup(node->name);
+ cs->hw.clk.ops = &clk_socfpga_ops;
- ret = clk_register(&cs->clk);
+ ret = bclk_register(&cs->hw.clk);
if (ret) {
free(cs);
return ERR_PTR(ret);
}
- return &cs->clk;
+ return &cs->hw.clk;
}
-static void socfpga_register_clocks(struct device_d *dev, struct device_node *node)
+static void socfpga_register_clocks(struct device *dev,
+ struct device_node *node)
{
struct device_node *child;
struct clk *clk;
@@ -400,7 +395,7 @@ static void socfpga_register_clocks(struct device_d *dev, struct device_node *no
of_clk_add_provider(node, of_clk_src_simple_get, clk);
}
-static int socfpga_ccm_probe(struct device_d *dev)
+static int socfpga_ccm_probe(struct device *dev)
{
struct resource *iores;
void __iomem *regs;
@@ -413,7 +408,7 @@ static int socfpga_ccm_probe(struct device_d *dev)
clk_mgr_base_addr = regs;
- clknode = of_get_child_by_name(dev->device_node, "clocks");
+ clknode = of_get_child_by_name(dev->of_node, "clocks");
if (!clknode)
return -EINVAL;
@@ -429,15 +424,12 @@ static __maybe_unused struct of_device_id socfpga_ccm_dt_ids[] = {
/* sentinel */
}
};
+MODULE_DEVICE_TABLE(of, socfpga_ccm_dt_ids);
-static struct driver_d socfpga_ccm_driver = {
+static struct driver socfpga_ccm_driver = {
.probe = socfpga_ccm_probe,
.name = "socfpga-ccm",
.of_compatible = DRV_OF_COMPAT(socfpga_ccm_dt_ids),
};
-static int socfpga_ccm_init(void)
-{
- return platform_driver_register(&socfpga_ccm_driver);
-}
-core_initcall(socfpga_ccm_init);
+core_platform_driver(socfpga_ccm_driver);
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index cea3fcf5ee..402f714436 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -1,17 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
*
* based on drivers/clk/tegra/clk.h
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
*/
#ifndef __SOCFPGA_CLK_H
@@ -56,14 +47,14 @@ static inline struct clk *socfpga_a10_gate_init(struct device_node *node)
#endif
struct socfpga_pll {
- struct clk clk;
+ struct clk_hw hw;
void __iomem *reg;
u32 bit_idx;
const char *parent_names[SOCFPGA_MAX_PARENTS];
};
struct socfpga_gate_clk {
- struct clk clk;
+ struct clk_hw hw;
char *parent_name;
u32 fixed_div;
void __iomem *div_reg;
@@ -77,7 +68,7 @@ struct socfpga_gate_clk {
};
struct socfpga_periph_clk {
- struct clk clk;
+ struct clk_hw hw;
void __iomem *reg;
char *parent_name;
u32 fixed_div;
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-01 03:53:06 +0000