diff options
Diffstat (limited to 'drivers/clk/tegra/clk-pll-out.c')
| -rw-r--r-- | drivers/clk/tegra/clk-pll-out.c | 43 |
1 files changed, 16 insertions, 27 deletions
diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c index 52d8473d67..f14b41c04a 100644 --- a/drivers/clk/tegra/clk-pll-out.c +++ b/drivers/clk/tegra/clk-pll-out.c @@ -1,19 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> * * Based on the Linux Tegra clock code - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> @@ -29,7 +18,7 @@ #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) -static int clk_pll_out_is_enabled(struct clk *hw) +static int clk_pll_out_is_enabled(struct clk_hw *hw) { struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); u32 val = readl(pll_out->reg); @@ -41,7 +30,7 @@ static int clk_pll_out_is_enabled(struct clk *hw) return state; } -static int clk_pll_out_enable(struct clk *hw) +static int clk_pll_out_enable(struct clk_hw *hw) { struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); u32 val; @@ -56,7 +45,7 @@ static int clk_pll_out_enable(struct clk *hw) return 0; } -static void clk_pll_out_disable(struct clk *hw) +static void clk_pll_out_disable(struct clk_hw *hw) { struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); u32 val; @@ -69,28 +58,28 @@ static void clk_pll_out_disable(struct clk *hw) udelay(2); } -static unsigned long clk_pll_out_recalc_rate(struct clk *hw, +static unsigned long clk_pll_out_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); - return pll_out->div->ops->recalc_rate(pll_out->div, parent_rate); + return pll_out->div->ops->recalc_rate(clk_to_clk_hw(pll_out->div), parent_rate); } -static long clk_pll_out_round_rate(struct clk *hw, unsigned long rate, +static long clk_pll_out_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); - return pll_out->div->ops->round_rate(pll_out->div, rate, prate); + return pll_out->div->ops->round_rate(clk_to_clk_hw(pll_out->div), rate, prate); } -static int clk_pll_out_set_rate(struct clk *hw, unsigned long rate, +static int clk_pll_out_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); - return pll_out->div->ops->set_rate(pll_out->div, rate, parent_rate); + return pll_out->div->ops->set_rate(clk_to_clk_hw(pll_out->div), rate, parent_rate); } const struct clk_ops tegra_clk_pll_out_ops = { @@ -119,21 +108,21 @@ struct clk *tegra_clk_register_pll_out(const char *name, } pll_out->parent = parent_name; - pll_out->hw.name = name; - pll_out->hw.ops = &tegra_clk_pll_out_ops; - pll_out->hw.parent_names = (pll_out->parent ? &pll_out->parent : NULL); - pll_out->hw.num_parents = (pll_out->parent ? 1 : 0); + pll_out->hw.clk.name = name; + pll_out->hw.clk.ops = &tegra_clk_pll_out_ops; + pll_out->hw.clk.parent_names = (pll_out->parent ? &pll_out->parent : NULL); + pll_out->hw.clk.num_parents = (pll_out->parent ? 1 : 0); pll_out->reg = reg; pll_out->enb_bit_idx = shift + 1; pll_out->rst_bit_idx = shift; - ret = clk_register(&pll_out->hw); + ret = bclk_register(&pll_out->hw.clk); if (ret) { tegra_clk_divider_free(pll_out->div); kfree(pll_out); return ERR_PTR(ret); } - return &pll_out->hw; + return &pll_out->hw.clk; } |