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Diffstat (limited to 'drivers/ddr/fsl/ctrl_regs.c')
-rw-r--r--drivers/ddr/fsl/ctrl_regs.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 4957320d60..7c882946b9 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2008-2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP Semiconductor
@@ -284,7 +284,7 @@ static void set_timing_cfg_0(struct fsl_ddr_controller *c)
/*
* for single quad-rank DIMM and two-slot DIMMs
* to avoid ODT overlap
- */
+ */
switch (avoid_odt_overlap(c, dimm_params)) {
case 2:
twrt_mclk = 2;
@@ -1111,7 +1111,7 @@ static void set_ddr_sdram_mode_9(struct fsl_ddr_controller *c,
unsigned short esdmode5; /* Extended SDRAM mode 5 */
int rtt_park = 0;
bool four_cs = false;
- const unsigned int mclk_ps = get_memory_clk_period_ps(0);
+ const unsigned int mclk_ps = get_memory_clk_period_ps(c);
if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
(ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&