diff options
Diffstat (limited to 'drivers/ddr/fsl/main.c')
| -rw-r--r-- | drivers/ddr/fsl/main.c | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index b0df34c933..c8217a86dd 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright 2008-2014 Freescale Semiconductor, Inc. */ @@ -13,6 +13,8 @@ #include <linux/log2.h> #include "fsl_ddr.h" +enum ddr_endianess ddr_endianess; + /* * ASSUMPTIONS: * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller @@ -95,7 +97,7 @@ static unsigned long long step_assign_addresses_linear(struct fsl_ddr_info *pinf static unsigned long long step_assign_addresses_interleaved(struct fsl_ddr_info *pinfo, unsigned long long current_mem_base) { - unsigned long long total_mem, total_ctlr_mem; + unsigned long long total_mem = 0, total_ctlr_mem; unsigned long long rank_density, ctlr_density = 0; int i; @@ -238,19 +240,20 @@ static int compute_dimm_parameters(struct fsl_ddr_controller *c, struct spd_eeprom *spd, struct dimm_params *pdimm) { + unsigned int mclk_ps = get_memory_clk_period_ps(c); const memctl_options_t *popts = &c->memctl_opts; int ret = -EINVAL; memset(pdimm, 0, sizeof(*pdimm)); if (is_ddr1(popts)) - ret = ddr1_compute_dimm_parameters(c, (void *)spd, pdimm); + ret = ddr1_compute_dimm_parameters(mclk_ps, (void *)spd, pdimm); else if (is_ddr2(popts)) - ret = ddr2_compute_dimm_parameters(c, (void *)spd, pdimm); + ret = ddr2_compute_dimm_parameters(mclk_ps, (void *)spd, pdimm); else if (is_ddr3(popts)) - ret = ddr3_compute_dimm_parameters(c, (void *)spd, pdimm); + ret = ddr3_compute_dimm_parameters((void *)spd, pdimm); else if (is_ddr4(popts)) - ret = ddr4_compute_dimm_parameters(c, (void *)spd, pdimm); + ret = ddr4_compute_dimm_parameters((void *)spd, pdimm); return ret; } @@ -377,12 +380,17 @@ static unsigned long long fsl_ddr_compute(struct fsl_ddr_info *pinfo) return total_mem; } -phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo) +phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo, bool little_endian) { unsigned int i; unsigned long long total_memory; int deassert_reset = 0; + if (little_endian) + ddr_endianess = DDR_ENDIANESS_LE; + else + ddr_endianess = DDR_ENDIANESS_BE; + total_memory = fsl_ddr_compute(pinfo); /* setup 3-way interleaving before enabling DDRC */ @@ -427,14 +435,14 @@ phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo) * The following call with step = 1 returns before enabling * the controller. It has to finish with step = 2 later. */ - fsl_ddr_set_memctl_regs(c, deassert_reset ? 1 : 0); + fsl_ddr_set_memctl_regs(c, deassert_reset ? 1 : 0, little_endian); } if (deassert_reset) { for (i = 0; i < pinfo->num_ctrls; i++) { struct fsl_ddr_controller *c = &pinfo->c[i]; /* Call with step = 2 to continue initialization */ - fsl_ddr_set_memctl_regs(c, 2); + fsl_ddr_set_memctl_regs(c, 2, little_endian); } } |