diff options
Diffstat (limited to 'drivers/pci/pcie-designware-host.c')
| -rw-r--r-- | drivers/pci/pcie-designware-host.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/pci/pcie-designware-host.c b/drivers/pci/pcie-designware-host.c index 29967fbc5d..5de9cd8ea3 100644 --- a/drivers/pci/pcie-designware-host.c +++ b/drivers/pci/pcie-designware-host.c @@ -99,11 +99,11 @@ int __init dw_pcie_host_init(struct pcie_port *pp) pp->cfg0_mod_base = of_read_number(addrp, ns); pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size; } else { - dev_err(dev, "missing *config* reg space\n"); + dev_err(dev, "Missing *config* reg space\n"); } if (of_pci_range_parser_init(&parser, np)) { - dev_err(dev, "missing ranges property\n"); + dev_err(dev, "Missing ranges property\n"); return -EINVAL; } @@ -270,12 +270,12 @@ static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus, return 0; } - /* access only one slot on each root port */ + /* Access only one slot on each root port */ if (bus->number == pp->root_bus_nr && dev > 0) return 0; /* - * do not read more than one device on the bus directly attached + * Do not read more than one device on the bus directly attached * to RC's (Virtual Bridge's) DS side. */ if (bus->primary == pp->root_bus_nr && dev > 0) @@ -361,17 +361,17 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_setup(pci); - /* setup RC BARs */ + /* Setup RC BARs */ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); - /* setup bus numbers */ + /* Setup bus numbers */ val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); val &= 0xff000000; val |= 0x00010100; dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); - /* setup command register */ + /* Setup command register */ val = dw_pcie_readl_dbi(pci, PCI_COMMAND); val &= 0xffff0000; val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | @@ -400,7 +400,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); - /* program correct class for RC */ + /* Program correct class for RC */ dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); |