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path: root/drivers/usb/dwc3/core.c
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Diffstat (limited to 'drivers/usb/dwc3/core.c')
-rw-r--r--drivers/usb/dwc3/core.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 2e7031a348..60fd6318db 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -663,6 +663,25 @@ static void dwc3_check_params(struct dwc3 *dwc)
}
}
+static void dwc3_coresoft_reset(struct dwc3 *dwc)
+{
+ u32 reg;
+
+ reg = dwc3_readl(dwc->regs, DWC3_GCTL);
+ reg |= DWC3_GCTL_CORESOFTRESET;
+ dwc3_writel(dwc->regs, DWC3_GCTL, reg);
+
+ /*
+ * Similar reset sequence in U-Boot has a 100ms delay here. In
+ * practice reset sequence seem to work as expected even
+ * without a delay.
+ */
+
+ reg = dwc3_readl(dwc->regs, DWC3_GCTL);
+ reg &= ~DWC3_GCTL_CORESOFTRESET;
+ dwc3_writel(dwc->regs, DWC3_GCTL, reg);
+}
+
static int dwc3_probe(struct device_d *dev)
{
struct dwc3 *dwc;
@@ -695,6 +714,8 @@ static int dwc3_probe(struct device_d *dev)
if (ret)
return ret;
+ dwc3_coresoft_reset(dwc);
+
dwc3_cache_hwparams(dwc);
ret = dwc3_core_init(dwc);