diff options
Diffstat (limited to 'drivers')
177 files changed, 5703 insertions, 543 deletions
diff --git a/drivers/Kconfig b/drivers/Kconfig index 5984ccca2c..3236696564 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -31,5 +31,6 @@ source "drivers/pci/Kconfig" source "drivers/rtc/Kconfig" source "drivers/firmware/Kconfig" source "drivers/phy/Kconfig" +source "drivers/crypto/Kconfig" endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 8a8c8c44bd..a4467a0e79 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -31,3 +31,4 @@ obj-y += rtc/ obj-$(CONFIG_FIRMWARE) += firmware/ obj-$(CONFIG_GENERIC_PHY) += phy/ obj-$(CONFIG_HAB) += hab/ +obj-$(CONFIG_CRYPTO_HW) += crypto/ diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 4e42180d9e..c31b337ba2 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -659,15 +659,17 @@ int ahci_add_host(struct ahci_device *ahci) static int ahci_probe(struct device_d *dev) { + struct resource *iores; struct ahci_device *ahci; void __iomem *regs; int ret; ahci = xzalloc(sizeof(*ahci)); - regs = dev_request_mem_region(dev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + regs = IOMEM(iores->start); ahci->dev = dev; ahci->mmio_base = regs; diff --git a/drivers/ata/intf_platform_ide.c b/drivers/ata/intf_platform_ide.c index d0f7984a2c..6e74bfb089 100644 --- a/drivers/ata/intf_platform_ide.c +++ b/drivers/ata/intf_platform_ide.c @@ -80,6 +80,7 @@ static void platform_ide_setup_port(void *reg_base, void *alt_base, static int platform_ide_probe(struct device_d *dev) { + struct resource *iores; int rc; struct ide_port_info *pdata = dev->platform_data; struct ide_port *ide; @@ -102,11 +103,17 @@ static int platform_ide_probe(struct device_d *dev) return -EINVAL; } - reg_base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + reg_base = IOMEM(iores->start); if (!IS_ERR(reg_base)) { mmio = 1; - alt_base = dev_request_mem_region(dev, 1); + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + alt_base = IOMEM(iores->start); if (IS_ERR(alt_base)) alt_base = NULL; } else { diff --git a/drivers/ata/pata-imx.c b/drivers/ata/pata-imx.c index d8deba1461..842957331e 100644 --- a/drivers/ata/pata-imx.c +++ b/drivers/ata/pata-imx.c @@ -153,6 +153,7 @@ static int pata_imx_detect(struct device_d *dev) static int imx_pata_probe(struct device_d *dev) { + struct resource *iores; struct ide_port *ide; struct clk *clk; void __iomem *base; @@ -160,9 +161,10 @@ static int imx_pata_probe(struct device_d *dev) const char *devname = NULL; ide = xzalloc(sizeof(*ide)); - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); clk = clk_get(dev, NULL); if (IS_ERR(clk)) { diff --git a/drivers/ata/sata-imx.c b/drivers/ata/sata-imx.c index 612762e229..6a601956db 100644 --- a/drivers/ata/sata-imx.c +++ b/drivers/ata/sata-imx.c @@ -84,6 +84,7 @@ static int imx_sata_init_1ms(struct imx_ahci *imx_ahci) static int imx_sata_probe(struct device_d *dev) { + struct resource *iores; struct imx_ahci *imx_ahci; struct imx_sata_data *data; int ret; @@ -100,9 +101,10 @@ static int imx_sata_probe(struct device_d *dev) goto err_free; } - imx_ahci->ahci.mmio_base = dev_request_mem_region(dev, 0); - if (IS_ERR(imx_ahci->ahci.mmio_base)) - return PTR_ERR(imx_ahci->ahci.mmio_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + imx_ahci->ahci.mmio_base = IOMEM(iores->start); data->init(imx_ahci); diff --git a/drivers/base/driver.c b/drivers/base/driver.c index c529296fc6..5867fe45d0 100644 --- a/drivers/base/driver.c +++ b/drivers/base/driver.c @@ -404,7 +404,7 @@ void __iomem *dev_request_mem_region_err_null(struct device_d *dev, int num) } EXPORT_SYMBOL(dev_request_mem_region_err_null); -void __iomem *dev_request_mem_region(struct device_d *dev, int num) +struct resource *dev_request_mem_resource(struct device_d *dev, int num) { struct resource *res; @@ -412,7 +412,14 @@ void __iomem *dev_request_mem_region(struct device_d *dev, int num) if (IS_ERR(res)) return ERR_CAST(res); - res = request_iomem_region(dev_name(dev), res->start, res->end); + return request_iomem_region(dev_name(dev), res->start, res->end); +} + +void __iomem *dev_request_mem_region(struct device_d *dev, int num) +{ + struct resource *res; + + res = dev_request_mem_resource(dev, num); if (IS_ERR(res)) return ERR_CAST(res); diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c index bc090cf191..c62e948f5b 100644 --- a/drivers/bus/imx-weim.c +++ b/drivers/bus/imx-weim.c @@ -130,6 +130,7 @@ static int weim_parse_dt(struct imx_weim *weim) static int weim_probe(struct device_d *dev) { + struct resource *iores; struct imx_weim_devtype *devtype; struct imx_weim *weim; int ret; @@ -144,11 +145,12 @@ static int weim_probe(struct device_d *dev) weim->devtype = devtype; /* get the resource */ - weim->base = dev_request_mem_region(dev, 0); - if (IS_ERR(weim->base)) { - ret = PTR_ERR(weim->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto weim_err; } + weim->base = IOMEM(iores->start); /* parse the device node */ ret = weim_parse_dt(weim); diff --git a/drivers/clk/clk-ar933x.c b/drivers/clk/clk-ar933x.c index 79b257133c..373f8cc085 100644 --- a/drivers/clk/clk-ar933x.c +++ b/drivers/clk/clk-ar933x.c @@ -137,11 +137,13 @@ static void ar933x_pll_init(void __iomem *base) static int ar933x_clk_probe(struct device_d *dev) { + struct resource *iores; void __iomem *base; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); ar933x_ref_clk_init(base); ar933x_pll_init(base); diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c index c4774979bd..a06b29f4e7 100644 --- a/drivers/clk/mvebu/common.c +++ b/drivers/clk/mvebu/common.c @@ -42,6 +42,7 @@ static struct of_device_id mvebu_coreclk_ids[] = { int mvebu_coreclk_probe(struct device_d *dev) { + struct resource *iores; struct device_node *np = dev->device_node; const struct of_device_id *match; const struct coreclk_soc_desc *desc; @@ -57,9 +58,10 @@ int mvebu_coreclk_probe(struct device_d *dev) desc = (const struct coreclk_soc_desc *)match->data; /* Get SAR base address */ - base = dev_request_mem_region(dev, 0); - if (!base) - return -EINVAL; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ clk_data.clk_num = 2 + desc->num_ratios; @@ -151,6 +153,7 @@ static struct of_device_id mvebu_clk_gating_ids[] = { int mvebu_clk_gating_probe(struct device_d *dev) { + struct resource *iores; struct device_node *np = dev->device_node; const struct of_device_id *match; const struct clk_gating_soc_desc *desc; @@ -166,9 +169,10 @@ int mvebu_clk_gating_probe(struct device_d *dev) return -EINVAL; desc = (const struct clk_gating_soc_desc *)match->data; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); clk = of_clk_get(np, 0); if (IS_ERR(clk)) diff --git a/drivers/clk/mvebu/corediv.c b/drivers/clk/mvebu/corediv.c index 55f6e6ad62..87b1f8bd7c 100644 --- a/drivers/clk/mvebu/corediv.c +++ b/drivers/clk/mvebu/corediv.c @@ -199,6 +199,7 @@ static struct of_device_id mvebu_corediv_clk_ids[] = { static int mvebu_corediv_clk_probe(struct device_d *dev) { + struct resource *iores; struct device_node *np = dev->device_node; const struct of_device_id *match; const struct clk_corediv_soc_desc *soc_desc; @@ -212,9 +213,10 @@ static int mvebu_corediv_clk_probe(struct device_d *dev) return -EINVAL; soc_desc = (const struct clk_corediv_soc_desc *)match->data; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); parent = of_clk_get(np, 0); if (IS_ERR(parent)) diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c index 8bf27c1c07..e28dae12f1 100644 --- a/drivers/clk/mxs/clk-imx23.c +++ b/drivers/clk/mxs/clk-imx23.c @@ -126,11 +126,13 @@ int __init mx23_clocks_init(void __iomem *regs) static int imx23_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *regs; - regs = dev_request_mem_region(dev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + regs = IOMEM(iores->start); mx23_clocks_init(regs); diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index a408044264..ffe03c8668 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c @@ -167,11 +167,13 @@ int __init mx28_clocks_init(void __iomem *regs) static int imx28_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *regs; - regs = dev_request_mem_region(dev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + regs = IOMEM(iores->start); mx28_clocks_init(regs); diff --git a/drivers/clk/socfpga.c b/drivers/clk/socfpga.c index 5952efb336..37ed038be8 100644 --- a/drivers/clk/socfpga.c +++ b/drivers/clk/socfpga.c @@ -374,12 +374,14 @@ static void socfpga_register_clocks(struct device_d *dev, struct device_node *no static int socfpga_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *regs; struct device_node *clknode; - regs = dev_request_mem_region(dev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + regs = IOMEM(iores->start); clk_mgr_base_addr = regs; diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 7a2f7c081f..cec7b5f803 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -335,9 +335,11 @@ static struct tegra_clk_init_table init_table[] = { static int tegra124_car_probe(struct device_d *dev) { - car_base = dev_request_mem_region(dev, 0); - if (IS_ERR(car_base)) - return PTR_ERR(car_base); + struct resource *iores; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + car_base = IOMEM(iores->start); tegra124_osc_clk_init(); tegra124_pll_init(); diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 2ff42d8bdb..2f843bb9ac 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -338,9 +338,11 @@ static struct tegra_clk_init_table init_table[] = { static int tegra20_car_probe(struct device_d *dev) { - car_base = dev_request_mem_region(dev, 0); - if (IS_ERR(car_base)) - return PTR_ERR(car_base); + struct resource *iores; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + car_base = IOMEM(iores->start); tegra20_osc_clk_init(); tegra20_pll_init(); diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 46fd6dddea..77f31d213e 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -366,9 +366,11 @@ static struct tegra_clk_init_table init_table[] = { static int tegra30_car_probe(struct device_d *dev) { - car_base = dev_request_mem_region(dev, 0); - if (IS_ERR(car_base)) - return PTR_ERR(car_base); + struct resource *iores; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + car_base = IOMEM(iores->start); tegra30_osc_clk_init(); tegra30_pll_init(); diff --git a/drivers/clocksource/arm_smp_twd.c b/drivers/clocksource/arm_smp_twd.c index c0296cdfd8..226150aa42 100644 --- a/drivers/clocksource/arm_smp_twd.c +++ b/drivers/clocksource/arm_smp_twd.c @@ -42,6 +42,7 @@ static struct clocksource smp_twd_clksrc = { static int smp_twd_probe(struct device_d *dev) { + struct resource *iores; u32 tick_rate; u32 val; int ret; @@ -61,9 +62,10 @@ static int smp_twd_probe(struct device_d *dev) return ret; } - twd_base = dev_request_mem_region(dev, 0); - if (IS_ERR(twd_base)) - return PTR_ERR(twd_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + twd_base = IOMEM(iores->start); tick_rate = clk_get_rate(twd_clk); if (tick_rate > SMP_TWD_MAX_FREQ) { diff --git a/drivers/clocksource/bcm2835.c b/drivers/clocksource/bcm2835.c index 0cb8e57993..b5831d5f10 100644 --- a/drivers/clocksource/bcm2835.c +++ b/drivers/clocksource/bcm2835.c @@ -42,6 +42,7 @@ static struct clocksource bcm2835_stc = { static int bcm2835_cs_probe(struct device_d *dev) { + struct resource *iores; static struct clk *stc_clk; u32 rate; int ret; @@ -61,9 +62,10 @@ static int bcm2835_cs_probe(struct device_d *dev) } rate = clk_get_rate(stc_clk); - stc_base = dev_request_mem_region(dev, 0); - if (IS_ERR(stc_base)) - return PTR_ERR(stc_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + stc_base = IOMEM(iores->start); clocks_calc_mult_shift(&bcm2835_stc.mult, &bcm2835_stc.shift, rate, NSEC_PER_SEC, 60); diff --git a/drivers/clocksource/clps711x.c b/drivers/clocksource/clps711x.c index a49853f2b5..f6399e9300 100644 --- a/drivers/clocksource/clps711x.c +++ b/drivers/clocksource/clps711x.c @@ -29,6 +29,7 @@ static struct clocksource clps711x_cs = { static int clps711x_cs_probe(struct device_d *dev) { + struct resource *iores; u32 rate; struct clk *timer_clk; @@ -37,11 +38,12 @@ static int clps711x_cs_probe(struct device_d *dev) return PTR_ERR(timer_clk); rate = clk_get_rate(timer_clk); - clps711x_timer_base = dev_request_mem_region(dev, 0); - if (IS_ERR(clps711x_timer_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { clk_put(timer_clk); - return PTR_ERR(clps711x_timer_base); + return PTR_ERR(iores); } + clps711x_timer_base = IOMEM(iores->start); clocks_calc_mult_shift(&clps711x_cs.mult, &clps711x_cs.shift, rate, NSEC_PER_SEC, 10); diff --git a/drivers/clocksource/digic.c b/drivers/clocksource/digic.c index 277bb02b63..1ecd839160 100644 --- a/drivers/clocksource/digic.c +++ b/drivers/clocksource/digic.c @@ -40,15 +40,17 @@ static struct clocksource digic_cs = { static int digic_timer_probe(struct device_d *dev) { + struct resource *iores; /* use only one timer */ if (timer_base) return -EBUSY; - timer_base = dev_request_mem_region(dev, 0); - if (IS_ERR(timer_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(timer_base); + return PTR_ERR(iores); } + timer_base = IOMEM(iores->start); clocks_calc_mult_shift(&digic_cs.mult, &digic_cs.shift, DIGIC_TIMER_CLOCK, NSEC_PER_SEC, 1); diff --git a/drivers/clocksource/mvebu.c b/drivers/clocksource/mvebu.c index 88db0b06c3..cf80571263 100644 --- a/drivers/clocksource/mvebu.c +++ b/drivers/clocksource/mvebu.c @@ -56,12 +56,14 @@ static struct clocksource cs = { static int mvebu_timer_probe(struct device_d *dev) { + struct resource *iores; struct clk *clk; u32 rate, div, val; - timer_base = dev_request_mem_region(dev, 0); - if (IS_ERR(timer_base)) - return PTR_ERR(timer_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + timer_base = IOMEM(iores->start); val = __raw_readl(timer_base + TIMER_CTRL_OFF); val &= ~(TIMER0_25MHZ | TIMER0_DIV_MASK); diff --git a/drivers/clocksource/nomadik.c b/drivers/clocksource/nomadik.c index 48f4715c8f..9b20cbc946 100644 --- a/drivers/clocksource/nomadik.c +++ b/drivers/clocksource/nomadik.c @@ -94,6 +94,7 @@ static void nmdk_timer_reset(void) static int nmdk_mtu_probe(struct device_d *dev) { + struct resource *iores; static struct clk *mtu_clk; u32 rate; int ret; @@ -123,9 +124,10 @@ static int nmdk_mtu_probe(struct device_d *dev) nmdk_cycle = (rate + 1000 / 2) / 1000; /* Save global pointer to mtu, used by functions above */ - mtu_base = dev_request_mem_region(dev, 0); - if (IS_ERR(mtu_base)) - return PTR_ERR(mtu_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mtu_base = IOMEM(iores->start); /* Init the timer and register clocksource */ nmdk_timer_reset(); diff --git a/drivers/clocksource/orion.c b/drivers/clocksource/orion.c index 2e40b49ee7..97008dabab 100644 --- a/drivers/clocksource/orion.c +++ b/drivers/clocksource/orion.c @@ -45,12 +45,14 @@ static struct clocksource clksrc = { static int orion_timer_probe(struct device_d *dev) { + struct resource *iores; struct clk *tclk; uint32_t val; - timer_base = dev_request_mem_region(dev, 0); - if (IS_ERR(timer_base)) - return PTR_ERR(timer_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + timer_base = IOMEM(iores->start); tclk = clk_get(dev, NULL); diff --git a/drivers/clocksource/uemd.c b/drivers/clocksource/uemd.c index d4291dd736..b80908f3b0 100644 --- a/drivers/clocksource/uemd.c +++ b/drivers/clocksource/uemd.c @@ -66,6 +66,7 @@ static struct clocksource uemd_cs = { static int uemd_timer_probe(struct device_d *dev) { + struct resource *iores; int mode; struct clk *timer_clk; @@ -73,11 +74,12 @@ static int uemd_timer_probe(struct device_d *dev) if (timer_base) return -EBUSY; - timer_base = dev_request_mem_region(dev, 0); - if (IS_ERR(timer_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(timer_base); + return PTR_ERR(iores); } + timer_base = IOMEM(iores->start); timer_clk = clk_get(dev, NULL); if (IS_ERR(timer_clk)) { diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig new file mode 100644 index 0000000000..9f02c17c26 --- /dev/null +++ b/drivers/crypto/Kconfig @@ -0,0 +1,10 @@ + +menuconfig CRYPTO_HW + bool "Hardware crypto devices" + help + +if CRYPTO_HW + +source drivers/crypto/caam/Kconfig + +endif diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile new file mode 100644 index 0000000000..67f968f76c --- /dev/null +++ b/drivers/crypto/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam/ diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig new file mode 100644 index 0000000000..cf05d1c077 --- /dev/null +++ b/drivers/crypto/caam/Kconfig @@ -0,0 +1,34 @@ +config CRYPTO_DEV_FSL_CAAM + bool "Freescale CAAM-Multicore driver backend" + depends on ARCH_IMX6 + help + Enables the driver module for Freescale's Cryptographic Accelerator + and Assurance Module (CAAM), also known as the SEC version 4 (SEC4). + This module creates job ring devices, and configures h/w + to operate as a DPAA component automatically, depending + on h/w feature availability. + +config CRYPTO_DEV_FSL_CAAM_RINGSIZE + int "Job Ring size" + depends on CRYPTO_DEV_FSL_CAAM + range 2 9 + default "9" + help + Select size of Job Rings as a power of 2, within the + range 2-9 (ring size 4-512). + Examples: + 2 => 4 + 3 => 8 + 4 => 16 + 5 => 32 + 6 => 64 + 7 => 128 + 8 => 256 + 9 => 512 + +config CRYPTO_DEV_FSL_CAAM_RNG + bool "Register caam RNG device" + depends on CRYPTO_DEV_FSL_CAAM + default y + help + Selecting this will register the SEC4 hardware rng. diff --git a/drivers/crypto/caam/Makefile b/drivers/crypto/caam/Makefile new file mode 100644 index 0000000000..74d32da00e --- /dev/null +++ b/drivers/crypto/caam/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the CAAM backend and dependent components +# +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += ctrl.o error.o jr.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG) += caamrng.o diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c new file mode 100644 index 0000000000..0fef171a2b --- /dev/null +++ b/drivers/crypto/caam/caamrng.c @@ -0,0 +1,291 @@ +/* + * caam - Freescale FSL CAAM support for hw_random + * + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. + * + * Based on caamalg.c crypto API driver. + * + * relationship between job descriptors to shared descriptors: + * + * --------------- -------------- + * | JobDesc #0 |-------------------->| ShareDesc | + * | *(buffer 0) | |------------->| (generate) | + * --------------- | | (move) | + * | | (store) | + * --------------- | -------------- + * | JobDesc #1 |------| + * | *(buffer 1) | + * --------------- + * + * A job desc looks like this: + * + * --------------------- + * | Header | + * | ShareDesc Pointer | + * | SEQ_OUT_PTR | + * | (output buffer) | + * --------------------- + * + * The SharedDesc never changes, and each job descriptor points to one of two + * buffers for each device, from which the data will be copied into the + * requested destination + */ +#include <common.h> +#include <dma.h> +#include <driver.h> +#include <init.h> +#include <linux/spinlock.h> + +#include "regs.h" +#include "intern.h" +#include "desc_constr.h" +#include "jr.h" +#include "error.h" + +/* + * Maximum buffer size: maximum number of random, cache-aligned bytes that + * will be generated and moved to seq out ptr (extlen not allowed) + */ +#define RN_BUF_SIZE 32767 + +/* length of descriptors */ +#define DESC_JOB_O_LEN (CAAM_CMD_SZ * 2 + CAAM_PTR_SZ * 2) +#define DESC_RNG_LEN (10 * CAAM_CMD_SZ) + +/* Buffer, its dma address and lock */ +struct buf_data { + u8 buf[RN_BUF_SIZE]; + dma_addr_t addr; + u32 hw_desc[DESC_JOB_O_LEN]; +#define BUF_NOT_EMPTY 0 +#define BUF_EMPTY 1 +#define BUF_PENDING 2 /* Empty, but with job pending --don't submit another */ + int empty; +}; + +/* rng per-device context */ +struct caam_rng_ctx { + struct device_d *jrdev; + dma_addr_t sh_desc_dma; + u32 sh_desc[DESC_RNG_LEN]; + unsigned int cur_buf_idx; + int current_buf; + struct buf_data bufs[2]; + struct cdev cdev; +}; + +static struct caam_rng_ctx *rng_ctx; + +static void rng_done(struct device_d *jrdev, u32 *desc, u32 err, void *context) +{ + struct buf_data *bd; + + bd = (struct buf_data *)((char *)desc - + offsetof(struct buf_data, hw_desc)); + + if (err) + caam_jr_strstatus(jrdev, err); + + bd->empty = BUF_NOT_EMPTY; + + /* Buffer refilled, invalidate cache */ + dma_sync_single_for_cpu(bd->addr, RN_BUF_SIZE, DMA_FROM_DEVICE); + +#ifdef DEBUG + print_hex_dump(KERN_ERR, "rng refreshed buf@: ", + DUMP_PREFIX_OFFSET, 16, 4, bd->buf, RN_BUF_SIZE, 1); +#endif +} + +static inline int submit_job(struct caam_rng_ctx *ctx, int to_current) +{ + struct buf_data *bd = &ctx->bufs[!(to_current ^ ctx->current_buf)]; + struct device_d *jrdev = ctx->jrdev; + u32 *desc = bd->hw_desc; + int err; + + dev_dbg(jrdev, "submitting job %d\n", !(to_current ^ ctx->current_buf)); + + dma_sync_single_for_device((unsigned long)desc, desc_bytes(desc), + DMA_TO_DEVICE); + + err = caam_jr_enqueue(jrdev, desc, rng_done, ctx); + if (!err) + bd->empty += 1; /* note if pending */ + + return err; +} + +static int caam_read(struct caam_rng_ctx *ctx, void *data, size_t max, bool wait) +{ + struct buf_data *bd = &ctx->bufs[ctx->current_buf]; + int next_buf_idx, copied_idx; + int err; + + if (bd->empty) { + /* try to submit job if there wasn't one */ + if (bd->empty == BUF_EMPTY) { + err = submit_job(ctx, 1); + /* if can't submit job, can't even wait */ + if (err) + return 0; + } + /* no immediate data, so exit if not waiting */ + if (!wait) + return 0; + } + + next_buf_idx = ctx->cur_buf_idx + max; + dev_dbg(ctx->jrdev, "%s: start reading at buffer %d, idx %d\n", + __func__, ctx->current_buf, ctx->cur_buf_idx); + + /* if enough data in current buffer */ + if (next_buf_idx < RN_BUF_SIZE) { + memcpy(data, bd->buf + ctx->cur_buf_idx, max); + ctx->cur_buf_idx = next_buf_idx; + return max; + } + + /* else, copy what's left... */ + copied_idx = RN_BUF_SIZE - ctx->cur_buf_idx; + memcpy(data, bd->buf + ctx->cur_buf_idx, copied_idx); + ctx->cur_buf_idx = 0; + bd->empty = BUF_EMPTY; + + /* ...refill... */ + err = submit_job(ctx, 1); + if (err) + return err; + + /* and use next buffer */ + ctx->current_buf = !ctx->current_buf; + dev_dbg(ctx->jrdev, "switched to buffer %d\n", ctx->current_buf); + + /* since there already is some data read, don't wait */ + return copied_idx + caam_read(ctx, data + copied_idx, + max - copied_idx, false); +} + +static inline int rng_create_sh_desc(struct caam_rng_ctx *ctx) +{ + u32 *desc = ctx->sh_desc; + + init_sh_desc(desc, HDR_SHARE_SERIAL); + + /* Propagate errors from shared to job descriptor */ + append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD); + + /* Generate random bytes */ + append_operation(desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG); + + /* Store bytes */ + append_seq_fifo_store(desc, RN_BUF_SIZE, FIFOST_TYPE_RNGSTORE); + + ctx->sh_desc_dma = (dma_addr_t)desc; + + dma_sync_single_for_device((unsigned long)desc, desc_bytes(desc), + DMA_TO_DEVICE); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "rng shdesc@: ", DUMP_PREFIX_OFFSET, 16, 4, + desc, desc_bytes(desc), 1); +#endif + return 0; +} + +static inline int rng_create_job_desc(struct caam_rng_ctx *ctx, int buf_id) +{ + struct buf_data *bd = &ctx->bufs[buf_id]; + u32 *desc = bd->hw_desc; + int sh_len = desc_len(ctx->sh_desc); + + init_job_desc_shared(desc, ctx->sh_desc_dma, sh_len, HDR_SHARE_DEFER | + HDR_REVERSE); + + bd->addr = (dma_addr_t)bd->buf; + + append_seq_out_ptr_intlen(desc, bd->addr, RN_BUF_SIZE, 0); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "rng job desc@: ", DUMP_PREFIX_OFFSET, 16, 4, + desc, desc_bytes(desc), 1); +#endif + return 0; +} + +static int caam_init_buf(struct caam_rng_ctx *ctx, int buf_id) +{ + struct buf_data *bd = &ctx->bufs[buf_id]; + int err; + + err = rng_create_job_desc(ctx, buf_id); + if (err) + return err; + + bd->empty = BUF_EMPTY; + return submit_job(ctx, buf_id == ctx->current_buf); +} + +static int caam_init_rng(struct caam_rng_ctx *ctx, struct device_d *jrdev) +{ + int err; + + ctx->jrdev = jrdev; + + err = rng_create_sh_desc(ctx); + if (err) + return err; + + ctx->current_buf = 0; + ctx->cur_buf_idx = 0; + + err = caam_init_buf(ctx, 0); + if (err) + return err; + + err = caam_init_buf(ctx, 1); + if (err) + return err; + + return 0; +} + +static ssize_t random_read(struct cdev *cdev, void *buf, size_t count, + loff_t offset, ulong flags) +{ + struct caam_rng_ctx *ctx = container_of(cdev, struct caam_rng_ctx, cdev); + + return caam_read(ctx, buf, count, true); +} + +static struct file_operations randomops = { + .read = random_read, + .lseek = dev_lseek_default, +}; + +static int caam_init_devrandom(struct caam_rng_ctx *ctx, struct device_d *dev) +{ + ctx->cdev.name = "hwrng"; + ctx->cdev.flags = DEVFS_IS_CHARACTER_DEV; + ctx->cdev.ops = &randomops; + ctx->cdev.dev = dev; + + return devfs_create(&ctx->cdev); +} + +int caam_rng_probe(struct device_d *dev, struct device_d *jrdev) +{ + int err; + + rng_ctx = xzalloc(sizeof(*rng_ctx)); + + err = caam_init_rng(rng_ctx, jrdev); + if (err) + return err; + + err = caam_init_devrandom(rng_ctx, dev); + if (err) + return err; + + dev_info(dev, "registering rng-caam\n"); + + return 0; +} diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c new file mode 100644 index 0000000000..4deed8a195 --- /dev/null +++ b/drivers/crypto/caam/ctrl.c @@ -0,0 +1,601 @@ +/* + * CAAM control-plane driver backend + * Controller-level driver, kernel property detection, initialization + * + * Copyright 2008-2012 Freescale Semiconductor, Inc. + */ + +#include <common.h> +#include <clock.h> +#include <driver.h> +#include <init.h> +#include <linux/barebox-wrapper.h> +#include <linux/spinlock.h> +#include <linux/clk.h> + +#include "regs.h" +#include "intern.h" +#include "jr.h" +#include "desc_constr.h" +#include "error.h" +#include "ctrl.h" + +/* + * Descriptor to instantiate RNG State Handle 0 in normal mode and + * load the JDKEK, TDKEK and TDSK registers + */ +static void build_instantiation_desc(u32 *desc, int handle, int do_sk) +{ + u32 *jump_cmd, op_flags; + + init_job_desc(desc, 0); + + op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | + (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT; + + /* INIT RNG in non-test mode */ + append_operation(desc, op_flags); + + if (!handle && do_sk) { + /* + * For SH0, Secure Keys must be generated as well + */ + + /* wait for done */ + jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); + set_jump_tgt_here(desc, jump_cmd); + + /* + * load 1 to clear written reg: + * resets the done interrrupt and returns the RNG to idle. + */ + append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); + + /* Initialize State Handle */ + append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | + OP_ALG_AAI_RNG4_SK); + } + + append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); +} + +/* + * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of + * the software (no JR/QI used). + * @ctrldev - pointer to device + * @status - descriptor status, after being run + * + * Return: - 0 if no error occurred + * - -ENODEV if the DECO couldn't be acquired + * - -EAGAIN if an error occurred while executing the descriptor + */ +static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc, + u32 *status) +{ + struct caam_drv_private *ctrlpriv = ctrldev->priv; + struct caam_ctrl __iomem *ctrl; + struct caam_deco __iomem *deco; + u32 deco_dbg_reg, flags; + uint64_t start; + int i; + + ctrl = ctrlpriv->ctrl; + deco = ctrlpriv->deco; + + if (ctrlpriv->virt_en == 1) { + setbits32(&ctrl->deco_rsr, DECORSR_JR0); + + start = get_time_ns(); + while (!(readl(&ctrl->deco_rsr) & DECORSR_VALID)) { + if (is_timeout(start, 100 * MSECOND)) { + dev_err(ctrldev, "DECO timed out\n"); + return -ETIMEDOUT; + } + } + } + + setbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); + + start = get_time_ns(); + while (!(readl(&ctrl->deco_rq) & DECORR_DEN0)) { + if (is_timeout(start, 100 * MSECOND)) { + dev_err(ctrldev, "failed to acquire DECO 0\n"); + clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); + return -ETIMEDOUT; + } + } + + for (i = 0; i < desc_len(desc); i++) + writel(*(desc + i), &deco->descbuf[i]); + + flags = DECO_JQCR_WHL; + /* + * If the descriptor length is longer than 4 words, then the + * FOUR bit in JRCTRL register must be set. + */ + if (desc_len(desc) >= 4) + flags |= DECO_JQCR_FOUR; + + /* Instruct the DECO to execute it */ + writel(flags, &deco->jr_ctl_hi); + + start = get_time_ns(); + while ((deco_dbg_reg = readl(&deco->desc_dbg)) & + DESC_DBG_DECO_STAT_VALID) { + /* + * If an error occured in the descriptor, then + * the DECO status field will be set to 0x0D + */ + if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) == + DESC_DBG_DECO_STAT_HOST_ERR) + break; + } + + *status = readl(&deco->op_status_hi) & + DECO_OP_STATUS_HI_ERR_MASK; + + if (ctrlpriv->virt_en == 1) + clrbits32(&ctrl->deco_rsr, DECORSR_JR0); + + /* Mark the DECO as free */ + clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); + + if (is_timeout(start, 100 * MSECOND)) + return -EAGAIN; + + return 0; +} + +/* + * instantiate_rng - builds and executes a descriptor on DECO0, + * which initializes the RNG block. + * @ctrldev - pointer to device + * @state_handle_mask - bitmask containing the instantiation status + * for the RNG4 state handles which exist in + * the RNG4 block: 1 if it's been instantiated + * by an external entry, 0 otherwise. + * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK; + * Caution: this can be done only once; if the keys need to be + * regenerated, a POR is required + * + * Return: - 0 if no error occurred + * - -ENOMEM if there isn't enough memory to allocate the descriptor + * - -ENODEV if DECO0 couldn't be acquired + * - -EAGAIN if an error occurred when executing the descriptor + * f.i. there was a RNG hardware error due to not "good enough" + * entropy being aquired. + */ +static int instantiate_rng(struct device_d *ctrldev, int state_handle_mask, + int gen_sk) +{ + struct caam_drv_private *ctrlpriv = ctrldev->priv; + struct caam_ctrl __iomem *ctrl; + u32 *desc, status, rdsta_val; + int ret = 0, sh_idx; + + ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; + desc = xzalloc(CAAM_CMD_SZ * 7); + + for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { + /* + * If the corresponding bit is set, this state handle + * was initialized by somebody else, so it's left alone. + */ + if ((1 << sh_idx) & state_handle_mask) + continue; + + /* Create the descriptor for instantiating RNG State Handle */ + build_instantiation_desc(desc, sh_idx, gen_sk); + + /* Try to run it through DECO0 */ + ret = run_descriptor_deco0(ctrldev, desc, &status); + + /* + * If ret is not 0, or descriptor status is not 0, then + * something went wrong. No need to try the next state + * handle (if available), bail out here. + * Also, if for some reason, the State Handle didn't get + * instantiated although the descriptor has finished + * without any error (HW optimizations for later + * CAAM eras), then try again. + */ + rdsta_val = readl(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; + if (status || !(rdsta_val & (1 << sh_idx))) + ret = -EAGAIN; + if (ret) + break; + dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx); + /* Clear the contents before recreating the descriptor */ + memset(desc, 0x00, CAAM_CMD_SZ * 7); + } + + return ret; +} + +static void caam_remove(struct device_d *dev) +{ + struct caam_drv_private *ctrlpriv = dev->priv; + + /* shut clocks off before finalizing shutdown */ + clk_disable(ctrlpriv->caam_ipg); + clk_disable(ctrlpriv->caam_mem); + clk_disable(ctrlpriv->caam_aclk); + clk_disable(ctrlpriv->caam_emi_slow); +} + +/* + * kick_trng - sets the various parameters for enabling the initialization + * of the RNG4 block in CAAM + * @pdev - pointer to the platform device + * @ent_delay - Defines the length (in system clocks) of each entropy sample. + */ +static void kick_trng(struct device_d *ctrldev, int ent_delay) +{ + struct caam_drv_private *ctrlpriv = ctrldev->priv; + struct caam_ctrl __iomem *ctrl; + struct rng4tst __iomem *r4tst; + u32 val; + + ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; + r4tst = &ctrl->r4tst[0]; + + /* put RNG4 into program mode */ + setbits32(&r4tst->rtmctl, RTMCTL_PRGM); + + /* + * Performance-wise, it does not make sense to + * set the delay to a value that is lower + * than the last one that worked (i.e. the state handles + * were instantiated properly. Thus, instead of wasting + * time trying to set the values controlling the sample + * frequency, the function simply returns. + */ + val = (readl(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) + >> RTSDCTL_ENT_DLY_SHIFT; + if (ent_delay <= val) { + /* put RNG4 into run mode */ + clrbits32(&r4tst->rtmctl, RTMCTL_PRGM); + return; + } + + val = readl(&r4tst->rtsdctl); + val = (val & ~RTSDCTL_ENT_DLY_MASK) | + (ent_delay << RTSDCTL_ENT_DLY_SHIFT); + writel(val, &r4tst->rtsdctl); + /* min. freq. count, equal to 1/4 of the entropy sample length */ + writel(ent_delay >> 2, &r4tst->rtfrqmin); + /* disable maximum frequency count */ + writel(RTFRQMAX_DISABLE, &r4tst->rtfrqmax); + /* read the control register */ + val = readl(&r4tst->rtmctl); + /* + * select raw sampling in both entropy shifter + * and statistical checker + */ + setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC); + /* put RNG4 into run mode */ + clrbits32(&val, RTMCTL_PRGM); + /* write back the control register */ + writel(val, &r4tst->rtmctl); +} + +/** + * caam_get_era() - Return the ERA of the SEC on SoC, based + * on "sec-era" propery in the DTS. This property is updated by u-boot. + **/ +int caam_get_era(void) +{ + struct device_node *caam_node; + int ret; + u32 prop; + + caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); + ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop); + + return IS_ERR_VALUE(ret) ? -ENOTSUPP : prop; +} +EXPORT_SYMBOL(caam_get_era); + +/* Probe routine for CAAM top (controller) level */ +static int caam_probe(struct device_d *dev) +{ + int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; + u64 caam_id; + struct device_node *nprop, *np; + struct caam_ctrl __iomem *ctrl; + struct caam_drv_private *ctrlpriv; + u32 scfgr, comp_params; + u32 cha_vid_ls; + int pg_size; + int BLOCK_OFFSET = 0; + + ctrlpriv = xzalloc(sizeof(struct caam_drv_private)); + + dev->priv = ctrlpriv; + ctrlpriv->pdev = dev; + nprop = dev->device_node; + + ctrlpriv->caam_ipg = clk_get(dev, "ipg"); + if (IS_ERR(ctrlpriv->caam_ipg)) { + ret = PTR_ERR(ctrlpriv->caam_ipg); + dev_err(dev, "can't identify CAAM ipg clk: %d\n", ret); + return -ENODEV; + } + + ctrlpriv->caam_mem = clk_get(dev, "mem"); + if (IS_ERR(ctrlpriv->caam_mem)) { + ret = PTR_ERR(ctrlpriv->caam_mem); + dev_err(dev, "can't identify CAAM secure mem clk: %d\n", ret); + return -ENODEV; + } + + ctrlpriv->caam_aclk = clk_get(dev, "aclk"); + if (IS_ERR(ctrlpriv->caam_aclk)) { + ret = PTR_ERR(ctrlpriv->caam_aclk); + dev_err(dev, + "can't identify CAAM aclk clk: %d\n", ret); + return -ENODEV; + } + + ctrlpriv->caam_emi_slow = clk_get(dev, "emi_slow"); + if (IS_ERR(ctrlpriv->caam_emi_slow)) { + ret = PTR_ERR(ctrlpriv->caam_emi_slow); + dev_err(dev, + "can't identify CAAM emi slow clk: %d\n", ret); + return -ENODEV; + } + + ret = clk_enable(ctrlpriv->caam_ipg); + if (ret < 0) { + dev_err(dev, "can't enable CAAM ipg clock: %d\n", ret); + return -ENODEV; + } + + ret = clk_enable(ctrlpriv->caam_mem); + if (ret < 0) { + dev_err(dev, "can't enable CAAM secure mem clock: %d\n", + ret); + return -ENODEV; + } + + ret = clk_enable(ctrlpriv->caam_aclk); + if (ret < 0) { + dev_err(dev, "can't enable CAAM aclk clock: %d\n", ret); + return -ENODEV; + } + + ret = clk_enable(ctrlpriv->caam_emi_slow); + if (ret < 0) { + dev_err(dev, "can't enable CAAM emi slow clock: %d\n", + ret); + return -ENODEV; + } + + /* Get configuration properties from device tree */ + /* First, get register page */ + ctrl = dev_request_mem_region(dev, 0); + if (ctrl == NULL) { + dev_err(dev, "caam: of_iomap() failed\n"); + return -ENOMEM; + } + /* Finding the page size for using the CTPR_MS register */ + comp_params = readl(&ctrl->perfmon.comp_parms_ms); + pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT; + + /* Allocating the BLOCK_OFFSET based on the supported page size on + * the platform + */ + if (pg_size == 0) + BLOCK_OFFSET = PG_SIZE_4K; + else + BLOCK_OFFSET = PG_SIZE_64K; + + ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl; + ctrlpriv->assure = (struct caam_assurance __force *) + ((uint8_t *)ctrl + + BLOCK_OFFSET * ASSURE_BLOCK_NUMBER); + ctrlpriv->deco = (struct caam_deco __force *) + ((uint8_t *)ctrl + + BLOCK_OFFSET * DECO_BLOCK_NUMBER); + + /* + * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, + * long pointers in master configuration register + */ + clrsetbits_be32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_ARCACHE_MASK, + MCFGR_AWCACHE_CACH | MCFGR_ARCACHE_MASK | + MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ? + MCFGR_LONG_PTR : 0)); + + /* + * Read the Compile Time paramters and SCFGR to determine + * if Virtualization is enabled for this platform + */ + scfgr = readl(&ctrl->scfgr); + + ctrlpriv->virt_en = 0; + if (comp_params & CTPR_MS_VIRT_EN_INCL) { + /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or + * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1 + */ + if ((comp_params & CTPR_MS_VIRT_EN_POR) || + (!(comp_params & CTPR_MS_VIRT_EN_POR) && + (scfgr & SCFGR_VIRT_EN))) + ctrlpriv->virt_en = 1; + } else { + /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ + if (comp_params & CTPR_MS_VIRT_EN_POR) + ctrlpriv->virt_en = 1; + } + + if (ctrlpriv->virt_en == 1) + setbits32(&ctrl->jrstart, JRSTART_JR0_START | + JRSTART_JR1_START | JRSTART_JR2_START | + JRSTART_JR3_START); + + /* + * ERRATA: mx6 devices have an issue wherein AXI bus transactions + * may not occur in the correct order. This isn't a problem running + * single descriptors, but can be if running multiple concurrent + * descriptors. Reworking the driver to throttle to single requests + * is impractical, thus the workaround is to limit the AXI pipeline + * to a depth of 1 (from it's default of 4) to preclude this situation + * from occurring. + */ + writel((readl(&ctrl->mcr) & ~(MCFGR_AXIPIPE_MASK)) | + ((1 << MCFGR_AXIPIPE_SHIFT) & MCFGR_AXIPIPE_MASK), &ctrl->mcr); + + /* + * Detect and enable JobRs + * First, find out how many ring spec'ed, allocate references + * for all, then go probe each one. + */ + rspec = 0; + for_each_available_child_of_node(nprop, np) + if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || + of_device_is_compatible(np, "fsl,sec4.0-job-ring")) + rspec++; + + ctrlpriv->jrpdev = xzalloc(sizeof(struct device_d *) * rspec); + + ring = 0; + ctrlpriv->total_jobrs = 0; + for_each_available_child_of_node(nprop, np) { + if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || + of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { + struct device_d *jrdev; + + jrdev = of_platform_device_create(np, dev); + if (!jrdev) + continue; + + ret = caam_jr_probe(jrdev); + if (ret) { + dev_err(dev, "Could not add jobring %d\n", ring); + return ret; + } + + ctrlpriv->jrpdev[ring] = jrdev; + ctrlpriv->jr[ring] = (struct caam_job_ring __force *) + ((uint8_t *)ctrl + + (ring + JR_BLOCK_NUMBER) * + BLOCK_OFFSET); + ctrlpriv->total_jobrs++; + ring++; + } + } + + /* Check to see if QI present. If so, enable */ + ctrlpriv->qi_present = + !!(readl(&ctrl->perfmon.comp_parms_ms) & + CTPR_MS_QI_MASK); + if (ctrlpriv->qi_present) { + ctrlpriv->qi = (struct caam_queue_if __force *) + ((uint8_t *)ctrl + + BLOCK_OFFSET * QI_BLOCK_NUMBER); + /* This is all that's required to physically enable QI */ + writel(QICTL_DQEN, &ctrlpriv->qi->qi_control_lo); + } + + /* If no QI and no rings specified, quit and go home */ + if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { + dev_err(dev, "no queues configured, terminating\n"); + caam_remove(dev); + return -ENOMEM; + } + + cha_vid_ls = readl(&ctrl->perfmon.cha_id_ls); + + /* + * If SEC has RNG version >= 4 and RNG state handle has not been + * already instantiated, do RNG instantiation + */ + if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) { + ctrlpriv->rng4_sh_init = + readl(&ctrl->r4tst[0].rdsta); + /* + * If the secure keys (TDKEK, JDKEK, TDSK), were already + * generated, signal this to the function that is instantiating + * the state handles. An error would occur if RNG4 attempts + * to regenerate these keys before the next POR. + */ + gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; + ctrlpriv->rng4_sh_init &= RDSTA_IFMASK; + do { + int inst_handles = + readl(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; + /* + * If either SH were instantiated by somebody else + * (e.g. u-boot) then it is assumed that the entropy + * parameters are properly set and thus the function + * setting these (kick_trng(...)) is skipped. + * Also, if a handle was instantiated, do not change + * the TRNG parameters. + */ + if (!(ctrlpriv->rng4_sh_init || inst_handles)) { + dev_dbg(dev, "Entropy delay = %u\n", ent_delay); + kick_trng(dev, ent_delay); + ent_delay += 400; + } + /* + * if instantiate_rng(...) fails, the loop will rerun + * and the kick_trng(...) function will modfiy the + * upper and lower limits of the entropy sampling + * interval, leading to a sucessful initialization of + * the RNG. + */ + ret = instantiate_rng(dev, inst_handles, gen_sk); + } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); + + if (ret) { + dev_err(dev, "failed to instantiate RNG"); + caam_remove(dev); + return ret; + } + /* + * Set handles init'ed by this module as the complement of the + * already initialized ones + */ + ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK; + + /* Enable RDB bit so that RNG works faster */ + setbits32(&ctrl->scfgr, SCFGR_RDBENABLE); + } + + if (IS_ENABLED(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG)) { + ret = caam_rng_probe(dev, ctrlpriv->jrpdev[0]); + if (ret) { + dev_err(dev, "failed to instantiate RNG device"); + caam_remove(dev); + return ret; + } + } + + /* NOTE: RTIC detection ought to go here, around Si time */ + caam_id = (u64)readl(&ctrl->perfmon.caam_id_ms) << 32 | + (u64)readl(&ctrl->perfmon.caam_id_ls); + + /* Report "alive" for developer to see */ + dev_dbg(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, + caam_get_era()); + dev_dbg(dev, "job rings = %d, qi = %d\n", + ctrlpriv->total_jobrs, ctrlpriv->qi_present); + + return 0; +} + +static __maybe_unused struct of_device_id caam_match[] = { + { + .compatible = "fsl,sec-v4.0", + }, { + .compatible = "fsl,sec4.0", + }, + {}, +}; + +static struct driver_d caam_driver = { + .name = "caam", + .probe = caam_probe, + .of_compatible = DRV_OF_COMPAT(caam_match), +}; +device_platform_driver(caam_driver); diff --git a/drivers/crypto/caam/ctrl.h b/drivers/crypto/caam/ctrl.h new file mode 100644 index 0000000000..cac5402a46 --- /dev/null +++ b/drivers/crypto/caam/ctrl.h @@ -0,0 +1,13 @@ +/* + * CAAM control-plane driver backend public-level include definitions + * + * Copyright 2012 Freescale Semiconductor, Inc. + */ + +#ifndef CTRL_H +#define CTRL_H + +/* Prototypes for backend-level services exposed to APIs */ +int caam_get_era(void); + +#endif /* CTRL_H */ diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h new file mode 100644 index 0000000000..a12eb86037 --- /dev/null +++ b/drivers/crypto/caam/desc.h @@ -0,0 +1,1665 @@ +/* + * CAAM descriptor composition header + * Definitions to support CAAM descriptor instruction generation + * + * Copyright (C) 2008-2015 Freescale Semiconductor, Inc. + */ + +#ifndef DESC_H +#define DESC_H + +/* + * 16-byte hardware scatter/gather table + * An 8-byte table exists in the hardware spec, but has never been + * implemented to date. The 8/16 option is selected at RTL-compile-time. + * and this selection is visible in the Compile Time Parameters Register + */ + +#define SEC4_SG_LEN_EXT 0x80000000 /* Entry points to table */ +#define SEC4_SG_LEN_FIN 0x40000000 /* Last ent in table */ +#define SEC4_SG_BPID_MASK 0x000000ff +#define SEC4_SG_BPID_SHIFT 16 +#define SEC4_SG_LEN_MASK 0x3fffffff /* Excludes EXT and FINAL */ +#define SEC4_SG_OFFS_MASK 0x00001fff + +struct sec4_sg_entry { +#ifdef CONFIG_64BIT + u64 ptr; +#else + u32 reserved; + u32 ptr; +#endif + u32 len; + u16 buf_pool_id; + u16 offset; +}; + +/* Max size of any CAAM descriptor in 32-bit words, inclusive of header */ +#define MAX_CAAM_DESCSIZE 64 + +/* Block size of any entity covered/uncovered with a KEK/TKEK */ +#define KEK_BLOCKSIZE 16 + +/* + * Supported descriptor command types as they show up + * inside a descriptor command word. + */ +#define CMD_SHIFT 27 +#define CMD_MASK 0xf8000000 + +#define CMD_KEY (0x00 << CMD_SHIFT) +#define CMD_SEQ_KEY (0x01 << CMD_SHIFT) +#define CMD_LOAD (0x02 << CMD_SHIFT) +#define CMD_SEQ_LOAD (0x03 << CMD_SHIFT) +#define CMD_FIFO_LOAD (0x04 << CMD_SHIFT) +#define CMD_SEQ_FIFO_LOAD (0x05 << CMD_SHIFT) +#define CMD_STORE (0x0a << CMD_SHIFT) +#define CMD_SEQ_STORE (0x0b << CMD_SHIFT) +#define CMD_FIFO_STORE (0x0c << CMD_SHIFT) +#define CMD_SEQ_FIFO_STORE (0x0d << CMD_SHIFT) +#define CMD_MOVE_LEN (0x0e << CMD_SHIFT) +#define CMD_MOVE (0x0f << CMD_SHIFT) +#define CMD_OPERATION (0x10 << CMD_SHIFT) +#define CMD_SIGNATURE (0x12 << CMD_SHIFT) +#define CMD_JUMP (0x14 << CMD_SHIFT) +#define CMD_MATH (0x15 << CMD_SHIFT) +#define CMD_DESC_HDR (0x16 << CMD_SHIFT) +#define CMD_SHARED_DESC_HDR (0x17 << CMD_SHIFT) +#define CMD_SEQ_IN_PTR (0x1e << CMD_SHIFT) +#define CMD_SEQ_OUT_PTR (0x1f << CMD_SHIFT) + +/* General-purpose class selector for all commands */ +#define CLASS_SHIFT 25 +#define CLASS_MASK (0x03 << CLASS_SHIFT) + +#define CLASS_NONE (0x00 << CLASS_SHIFT) +#define CLASS_1 (0x01 << CLASS_SHIFT) +#define CLASS_2 (0x02 << CLASS_SHIFT) +#define CLASS_BOTH (0x03 << CLASS_SHIFT) + +/* + * Descriptor header command constructs + * Covers shared, job, and trusted descriptor headers + */ + +/* + * Do Not Run - marks a descriptor inexecutable if there was + * a preceding error somewhere + */ +#define HDR_DNR 0x01000000 + +/* + * ONE - should always be set. Combination of ONE (always + * set) and ZRO (always clear) forms an endianness sanity check + */ +#define HDR_ONE 0x00800000 +#define HDR_ZRO 0x00008000 + +/* Start Index or SharedDesc Length */ +#define HDR_START_IDX_MASK 0x3f +#define HDR_START_IDX_SHIFT 16 + +/* If shared descriptor header, 6-bit length */ +#define HDR_DESCLEN_SHR_MASK 0x3f + +/* If non-shared header, 7-bit length */ +#define HDR_DESCLEN_MASK 0x7f + +/* This is a TrustedDesc (if not SharedDesc) */ +#define HDR_TRUSTED 0x00004000 + +/* Make into TrustedDesc (if not SharedDesc) */ +#define HDR_MAKE_TRUSTED 0x00002000 + +/* Save context if self-shared (if SharedDesc) */ +#define HDR_SAVECTX 0x00001000 + +/* Next item points to SharedDesc */ +#define HDR_SHARED 0x00001000 + +/* + * Reverse Execution Order - execute JobDesc first, then + * execute SharedDesc (normally SharedDesc goes first). + */ +#define HDR_REVERSE 0x00000800 + +/* Propogate DNR property to SharedDesc */ +#define HDR_PROP_DNR 0x00000800 + +/* JobDesc/SharedDesc share property */ +#define HDR_SD_SHARE_MASK 0x03 +#define HDR_SD_SHARE_SHIFT 8 +#define HDR_JD_SHARE_MASK 0x07 +#define HDR_JD_SHARE_SHIFT 8 + +#define HDR_SHARE_NEVER (0x00 << HDR_SD_SHARE_SHIFT) +#define HDR_SHARE_WAIT (0x01 << HDR_SD_SHARE_SHIFT) +#define HDR_SHARE_SERIAL (0x02 << HDR_SD_SHARE_SHIFT) +#define HDR_SHARE_ALWAYS (0x03 << HDR_SD_SHARE_SHIFT) +#define HDR_SHARE_DEFER (0x04 << HDR_SD_SHARE_SHIFT) + +/* JobDesc/SharedDesc descriptor length */ +#define HDR_JD_LENGTH_MASK 0x7f +#define HDR_SD_LENGTH_MASK 0x3f + +/* + * KEY/SEQ_KEY Command Constructs + */ + +/* Key Destination Class: 01 = Class 1, 02 - Class 2 */ +#define KEY_DEST_CLASS_SHIFT 25 /* use CLASS_1 or CLASS_2 */ +#define KEY_DEST_CLASS_MASK (0x03 << KEY_DEST_CLASS_SHIFT) + +/* Scatter-Gather Table/Variable Length Field */ +#define KEY_SGF 0x01000000 +#define KEY_VLF 0x01000000 + +/* Immediate - Key follows command in the descriptor */ +#define KEY_IMM 0x00800000 + +/* + * Encrypted - Key is encrypted either with the KEK, or + * with the TDKEK if TK is set + */ +#define KEY_ENC 0x00400000 + +/* + * No Write Back - Do not allow key to be FIFO STOREd + */ +#define KEY_NWB 0x00200000 + +/* + * Enhanced Encryption of Key + */ +#define KEY_EKT 0x00100000 + +/* + * Encrypted with Trusted Key + */ +#define KEY_TK 0x00008000 + +/* + * KDEST - Key Destination: 0 - class key register, + * 1 - PKHA 'e', 2 - AFHA Sbox, 3 - MDHA split-key + */ +#define KEY_DEST_SHIFT 16 +#define KEY_DEST_MASK (0x03 << KEY_DEST_SHIFT) + +#define KEY_DEST_CLASS_REG (0x00 << KEY_DEST_SHIFT) +#define KEY_DEST_PKHA_E (0x01 << KEY_DEST_SHIFT) +#define KEY_DEST_AFHA_SBOX (0x02 << KEY_DEST_SHIFT) +#define KEY_DEST_MDHA_SPLIT (0x03 << KEY_DEST_SHIFT) + +/* Length in bytes */ +#define KEY_LENGTH_MASK 0x000003ff + +/* + * LOAD/SEQ_LOAD/STORE/SEQ_STORE Command Constructs + */ + +/* + * Load/Store Destination: 0 = class independent CCB, + * 1 = class 1 CCB, 2 = class 2 CCB, 3 = DECO + */ +#define LDST_CLASS_SHIFT 25 +#define LDST_CLASS_MASK (0x03 << LDST_CLASS_SHIFT) +#define LDST_CLASS_IND_CCB (0x00 << LDST_CLASS_SHIFT) +#define LDST_CLASS_1_CCB (0x01 << LDST_CLASS_SHIFT) +#define LDST_CLASS_2_CCB (0x02 << LDST_CLASS_SHIFT) +#define LDST_CLASS_DECO (0x03 << LDST_CLASS_SHIFT) + +/* Scatter-Gather Table/Variable Length Field */ +#define LDST_SGF 0x01000000 +#define LDST_VLF LDST_SGF + +/* Immediate - Key follows this command in descriptor */ +#define LDST_IMM_MASK 1 +#define LDST_IMM_SHIFT 23 +#define LDST_IMM (LDST_IMM_MASK << LDST_IMM_SHIFT) + +/* SRC/DST - Destination for LOAD, Source for STORE */ +#define LDST_SRCDST_SHIFT 16 +#define LDST_SRCDST_MASK (0x7f << LDST_SRCDST_SHIFT) + +#define LDST_SRCDST_BYTE_CONTEXT (0x20 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_BYTE_KEY (0x40 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_BYTE_INFIFO (0x7c << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_BYTE_OUTFIFO (0x7e << LDST_SRCDST_SHIFT) + +#define LDST_SRCDST_WORD_MODE_REG (0x00 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_KEYSZ_REG (0x01 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DATASZ_REG (0x02 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_ICVSZ_REG (0x03 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_CHACTRL (0x06 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECOCTRL (0x06 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_IRQCTRL (0x07 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_PCLOVRD (0x07 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_CLRW (0x08 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_MATH0 (0x08 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_STAT (0x09 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_MATH1 (0x09 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_MATH2 (0x0a << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_AAD_SZ (0x0b << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_MATH3 (0x0b << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_CLASS1_ICV_SZ (0x0c << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_ALTDS_CLASS1 (0x0f << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_PKHA_A_SZ (0x10 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_PKHA_B_SZ (0x11 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_PKHA_N_SZ (0x12 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_PKHA_E_SZ (0x13 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_CLASS_CTX (0x20 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF (0x40 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF_JOB (0x41 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF_SHARED (0x42 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF_JOB_WE (0x45 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF_SHARED_WE (0x46 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_INFO_FIFO (0x7a << LDST_SRCDST_SHIFT) + +/* Offset in source/destination */ +#define LDST_OFFSET_SHIFT 8 +#define LDST_OFFSET_MASK (0xff << LDST_OFFSET_SHIFT) + +/* LDOFF definitions used when DST = LDST_SRCDST_WORD_DECOCTRL */ +/* These could also be shifted by LDST_OFFSET_SHIFT - this reads better */ +#define LDOFF_CHG_SHARE_SHIFT 0 +#define LDOFF_CHG_SHARE_MASK (0x3 << LDOFF_CHG_SHARE_SHIFT) +#define LDOFF_CHG_SHARE_NEVER (0x1 << LDOFF_CHG_SHARE_SHIFT) +#define LDOFF_CHG_SHARE_OK_PROP (0x2 << LDOFF_CHG_SHARE_SHIFT) +#define LDOFF_CHG_SHARE_OK_NO_PROP (0x3 << LDOFF_CHG_SHARE_SHIFT) + +#define LDOFF_ENABLE_AUTO_NFIFO (1 << 2) +#define LDOFF_DISABLE_AUTO_NFIFO (1 << 3) + +#define LDOFF_CHG_NONSEQLIODN_SHIFT 4 +#define LDOFF_CHG_NONSEQLIODN_MASK (0x3 << LDOFF_CHG_NONSEQLIODN_SHIFT) +#define LDOFF_CHG_NONSEQLIODN_SEQ (0x1 << LDOFF_CHG_NONSEQLIODN_SHIFT) +#define LDOFF_CHG_NONSEQLIODN_NON_SEQ (0x2 << LDOFF_CHG_NONSEQLIODN_SHIFT) +#define LDOFF_CHG_NONSEQLIODN_TRUSTED (0x3 << LDOFF_CHG_NONSEQLIODN_SHIFT) + +#define LDOFF_CHG_SEQLIODN_SHIFT 6 +#define LDOFF_CHG_SEQLIODN_MASK (0x3 << LDOFF_CHG_SEQLIODN_SHIFT) +#define LDOFF_CHG_SEQLIODN_SEQ (0x1 << LDOFF_CHG_SEQLIODN_SHIFT) +#define LDOFF_CHG_SEQLIODN_NON_SEQ (0x2 << LDOFF_CHG_SEQLIODN_SHIFT) +#define LDOFF_CHG_SEQLIODN_TRUSTED (0x3 << LDOFF_CHG_SEQLIODN_SHIFT) + +/* Data length in bytes */ +#define LDST_LEN_SHIFT 0 +#define LDST_LEN_MASK (0xff << LDST_LEN_SHIFT) + +/* Special Length definitions when dst=deco-ctrl */ +#define LDLEN_ENABLE_OSL_COUNT (1 << 7) +#define LDLEN_RST_CHA_OFIFO_PTR (1 << 6) +#define LDLEN_RST_OFIFO (1 << 5) +#define LDLEN_SET_OFIFO_OFF_VALID (1 << 4) +#define LDLEN_SET_OFIFO_OFF_RSVD (1 << 3) +#define LDLEN_SET_OFIFO_OFFSET_SHIFT 0 +#define LDLEN_SET_OFIFO_OFFSET_MASK (3 << LDLEN_SET_OFIFO_OFFSET_SHIFT) + +/* + * FIFO_LOAD/FIFO_STORE/SEQ_FIFO_LOAD/SEQ_FIFO_STORE + * Command Constructs + */ + +/* + * Load Destination: 0 = skip (SEQ_FIFO_LOAD only), + * 1 = Load for Class1, 2 = Load for Class2, 3 = Load both + * Store Source: 0 = normal, 1 = Class1key, 2 = Class2key + */ +#define FIFOLD_CLASS_SHIFT 25 +#define FIFOLD_CLASS_MASK (0x03 << FIFOLD_CLASS_SHIFT) +#define FIFOLD_CLASS_SKIP (0x00 << FIFOLD_CLASS_SHIFT) +#define FIFOLD_CLASS_CLASS1 (0x01 << FIFOLD_CLASS_SHIFT) +#define FIFOLD_CLASS_CLASS2 (0x02 << FIFOLD_CLASS_SHIFT) +#define FIFOLD_CLASS_BOTH (0x03 << FIFOLD_CLASS_SHIFT) + +#define FIFOST_CLASS_SHIFT 25 +#define FIFOST_CLASS_MASK (0x03 << FIFOST_CLASS_SHIFT) +#define FIFOST_CLASS_NORMAL (0x00 << FIFOST_CLASS_SHIFT) +#define FIFOST_CLASS_CLASS1KEY (0x01 << FIFOST_CLASS_SHIFT) +#define FIFOST_CLASS_CLASS2KEY (0x02 << FIFOST_CLASS_SHIFT) + +/* + * Scatter-Gather Table/Variable Length Field + * If set for FIFO_LOAD, refers to a SG table. Within + * SEQ_FIFO_LOAD, is variable input sequence + */ +#define FIFOLDST_SGF_SHIFT 24 +#define FIFOLDST_SGF_MASK (1 << FIFOLDST_SGF_SHIFT) +#define FIFOLDST_VLF_MASK (1 << FIFOLDST_SGF_SHIFT) +#define FIFOLDST_SGF (1 << FIFOLDST_SGF_SHIFT) +#define FIFOLDST_VLF (1 << FIFOLDST_SGF_SHIFT) + +/* Immediate - Data follows command in descriptor */ +#define FIFOLD_IMM_SHIFT 23 +#define FIFOLD_IMM_MASK (1 << FIFOLD_IMM_SHIFT) +#define FIFOLD_IMM (1 << FIFOLD_IMM_SHIFT) + +/* Continue - Not the last FIFO store to come */ +#define FIFOST_CONT_SHIFT 23 +#define FIFOST_CONT_MASK (1 << FIFOST_CONT_SHIFT) + +/* + * Extended Length - use 32-bit extended length that + * follows the pointer field. Illegal with IMM set + */ +#define FIFOLDST_EXT_SHIFT 22 +#define FIFOLDST_EXT_MASK (1 << FIFOLDST_EXT_SHIFT) +#define FIFOLDST_EXT (1 << FIFOLDST_EXT_SHIFT) + +/* Input data type.*/ +#define FIFOLD_TYPE_SHIFT 16 +#define FIFOLD_CONT_TYPE_SHIFT 19 /* shift past last-flush bits */ +#define FIFOLD_TYPE_MASK (0x3f << FIFOLD_TYPE_SHIFT) + +/* PK types */ +#define FIFOLD_TYPE_PK (0x00 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_MASK (0x30 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_TYPEMASK (0x0f << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A0 (0x00 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A1 (0x01 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A2 (0x02 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A3 (0x03 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B0 (0x04 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B1 (0x05 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B2 (0x06 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B3 (0x07 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_N (0x08 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A (0x0c << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B (0x0d << FIFOLD_TYPE_SHIFT) + +/* Other types. Need to OR in last/flush bits as desired */ +#define FIFOLD_TYPE_MSG_MASK (0x38 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_MSG (0x10 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_MSG1OUT2 (0x18 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_IV (0x20 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_BITDATA (0x28 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_AAD (0x30 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_ICV (0x38 << FIFOLD_TYPE_SHIFT) + +/* Last/Flush bits for use with "other" types above */ +#define FIFOLD_TYPE_ACT_MASK (0x07 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_NOACTION (0x00 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_FLUSH1 (0x01 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LAST1 (0x02 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LAST2FLUSH (0x03 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LAST2 (0x04 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LAST2FLUSH1 (0x05 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LASTBOTH (0x06 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LASTBOTHFL (0x07 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_NOINFOFIFO (0x0F << FIFOLD_TYPE_SHIFT) + +#define FIFOLDST_LEN_MASK 0xffff +#define FIFOLDST_EXT_LEN_MASK 0xffffffff + +/* Output data types */ +#define FIFOST_TYPE_SHIFT 16 +#define FIFOST_TYPE_MASK (0x3f << FIFOST_TYPE_SHIFT) + +#define FIFOST_TYPE_PKHA_A0 (0x00 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_A1 (0x01 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_A2 (0x02 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_A3 (0x03 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B0 (0x04 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B1 (0x05 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B2 (0x06 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B3 (0x07 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_N (0x08 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_A (0x0c << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B (0x0d << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_AF_SBOX_CCM_JKEK (0x10 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_AF_SBOX_CCM_TKEK (0x11 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_CCM_JKEK (0x14 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_CCM_TKEK (0x15 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_E_JKEK (0x22 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_E_TKEK (0x23 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_KEK (0x24 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_TKEK (0x25 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_SPLIT_KEK (0x26 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_SPLIT_TKEK (0x27 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_OUTFIFO_KEK (0x28 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_OUTFIFO_TKEK (0x29 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_MESSAGE_DATA (0x30 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_RNGSTORE (0x34 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_RNGFIFO (0x35 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_SKIP (0x3f << FIFOST_TYPE_SHIFT) + +/* + * OPERATION Command Constructs + */ + +/* Operation type selectors - OP TYPE */ +#define OP_TYPE_SHIFT 24 +#define OP_TYPE_MASK (0x07 << OP_TYPE_SHIFT) + +#define OP_TYPE_UNI_PROTOCOL (0x00 << OP_TYPE_SHIFT) +#define OP_TYPE_PK (0x01 << OP_TYPE_SHIFT) +#define OP_TYPE_CLASS1_ALG (0x02 << OP_TYPE_SHIFT) +#define OP_TYPE_CLASS2_ALG (0x04 << OP_TYPE_SHIFT) +#define OP_TYPE_DECAP_PROTOCOL (0x06 << OP_TYPE_SHIFT) +#define OP_TYPE_ENCAP_PROTOCOL (0x07 << OP_TYPE_SHIFT) + +/* ProtocolID selectors - PROTID */ +#define OP_PCLID_SHIFT 16 +#define OP_PCLID_MASK (0xff << 16) + +/* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */ +#define OP_PCLID_IKEV1_PRF (0x01 << OP_PCLID_SHIFT) +#define OP_PCLID_IKEV2_PRF (0x02 << OP_PCLID_SHIFT) +#define OP_PCLID_SSL30_PRF (0x08 << OP_PCLID_SHIFT) +#define OP_PCLID_TLS10_PRF (0x09 << OP_PCLID_SHIFT) +#define OP_PCLID_TLS11_PRF (0x0a << OP_PCLID_SHIFT) +#define OP_PCLID_DTLS10_PRF (0x0c << OP_PCLID_SHIFT) +#define OP_PCLID_PRF (0x06 << OP_PCLID_SHIFT) +#define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT) +#define OP_PCLID_SECRETKEY (0x11 << OP_PCLID_SHIFT) +#define OP_PCLID_PUBLICKEYPAIR (0x14 << OP_PCLID_SHIFT) +#define OP_PCLID_DSASIGN (0x15 << OP_PCLID_SHIFT) +#define OP_PCLID_DSAVERIFY (0x16 << OP_PCLID_SHIFT) + +/* Assuming OP_TYPE = OP_TYPE_DECAP_PROTOCOL/ENCAP_PROTOCOL */ +#define OP_PCLID_IPSEC (0x01 << OP_PCLID_SHIFT) +#define OP_PCLID_SRTP (0x02 << OP_PCLID_SHIFT) +#define OP_PCLID_MACSEC (0x03 << OP_PCLID_SHIFT) +#define OP_PCLID_WIFI (0x04 << OP_PCLID_SHIFT) +#define OP_PCLID_WIMAX (0x05 << OP_PCLID_SHIFT) +#define OP_PCLID_SSL30 (0x08 << OP_PCLID_SHIFT) +#define OP_PCLID_TLS10 (0x09 << OP_PCLID_SHIFT) +#define OP_PCLID_TLS11 (0x0a << OP_PCLID_SHIFT) +#define OP_PCLID_TLS12 (0x0b << OP_PCLID_SHIFT) +#define OP_PCLID_DTLS (0x0c << OP_PCLID_SHIFT) + +/* + * ProtocolInfo selectors + */ +#define OP_PCLINFO_MASK 0xffff + +/* for OP_PCLID_IPSEC */ +#define OP_PCL_IPSEC_CIPHER_MASK 0xff00 +#define OP_PCL_IPSEC_AUTH_MASK 0x00ff + +#define OP_PCL_IPSEC_DES_IV64 0x0100 +#define OP_PCL_IPSEC_DES 0x0200 +#define OP_PCL_IPSEC_3DES 0x0300 +#define OP_PCL_IPSEC_AES_CBC 0x0c00 +#define OP_PCL_IPSEC_AES_CTR 0x0d00 +#define OP_PCL_IPSEC_AES_XTS 0x1600 +#define OP_PCL_IPSEC_AES_CCM8 0x0e00 +#define OP_PCL_IPSEC_AES_CCM12 0x0f00 +#define OP_PCL_IPSEC_AES_CCM16 0x1000 +#define OP_PCL_IPSEC_AES_GCM8 0x1200 +#define OP_PCL_IPSEC_AES_GCM12 0x1300 +#define OP_PCL_IPSEC_AES_GCM16 0x1400 + +#define OP_PCL_IPSEC_HMAC_NULL 0x0000 +#define OP_PCL_IPSEC_HMAC_MD5_96 0x0001 +#define OP_PCL_IPSEC_HMAC_SHA1_96 0x0002 +#define OP_PCL_IPSEC_AES_XCBC_MAC_96 0x0005 +#define OP_PCL_IPSEC_HMAC_MD5_128 0x0006 +#define OP_PCL_IPSEC_HMAC_SHA1_160 0x0007 +#define OP_PCL_IPSEC_HMAC_SHA2_256_128 0x000c +#define OP_PCL_IPSEC_HMAC_SHA2_384_192 0x000d +#define OP_PCL_IPSEC_HMAC_SHA2_512_256 0x000e + +/* For SRTP - OP_PCLID_SRTP */ +#define OP_PCL_SRTP_CIPHER_MASK 0xff00 +#define OP_PCL_SRTP_AUTH_MASK 0x00ff + +#define OP_PCL_SRTP_AES_CTR 0x0d00 + +#define OP_PCL_SRTP_HMAC_SHA1_160 0x0007 + +/* For SSL 3.0 - OP_PCLID_SSL30 */ +#define OP_PCL_SSL30_AES_128_CBC_SHA 0x002f +#define OP_PCL_SSL30_AES_128_CBC_SHA_2 0x0030 +#define OP_PCL_SSL30_AES_128_CBC_SHA_3 0x0031 +#define OP_PCL_SSL30_AES_128_CBC_SHA_4 0x0032 +#define OP_PCL_SSL30_AES_128_CBC_SHA_5 0x0033 +#define OP_PCL_SSL30_AES_128_CBC_SHA_6 0x0034 +#define OP_PCL_SSL30_AES_128_CBC_SHA_7 0x008c +#define OP_PCL_SSL30_AES_128_CBC_SHA_8 0x0090 +#define OP_PCL_SSL30_AES_128_CBC_SHA_9 0x0094 +#define OP_PCL_SSL30_AES_128_CBC_SHA_10 0xc004 +#define OP_PCL_SSL30_AES_128_CBC_SHA_11 0xc009 +#define OP_PCL_SSL30_AES_128_CBC_SHA_12 0xc00e +#define OP_PCL_SSL30_AES_128_CBC_SHA_13 0xc013 +#define OP_PCL_SSL30_AES_128_CBC_SHA_14 0xc018 +#define OP_PCL_SSL30_AES_128_CBC_SHA_15 0xc01d +#define OP_PCL_SSL30_AES_128_CBC_SHA_16 0xc01e +#define OP_PCL_SSL30_AES_128_CBC_SHA_17 0xc01f + +#define OP_PCL_SSL30_AES_256_CBC_SHA 0x0035 +#define OP_PCL_SSL30_AES_256_CBC_SHA_2 0x0036 +#define OP_PCL_SSL30_AES_256_CBC_SHA_3 0x0037 +#define OP_PCL_SSL30_AES_256_CBC_SHA_4 0x0038 +#define OP_PCL_SSL30_AES_256_CBC_SHA_5 0x0039 +#define OP_PCL_SSL30_AES_256_CBC_SHA_6 0x003a +#define OP_PCL_SSL30_AES_256_CBC_SHA_7 0x008d +#define OP_PCL_SSL30_AES_256_CBC_SHA_8 0x0091 +#define OP_PCL_SSL30_AES_256_CBC_SHA_9 0x0095 +#define OP_PCL_SSL30_AES_256_CBC_SHA_10 0xc005 +#define OP_PCL_SSL30_AES_256_CBC_SHA_11 0xc00a +#define OP_PCL_SSL30_AES_256_CBC_SHA_12 0xc00f +#define OP_PCL_SSL30_AES_256_CBC_SHA_13 0xc014 +#define OP_PCL_SSL30_AES_256_CBC_SHA_14 0xc019 +#define OP_PCL_SSL30_AES_256_CBC_SHA_15 0xc020 +#define OP_PCL_SSL30_AES_256_CBC_SHA_16 0xc021 +#define OP_PCL_SSL30_AES_256_CBC_SHA_17 0xc022 + +#define OP_PCL_SSL30_3DES_EDE_CBC_MD5 0x0023 + +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA 0x001f +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_2 0x008b +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_3 0x008f +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_4 0x0093 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_5 0x000a +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_6 0x000d +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_7 0x0010 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_8 0x0013 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_9 0x0016 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_10 0x001b +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_11 0xc003 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_12 0xc008 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_13 0xc00d +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_14 0xc012 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_15 0xc017 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_16 0xc01a +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_17 0xc01b +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_18 0xc01c + +#define OP_PCL_SSL30_DES40_CBC_MD5 0x0029 + +#define OP_PCL_SSL30_DES_CBC_MD5 0x0022 + +#define OP_PCL_SSL30_DES40_CBC_SHA 0x0008 +#define OP_PCL_SSL30_DES40_CBC_SHA_2 0x000b +#define OP_PCL_SSL30_DES40_CBC_SHA_3 0x000e +#define OP_PCL_SSL30_DES40_CBC_SHA_4 0x0011 +#define OP_PCL_SSL30_DES40_CBC_SHA_5 0x0014 +#define OP_PCL_SSL30_DES40_CBC_SHA_6 0x0019 +#define OP_PCL_SSL30_DES40_CBC_SHA_7 0x0026 + +#define OP_PCL_SSL30_DES_CBC_SHA 0x001e +#define OP_PCL_SSL30_DES_CBC_SHA_2 0x0009 +#define OP_PCL_SSL30_DES_CBC_SHA_3 0x000c +#define OP_PCL_SSL30_DES_CBC_SHA_4 0x000f +#define OP_PCL_SSL30_DES_CBC_SHA_5 0x0012 +#define OP_PCL_SSL30_DES_CBC_SHA_6 0x0015 +#define OP_PCL_SSL30_DES_CBC_SHA_7 0x001a + +#define OP_PCL_SSL30_RC4_128_MD5 0x0024 +#define OP_PCL_SSL30_RC4_128_MD5_2 0x0004 +#define OP_PCL_SSL30_RC4_128_MD5_3 0x0018 + +#define OP_PCL_SSL30_RC4_40_MD5 0x002b +#define OP_PCL_SSL30_RC4_40_MD5_2 0x0003 +#define OP_PCL_SSL30_RC4_40_MD5_3 0x0017 + +#define OP_PCL_SSL30_RC4_128_SHA 0x0020 +#define OP_PCL_SSL30_RC4_128_SHA_2 0x008a +#define OP_PCL_SSL30_RC4_128_SHA_3 0x008e +#define OP_PCL_SSL30_RC4_128_SHA_4 0x0092 +#define OP_PCL_SSL30_RC4_128_SHA_5 0x0005 +#define OP_PCL_SSL30_RC4_128_SHA_6 0xc002 +#define OP_PCL_SSL30_RC4_128_SHA_7 0xc007 +#define OP_PCL_SSL30_RC4_128_SHA_8 0xc00c +#define OP_PCL_SSL30_RC4_128_SHA_9 0xc011 +#define OP_PCL_SSL30_RC4_128_SHA_10 0xc016 + +#define OP_PCL_SSL30_RC4_40_SHA 0x0028 + + +/* For TLS 1.0 - OP_PCLID_TLS10 */ +#define OP_PCL_TLS10_AES_128_CBC_SHA 0x002f +#define OP_PCL_TLS10_AES_128_CBC_SHA_2 0x0030 +#define OP_PCL_TLS10_AES_128_CBC_SHA_3 0x0031 +#define OP_PCL_TLS10_AES_128_CBC_SHA_4 0x0032 +#define OP_PCL_TLS10_AES_128_CBC_SHA_5 0x0033 +#define OP_PCL_TLS10_AES_128_CBC_SHA_6 0x0034 +#define OP_PCL_TLS10_AES_128_CBC_SHA_7 0x008c +#define OP_PCL_TLS10_AES_128_CBC_SHA_8 0x0090 +#define OP_PCL_TLS10_AES_128_CBC_SHA_9 0x0094 +#define OP_PCL_TLS10_AES_128_CBC_SHA_10 0xc004 +#define OP_PCL_TLS10_AES_128_CBC_SHA_11 0xc009 +#define OP_PCL_TLS10_AES_128_CBC_SHA_12 0xc00e +#define OP_PCL_TLS10_AES_128_CBC_SHA_13 0xc013 +#define OP_PCL_TLS10_AES_128_CBC_SHA_14 0xc018 +#define OP_PCL_TLS10_AES_128_CBC_SHA_15 0xc01d +#define OP_PCL_TLS10_AES_128_CBC_SHA_16 0xc01e +#define OP_PCL_TLS10_AES_128_CBC_SHA_17 0xc01f + +#define OP_PCL_TLS10_AES_256_CBC_SHA 0x0035 +#define OP_PCL_TLS10_AES_256_CBC_SHA_2 0x0036 +#define OP_PCL_TLS10_AES_256_CBC_SHA_3 0x0037 +#define OP_PCL_TLS10_AES_256_CBC_SHA_4 0x0038 +#define OP_PCL_TLS10_AES_256_CBC_SHA_5 0x0039 +#define OP_PCL_TLS10_AES_256_CBC_SHA_6 0x003a +#define OP_PCL_TLS10_AES_256_CBC_SHA_7 0x008d +#define OP_PCL_TLS10_AES_256_CBC_SHA_8 0x0091 +#define OP_PCL_TLS10_AES_256_CBC_SHA_9 0x0095 +#define OP_PCL_TLS10_AES_256_CBC_SHA_10 0xc005 +#define OP_PCL_TLS10_AES_256_CBC_SHA_11 0xc00a +#define OP_PCL_TLS10_AES_256_CBC_SHA_12 0xc00f +#define OP_PCL_TLS10_AES_256_CBC_SHA_13 0xc014 +#define OP_PCL_TLS10_AES_256_CBC_SHA_14 0xc019 +#define OP_PCL_TLS10_AES_256_CBC_SHA_15 0xc020 +#define OP_PCL_TLS10_AES_256_CBC_SHA_16 0xc021 +#define OP_PCL_TLS10_AES_256_CBC_SHA_17 0xc022 + +/* #define OP_PCL_TLS10_3DES_EDE_CBC_MD5 0x0023 */ + +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA 0x001f +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_2 0x008b +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_3 0x008f +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_4 0x0093 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_5 0x000a +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_6 0x000d +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_7 0x0010 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_8 0x0013 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_9 0x0016 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_10 0x001b +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_11 0xc003 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_12 0xc008 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_13 0xc00d +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_14 0xc012 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_15 0xc017 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_16 0xc01a +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_17 0xc01b +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_18 0xc01c + +#define OP_PCL_TLS10_DES40_CBC_MD5 0x0029 + +#define OP_PCL_TLS10_DES_CBC_MD5 0x0022 + +#define OP_PCL_TLS10_DES40_CBC_SHA 0x0008 +#define OP_PCL_TLS10_DES40_CBC_SHA_2 0x000b +#define OP_PCL_TLS10_DES40_CBC_SHA_3 0x000e +#define OP_PCL_TLS10_DES40_CBC_SHA_4 0x0011 +#define OP_PCL_TLS10_DES40_CBC_SHA_5 0x0014 +#define OP_PCL_TLS10_DES40_CBC_SHA_6 0x0019 +#define OP_PCL_TLS10_DES40_CBC_SHA_7 0x0026 + + +#define OP_PCL_TLS10_DES_CBC_SHA 0x001e +#define OP_PCL_TLS10_DES_CBC_SHA_2 0x0009 +#define OP_PCL_TLS10_DES_CBC_SHA_3 0x000c +#define OP_PCL_TLS10_DES_CBC_SHA_4 0x000f +#define OP_PCL_TLS10_DES_CBC_SHA_5 0x0012 +#define OP_PCL_TLS10_DES_CBC_SHA_6 0x0015 +#define OP_PCL_TLS10_DES_CBC_SHA_7 0x001a + +#define OP_PCL_TLS10_RC4_128_MD5 0x0024 +#define OP_PCL_TLS10_RC4_128_MD5_2 0x0004 +#define OP_PCL_TLS10_RC4_128_MD5_3 0x0018 + +#define OP_PCL_TLS10_RC4_40_MD5 0x002b +#define OP_PCL_TLS10_RC4_40_MD5_2 0x0003 +#define OP_PCL_TLS10_RC4_40_MD5_3 0x0017 + +#define OP_PCL_TLS10_RC4_128_SHA 0x0020 +#define OP_PCL_TLS10_RC4_128_SHA_2 0x008a +#define OP_PCL_TLS10_RC4_128_SHA_3 0x008e +#define OP_PCL_TLS10_RC4_128_SHA_4 0x0092 +#define OP_PCL_TLS10_RC4_128_SHA_5 0x0005 +#define OP_PCL_TLS10_RC4_128_SHA_6 0xc002 +#define OP_PCL_TLS10_RC4_128_SHA_7 0xc007 +#define OP_PCL_TLS10_RC4_128_SHA_8 0xc00c +#define OP_PCL_TLS10_RC4_128_SHA_9 0xc011 +#define OP_PCL_TLS10_RC4_128_SHA_10 0xc016 + +#define OP_PCL_TLS10_RC4_40_SHA 0x0028 + +#define OP_PCL_TLS10_3DES_EDE_CBC_MD5 0xff23 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA160 0xff30 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA224 0xff34 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA256 0xff36 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA384 0xff33 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA512 0xff35 +#define OP_PCL_TLS10_AES_128_CBC_SHA160 0xff80 +#define OP_PCL_TLS10_AES_128_CBC_SHA224 0xff84 +#define OP_PCL_TLS10_AES_128_CBC_SHA256 0xff86 +#define OP_PCL_TLS10_AES_128_CBC_SHA384 0xff83 +#define OP_PCL_TLS10_AES_128_CBC_SHA512 0xff85 +#define OP_PCL_TLS10_AES_192_CBC_SHA160 0xff20 +#define OP_PCL_TLS10_AES_192_CBC_SHA224 0xff24 +#define OP_PCL_TLS10_AES_192_CBC_SHA256 0xff26 +#define OP_PCL_TLS10_AES_192_CBC_SHA384 0xff23 +#define OP_PCL_TLS10_AES_192_CBC_SHA512 0xff25 +#define OP_PCL_TLS10_AES_256_CBC_SHA160 0xff60 +#define OP_PCL_TLS10_AES_256_CBC_SHA224 0xff64 +#define OP_PCL_TLS10_AES_256_CBC_SHA256 0xff66 +#define OP_PCL_TLS10_AES_256_CBC_SHA384 0xff63 +#define OP_PCL_TLS10_AES_256_CBC_SHA512 0xff65 + + + +/* For TLS 1.1 - OP_PCLID_TLS11 */ +#define OP_PCL_TLS11_AES_128_CBC_SHA 0x002f +#define OP_PCL_TLS11_AES_128_CBC_SHA_2 0x0030 +#define OP_PCL_TLS11_AES_128_CBC_SHA_3 0x0031 +#define OP_PCL_TLS11_AES_128_CBC_SHA_4 0x0032 +#define OP_PCL_TLS11_AES_128_CBC_SHA_5 0x0033 +#define OP_PCL_TLS11_AES_128_CBC_SHA_6 0x0034 +#define OP_PCL_TLS11_AES_128_CBC_SHA_7 0x008c +#define OP_PCL_TLS11_AES_128_CBC_SHA_8 0x0090 +#define OP_PCL_TLS11_AES_128_CBC_SHA_9 0x0094 +#define OP_PCL_TLS11_AES_128_CBC_SHA_10 0xc004 +#define OP_PCL_TLS11_AES_128_CBC_SHA_11 0xc009 +#define OP_PCL_TLS11_AES_128_CBC_SHA_12 0xc00e +#define OP_PCL_TLS11_AES_128_CBC_SHA_13 0xc013 +#define OP_PCL_TLS11_AES_128_CBC_SHA_14 0xc018 +#define OP_PCL_TLS11_AES_128_CBC_SHA_15 0xc01d +#define OP_PCL_TLS11_AES_128_CBC_SHA_16 0xc01e +#define OP_PCL_TLS11_AES_128_CBC_SHA_17 0xc01f + +#define OP_PCL_TLS11_AES_256_CBC_SHA 0x0035 +#define OP_PCL_TLS11_AES_256_CBC_SHA_2 0x0036 +#define OP_PCL_TLS11_AES_256_CBC_SHA_3 0x0037 +#define OP_PCL_TLS11_AES_256_CBC_SHA_4 0x0038 +#define OP_PCL_TLS11_AES_256_CBC_SHA_5 0x0039 +#define OP_PCL_TLS11_AES_256_CBC_SHA_6 0x003a +#define OP_PCL_TLS11_AES_256_CBC_SHA_7 0x008d +#define OP_PCL_TLS11_AES_256_CBC_SHA_8 0x0091 +#define OP_PCL_TLS11_AES_256_CBC_SHA_9 0x0095 +#define OP_PCL_TLS11_AES_256_CBC_SHA_10 0xc005 +#define OP_PCL_TLS11_AES_256_CBC_SHA_11 0xc00a +#define OP_PCL_TLS11_AES_256_CBC_SHA_12 0xc00f +#define OP_PCL_TLS11_AES_256_CBC_SHA_13 0xc014 +#define OP_PCL_TLS11_AES_256_CBC_SHA_14 0xc019 +#define OP_PCL_TLS11_AES_256_CBC_SHA_15 0xc020 +#define OP_PCL_TLS11_AES_256_CBC_SHA_16 0xc021 +#define OP_PCL_TLS11_AES_256_CBC_SHA_17 0xc022 + +/* #define OP_PCL_TLS11_3DES_EDE_CBC_MD5 0x0023 */ + +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA 0x001f +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_2 0x008b +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_3 0x008f +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_4 0x0093 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_5 0x000a +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_6 0x000d +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_7 0x0010 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_8 0x0013 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_9 0x0016 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_10 0x001b +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_11 0xc003 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_12 0xc008 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_13 0xc00d +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_14 0xc012 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_15 0xc017 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_16 0xc01a +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_17 0xc01b +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_18 0xc01c + +#define OP_PCL_TLS11_DES40_CBC_MD5 0x0029 + +#define OP_PCL_TLS11_DES_CBC_MD5 0x0022 + +#define OP_PCL_TLS11_DES40_CBC_SHA 0x0008 +#define OP_PCL_TLS11_DES40_CBC_SHA_2 0x000b +#define OP_PCL_TLS11_DES40_CBC_SHA_3 0x000e +#define OP_PCL_TLS11_DES40_CBC_SHA_4 0x0011 +#define OP_PCL_TLS11_DES40_CBC_SHA_5 0x0014 +#define OP_PCL_TLS11_DES40_CBC_SHA_6 0x0019 +#define OP_PCL_TLS11_DES40_CBC_SHA_7 0x0026 + +#define OP_PCL_TLS11_DES_CBC_SHA 0x001e +#define OP_PCL_TLS11_DES_CBC_SHA_2 0x0009 +#define OP_PCL_TLS11_DES_CBC_SHA_3 0x000c +#define OP_PCL_TLS11_DES_CBC_SHA_4 0x000f +#define OP_PCL_TLS11_DES_CBC_SHA_5 0x0012 +#define OP_PCL_TLS11_DES_CBC_SHA_6 0x0015 +#define OP_PCL_TLS11_DES_CBC_SHA_7 0x001a + +#define OP_PCL_TLS11_RC4_128_MD5 0x0024 +#define OP_PCL_TLS11_RC4_128_MD5_2 0x0004 +#define OP_PCL_TLS11_RC4_128_MD5_3 0x0018 + +#define OP_PCL_TLS11_RC4_40_MD5 0x002b +#define OP_PCL_TLS11_RC4_40_MD5_2 0x0003 +#define OP_PCL_TLS11_RC4_40_MD5_3 0x0017 + +#define OP_PCL_TLS11_RC4_128_SHA 0x0020 +#define OP_PCL_TLS11_RC4_128_SHA_2 0x008a +#define OP_PCL_TLS11_RC4_128_SHA_3 0x008e +#define OP_PCL_TLS11_RC4_128_SHA_4 0x0092 +#define OP_PCL_TLS11_RC4_128_SHA_5 0x0005 +#define OP_PCL_TLS11_RC4_128_SHA_6 0xc002 +#define OP_PCL_TLS11_RC4_128_SHA_7 0xc007 +#define OP_PCL_TLS11_RC4_128_SHA_8 0xc00c +#define OP_PCL_TLS11_RC4_128_SHA_9 0xc011 +#define OP_PCL_TLS11_RC4_128_SHA_10 0xc016 + +#define OP_PCL_TLS11_RC4_40_SHA 0x0028 + +#define OP_PCL_TLS11_3DES_EDE_CBC_MD5 0xff23 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA160 0xff30 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA224 0xff34 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA256 0xff36 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA384 0xff33 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA512 0xff35 +#define OP_PCL_TLS11_AES_128_CBC_SHA160 0xff80 +#define OP_PCL_TLS11_AES_128_CBC_SHA224 0xff84 +#define OP_PCL_TLS11_AES_128_CBC_SHA256 0xff86 +#define OP_PCL_TLS11_AES_128_CBC_SHA384 0xff83 +#define OP_PCL_TLS11_AES_128_CBC_SHA512 0xff85 +#define OP_PCL_TLS11_AES_192_CBC_SHA160 0xff20 +#define OP_PCL_TLS11_AES_192_CBC_SHA224 0xff24 +#define OP_PCL_TLS11_AES_192_CBC_SHA256 0xff26 +#define OP_PCL_TLS11_AES_192_CBC_SHA384 0xff23 +#define OP_PCL_TLS11_AES_192_CBC_SHA512 0xff25 +#define OP_PCL_TLS11_AES_256_CBC_SHA160 0xff60 +#define OP_PCL_TLS11_AES_256_CBC_SHA224 0xff64 +#define OP_PCL_TLS11_AES_256_CBC_SHA256 0xff66 +#define OP_PCL_TLS11_AES_256_CBC_SHA384 0xff63 +#define OP_PCL_TLS11_AES_256_CBC_SHA512 0xff65 + + +/* For TLS 1.2 - OP_PCLID_TLS12 */ +#define OP_PCL_TLS12_AES_128_CBC_SHA 0x002f +#define OP_PCL_TLS12_AES_128_CBC_SHA_2 0x0030 +#define OP_PCL_TLS12_AES_128_CBC_SHA_3 0x0031 +#define OP_PCL_TLS12_AES_128_CBC_SHA_4 0x0032 +#define OP_PCL_TLS12_AES_128_CBC_SHA_5 0x0033 +#define OP_PCL_TLS12_AES_128_CBC_SHA_6 0x0034 +#define OP_PCL_TLS12_AES_128_CBC_SHA_7 0x008c +#define OP_PCL_TLS12_AES_128_CBC_SHA_8 0x0090 +#define OP_PCL_TLS12_AES_128_CBC_SHA_9 0x0094 +#define OP_PCL_TLS12_AES_128_CBC_SHA_10 0xc004 +#define OP_PCL_TLS12_AES_128_CBC_SHA_11 0xc009 +#define OP_PCL_TLS12_AES_128_CBC_SHA_12 0xc00e +#define OP_PCL_TLS12_AES_128_CBC_SHA_13 0xc013 +#define OP_PCL_TLS12_AES_128_CBC_SHA_14 0xc018 +#define OP_PCL_TLS12_AES_128_CBC_SHA_15 0xc01d +#define OP_PCL_TLS12_AES_128_CBC_SHA_16 0xc01e +#define OP_PCL_TLS12_AES_128_CBC_SHA_17 0xc01f + +#define OP_PCL_TLS12_AES_256_CBC_SHA 0x0035 +#define OP_PCL_TLS12_AES_256_CBC_SHA_2 0x0036 +#define OP_PCL_TLS12_AES_256_CBC_SHA_3 0x0037 +#define OP_PCL_TLS12_AES_256_CBC_SHA_4 0x0038 +#define OP_PCL_TLS12_AES_256_CBC_SHA_5 0x0039 +#define OP_PCL_TLS12_AES_256_CBC_SHA_6 0x003a +#define OP_PCL_TLS12_AES_256_CBC_SHA_7 0x008d +#define OP_PCL_TLS12_AES_256_CBC_SHA_8 0x0091 +#define OP_PCL_TLS12_AES_256_CBC_SHA_9 0x0095 +#define OP_PCL_TLS12_AES_256_CBC_SHA_10 0xc005 +#define OP_PCL_TLS12_AES_256_CBC_SHA_11 0xc00a +#define OP_PCL_TLS12_AES_256_CBC_SHA_12 0xc00f +#define OP_PCL_TLS12_AES_256_CBC_SHA_13 0xc014 +#define OP_PCL_TLS12_AES_256_CBC_SHA_14 0xc019 +#define OP_PCL_TLS12_AES_256_CBC_SHA_15 0xc020 +#define OP_PCL_TLS12_AES_256_CBC_SHA_16 0xc021 +#define OP_PCL_TLS12_AES_256_CBC_SHA_17 0xc022 + +/* #define OP_PCL_TLS12_3DES_EDE_CBC_MD5 0x0023 */ + +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA 0x001f +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_2 0x008b +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_3 0x008f +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_4 0x0093 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_5 0x000a +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_6 0x000d +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_7 0x0010 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_8 0x0013 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_9 0x0016 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_10 0x001b +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_11 0xc003 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_12 0xc008 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_13 0xc00d +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_14 0xc012 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_15 0xc017 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_16 0xc01a +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_17 0xc01b +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_18 0xc01c + +#define OP_PCL_TLS12_DES40_CBC_MD5 0x0029 + +#define OP_PCL_TLS12_DES_CBC_MD5 0x0022 + +#define OP_PCL_TLS12_DES40_CBC_SHA 0x0008 +#define OP_PCL_TLS12_DES40_CBC_SHA_2 0x000b +#define OP_PCL_TLS12_DES40_CBC_SHA_3 0x000e +#define OP_PCL_TLS12_DES40_CBC_SHA_4 0x0011 +#define OP_PCL_TLS12_DES40_CBC_SHA_5 0x0014 +#define OP_PCL_TLS12_DES40_CBC_SHA_6 0x0019 +#define OP_PCL_TLS12_DES40_CBC_SHA_7 0x0026 + +#define OP_PCL_TLS12_DES_CBC_SHA 0x001e +#define OP_PCL_TLS12_DES_CBC_SHA_2 0x0009 +#define OP_PCL_TLS12_DES_CBC_SHA_3 0x000c +#define OP_PCL_TLS12_DES_CBC_SHA_4 0x000f +#define OP_PCL_TLS12_DES_CBC_SHA_5 0x0012 +#define OP_PCL_TLS12_DES_CBC_SHA_6 0x0015 +#define OP_PCL_TLS12_DES_CBC_SHA_7 0x001a + +#define OP_PCL_TLS12_RC4_128_MD5 0x0024 +#define OP_PCL_TLS12_RC4_128_MD5_2 0x0004 +#define OP_PCL_TLS12_RC4_128_MD5_3 0x0018 + +#define OP_PCL_TLS12_RC4_40_MD5 0x002b +#define OP_PCL_TLS12_RC4_40_MD5_2 0x0003 +#define OP_PCL_TLS12_RC4_40_MD5_3 0x0017 + +#define OP_PCL_TLS12_RC4_128_SHA 0x0020 +#define OP_PCL_TLS12_RC4_128_SHA_2 0x008a +#define OP_PCL_TLS12_RC4_128_SHA_3 0x008e +#define OP_PCL_TLS12_RC4_128_SHA_4 0x0092 +#define OP_PCL_TLS12_RC4_128_SHA_5 0x0005 +#define OP_PCL_TLS12_RC4_128_SHA_6 0xc002 +#define OP_PCL_TLS12_RC4_128_SHA_7 0xc007 +#define OP_PCL_TLS12_RC4_128_SHA_8 0xc00c +#define OP_PCL_TLS12_RC4_128_SHA_9 0xc011 +#define OP_PCL_TLS12_RC4_128_SHA_10 0xc016 + +#define OP_PCL_TLS12_RC4_40_SHA 0x0028 + +/* #define OP_PCL_TLS12_AES_128_CBC_SHA256 0x003c */ +#define OP_PCL_TLS12_AES_128_CBC_SHA256_2 0x003e +#define OP_PCL_TLS12_AES_128_CBC_SHA256_3 0x003f +#define OP_PCL_TLS12_AES_128_CBC_SHA256_4 0x0040 +#define OP_PCL_TLS12_AES_128_CBC_SHA256_5 0x0067 +#define OP_PCL_TLS12_AES_128_CBC_SHA256_6 0x006c + +/* #define OP_PCL_TLS12_AES_256_CBC_SHA256 0x003d */ +#define OP_PCL_TLS12_AES_256_CBC_SHA256_2 0x0068 +#define OP_PCL_TLS12_AES_256_CBC_SHA256_3 0x0069 +#define OP_PCL_TLS12_AES_256_CBC_SHA256_4 0x006a +#define OP_PCL_TLS12_AES_256_CBC_SHA256_5 0x006b +#define OP_PCL_TLS12_AES_256_CBC_SHA256_6 0x006d + +/* AEAD_AES_xxx_CCM/GCM remain to be defined... */ + +#define OP_PCL_TLS12_3DES_EDE_CBC_MD5 0xff23 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA160 0xff30 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA224 0xff34 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA256 0xff36 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA384 0xff33 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA512 0xff35 +#define OP_PCL_TLS12_AES_128_CBC_SHA160 0xff80 +#define OP_PCL_TLS12_AES_128_CBC_SHA224 0xff84 +#define OP_PCL_TLS12_AES_128_CBC_SHA256 0xff86 +#define OP_PCL_TLS12_AES_128_CBC_SHA384 0xff83 +#define OP_PCL_TLS12_AES_128_CBC_SHA512 0xff85 +#define OP_PCL_TLS12_AES_192_CBC_SHA160 0xff20 +#define OP_PCL_TLS12_AES_192_CBC_SHA224 0xff24 +#define OP_PCL_TLS12_AES_192_CBC_SHA256 0xff26 +#define OP_PCL_TLS12_AES_192_CBC_SHA384 0xff23 +#define OP_PCL_TLS12_AES_192_CBC_SHA512 0xff25 +#define OP_PCL_TLS12_AES_256_CBC_SHA160 0xff60 +#define OP_PCL_TLS12_AES_256_CBC_SHA224 0xff64 +#define OP_PCL_TLS12_AES_256_CBC_SHA256 0xff66 +#define OP_PCL_TLS12_AES_256_CBC_SHA384 0xff63 +#define OP_PCL_TLS12_AES_256_CBC_SHA512 0xff65 + +/* For DTLS - OP_PCLID_DTLS */ + +#define OP_PCL_DTLS_AES_128_CBC_SHA 0x002f +#define OP_PCL_DTLS_AES_128_CBC_SHA_2 0x0030 +#define OP_PCL_DTLS_AES_128_CBC_SHA_3 0x0031 +#define OP_PCL_DTLS_AES_128_CBC_SHA_4 0x0032 +#define OP_PCL_DTLS_AES_128_CBC_SHA_5 0x0033 +#define OP_PCL_DTLS_AES_128_CBC_SHA_6 0x0034 +#define OP_PCL_DTLS_AES_128_CBC_SHA_7 0x008c +#define OP_PCL_DTLS_AES_128_CBC_SHA_8 0x0090 +#define OP_PCL_DTLS_AES_128_CBC_SHA_9 0x0094 +#define OP_PCL_DTLS_AES_128_CBC_SHA_10 0xc004 +#define OP_PCL_DTLS_AES_128_CBC_SHA_11 0xc009 +#define OP_PCL_DTLS_AES_128_CBC_SHA_12 0xc00e +#define OP_PCL_DTLS_AES_128_CBC_SHA_13 0xc013 +#define OP_PCL_DTLS_AES_128_CBC_SHA_14 0xc018 +#define OP_PCL_DTLS_AES_128_CBC_SHA_15 0xc01d +#define OP_PCL_DTLS_AES_128_CBC_SHA_16 0xc01e +#define OP_PCL_DTLS_AES_128_CBC_SHA_17 0xc01f + +#define OP_PCL_DTLS_AES_256_CBC_SHA 0x0035 +#define OP_PCL_DTLS_AES_256_CBC_SHA_2 0x0036 +#define OP_PCL_DTLS_AES_256_CBC_SHA_3 0x0037 +#define OP_PCL_DTLS_AES_256_CBC_SHA_4 0x0038 +#define OP_PCL_DTLS_AES_256_CBC_SHA_5 0x0039 +#define OP_PCL_DTLS_AES_256_CBC_SHA_6 0x003a +#define OP_PCL_DTLS_AES_256_CBC_SHA_7 0x008d +#define OP_PCL_DTLS_AES_256_CBC_SHA_8 0x0091 +#define OP_PCL_DTLS_AES_256_CBC_SHA_9 0x0095 +#define OP_PCL_DTLS_AES_256_CBC_SHA_10 0xc005 +#define OP_PCL_DTLS_AES_256_CBC_SHA_11 0xc00a +#define OP_PCL_DTLS_AES_256_CBC_SHA_12 0xc00f +#define OP_PCL_DTLS_AES_256_CBC_SHA_13 0xc014 +#define OP_PCL_DTLS_AES_256_CBC_SHA_14 0xc019 +#define OP_PCL_DTLS_AES_256_CBC_SHA_15 0xc020 +#define OP_PCL_DTLS_AES_256_CBC_SHA_16 0xc021 +#define OP_PCL_DTLS_AES_256_CBC_SHA_17 0xc022 + +/* #define OP_PCL_DTLS_3DES_EDE_CBC_MD5 0x0023 */ + +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA 0x001f +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_2 0x008b +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_3 0x008f +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_4 0x0093 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_5 0x000a +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_6 0x000d +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_7 0x0010 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_8 0x0013 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_9 0x0016 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_10 0x001b +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_11 0xc003 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_12 0xc008 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_13 0xc00d +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_14 0xc012 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_15 0xc017 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_16 0xc01a +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_17 0xc01b +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_18 0xc01c + +#define OP_PCL_DTLS_DES40_CBC_MD5 0x0029 + +#define OP_PCL_DTLS_DES_CBC_MD5 0x0022 + +#define OP_PCL_DTLS_DES40_CBC_SHA 0x0008 +#define OP_PCL_DTLS_DES40_CBC_SHA_2 0x000b +#define OP_PCL_DTLS_DES40_CBC_SHA_3 0x000e +#define OP_PCL_DTLS_DES40_CBC_SHA_4 0x0011 +#define OP_PCL_DTLS_DES40_CBC_SHA_5 0x0014 +#define OP_PCL_DTLS_DES40_CBC_SHA_6 0x0019 +#define OP_PCL_DTLS_DES40_CBC_SHA_7 0x0026 + + +#define OP_PCL_DTLS_DES_CBC_SHA 0x001e +#define OP_PCL_DTLS_DES_CBC_SHA_2 0x0009 +#define OP_PCL_DTLS_DES_CBC_SHA_3 0x000c +#define OP_PCL_DTLS_DES_CBC_SHA_4 0x000f +#define OP_PCL_DTLS_DES_CBC_SHA_5 0x0012 +#define OP_PCL_DTLS_DES_CBC_SHA_6 0x0015 +#define OP_PCL_DTLS_DES_CBC_SHA_7 0x001a + + +#define OP_PCL_DTLS_3DES_EDE_CBC_MD5 0xff23 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA160 0xff30 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA224 0xff34 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA256 0xff36 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA384 0xff33 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA512 0xff35 +#define OP_PCL_DTLS_AES_128_CBC_SHA160 0xff80 +#define OP_PCL_DTLS_AES_128_CBC_SHA224 0xff84 +#define OP_PCL_DTLS_AES_128_CBC_SHA256 0xff86 +#define OP_PCL_DTLS_AES_128_CBC_SHA384 0xff83 +#define OP_PCL_DTLS_AES_128_CBC_SHA512 0xff85 +#define OP_PCL_DTLS_AES_192_CBC_SHA160 0xff20 +#define OP_PCL_DTLS_AES_192_CBC_SHA224 0xff24 +#define OP_PCL_DTLS_AES_192_CBC_SHA256 0xff26 +#define OP_PCL_DTLS_AES_192_CBC_SHA384 0xff23 +#define OP_PCL_DTLS_AES_192_CBC_SHA512 0xff25 +#define OP_PCL_DTLS_AES_256_CBC_SHA160 0xff60 +#define OP_PCL_DTLS_AES_256_CBC_SHA224 0xff64 +#define OP_PCL_DTLS_AES_256_CBC_SHA256 0xff66 +#define OP_PCL_DTLS_AES_256_CBC_SHA384 0xff63 +#define OP_PCL_DTLS_AES_256_CBC_SHA512 0xff65 + +/* 802.16 WiMAX protinfos */ +#define OP_PCL_WIMAX_OFDM 0x0201 +#define OP_PCL_WIMAX_OFDMA 0x0231 + +/* 802.11 WiFi protinfos */ +#define OP_PCL_WIFI 0xac04 + +/* MacSec protinfos */ +#define OP_PCL_MACSEC 0x0001 + +/* PKI unidirectional protocol protinfo bits */ +#define OP_PCL_PKPROT_TEST 0x0008 +#define OP_PCL_PKPROT_DECRYPT 0x0004 +#define OP_PCL_PKPROT_ECC 0x0002 +#define OP_PCL_PKPROT_F2M 0x0001 + +/* Blob protocol protinfo bits */ +#define OP_PCL_BLOB_TK 0x0200 +#define OP_PCL_BLOB_EKT 0x0100 + +#define OP_PCL_BLOB_K2KR_MEM 0x0000 +#define OP_PCL_BLOB_K2KR_C1KR 0x0010 +#define OP_PCL_BLOB_K2KR_C2KR 0x0030 +#define OP_PCL_BLOB_K2KR_AFHAS 0x0050 +#define OP_PCL_BLOB_K2KR_C2KR_SPLIT 0x0070 + +#define OP_PCL_BLOB_PTXT_SECMEM 0x0008 +#define OP_PCL_BLOB_BLACK 0x0004 + +#define OP_PCL_BLOB_FMT_NORMAL 0x0000 +#define OP_PCL_BLOB_FMT_MSTR 0x0002 +#define OP_PCL_BLOB_FMT_TEST 0x0003 + +/* For non-protocol/alg-only op commands */ +#define OP_ALG_TYPE_SHIFT 24 +#define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT) +#define OP_ALG_TYPE_CLASS1 2 +#define OP_ALG_TYPE_CLASS2 4 + +#define OP_ALG_ALGSEL_SHIFT 16 +#define OP_ALG_ALGSEL_MASK (0xff << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SUBMASK (0x0f << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_AES (0x10 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_DES (0x20 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_3DES (0x21 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_ARC4 (0x30 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_MD5 (0x40 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA1 (0x41 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA224 (0x42 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA256 (0x43 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA384 (0x44 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA512 (0x45 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_RNG (0x50 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SNOW (0x60 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SNOW_F8 (0x60 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_KASUMI (0x70 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_CRC (0x90 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SNOW_F9 (0xA0 << OP_ALG_ALGSEL_SHIFT) + +#define OP_ALG_AAI_SHIFT 4 +#define OP_ALG_AAI_MASK (0x1ff << OP_ALG_AAI_SHIFT) + +/* blockcipher AAI set */ +#define OP_ALG_AAI_CTR_MOD128 (0x00 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD8 (0x01 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD16 (0x02 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD24 (0x03 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD32 (0x04 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD40 (0x05 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD48 (0x06 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD56 (0x07 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD64 (0x08 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD72 (0x09 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD80 (0x0a << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD88 (0x0b << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD96 (0x0c << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD104 (0x0d << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD112 (0x0e << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD120 (0x0f << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CBC (0x10 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_ECB (0x20 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CFB (0x30 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_OFB (0x40 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_XTS (0x50 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CMAC (0x60 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_XCBC_MAC (0x70 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CCM (0x80 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_GCM (0x90 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CBC_XCBCMAC (0xa0 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_XCBCMAC (0xb0 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CHECKODD (0x80 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_DK (0x100 << OP_ALG_AAI_SHIFT) + +/* randomizer AAI set */ +#define OP_ALG_AAI_RNG (0x00 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG_NZB (0x10 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG_OBP (0x20 << OP_ALG_AAI_SHIFT) + +/* RNG4 AAI set */ +#define OP_ALG_AAI_RNG4_SH_0 (0x00 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG4_SH_1 (0x01 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG4_PS (0x40 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG4_AI (0x80 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG4_SK (0x100 << OP_ALG_AAI_SHIFT) + +/* hmac/smac AAI set */ +#define OP_ALG_AAI_HASH (0x00 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_HMAC (0x01 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_SMAC (0x02 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_HMAC_PRECOMP (0x04 << OP_ALG_AAI_SHIFT) + +/* CRC AAI set*/ +#define OP_ALG_AAI_802 (0x01 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_3385 (0x02 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CUST_POLY (0x04 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_DIS (0x10 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_DOS (0x20 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_DOC (0x40 << OP_ALG_AAI_SHIFT) + +/* Kasumi/SNOW AAI set */ +#define OP_ALG_AAI_F8 (0xc0 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_F9 (0xc8 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_GSM (0x10 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_EDGE (0x20 << OP_ALG_AAI_SHIFT) + +#define OP_ALG_AS_SHIFT 2 +#define OP_ALG_AS_MASK (0x3 << OP_ALG_AS_SHIFT) +#define OP_ALG_AS_UPDATE (0 << OP_ALG_AS_SHIFT) +#define OP_ALG_AS_INIT (1 << OP_ALG_AS_SHIFT) +#define OP_ALG_AS_FINALIZE (2 << OP_ALG_AS_SHIFT) +#define OP_ALG_AS_INITFINAL (3 << OP_ALG_AS_SHIFT) + +#define OP_ALG_ICV_SHIFT 1 +#define OP_ALG_ICV_MASK (1 << OP_ALG_ICV_SHIFT) +#define OP_ALG_ICV_OFF (0 << OP_ALG_ICV_SHIFT) +#define OP_ALG_ICV_ON (1 << OP_ALG_ICV_SHIFT) + +#define OP_ALG_DIR_SHIFT 0 +#define OP_ALG_DIR_MASK 1 +#define OP_ALG_DECRYPT 0 +#define OP_ALG_ENCRYPT 1 + +/* PKHA algorithm type set */ +#define OP_ALG_PK 0x00800000 +#define OP_ALG_PK_FUN_MASK 0x3f /* clrmem, modmath, or cpymem */ + +/* PKHA mode clear memory functions */ +#define OP_ALG_PKMODE_A_RAM 0x80000 +#define OP_ALG_PKMODE_B_RAM 0x40000 +#define OP_ALG_PKMODE_E_RAM 0x20000 +#define OP_ALG_PKMODE_N_RAM 0x10000 +#define OP_ALG_PKMODE_CLEARMEM 0x00001 + +/* PKHA mode modular-arithmetic functions */ +#define OP_ALG_PKMODE_MOD_IN_MONTY 0x80000 +#define OP_ALG_PKMODE_MOD_OUT_MONTY 0x40000 +#define OP_ALG_PKMODE_MOD_F2M 0x20000 +#define OP_ALG_PKMODE_MOD_R2_IN 0x10000 +#define OP_ALG_PKMODE_PRJECTV 0x00800 +#define OP_ALG_PKMODE_TIME_EQ 0x400 +#define OP_ALG_PKMODE_OUT_B 0x000 +#define OP_ALG_PKMODE_OUT_A 0x100 +#define OP_ALG_PKMODE_MOD_ADD 0x002 +#define OP_ALG_PKMODE_MOD_SUB_AB 0x003 +#define OP_ALG_PKMODE_MOD_SUB_BA 0x004 +#define OP_ALG_PKMODE_MOD_MULT 0x005 +#define OP_ALG_PKMODE_MOD_EXPO 0x006 +#define OP_ALG_PKMODE_MOD_REDUCT 0x007 +#define OP_ALG_PKMODE_MOD_INV 0x008 +#define OP_ALG_PKMODE_MOD_ECC_ADD 0x009 +#define OP_ALG_PKMODE_MOD_ECC_DBL 0x00a +#define OP_ALG_PKMODE_MOD_ECC_MULT 0x00b +#define OP_ALG_PKMODE_MOD_MONT_CNST 0x00c +#define OP_ALG_PKMODE_MOD_CRT_CNST 0x00d +#define OP_ALG_PKMODE_MOD_GCD 0x00e +#define OP_ALG_PKMODE_MOD_PRIMALITY 0x00f + +/* PKHA mode copy-memory functions */ +#define OP_ALG_PKMODE_SRC_REG_SHIFT 13 +#define OP_ALG_PKMODE_SRC_REG_MASK (7 << OP_ALG_PKMODE_SRC_REG_SHIFT) +#define OP_ALG_PKMODE_DST_REG_SHIFT 10 +#define OP_ALG_PKMODE_DST_REG_MASK (7 << OP_ALG_PKMODE_DST_REG_SHIFT) +#define OP_ALG_PKMODE_SRC_SEG_SHIFT 8 +#define OP_ALG_PKMODE_SRC_SEG_MASK (3 << OP_ALG_PKMODE_SRC_SEG_SHIFT) +#define OP_ALG_PKMODE_DST_SEG_SHIFT 6 +#define OP_ALG_PKMODE_DST_SEG_MASK (3 << OP_ALG_PKMODE_DST_SEG_SHIFT) + +#define OP_ALG_PKMODE_SRC_REG_A (0 << OP_ALG_PKMODE_SRC_REG_SHIFT) +#define OP_ALG_PKMODE_SRC_REG_B (1 << OP_ALG_PKMODE_SRC_REG_SHIFT) +#define OP_ALG_PKMODE_SRC_REG_N (3 << OP_ALG_PKMODE_SRC_REG_SHIFT) +#define OP_ALG_PKMODE_DST_REG_A (0 << OP_ALG_PKMODE_DST_REG_SHIFT) +#define OP_ALG_PKMODE_DST_REG_B (1 << OP_ALG_PKMODE_DST_REG_SHIFT) +#define OP_ALG_PKMODE_DST_REG_E (2 << OP_ALG_PKMODE_DST_REG_SHIFT) +#define OP_ALG_PKMODE_DST_REG_N (3 << OP_ALG_PKMODE_DST_REG_SHIFT) +#define OP_ALG_PKMODE_SRC_SEG_0 (0 << OP_ALG_PKMODE_SRC_SEG_SHIFT) +#define OP_ALG_PKMODE_SRC_SEG_1 (1 << OP_ALG_PKMODE_SRC_SEG_SHIFT) +#define OP_ALG_PKMODE_SRC_SEG_2 (2 << OP_ALG_PKMODE_SRC_SEG_SHIFT) +#define OP_ALG_PKMODE_SRC_SEG_3 (3 << OP_ALG_PKMODE_SRC_SEG_SHIFT) +#define OP_ALG_PKMODE_DST_SEG_0 (0 << OP_ALG_PKMODE_DST_SEG_SHIFT) +#define OP_ALG_PKMODE_DST_SEG_1 (1 << OP_ALG_PKMODE_DST_SEG_SHIFT) +#define OP_ALG_PKMODE_DST_SEG_2 (2 << OP_ALG_PKMODE_DST_SEG_SHIFT) +#define OP_ALG_PKMODE_DST_SEG_3 (3 << OP_ALG_PKMODE_DST_SEG_SHIFT) +#define OP_ALG_PKMODE_CPYMEM_N_SZ 0x80 +#define OP_ALG_PKMODE_CPYMEM_SRC_SZ 0x81 + +/* + * SEQ_IN_PTR Command Constructs + */ + +/* Release Buffers */ +#define SQIN_RBS 0x04000000 + +/* Sequence pointer is really a descriptor */ +#define SQIN_INL 0x02000000 + +/* Sequence pointer is a scatter-gather table */ +#define SQIN_SGF 0x01000000 + +/* Appends to a previous pointer */ +#define SQIN_PRE 0x00800000 + +/* Use extended length following pointer */ +#define SQIN_EXT 0x00400000 + +/* Restore sequence with pointer/length */ +#define SQIN_RTO 0x00200000 + +/* Replace job descriptor */ +#define SQIN_RJD 0x00100000 + +#define SQIN_LEN_SHIFT 0 +#define SQIN_LEN_MASK (0xffff << SQIN_LEN_SHIFT) + +/* + * SEQ_OUT_PTR Command Constructs + */ + +/* Sequence pointer is a scatter-gather table */ +#define SQOUT_SGF 0x01000000 + +/* Appends to a previous pointer */ +#define SQOUT_PRE SQIN_PRE + +/* Restore sequence with pointer/length */ +#define SQOUT_RTO SQIN_RTO + +/* Use extended length following pointer */ +#define SQOUT_EXT 0x00400000 + +#define SQOUT_LEN_SHIFT 0 +#define SQOUT_LEN_MASK (0xffff << SQOUT_LEN_SHIFT) + + +/* + * SIGNATURE Command Constructs + */ + +/* TYPE field is all that's relevant */ +#define SIGN_TYPE_SHIFT 16 +#define SIGN_TYPE_MASK (0x0f << SIGN_TYPE_SHIFT) + +#define SIGN_TYPE_FINAL (0x00 << SIGN_TYPE_SHIFT) +#define SIGN_TYPE_FINAL_RESTORE (0x01 << SIGN_TYPE_SHIFT) +#define SIGN_TYPE_FINAL_NONZERO (0x02 << SIGN_TYPE_SHIFT) +#define SIGN_TYPE_IMM_2 (0x0a << SIGN_TYPE_SHIFT) +#define SIGN_TYPE_IMM_3 (0x0b << SIGN_TYPE_SHIFT) +#define SIGN_TYPE_IMM_4 (0x0c << SIGN_TYPE_SHIFT) + +/* + * MOVE Command Constructs + */ + +#define MOVE_AUX_SHIFT 25 +#define MOVE_AUX_MASK (3 << MOVE_AUX_SHIFT) +#define MOVE_AUX_MS (2 << MOVE_AUX_SHIFT) +#define MOVE_AUX_LS (1 << MOVE_AUX_SHIFT) + +#define MOVE_WAITCOMP_SHIFT 24 +#define MOVE_WAITCOMP_MASK (1 << MOVE_WAITCOMP_SHIFT) +#define MOVE_WAITCOMP (1 << MOVE_WAITCOMP_SHIFT) + +#define MOVE_SRC_SHIFT 20 +#define MOVE_SRC_MASK (0x0f << MOVE_SRC_SHIFT) +#define MOVE_SRC_CLASS1CTX (0x00 << MOVE_SRC_SHIFT) +#define MOVE_SRC_CLASS2CTX (0x01 << MOVE_SRC_SHIFT) +#define MOVE_SRC_OUTFIFO (0x02 << MOVE_SRC_SHIFT) +#define MOVE_SRC_DESCBUF (0x03 << MOVE_SRC_SHIFT) +#define MOVE_SRC_MATH0 (0x04 << MOVE_SRC_SHIFT) +#define MOVE_SRC_MATH1 (0x05 << MOVE_SRC_SHIFT) +#define MOVE_SRC_MATH2 (0x06 << MOVE_SRC_SHIFT) +#define MOVE_SRC_MATH3 (0x07 << MOVE_SRC_SHIFT) +#define MOVE_SRC_INFIFO (0x08 << MOVE_SRC_SHIFT) +#define MOVE_SRC_INFIFO_CL (0x09 << MOVE_SRC_SHIFT) + +#define MOVE_DEST_SHIFT 16 +#define MOVE_DEST_MASK (0x0f << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS1CTX (0x00 << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS2CTX (0x01 << MOVE_DEST_SHIFT) +#define MOVE_DEST_OUTFIFO (0x02 << MOVE_DEST_SHIFT) +#define MOVE_DEST_DESCBUF (0x03 << MOVE_DEST_SHIFT) +#define MOVE_DEST_MATH0 (0x04 << MOVE_DEST_SHIFT) +#define MOVE_DEST_MATH1 (0x05 << MOVE_DEST_SHIFT) +#define MOVE_DEST_MATH2 (0x06 << MOVE_DEST_SHIFT) +#define MOVE_DEST_MATH3 (0x07 << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS1INFIFO (0x08 << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS2INFIFO (0x09 << MOVE_DEST_SHIFT) +#define MOVE_DEST_INFIFO_NOINFO (0x0a << MOVE_DEST_SHIFT) +#define MOVE_DEST_PK_A (0x0c << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS1KEY (0x0d << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS2KEY (0x0e << MOVE_DEST_SHIFT) + +#define MOVE_OFFSET_SHIFT 8 +#define MOVE_OFFSET_MASK (0xff << MOVE_OFFSET_SHIFT) + +#define MOVE_LEN_SHIFT 0 +#define MOVE_LEN_MASK (0xff << MOVE_LEN_SHIFT) + +#define MOVELEN_MRSEL_SHIFT 0 +#define MOVELEN_MRSEL_MASK (0x3 << MOVE_LEN_SHIFT) + +/* + * MATH Command Constructs + */ + +#define MATH_IFB_SHIFT 26 +#define MATH_IFB_MASK (1 << MATH_IFB_SHIFT) +#define MATH_IFB (1 << MATH_IFB_SHIFT) + +#define MATH_NFU_SHIFT 25 +#define MATH_NFU_MASK (1 << MATH_NFU_SHIFT) +#define MATH_NFU (1 << MATH_NFU_SHIFT) + +#define MATH_STL_SHIFT 24 +#define MATH_STL_MASK (1 << MATH_STL_SHIFT) +#define MATH_STL (1 << MATH_STL_SHIFT) + +/* Function selectors */ +#define MATH_FUN_SHIFT 20 +#define MATH_FUN_MASK (0x0f << MATH_FUN_SHIFT) +#define MATH_FUN_ADD (0x00 << MATH_FUN_SHIFT) +#define MATH_FUN_ADDC (0x01 << MATH_FUN_SHIFT) +#define MATH_FUN_SUB (0x02 << MATH_FUN_SHIFT) +#define MATH_FUN_SUBB (0x03 << MATH_FUN_SHIFT) +#define MATH_FUN_OR (0x04 << MATH_FUN_SHIFT) +#define MATH_FUN_AND (0x05 << MATH_FUN_SHIFT) +#define MATH_FUN_XOR (0x06 << MATH_FUN_SHIFT) +#define MATH_FUN_LSHIFT (0x07 << MATH_FUN_SHIFT) +#define MATH_FUN_RSHIFT (0x08 << MATH_FUN_SHIFT) +#define MATH_FUN_SHLD (0x09 << MATH_FUN_SHIFT) +#define MATH_FUN_ZBYT (0x0a << MATH_FUN_SHIFT) + +/* Source 0 selectors */ +#define MATH_SRC0_SHIFT 16 +#define MATH_SRC0_MASK (0x0f << MATH_SRC0_SHIFT) +#define MATH_SRC0_REG0 (0x00 << MATH_SRC0_SHIFT) +#define MATH_SRC0_REG1 (0x01 << MATH_SRC0_SHIFT) +#define MATH_SRC0_REG2 (0x02 << MATH_SRC0_SHIFT) +#define MATH_SRC0_REG3 (0x03 << MATH_SRC0_SHIFT) +#define MATH_SRC0_IMM (0x04 << MATH_SRC0_SHIFT) +#define MATH_SRC0_DPOVRD (0x07 << MATH_SRC0_SHIFT) +#define MATH_SRC0_SEQINLEN (0x08 << MATH_SRC0_SHIFT) +#define MATH_SRC0_SEQOUTLEN (0x09 << MATH_SRC0_SHIFT) +#define MATH_SRC0_VARSEQINLEN (0x0a << MATH_SRC0_SHIFT) +#define MATH_SRC0_VARSEQOUTLEN (0x0b << MATH_SRC0_SHIFT) +#define MATH_SRC0_ZERO (0x0c << MATH_SRC0_SHIFT) + +/* Source 1 selectors */ +#define MATH_SRC1_SHIFT 12 +#define MATH_SRC1_MASK (0x0f << MATH_SRC1_SHIFT) +#define MATH_SRC1_REG0 (0x00 << MATH_SRC1_SHIFT) +#define MATH_SRC1_REG1 (0x01 << MATH_SRC1_SHIFT) +#define MATH_SRC1_REG2 (0x02 << MATH_SRC1_SHIFT) +#define MATH_SRC1_REG3 (0x03 << MATH_SRC1_SHIFT) +#define MATH_SRC1_IMM (0x04 << MATH_SRC1_SHIFT) +#define MATH_SRC1_DPOVRD (0x07 << MATH_SRC0_SHIFT) +#define MATH_SRC1_INFIFO (0x0a << MATH_SRC1_SHIFT) +#define MATH_SRC1_OUTFIFO (0x0b << MATH_SRC1_SHIFT) +#define MATH_SRC1_ONE (0x0c << MATH_SRC1_SHIFT) + +/* Destination selectors */ +#define MATH_DEST_SHIFT 8 +#define MATH_DEST_MASK (0x0f << MATH_DEST_SHIFT) +#define MATH_DEST_REG0 (0x00 << MATH_DEST_SHIFT) +#define MATH_DEST_REG1 (0x01 << MATH_DEST_SHIFT) +#define MATH_DEST_REG2 (0x02 << MATH_DEST_SHIFT) +#define MATH_DEST_REG3 (0x03 << MATH_DEST_SHIFT) +#define MATH_DEST_SEQINLEN (0x08 << MATH_DEST_SHIFT) +#define MATH_DEST_SEQOUTLEN (0x09 << MATH_DEST_SHIFT) +#define MATH_DEST_VARSEQINLEN (0x0a << MATH_DEST_SHIFT) +#define MATH_DEST_VARSEQOUTLEN (0x0b << MATH_DEST_SHIFT) +#define MATH_DEST_NONE (0x0f << MATH_DEST_SHIFT) + +/* Length selectors */ +#define MATH_LEN_SHIFT 0 +#define MATH_LEN_MASK (0x0f << MATH_LEN_SHIFT) +#define MATH_LEN_1BYTE 0x01 +#define MATH_LEN_2BYTE 0x02 +#define MATH_LEN_4BYTE 0x04 +#define MATH_LEN_8BYTE 0x08 + +/* + * JUMP Command Constructs + */ + +#define JUMP_CLASS_SHIFT 25 +#define JUMP_CLASS_MASK (3 << JUMP_CLASS_SHIFT) +#define JUMP_CLASS_NONE 0 +#define JUMP_CLASS_CLASS1 (1 << JUMP_CLASS_SHIFT) +#define JUMP_CLASS_CLASS2 (2 << JUMP_CLASS_SHIFT) +#define JUMP_CLASS_BOTH (3 << JUMP_CLASS_SHIFT) + +#define JUMP_JSL_SHIFT 24 +#define JUMP_JSL_MASK (1 << JUMP_JSL_SHIFT) +#define JUMP_JSL (1 << JUMP_JSL_SHIFT) + +#define JUMP_TYPE_SHIFT 22 +#define JUMP_TYPE_MASK (0x03 << JUMP_TYPE_SHIFT) +#define JUMP_TYPE_LOCAL (0x00 << JUMP_TYPE_SHIFT) +#define JUMP_TYPE_NONLOCAL (0x01 << JUMP_TYPE_SHIFT) +#define JUMP_TYPE_HALT (0x02 << JUMP_TYPE_SHIFT) +#define JUMP_TYPE_HALT_USER (0x03 << JUMP_TYPE_SHIFT) + +#define JUMP_TEST_SHIFT 16 +#define JUMP_TEST_MASK (0x03 << JUMP_TEST_SHIFT) +#define JUMP_TEST_ALL (0x00 << JUMP_TEST_SHIFT) +#define JUMP_TEST_INVALL (0x01 << JUMP_TEST_SHIFT) +#define JUMP_TEST_ANY (0x02 << JUMP_TEST_SHIFT) +#define JUMP_TEST_INVANY (0x03 << JUMP_TEST_SHIFT) + +/* Condition codes. JSL bit is factored in */ +#define JUMP_COND_SHIFT 8 +#define JUMP_COND_MASK (0x100ff << JUMP_COND_SHIFT) +#define JUMP_COND_PK_0 (0x80 << JUMP_COND_SHIFT) +#define JUMP_COND_PK_GCD_1 (0x40 << JUMP_COND_SHIFT) +#define JUMP_COND_PK_PRIME (0x20 << JUMP_COND_SHIFT) +#define JUMP_COND_MATH_N (0x08 << JUMP_COND_SHIFT) +#define JUMP_COND_MATH_Z (0x04 << JUMP_COND_SHIFT) +#define JUMP_COND_MATH_C (0x02 << JUMP_COND_SHIFT) +#define JUMP_COND_MATH_NV (0x01 << JUMP_COND_SHIFT) + +#define JUMP_COND_JRP ((0x80 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_SHRD ((0x40 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_SELF ((0x20 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_CALM ((0x10 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_NIP ((0x08 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_NIFP ((0x04 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_NOP ((0x02 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_NCP ((0x01 << JUMP_COND_SHIFT) | JUMP_JSL) + +#define JUMP_OFFSET_SHIFT 0 +#define JUMP_OFFSET_MASK (0xff << JUMP_OFFSET_SHIFT) + +/* + * NFIFO ENTRY + * Data Constructs + * + */ +#define NFIFOENTRY_DEST_SHIFT 30 +#define NFIFOENTRY_DEST_MASK (3 << NFIFOENTRY_DEST_SHIFT) +#define NFIFOENTRY_DEST_DECO (0 << NFIFOENTRY_DEST_SHIFT) +#define NFIFOENTRY_DEST_CLASS1 (1 << NFIFOENTRY_DEST_SHIFT) +#define NFIFOENTRY_DEST_CLASS2 (2 << NFIFOENTRY_DEST_SHIFT) +#define NFIFOENTRY_DEST_BOTH (3 << NFIFOENTRY_DEST_SHIFT) + +#define NFIFOENTRY_LC2_SHIFT 29 +#define NFIFOENTRY_LC2_MASK (1 << NFIFOENTRY_LC2_SHIFT) +#define NFIFOENTRY_LC2 (1 << NFIFOENTRY_LC2_SHIFT) + +#define NFIFOENTRY_LC1_SHIFT 28 +#define NFIFOENTRY_LC1_MASK (1 << NFIFOENTRY_LC1_SHIFT) +#define NFIFOENTRY_LC1 (1 << NFIFOENTRY_LC1_SHIFT) + +#define NFIFOENTRY_FC2_SHIFT 27 +#define NFIFOENTRY_FC2_MASK (1 << NFIFOENTRY_FC2_SHIFT) +#define NFIFOENTRY_FC2 (1 << NFIFOENTRY_FC2_SHIFT) + +#define NFIFOENTRY_FC1_SHIFT 26 +#define NFIFOENTRY_FC1_MASK (1 << NFIFOENTRY_FC1_SHIFT) +#define NFIFOENTRY_FC1 (1 << NFIFOENTRY_FC1_SHIFT) + +#define NFIFOENTRY_STYPE_SHIFT 24 +#define NFIFOENTRY_STYPE_MASK (3 << NFIFOENTRY_STYPE_SHIFT) +#define NFIFOENTRY_STYPE_DFIFO (0 << NFIFOENTRY_STYPE_SHIFT) +#define NFIFOENTRY_STYPE_OFIFO (1 << NFIFOENTRY_STYPE_SHIFT) +#define NFIFOENTRY_STYPE_PAD (2 << NFIFOENTRY_STYPE_SHIFT) +#define NFIFOENTRY_STYPE_SNOOP (3 << NFIFOENTRY_STYPE_SHIFT) + +#define NFIFOENTRY_DTYPE_SHIFT 20 +#define NFIFOENTRY_DTYPE_MASK (0xF << NFIFOENTRY_DTYPE_SHIFT) + +#define NFIFOENTRY_DTYPE_SBOX (0x0 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_AAD (0x1 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_IV (0x2 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_SAD (0x3 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_ICV (0xA << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_SKIP (0xE << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_MSG (0xF << NFIFOENTRY_DTYPE_SHIFT) + +#define NFIFOENTRY_DTYPE_PK_A0 (0x0 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_A1 (0x1 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_A2 (0x2 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_A3 (0x3 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_B0 (0x4 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_B1 (0x5 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_B2 (0x6 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_B3 (0x7 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_N (0x8 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_E (0x9 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_A (0xC << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_B (0xD << NFIFOENTRY_DTYPE_SHIFT) + + +#define NFIFOENTRY_BND_SHIFT 19 +#define NFIFOENTRY_BND_MASK (1 << NFIFOENTRY_BND_SHIFT) +#define NFIFOENTRY_BND (1 << NFIFOENTRY_BND_SHIFT) + +#define NFIFOENTRY_PTYPE_SHIFT 16 +#define NFIFOENTRY_PTYPE_MASK (0x7 << NFIFOENTRY_PTYPE_SHIFT) + +#define NFIFOENTRY_PTYPE_ZEROS (0x0 << NFIFOENTRY_PTYPE_SHIFT) +#define NFIFOENTRY_PTYPE_RND_NOZEROS (0x1 << NFIFOENTRY_PTYPE_SHIFT) +#define NFIFOENTRY_PTYPE_INCREMENT (0x2 << NFIFOENTRY_PTYPE_SHIFT) +#define NFIFOENTRY_PTYPE_RND (0x3 << NFIFOENTRY_PTYPE_SHIFT) +#define NFIFOENTRY_PTYPE_ZEROS_NZ (0x4 << NFIFOENTRY_PTYPE_SHIFT) +#define NFIFOENTRY_PTYPE_RND_NZ_LZ (0x5 << NFIFOENTRY_PTYPE_SHIFT) +#define NFIFOENTRY_PTYPE_N (0x6 << NFIFOENTRY_PTYPE_SHIFT) +#define NFIFOENTRY_PTYPE_RND_NZ_N (0x7 << NFIFOENTRY_PTYPE_SHIFT) + +#define NFIFOENTRY_OC_SHIFT 15 +#define NFIFOENTRY_OC_MASK (1 << NFIFOENTRY_OC_SHIFT) +#define NFIFOENTRY_OC (1 << NFIFOENTRY_OC_SHIFT) + +#define NFIFOENTRY_AST_SHIFT 14 +#define NFIFOENTRY_AST_MASK (1 << NFIFOENTRY_OC_SHIFT) +#define NFIFOENTRY_AST (1 << NFIFOENTRY_OC_SHIFT) + +#define NFIFOENTRY_BM_SHIFT 11 +#define NFIFOENTRY_BM_MASK (1 << NFIFOENTRY_BM_SHIFT) +#define NFIFOENTRY_BM (1 << NFIFOENTRY_BM_SHIFT) + +#define NFIFOENTRY_PS_SHIFT 10 +#define NFIFOENTRY_PS_MASK (1 << NFIFOENTRY_PS_SHIFT) +#define NFIFOENTRY_PS (1 << NFIFOENTRY_PS_SHIFT) + +#define NFIFOENTRY_DLEN_SHIFT 0 +#define NFIFOENTRY_DLEN_MASK (0xFFF << NFIFOENTRY_DLEN_SHIFT) + +#define NFIFOENTRY_PLEN_SHIFT 0 +#define NFIFOENTRY_PLEN_MASK (0xFF << NFIFOENTRY_PLEN_SHIFT) + +/* Append Load Immediate Command */ +#define FD_CMD_APPEND_LOAD_IMMEDIATE 0x80000000 + +/* Set SEQ LIODN equal to the Non-SEQ LIODN for the job */ +#define FD_CMD_SET_SEQ_LIODN_EQUAL_NONSEQ_LIODN 0x40000000 + +/* Frame Descriptor Command for Replacement Job Descriptor */ +#define FD_CMD_REPLACE_JOB_DESC 0x20000000 + +#define ARC4_BLOCK_SIZE 1 +#define ARC4_MAX_KEY_SIZE 256 +#define ARC4_MIN_KEY_SIZE 1 + +#define XCBC_MAC_DIGEST_SIZE 16 +#define XCBC_MAC_BLOCK_WORDS 16 + + +#endif /* DESC_H */ diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h new file mode 100644 index 0000000000..9f79fd7bd4 --- /dev/null +++ b/drivers/crypto/caam/desc_constr.h @@ -0,0 +1,390 @@ +/* + * caam descriptor construction helper functions + * + * Copyright 2008-2012 Freescale Semiconductor, Inc. + */ + +#include "desc.h" + +#define IMMEDIATE (1 << 23) +#define CAAM_CMD_SZ sizeof(u32) +#define CAAM_PTR_SZ sizeof(dma_addr_t) +#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE) +#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3) + +#ifdef DEBUG +#define PRINT_POS do { printk(KERN_DEBUG "%02d: %s\n", desc_len(desc),\ + &__func__[sizeof("append")]); } while (0) +#else +#define PRINT_POS +#endif + +#define SET_OK_NO_PROP_ERRORS (IMMEDIATE | LDST_CLASS_DECO | \ + LDST_SRCDST_WORD_DECOCTRL | \ + (LDOFF_CHG_SHARE_OK_NO_PROP << \ + LDST_OFFSET_SHIFT)) +#define DISABLE_AUTO_INFO_FIFO (IMMEDIATE | LDST_CLASS_DECO | \ + LDST_SRCDST_WORD_DECOCTRL | \ + (LDOFF_DISABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT)) +#define ENABLE_AUTO_INFO_FIFO (IMMEDIATE | LDST_CLASS_DECO | \ + LDST_SRCDST_WORD_DECOCTRL | \ + (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT)) + +static inline int desc_len(u32 *desc) +{ + return *desc & HDR_DESCLEN_MASK; +} + +static inline int desc_bytes(void *desc) +{ + return desc_len(desc) * CAAM_CMD_SZ; +} + +static inline u32 *desc_end(u32 *desc) +{ + return desc + desc_len(desc); +} + +static inline void *sh_desc_pdb(u32 *desc) +{ + return desc + 1; +} + +static inline void init_desc(u32 *desc, u32 options) +{ + *desc = (options | HDR_ONE) + 1; +} + +static inline void init_sh_desc(u32 *desc, u32 options) +{ + PRINT_POS; + init_desc(desc, CMD_SHARED_DESC_HDR | options); +} + +static inline void init_sh_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes) +{ + u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ; + + init_sh_desc(desc, (((pdb_len + 1) << HDR_START_IDX_SHIFT) + pdb_len) | + options); +} + +static inline void init_job_desc(u32 *desc, u32 options) +{ + init_desc(desc, CMD_DESC_HDR | options); +} + +static inline void append_ptr(u32 *desc, dma_addr_t ptr) +{ + dma_addr_t *offset = (dma_addr_t *)desc_end(desc); + + *offset = ptr; + + (*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ; +} + +static inline void init_job_desc_shared(u32 *desc, dma_addr_t ptr, int len, + u32 options) +{ + PRINT_POS; + init_job_desc(desc, HDR_SHARED | options | + (len << HDR_START_IDX_SHIFT)); + append_ptr(desc, ptr); +} + +static inline void append_data(u32 *desc, void *data, int len) +{ + u32 *offset = desc_end(desc); + + if (len) /* avoid sparse warning: memcpy with byte count of 0 */ + memcpy(offset, data, len); + + (*desc) += (len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ; +} + +static inline void append_cmd(u32 *desc, u32 command) +{ + u32 *cmd = desc_end(desc); + + *cmd = command; + + (*desc)++; +} + +#define append_u32 append_cmd + +static inline void append_u64(u32 *desc, u64 data) +{ + u32 *offset = desc_end(desc); + + *offset = upper_32_bits(data); + *(++offset) = lower_32_bits(data); + + (*desc) += 2; +} + +/* Write command without affecting header, and return pointer to next word */ +static inline u32 *write_cmd(u32 *desc, u32 command) +{ + *desc = command; + + return desc + 1; +} + +static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len, + u32 command) +{ + append_cmd(desc, command | len); + append_ptr(desc, ptr); +} + +/* Write length after pointer, rather than inside command */ +static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr, + unsigned int len, u32 command) +{ + append_cmd(desc, command); + if (!(command & (SQIN_RTO | SQIN_PRE))) + append_ptr(desc, ptr); + append_cmd(desc, len); +} + +static inline void append_cmd_data(u32 *desc, void *data, int len, + u32 command) +{ + append_cmd(desc, command | IMMEDIATE | len); + append_data(desc, data, len); +} + +#define APPEND_CMD_RET(cmd, op) \ +static inline u32 *append_##cmd(u32 *desc, u32 options) \ +{ \ + u32 *cmd = desc_end(desc); \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | options); \ + return cmd; \ +} +APPEND_CMD_RET(jump, JUMP) +APPEND_CMD_RET(move, MOVE) + +static inline void set_jump_tgt_here(u32 *desc, u32 *jump_cmd) +{ + *jump_cmd = *jump_cmd | (desc_len(desc) - (jump_cmd - desc)); +} + +static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd) +{ + *move_cmd &= ~MOVE_OFFSET_MASK; + *move_cmd = *move_cmd | ((desc_len(desc) << (MOVE_OFFSET_SHIFT + 2)) & + MOVE_OFFSET_MASK); +} + +#define APPEND_CMD(cmd, op) \ +static inline void append_##cmd(u32 *desc, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | options); \ +} +APPEND_CMD(operation, OPERATION) + +#define APPEND_CMD_LEN(cmd, op) \ +static inline void append_##cmd(u32 *desc, unsigned int len, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | len | options); \ +} + +APPEND_CMD_LEN(seq_load, SEQ_LOAD) +APPEND_CMD_LEN(seq_store, SEQ_STORE) +APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD) +APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE) + +#define APPEND_CMD_PTR(cmd, op) \ +static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \ + u32 options) \ +{ \ + PRINT_POS; \ + append_cmd_ptr(desc, ptr, len, CMD_##op | options); \ +} +APPEND_CMD_PTR(key, KEY) +APPEND_CMD_PTR(load, LOAD) +APPEND_CMD_PTR(fifo_load, FIFO_LOAD) +APPEND_CMD_PTR(fifo_store, FIFO_STORE) + +static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len, + u32 options) +{ + u32 cmd_src; + + cmd_src = options & LDST_SRCDST_MASK; + + append_cmd(desc, CMD_STORE | options | len); + + /* The following options do not require pointer */ + if (!(cmd_src == LDST_SRCDST_WORD_DESCBUF_SHARED || + cmd_src == LDST_SRCDST_WORD_DESCBUF_JOB || + cmd_src == LDST_SRCDST_WORD_DESCBUF_JOB_WE || + cmd_src == LDST_SRCDST_WORD_DESCBUF_SHARED_WE)) + append_ptr(desc, ptr); +} + +#define APPEND_SEQ_PTR_INTLEN(cmd, op) \ +static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \ + unsigned int len, \ + u32 options) \ +{ \ + PRINT_POS; \ + if (options & (SQIN_RTO | SQIN_PRE)) \ + append_cmd(desc, CMD_SEQ_##op##_PTR | len | options); \ + else \ + append_cmd_ptr(desc, ptr, len, CMD_SEQ_##op##_PTR | options); \ +} +APPEND_SEQ_PTR_INTLEN(in, IN) +APPEND_SEQ_PTR_INTLEN(out, OUT) + +#define APPEND_CMD_PTR_TO_IMM(cmd, op) \ +static inline void append_##cmd##_as_imm(u32 *desc, void *data, \ + unsigned int len, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd_data(desc, data, len, CMD_##op | options); \ +} +APPEND_CMD_PTR_TO_IMM(load, LOAD); +APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD); + +#define APPEND_CMD_PTR_EXTLEN(cmd, op) \ +static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \ + unsigned int len, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd_ptr_extlen(desc, ptr, len, CMD_##op | SQIN_EXT | options); \ +} +APPEND_CMD_PTR_EXTLEN(seq_in_ptr, SEQ_IN_PTR) +APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR) + +/* + * Determine whether to store length internally or externally depending on + * the size of its type + */ +#define APPEND_CMD_PTR_LEN(cmd, op, type) \ +static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \ + type len, u32 options) \ +{ \ + PRINT_POS; \ + if (sizeof(type) > sizeof(u16)) \ + append_##cmd##_extlen(desc, ptr, len, options); \ + else \ + append_##cmd##_intlen(desc, ptr, len, options); \ +} +APPEND_CMD_PTR_LEN(seq_in_ptr, SEQ_IN_PTR, u32) +APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_PTR, u32) + +/* + * 2nd variant for commands whose specified immediate length differs + * from length of immediate data provided, e.g., split keys + */ +#define APPEND_CMD_PTR_TO_IMM2(cmd, op) \ +static inline void append_##cmd##_as_imm(u32 *desc, void *data, \ + unsigned int data_len, \ + unsigned int len, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | IMMEDIATE | len | options); \ + append_data(desc, data, data_len); \ +} +APPEND_CMD_PTR_TO_IMM2(key, KEY); + +#define APPEND_CMD_RAW_IMM(cmd, op, type) \ +static inline void append_##cmd##_imm_##type(u32 *desc, type immediate, \ + u32 options) \ +{ \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | IMMEDIATE | options | sizeof(type)); \ + append_cmd(desc, immediate); \ +} +APPEND_CMD_RAW_IMM(load, LOAD, u32); + +/* + * Append math command. Only the last part of destination and source need to + * be specified + */ +#define APPEND_MATH(op, desc, dest, src_0, src_1, len) \ +append_cmd(desc, CMD_MATH | MATH_FUN_##op | MATH_DEST_##dest | \ + MATH_SRC0_##src_0 | MATH_SRC1_##src_1 | (u32)len); + +#define append_math_add(desc, dest, src0, src1, len) \ + APPEND_MATH(ADD, desc, dest, src0, src1, len) +#define append_math_sub(desc, dest, src0, src1, len) \ + APPEND_MATH(SUB, desc, dest, src0, src1, len) +#define append_math_add_c(desc, dest, src0, src1, len) \ + APPEND_MATH(ADDC, desc, dest, src0, src1, len) +#define append_math_sub_b(desc, dest, src0, src1, len) \ + APPEND_MATH(SUBB, desc, dest, src0, src1, len) +#define append_math_and(desc, dest, src0, src1, len) \ + APPEND_MATH(AND, desc, dest, src0, src1, len) +#define append_math_or(desc, dest, src0, src1, len) \ + APPEND_MATH(OR, desc, dest, src0, src1, len) +#define append_math_xor(desc, dest, src0, src1, len) \ + APPEND_MATH(XOR, desc, dest, src0, src1, len) +#define append_math_lshift(desc, dest, src0, src1, len) \ + APPEND_MATH(LSHIFT, desc, dest, src0, src1, len) +#define append_math_rshift(desc, dest, src0, src1, len) \ + APPEND_MATH(RSHIFT, desc, dest, src0, src1, len) +#define append_math_ldshift(desc, dest, src0, src1, len) \ + APPEND_MATH(SHLD, desc, dest, src0, src1, len) + +/* Exactly one source is IMM. Data is passed in as u32 value */ +#define APPEND_MATH_IMM_u32(op, desc, dest, src_0, src_1, data) \ +do { \ + APPEND_MATH(op, desc, dest, src_0, src_1, CAAM_CMD_SZ); \ + append_cmd(desc, data); \ +} while (0) + +#define append_math_add_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(ADD, desc, dest, src0, src1, data) +#define append_math_sub_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(SUB, desc, dest, src0, src1, data) +#define append_math_add_c_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(ADDC, desc, dest, src0, src1, data) +#define append_math_sub_b_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(SUBB, desc, dest, src0, src1, data) +#define append_math_and_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(AND, desc, dest, src0, src1, data) +#define append_math_or_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(OR, desc, dest, src0, src1, data) +#define append_math_xor_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(XOR, desc, dest, src0, src1, data) +#define append_math_lshift_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(LSHIFT, desc, dest, src0, src1, data) +#define append_math_rshift_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(RSHIFT, desc, dest, src0, src1, data) + +/* Exactly one source is IMM. Data is passed in as u64 value */ +#define APPEND_MATH_IMM_u64(op, desc, dest, src_0, src_1, data) \ +do { \ + u32 upper = (data >> 16) >> 16; \ + APPEND_MATH(op, desc, dest, src_0, src_1, CAAM_CMD_SZ * 2 | \ + (upper ? 0 : MATH_IFB)); \ + if (upper) \ + append_u64(desc, data); \ + else \ + append_u32(desc, data); \ +} while (0) + +#define append_math_add_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(ADD, desc, dest, src0, src1, data) +#define append_math_sub_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(SUB, desc, dest, src0, src1, data) +#define append_math_add_c_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(ADDC, desc, dest, src0, src1, data) +#define append_math_sub_b_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(SUBB, desc, dest, src0, src1, data) +#define append_math_and_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(AND, desc, dest, src0, src1, data) +#define append_math_or_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(OR, desc, dest, src0, src1, data) +#define append_math_xor_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(XOR, desc, dest, src0, src1, data) +#define append_math_lshift_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(LSHIFT, desc, dest, src0, src1, data) +#define append_math_rshift_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(RSHIFT, desc, dest, src0, src1, data) diff --git a/drivers/crypto/caam/error.c b/drivers/crypto/caam/error.c new file mode 100644 index 0000000000..9c875375df --- /dev/null +++ b/drivers/crypto/caam/error.c @@ -0,0 +1,257 @@ +/* + * CAAM Error Reporting + * + * Copyright 2009-2011 Freescale Semiconductor, Inc. + */ + +#include <common.h> +#include "regs.h" +#include "error.h" + +static const struct { + u8 value; + const char *error_text; +} desc_error_list[] = { + { 0x00, "No error." }, + { 0x01, "SGT Length Error. The descriptor is trying to read more data than is contained in the SGT table." }, + { 0x02, "SGT Null Entry Error." }, + { 0x03, "Job Ring Control Error. There is a bad value in the Job Ring Control register." }, + { 0x04, "Invalid Descriptor Command. The Descriptor Command field is invalid." }, + { 0x05, "Reserved." }, + { 0x06, "Invalid KEY Command" }, + { 0x07, "Invalid LOAD Command" }, + { 0x08, "Invalid STORE Command" }, + { 0x09, "Invalid OPERATION Command" }, + { 0x0A, "Invalid FIFO LOAD Command" }, + { 0x0B, "Invalid FIFO STORE Command" }, + { 0x0C, "Invalid MOVE/MOVE_LEN Command" }, + { 0x0D, "Invalid JUMP Command. A nonlocal JUMP Command is invalid because the target is not a Job Header Command, or the jump is from a Trusted Descriptor to a Job Descriptor, or because the target Descriptor contains a Shared Descriptor." }, + { 0x0E, "Invalid MATH Command" }, + { 0x0F, "Invalid SIGNATURE Command" }, + { 0x10, "Invalid Sequence Command. A SEQ IN PTR OR SEQ OUT PTR Command is invalid or a SEQ KEY, SEQ LOAD, SEQ FIFO LOAD, or SEQ FIFO STORE decremented the input or output sequence length below 0. This error may result if a built-in PROTOCOL Command has encountered a malformed PDU." }, + { 0x11, "Skip data type invalid. The type must be 0xE or 0xF."}, + { 0x12, "Shared Descriptor Header Error" }, + { 0x13, "Header Error. Invalid length or parity, or certain other problems." }, + { 0x14, "Burster Error. Burster has gotten to an illegal state" }, + { 0x15, "Context Register Length Error. The descriptor is trying to read or write past the end of the Context Register. A SEQ LOAD or SEQ STORE with the VLF bit set was executed with too large a length in the variable length register (VSOL for SEQ STORE or VSIL for SEQ LOAD)." }, + { 0x16, "DMA Error" }, + { 0x17, "Reserved." }, + { 0x1A, "Job failed due to JR reset" }, + { 0x1B, "Job failed due to Fail Mode" }, + { 0x1C, "DECO Watchdog timer timeout error" }, + { 0x1D, "DECO tried to copy a key from another DECO but the other DECO's Key Registers were locked" }, + { 0x1E, "DECO attempted to copy data from a DECO that had an unmasked Descriptor error" }, + { 0x1F, "LIODN error. DECO was trying to share from itself or from another DECO but the two Non-SEQ LIODN values didn't match or the 'shared from' DECO's Descriptor required that the SEQ LIODNs be the same and they aren't." }, + { 0x20, "DECO has completed a reset initiated via the DRR register" }, + { 0x21, "Nonce error. When using EKT (CCM) key encryption option in the FIFO STORE Command, the Nonce counter reached its maximum value and this encryption mode can no longer be used." }, + { 0x22, "Meta data is too large (> 511 bytes) for TLS decap (input frame; block ciphers) and IPsec decap (output frame, when doing the next header byte update) and DCRC (output frame)." }, + { 0x23, "Read Input Frame error" }, + { 0x24, "JDKEK, TDKEK or TDSK not loaded error" }, + { 0x80, "DNR (do not run) error" }, + { 0x81, "undefined protocol command" }, + { 0x82, "invalid setting in PDB" }, + { 0x83, "Anti-replay LATE error" }, + { 0x84, "Anti-replay REPLAY error" }, + { 0x85, "Sequence number overflow" }, + { 0x86, "Sigver invalid signature" }, + { 0x87, "DSA Sign Illegal test descriptor" }, + { 0x88, "Protocol Format Error - A protocol has seen an error in the format of data received. When running RSA, this means that formatting with random padding was used, and did not follow the form: 0x00, 0x02, 8-to-N bytes of non-zero pad, 0x00, F data." }, + { 0x89, "Protocol Size Error - A protocol has seen an error in size. When running RSA, pdb size N < (size of F) when no formatting is used; or pdb size N < (F + 11) when formatting is used." }, + { 0xC1, "Blob Command error: Undefined mode" }, + { 0xC2, "Blob Command error: Secure Memory Blob mode error" }, + { 0xC4, "Blob Command error: Black Blob key or input size error" }, + { 0xC5, "Blob Command error: Invalid key destination" }, + { 0xC8, "Blob Command error: Trusted/Secure mode error" }, + { 0xF0, "IPsec TTL or hop limit field either came in as 0, or was decremented to 0" }, + { 0xF1, "3GPP HFN matches or exceeds the Threshold" }, +}; + +static const char * const cha_id_list[] = { + "", + "AES", + "DES", + "ARC4", + "MDHA", + "RNG", + "SNOW f8", + "Kasumi f8/9", + "PKHA", + "CRCA", + "SNOW f9", + "ZUCE", + "ZUCA", +}; + +static const char * const err_id_list[] = { + "No error.", + "Mode error.", + "Data size error.", + "Key size error.", + "PKHA A memory size error.", + "PKHA B memory size error.", + "Data arrived out of sequence error.", + "PKHA divide-by-zero error.", + "PKHA modulus even error.", + "DES key parity error.", + "ICV check failed.", + "Hardware error.", + "Unsupported CCM AAD size.", + "Class 1 CHA is not reset", + "Invalid CHA combination was selected", + "Invalid CHA selected.", +}; + +static const char * const rng_err_id_list[] = { + "", + "", + "", + "Instantiate", + "Not instantiated", + "Test instantiate", + "Prediction resistance", + "Prediction resistance and test request", + "Uninstantiate", + "Secure key generation", +}; + +static void report_invalid_status(struct device_d *jrdev, const u32 status, + const char *error) +{ + dev_err(jrdev, "%08x: %s: %s() not implemented\n", + status, error, __func__); +} + +static void report_ccb_status(struct device_d *jrdev, const u32 status, + const char *error) +{ + u8 cha_id = (status & JRSTA_CCBERR_CHAID_MASK) >> + JRSTA_CCBERR_CHAID_SHIFT; + u8 err_id = status & JRSTA_CCBERR_ERRID_MASK; + u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >> + JRSTA_DECOERR_INDEX_SHIFT; + char *idx_str; + const char *cha_str = "unidentified cha_id value 0x"; + char cha_err_code[3] = { 0 }; + const char *err_str = "unidentified err_id value 0x"; + char err_err_code[3] = { 0 }; + + if (status & JRSTA_DECOERR_JUMP) + idx_str = "jump tgt desc idx"; + else + idx_str = "desc idx"; + + if (cha_id < ARRAY_SIZE(cha_id_list)) + cha_str = cha_id_list[cha_id]; + else + snprintf(cha_err_code, sizeof(cha_err_code), "%02x", cha_id); + + if ((cha_id << JRSTA_CCBERR_CHAID_SHIFT) == JRSTA_CCBERR_CHAID_RNG && + err_id < ARRAY_SIZE(rng_err_id_list) && + strlen(rng_err_id_list[err_id])) { + /* RNG-only error */ + err_str = rng_err_id_list[err_id]; + } else if (err_id < ARRAY_SIZE(err_id_list)) + err_str = err_id_list[err_id]; + else + snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id); + + /* + * CCB ICV check failures are part of normal operation life; + * we leave the upper layers to do what they want with them. + */ + if (err_id != JRSTA_CCBERR_ERRID_ICVCHK) + dev_err(jrdev, "%08x: %s: %s %d: %s%s: %s%s\n", + status, error, idx_str, idx, + cha_str, cha_err_code, + err_str, err_err_code); +} + +static void report_jump_status(struct device_d *jrdev, const u32 status, + const char *error) +{ + dev_err(jrdev, "%08x: %s: %s() not implemented\n", + status, error, __func__); +} + +static void report_deco_status(struct device_d *jrdev, const u32 status, + const char *error) +{ + u8 err_id = status & JRSTA_DECOERR_ERROR_MASK; + u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >> + JRSTA_DECOERR_INDEX_SHIFT; + char *idx_str; + const char *err_str = "unidentified error value 0x"; + char err_err_code[3] = { 0 }; + int i; + + if (status & JRSTA_DECOERR_JUMP) + idx_str = "jump tgt desc idx"; + else + idx_str = "desc idx"; + + for (i = 0; i < ARRAY_SIZE(desc_error_list); i++) + if (desc_error_list[i].value == err_id) + break; + + if (i != ARRAY_SIZE(desc_error_list) && desc_error_list[i].error_text) + err_str = desc_error_list[i].error_text; + else + snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id); + + dev_err(jrdev, "%08x: %s: %s %d: %s%s\n", + status, error, idx_str, idx, err_str, err_err_code); +} + +static void report_jr_status(struct device_d *jrdev, const u32 status, + const char *error) +{ + dev_err(jrdev, "%08x: %s: %s() not implemented\n", + status, error, __func__); +} + +static void report_cond_code_status(struct device_d *jrdev, const u32 status, + const char *error) +{ + dev_err(jrdev, "%08x: %s: %s() not implemented\n", + status, error, __func__); +} + +void caam_jr_strstatus(struct device_d *jrdev, u32 status) +{ + static const struct stat_src { + void (*report_ssed)(struct device_d *jrdev, const u32 status, + const char *error); + const char *error; + } status_src[16] = { + { NULL, "No error" }, + { report_invalid_status, "invalid 0x0001" }, + { report_ccb_status, "CCB" }, + { report_jump_status, "Jump" }, + { report_deco_status, "DECO" }, + { NULL, "Queue Manager Interface" }, + { report_jr_status, "Job Ring" }, + { report_cond_code_status, "Condition Code" }, + { report_invalid_status, "invalid 0x1000" }, + { report_invalid_status, "invalid 0x1001" }, + { report_invalid_status, "invalid 0x1010" }, + { report_invalid_status, "invalid 0x1011" }, + { report_invalid_status, "invalid 0x1100" }, + { report_invalid_status, "invalid 0x1101" }, + { report_invalid_status, "invalid 0x1110" }, + { report_invalid_status, "invalid 0x1111" }, + }; + u32 ssrc = status >> JRSTA_SSRC_SHIFT; + const char *error = status_src[ssrc].error; + + /* + * If there is an error handling function, call it to report the error. + * Otherwise print the error source name. + */ + if (status_src[ssrc].report_ssed) + status_src[ssrc].report_ssed(jrdev, status, error); + else if (error) + dev_err(jrdev, "%d: %s\n", ssrc, error); + else + dev_err(jrdev, "%d: unknown error source\n", ssrc); +} +EXPORT_SYMBOL(caam_jr_strstatus); diff --git a/drivers/crypto/caam/error.h b/drivers/crypto/caam/error.h new file mode 100644 index 0000000000..4ea908977e --- /dev/null +++ b/drivers/crypto/caam/error.h @@ -0,0 +1,11 @@ +/* + * CAAM Error Reporting code header + * + * Copyright 2009-2011 Freescale Semiconductor, Inc. + */ + +#ifndef CAAM_ERROR_H +#define CAAM_ERROR_H +#define CAAM_ERROR_STR_MAX 302 +void caam_jr_strstatus(struct device_d *jrdev, u32 status); +#endif /* CAAM_ERROR_H */ diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h new file mode 100644 index 0000000000..fe19a2c8d2 --- /dev/null +++ b/drivers/crypto/caam/intern.h @@ -0,0 +1,97 @@ +/* + * CAAM/SEC 4.x driver backend + * Private/internal definitions between modules + * + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + */ + +#ifndef INTERN_H +#define INTERN_H + +/* Currently comes from Kconfig param as a ^2 (driver-required) */ +#define JOBR_DEPTH (1 << CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE) + +/* + * Storage for tracking each in-process entry moving across a ring + * Each entry on an output ring needs one of these + */ +struct caam_jrentry_info { + void (*callbk)(struct device_d *dev, u32 *desc, u32 status, void *arg); + void *cbkarg; /* Argument per ring entry */ + u32 *desc_addr_virt; /* Stored virt addr for postprocessing */ + dma_addr_t desc_addr_dma; /* Stored bus addr for done matching */ + u32 desc_size; /* Stored size for postprocessing, header derived */ +}; + +/* Private sub-storage for a single JobR */ +struct caam_drv_private_jr { + struct list_head list_node; /* Job Ring device list */ + struct device_d *dev; + int ridx; + struct caam_job_ring __iomem *rregs; /* JobR's register space */ + int irq; /* One per queue */ + + /* Number of scatterlist crypt transforms active on the JobR */ + int tfm_count; + + /* Job ring info */ + int ringsize; /* Size of rings (assume input = output) */ + struct caam_jrentry_info *entinfo; /* Alloc'ed 1 per ring entry */ + spinlock_t inplock; /* Input ring index lock */ + int inp_ring_write_index; /* Input index "tail" */ + int head; /* entinfo (s/w ring) head index */ + dma_addr_t *inpring; /* Base of input ring, alloc DMA-safe */ + spinlock_t outlock; /* Output ring index lock */ + int out_ring_read_index; /* Output index "tail" */ + int tail; /* entinfo (s/w ring) tail index */ + struct jr_outentry *outring; /* Base of output ring, DMA-safe */ +}; + +/* + * Driver-private storage for a single CAAM block instance + */ +struct caam_drv_private { + + struct device *dev; + struct device *smdev; + struct device_d **jrpdev; /* Alloc'ed array per sub-device */ + struct device_d *pdev; + + /* Physical-presence section */ + struct caam_ctrl __iomem *ctrl; /* controller region */ + struct caam_deco __iomem *deco; /* DECO/CCB views */ + struct caam_assurance __iomem *assure; + struct caam_queue_if __iomem *qi; /* QI control region */ + struct caam_job_ring __iomem *jr[4]; /* JobR's register space */ + struct snvs_full __iomem *snvs; /* SNVS HP+LP register space */ + dma_addr_t __iomem *sm_base; /* Secure memory storage base */ + u32 sm_size; + + /* + * Detected geometry block. Filled in from device tree if powerpc, + * or from register-based version detection code + */ + u8 total_jobrs; /* Total Job Rings in device */ + u8 qi_present; /* Nonzero if QI present in device */ + int secvio_irq; /* Security violation interrupt number */ + int virt_en; /* Virtualization enabled in CAAM */ + +#define RNG4_MAX_HANDLES 2 + /* RNG4 block */ + u32 rng4_sh_init; /* This bitmap shows which of the State + Handles of the RNG4 block are initialized + by this driver */ + + struct clk *caam_ipg; + struct clk *caam_mem; + struct clk *caam_aclk; + struct clk *caam_emi_slow; +}; + +void caam_jr_algapi_init(struct device *dev); +void caam_jr_algapi_remove(struct device *dev); + +int caam_rng_probe(struct device_d *dev, struct device_d *jrdev); +int caam_jr_probe(struct device_d *dev); +#endif /* INTERN_H */ diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c new file mode 100644 index 0000000000..8f169d4060 --- /dev/null +++ b/drivers/crypto/caam/jr.c @@ -0,0 +1,348 @@ +/* +* CAAM/SEC 4.x transport/backend driver +* JobR backend functionality + * + * Copyright 2008-2015 Freescale Semiconductor, Inc. + */ + +#include <common.h> +#include <clock.h> +#include <dma.h> +#include <driver.h> +#include <init.h> +#include <linux/barebox-wrapper.h> +#include <linux/spinlock.h> +#include <linux/circ_buf.h> +#include <linux/compiler.h> +#include <linux/err.h> + +#include "regs.h" +#include "jr.h" +#include "desc.h" +#include "intern.h" + +/* + * The DMA address registers in the JR are a pair of 32-bit registers. + * The layout is: + * + * base + 0x0000 : most-significant 32 bits + * base + 0x0004 : least-significant 32 bits + * + * The 32-bit version of this core therefore has to write to base + 0x0004 + * to set the 32-bit wide DMA address. This seems to be independent of the + * endianness of the written/read data. + */ + +#define REG64_MS32(reg) ((u32 __iomem *)(reg)) +#define REG64_LS32(reg) ((u32 __iomem *)(reg) + 1) + +static inline void wr_reg64(u64 __iomem *reg, u64 data) +{ + writel(data >> 32, REG64_MS32(reg)); + writel(data, REG64_LS32(reg)); +} + +static inline u64 rd_reg64(u64 __iomem *reg) +{ + return ((u64)readl(REG64_MS32(reg)) << 32 | + (u64)readl(REG64_LS32(reg))); +} + +static int caam_reset_hw_jr(struct device_d *dev) +{ + struct caam_drv_private_jr *jrp = dev->priv; + uint64_t start; + + /* initiate flush (required prior to reset) */ + writel(JRCR_RESET, &jrp->rregs->jrcommand); + + start = get_time_ns(); + while ((readl(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) == + JRINT_ERR_HALT_INPROGRESS) { + if (is_timeout(start, 100 * MSECOND)) { + dev_err(dev, "job ring %d timed out on flush\n", + jrp->ridx); + return -ETIMEDOUT; + } + } + + /* initiate reset */ + writel(JRCR_RESET, &jrp->rregs->jrcommand); + + start = get_time_ns(); + while (readl(&jrp->rregs->jrcommand) & JRCR_RESET) { + if (is_timeout(start, 100 * MSECOND)) { + dev_err(dev, "job ring %d timed out on reset\n", + jrp->ridx); + return -ETIMEDOUT; + } + } + + return 0; +} + +/* Deferred service handler, run as interrupt-fired tasklet */ +static int caam_jr_dequeue(struct caam_drv_private_jr *jrp) +{ + int hw_idx, sw_idx, i, head, tail; + void (*usercall)(struct device_d *dev, u32 *desc, u32 status, void *arg); + u32 *userdesc, userstatus; + void *userarg; + int found; + + while (readl(&jrp->rregs->outring_used)) { + head = jrp->head; + + sw_idx = tail = jrp->tail; + hw_idx = jrp->out_ring_read_index; + + found = 0; + + for (i = 0; CIRC_CNT(head, tail + i, JOBR_DEPTH) >= 1; i++) { + sw_idx = (tail + i) & (JOBR_DEPTH - 1); + + if (jrp->outring[hw_idx].desc == + jrp->entinfo[sw_idx].desc_addr_dma) { + found = 1; + break; /* found */ + } + } + + if (!found) + return -ENOENT; + + barrier(); + + /* mark completed, avoid matching on a recycled desc addr */ + jrp->entinfo[sw_idx].desc_addr_dma = 0; + + /* Stash callback params for use outside of lock */ + usercall = jrp->entinfo[sw_idx].callbk; + userarg = jrp->entinfo[sw_idx].cbkarg; + userdesc = jrp->entinfo[sw_idx].desc_addr_virt; + userstatus = jrp->outring[hw_idx].jrstatus; + + barrier(); + + /* set done */ + writel(1, &jrp->rregs->outring_rmvd); + + jrp->out_ring_read_index = (jrp->out_ring_read_index + 1) & + (JOBR_DEPTH - 1); + + /* + * if this job completed out-of-order, do not increment + * the tail. Otherwise, increment tail by 1 plus the + * number of subsequent jobs already completed out-of-order + */ + if (sw_idx == tail) { + do { + tail = (tail + 1) & (JOBR_DEPTH - 1); + } while (CIRC_CNT(head, tail, JOBR_DEPTH) >= 1 && + jrp->entinfo[tail].desc_addr_dma == 0); + + jrp->tail = tail; + } + + /* Finally, execute user's callback */ + usercall(jrp->dev, userdesc, userstatus, userarg); + } + + return 0; +} + +/* Main per-ring interrupt handler */ +static int caam_jr_interrupt(struct caam_drv_private_jr *jrp) +{ + uint64_t start; + u32 irqstate; + + start = get_time_ns(); + while (!(irqstate = readl(&jrp->rregs->jrintstatus))) { + if (is_timeout(start, 100 * MSECOND)) { + dev_err(jrp->dev, "timeout waiting for interrupt\n"); + return -ETIMEDOUT; + } + } + + /* + * If JobR error, we got more development work to do + * Flag a bug now, but we really need to shut down and + * restart the queue (and fix code). + */ + if (irqstate & JRINT_JR_ERROR) { + dev_err(jrp->dev, "job ring error: irqstate: %08x\n", irqstate); + BUG(); + } + + /* Have valid interrupt at this point, just ACK and trigger */ + writel(irqstate, &jrp->rregs->jrintstatus); + + return caam_jr_dequeue(jrp); +} + + +/** + * caam_jr_enqueue() - Enqueue a job descriptor head. Returns 0 if OK, + * -EBUSY if the queue is full, -EIO if it cannot map the caller's + * descriptor. + * @dev: device of the job ring to be used. + * @desc: points to a job descriptor that execute our request. All + * descriptors (and all referenced data) must be in a DMAable + * region, and all data references must be physical addresses + * accessible to CAAM (i.e. within a PAMU window granted + * to it). + * @cbk: pointer to a callback function to be invoked upon completion + * of this request. This has the form: + * callback(struct device *dev, u32 *desc, u32 stat, void *arg) + * where: + * @dev: contains the job ring device that processed this + * response. + * @desc: descriptor that initiated the request, same as + * "desc" being argued to caam_jr_enqueue(). + * @status: untranslated status received from CAAM. See the + * reference manual for a detailed description of + * error meaning, or see the JRSTA definitions in the + * register header file + * @areq: optional pointer to an argument passed with the + * original request + * @areq: optional pointer to a user argument for use at callback + * time. + **/ +int caam_jr_enqueue(struct device_d *dev, u32 *desc, + void (*cbk)(struct device_d *dev, u32 *desc, + u32 status, void *areq), + void *areq) +{ + struct caam_drv_private_jr *jrp; + struct caam_jrentry_info *head_entry; + int head, tail, desc_size; + + desc_size = (*desc & HDR_JD_LENGTH_MASK) * sizeof(u32); + + if (!dev->priv) + return -ENODEV; + + jrp = dev->priv; + + head = jrp->head; + tail = jrp->tail; + if (!readl(&jrp->rregs->inpring_avail) || + CIRC_SPACE(head, tail, JOBR_DEPTH) <= 0) { + return -EBUSY; + } + + head_entry = &jrp->entinfo[head]; + head_entry->desc_addr_virt = phys_to_virt((u32) desc); + head_entry->desc_size = desc_size; + head_entry->callbk = (void *)cbk; + head_entry->cbkarg = areq; + head_entry->desc_addr_dma = (dma_addr_t)desc; + + if (!jrp->inpring) + return -EIO; + + jrp->inpring[jrp->inp_ring_write_index] = (dma_addr_t)desc; + + barrier(); + + jrp->inp_ring_write_index = (jrp->inp_ring_write_index + 1) & + (JOBR_DEPTH - 1); + jrp->head = (head + 1) & (JOBR_DEPTH - 1); + + barrier(); + writel(1, &jrp->rregs->inpring_jobadd); + + clrbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK); + + return caam_jr_interrupt(jrp); +} +EXPORT_SYMBOL(caam_jr_enqueue); + +/* + * Init JobR independent of platform property detection + */ +static int caam_jr_init(struct device_d *dev) +{ + struct caam_drv_private_jr *jrp; + dma_addr_t dma_inpring; + dma_addr_t dma_outring; + int i, error; + + jrp = dev->priv; + + error = caam_reset_hw_jr(dev); + if (error) + return error; + + jrp->inpring = dma_alloc_coherent(sizeof(*jrp->inpring) * JOBR_DEPTH, + &dma_inpring); + if (!jrp->inpring) + return -ENOMEM; + + jrp->outring = dma_alloc_coherent(sizeof(*jrp->outring) * + JOBR_DEPTH, &dma_outring); + if (!jrp->outring) { + dma_free_coherent(jrp->inpring, 0, sizeof(dma_addr_t) * JOBR_DEPTH); + dev_err(dev, "can't allocate job rings for %d\n", jrp->ridx); + return -ENOMEM; + } + + jrp->entinfo = xzalloc(sizeof(*jrp->entinfo) * JOBR_DEPTH); + + for (i = 0; i < JOBR_DEPTH; i++) + jrp->entinfo[i].desc_addr_dma = !0; + + /* Setup rings */ + jrp->inp_ring_write_index = 0; + jrp->out_ring_read_index = 0; + jrp->head = 0; + jrp->tail = 0; + + wr_reg64(&jrp->rregs->inpring_base, dma_inpring); + wr_reg64(&jrp->rregs->outring_base, dma_outring); + writel(JOBR_DEPTH, &jrp->rregs->inpring_size); + writel(JOBR_DEPTH, &jrp->rregs->outring_size); + + jrp->ringsize = JOBR_DEPTH; + + return 0; +} + +/* + * Probe routine for each detected JobR subsystem. + */ +int caam_jr_probe(struct device_d *dev) +{ + struct device_node *nprop; + struct caam_job_ring __iomem *ctrl; + struct caam_drv_private_jr *jrpriv; + static int total_jobrs; + int error; + + jrpriv = xzalloc(sizeof(*jrpriv)); + + dev->priv = jrpriv; + jrpriv->dev = dev; + + /* save ring identity relative to detection */ + jrpriv->ridx = total_jobrs++; + + nprop = dev->device_node; + /* Get configuration properties from device tree */ + /* First, get register page */ + ctrl = dev_get_mem_region(dev, 0); + if (IS_ERR(ctrl)) + return PTR_ERR(ctrl); + + jrpriv->rregs = (struct caam_job_ring __force *)ctrl; + + /* Now do the platform independent part */ + error = caam_jr_init(dev); /* now turn on hardware */ + if (error) + return error; + + jrpriv->tfm_count = 0; + + return 0; +} diff --git a/drivers/crypto/caam/jr.h b/drivers/crypto/caam/jr.h new file mode 100644 index 0000000000..e0e53c0f6c --- /dev/null +++ b/drivers/crypto/caam/jr.h @@ -0,0 +1,18 @@ +/* + * CAAM public-level include definitions for the JobR backend + * + * Copyright 2008-2011 Freescale Semiconductor, Inc. + */ + +#ifndef JR_H +#define JR_H + +/* Prototypes for backend-level services exposed to APIs */ +struct device *caam_jr_alloc(void); +void caam_jr_free(struct device *rdev); +int caam_jr_enqueue(struct device_d *dev, u32 *desc, + void (*cbk)(struct device_d *dev, u32 *desc, u32 status, + void *areq), + void *areq); + +#endif /* JR_H */ diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h new file mode 100644 index 0000000000..b8ca5e396a --- /dev/null +++ b/drivers/crypto/caam/regs.h @@ -0,0 +1,895 @@ +/* + * CAAM hardware register-level view + * + * Copyright 2008-2015 Freescale Semiconductor, Inc. + */ + +#ifndef REGS_H +#define REGS_H + +#include <linux/types.h> +#include <io.h> + +/* These are common macros for Power, put here for ARMs */ +#define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr)) +#define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr)) + +/* + * jr_outentry + * Represents each entry in a JobR output ring + */ +struct jr_outentry { + dma_addr_t desc;/* Pointer to completed descriptor */ + u32 jrstatus; /* Status for completed descriptor */ +} __packed; + +/* + * CHA version ID / instantiation bitfields + * Defined for use within cha_id in perfmon + * Note that the same shift/mask selectors can be used to pull out number + * of instantiated blocks within cha_num in perfmon, the locations are + * the same. + */ + +/* Number of DECOs */ +#define CHA_NUM_MS_DECONUM_SHIFT 24 +#define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT) + +/* CHA Version IDs */ +#define CHA_ID_LS_AES_SHIFT 0 +#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT) + +#define CHA_ID_LS_DES_SHIFT 4 +#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT) + +#define CHA_ID_LS_ARC4_SHIFT 8 +#define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT) + +#define CHA_ID_LS_MD_SHIFT 12 +#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT) + +#define CHA_ID_LS_RNG_SHIFT 16 +#define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT) + +#define CHA_ID_LS_SNW8_SHIFT 20 +#define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT) + +#define CHA_ID_LS_KAS_SHIFT 24 +#define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT) + +#define CHA_ID_LS_PK_SHIFT 28 +#define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT) + +#define CHA_ID_MS_CRC_SHIFT 0 +#define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT) + +#define CHA_ID_MS_SNW9_SHIFT 4 +#define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT) + +#define CHA_ID_MS_DECO_SHIFT 24 +#define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT) + +#define CHA_ID_MS_JR_SHIFT 28 +#define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT) + +/* ZUC-Authentication */ +#define CHA_ID_MS_ZA_SHIFT 12 +#define CHA_ID_MS_ZA_MASK (0xfull << CHA_ID_MS_ZA_SHIFT) + +/* ZUC-Encryption */ +#define CHA_ID_MS_ZE_SHIFT 8 +#define CHA_ID_MS_ZE_MASK (0xfull << CHA_ID_MS_ZE_SHIFT) + +/* SNOW f9 */ +#define CHA_ID_MS_SNW9_SHIFT 4 +#define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT) + +/* CRC */ +#define CHA_ID_MS_CRC_SHIFT 0 +#define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT) + +/* Public Key */ +#define CHA_ID_LS_PK_SHIFT 28 +#define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT) + +/* Kasumi */ +#define CHA_ID_LS_KAS_SHIFT 24 +#define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT) + +/* SNOW f8 */ +#define CHA_ID_LS_SNW8_SHIFT 20 +#define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT) + +/* + * Random Generator + * RNG4 = FIPS-verification-compliant, requires init kickstart for use + */ +#define CHA_ID_LS_RNG_SHIFT 16 +#define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT) +#define CHA_ID_LS_RNG_A (0x1ull << CHA_ID_LS_RNG_SHIFT) +#define CHA_ID_LS_RNG_B (0x2ull << CHA_ID_LS_RNG_SHIFT) +#define CHA_ID_LS_RNG_C (0x3ull << CHA_ID_LS_RNG_SHIFT) +#define CHA_ID_LS_RNG_4 (0x4ull << CHA_ID_LS_RNG_SHIFT) + +/* + * Message Digest + * LP256 = Low Power (MD5/SHA1/SHA224/SHA256 + HMAC) + * LP512 = Low Power (LP256 + SHA384/SHA512) + * HP = High Power (LP512 + SMAC) + */ +#define CHA_ID_LS_MD_SHIFT 12 +#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT) +#define CHA_ID_LS_MD_LP256 (0x0ull << CHA_ID_LS_MD_SHIFT) +#define CHA_ID_LS_MD_LP512 (0x1ull << CHA_ID_LS_MD_SHIFT) +#define CHA_ID_LS_MD_HP (0x2ull << CHA_ID_LS_MD_SHIFT) + +/* ARC4 Streamcipher */ +#define CHA_ID_LS_ARC4_SHIFT 8 +#define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT) +#define CHA_ID_LS_ARC4_LP (0x0ull << CHA_ID_LS_ARC4_SHIFT) +#define CHA_ID_LS_ARC4_HP (0x1ull << CHA_ID_LS_ARC4_SHIFT) + +/* DES Blockcipher Accelerator */ +#define CHA_ID_LS_DES_SHIFT 4 +#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT) + +/* + * AES Blockcipher + Combo Mode Accelerator + * LP = Low Power (includes ECB/CBC/CFB128/OFB/CTR/CCM/CMAC/XCBC-MAC) + * HP = High Power (LP + CBCXCBC/CTRXCBC/XTS/GCM) + * DIFFPWR = ORed in if differential-power-analysis resistance implemented + */ +#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT) +#define CHA_ID_LS_AES_LP (0x3ull << CHA_ID_LS_AES_SHIFT) +#define CHA_ID_LS_AES_HP (0x4ull << CHA_ID_LS_AES_SHIFT) +#define CHA_ID_LS_AES_DIFFPWR (0x1ull << CHA_ID_LS_AES_SHIFT) + +/* + * caam_perfmon - Performance Monitor/Secure Memory Status/ + * CAAM Global Status/Component Version IDs + * + * Spans f00-fff wherever instantiated + */ + +struct sec_vid { + u16 ip_id; + u8 maj_rev; + u8 min_rev; +}; + +struct caam_perfmon { + /* Performance Monitor Registers f00-f9f */ + u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */ + u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */ + u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */ + u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */ + u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */ + u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */ + u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */ + u64 rsvd[13]; + + /* CAAM Hardware Instantiation Parameters fa0-fbf */ + u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/ + u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/ +#define CTPR_MS_QI_SHIFT 25 +#define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT) +#define CTPR_MS_VIRT_EN_INCL 0x00000001 +#define CTPR_MS_VIRT_EN_POR 0x00000002 +#define CTPR_MS_PG_SZ_MASK 0x10 +#define CTPR_MS_PG_SZ_SHIFT 4 + u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ + u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ + /* Secure Memory State Visibility */ + u32 rsvd1; + u32 smstatus; /* Secure memory status */ + u32 rsvd2; + u32 smpartown; /* Secure memory partition owner */ + + /* CAAM Global Status fc0-fdf */ + u64 faultaddr; /* FAR - Fault Address */ + u32 faultliodn; /* FALR - Fault Address LIODN */ + u32 faultdetail; /* FADR - Fault Addr Detail */ + u32 rsvd3; + u32 status; /* CSTA - CAAM Status */ + u32 smpart; /* Secure Memory Partition Parameters */ + u32 smvid; /* Secure Memory Version ID */ + + /* Component Instantiation Parameters fe0-fff */ + u32 rtic_id; /* RVID - RTIC Version ID */ + u32 ccb_id; /* CCBVID - CCB Version ID */ + u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/ + u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/ + u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */ + u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/ + u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */ + u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */ +}; + +#define SMSTATUS_PART_SHIFT 28 +#define SMSTATUS_PART_MASK (0xf << SMSTATUS_PART_SHIFT) +#define SMSTATUS_PAGE_SHIFT 16 +#define SMSTATUS_PAGE_MASK (0x7ff << SMSTATUS_PAGE_SHIFT) +#define SMSTATUS_MID_SHIFT 8 +#define SMSTATUS_MID_MASK (0x3f << SMSTATUS_MID_SHIFT) +#define SMSTATUS_ACCERR_SHIFT 4 +#define SMSTATUS_ACCERR_MASK (0xf << SMSTATUS_ACCERR_SHIFT) +#define SMSTATUS_ACCERR_NONE 0 +#define SMSTATUS_ACCERR_ALLOC 1 /* Page not allocated */ +#define SMSTATUS_ACCESS_ID 2 /* Not granted by ID */ +#define SMSTATUS_ACCESS_WRITE 3 /* Writes not allowed */ +#define SMSTATUS_ACCESS_READ 4 /* Reads not allowed */ +#define SMSTATUS_ACCESS_NONKEY 6 /* Non-key reads not allowed */ +#define SMSTATUS_ACCESS_BLOB 9 /* Blob access not allowed */ +#define SMSTATUS_ACCESS_DESCB 10 /* Descriptor Blob access spans pages */ +#define SMSTATUS_ACCESS_NON_SM 11 /* Outside Secure Memory range */ +#define SMSTATUS_ACCESS_XPAGE 12 /* Access crosses pages */ +#define SMSTATUS_ACCESS_INITPG 13 /* Page still initializing */ +#define SMSTATUS_STATE_SHIFT 0 +#define SMSTATUS_STATE_MASK (0xf << SMSTATUS_STATE_SHIFT) +#define SMSTATUS_STATE_RESET 0 +#define SMSTATUS_STATE_INIT 1 +#define SMSTATUS_STATE_NORMAL 2 +#define SMSTATUS_STATE_FAIL 3 + +/* up to 15 rings, 2 bits shifted by ring number */ +#define SMPARTOWN_RING_SHIFT 2 +#define SMPARTOWN_RING_MASK 3 +#define SMPARTOWN_AVAILABLE 0 +#define SMPARTOWN_NOEXIST 1 +#define SMPARTOWN_UNAVAILABLE 2 +#define SMPARTOWN_OURS 3 + +/* Maximum number of pages possible */ +#define SMPART_MAX_NUMPG_SHIFT 16 +#define SMPART_MAX_NUMPG_MASK (0x3f << SMPART_MAX_NUMPG_SHIFT) + +/* Maximum partition number */ +#define SMPART_MAX_PNUM_SHIFT 12 +#define SMPART_MAX_PNUM_MASK (0xf << SMPART_MAX_PNUM_SHIFT) + +/* Highest possible page number */ +#define SMPART_MAX_PG_SHIFT 0 +#define SMPART_MAX_PG_MASK (0x3f << SMPART_MAX_PG_SHIFT) + +/* Max size of a page */ +#define SMVID_PG_SIZE_SHIFT 16 +#define SMVID_PG_SIZE_MASK (0x7 << SMVID_PG_SIZE_SHIFT) + +/* Major/Minor Version ID */ +#define SMVID_MAJ_VERS_SHIFT 8 +#define SMVID_MAJ_VERS (0xf << SMVID_MAJ_VERS_SHIFT) +#define SMVID_MIN_VERS_SHIFT 0 +#define SMVID_MIN_VERS (0xf << SMVID_MIN_VERS_SHIFT) + +/* LIODN programming for DMA configuration */ +#define MSTRID_LOCK_LIODN 0x80000000 +#define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */ + +#define MSTRID_LIODN_MASK 0x0fff +struct masterid { + u32 liodn_ms; /* lock and make-trusted control bits */ + u32 liodn_ls; /* LIODN for non-sequence and seq access */ +}; + +/* Partition ID for DMA configuration */ +struct partid { + u32 rsvd1; + u32 pidr; /* partition ID, DECO */ +}; + +/* RNGB test mode (replicated twice in some configurations) */ +/* Padded out to 0x100 */ +struct rngtst { + u32 mode; /* RTSTMODEx - Test mode */ + u32 rsvd1[3]; + u32 reset; /* RTSTRESETx - Test reset control */ + u32 rsvd2[3]; + u32 status; /* RTSTSSTATUSx - Test status */ + u32 rsvd3; + u32 errstat; /* RTSTERRSTATx - Test error status */ + u32 rsvd4; + u32 errctl; /* RTSTERRCTLx - Test error control */ + u32 rsvd5; + u32 entropy; /* RTSTENTROPYx - Test entropy */ + u32 rsvd6[15]; + u32 verifctl; /* RTSTVERIFCTLx - Test verification control */ + u32 rsvd7; + u32 verifstat; /* RTSTVERIFSTATx - Test verification status */ + u32 rsvd8; + u32 verifdata; /* RTSTVERIFDx - Test verification data */ + u32 rsvd9; + u32 xkey; /* RTSTXKEYx - Test XKEY */ + u32 rsvd10; + u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */ + u32 rsvd11; + u32 oscct; /* RTSTOSCCTx - Test oscillator counter */ + u32 rsvd12; + u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */ + u32 rsvd13[2]; + u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */ + u32 rsvd14[15]; +}; + +/* RNG4 TRNG test registers */ +struct rng4tst { +#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ +#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in + both entropy shifter and + statistical checker */ +#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both + entropy shifter and + statistical checker */ +#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in + entropy shifter, raw data + in statistical checker */ +#define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */ + u32 rtmctl; /* misc. control register */ + u32 rtscmisc; /* statistical check misc. register */ + u32 rtpkrrng; /* poker range register */ + union { + u32 rtpkrmax; /* PRGM=1: poker max. limit register */ + u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ + }; +#define RTSDCTL_ENT_DLY_SHIFT 16 +#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) +#define RTSDCTL_ENT_DLY_MIN 3200 +#define RTSDCTL_ENT_DLY_MAX 12800 + u32 rtsdctl; /* seed control register */ + union { + u32 rtsblim; /* PRGM=1: sparse bit limit register */ + u32 rttotsam; /* PRGM=0: total samples register */ + }; + u32 rtfrqmin; /* frequency count min. limit register */ +#define RTFRQMAX_DISABLE (1 << 20) + union { + u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */ + u32 rtfrqcnt; /* PRGM=0: freq. count register */ + }; + u32 rsvd1[40]; +#define RDSTA_SKVT 0x80000000 +#define RDSTA_SKVN 0x40000000 +#define RDSTA_IF0 0x00000001 +#define RDSTA_IF1 0x00000002 +#define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0) + u32 rdsta; + u32 rsvd2[15]; +}; + +/* + * caam_ctrl - basic core configuration + * starts base + 0x0000 padded out to 0x1000 + */ + +#define KEK_KEY_SIZE 8 +#define TKEK_KEY_SIZE 8 +#define TDSK_KEY_SIZE 8 + +#define DECO_RESET 1 /* Use with DECO reset/availability regs */ +#define DECO_RESET_0 (DECO_RESET << 0) +#define DECO_RESET_1 (DECO_RESET << 1) +#define DECO_RESET_2 (DECO_RESET << 2) +#define DECO_RESET_3 (DECO_RESET << 3) +#define DECO_RESET_4 (DECO_RESET << 4) + +struct caam_ctrl { + /* Basic Configuration Section 000-01f */ + /* Read/Writable */ + u32 rsvd1; + u32 mcr; /* MCFG Master Config Register */ + u32 rsvd2; + u32 scfgr; /* SCFGR, Security Config Register */ + + /* Bus Access Configuration Section 010-11f */ + /* Read/Writable */ + struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */ + u32 rsvd3[11]; + u32 jrstart; /* JRSTART - Job Ring Start Register */ + struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */ + u32 rsvd4[5]; + u32 deco_rsr; /* DECORSR - Deco Request Source */ + u32 rsvd11; + u32 deco_rq; /* DECORR - DECO Request */ + struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */ + u32 rsvd5[22]; + + /* DECO Availability/Reset Section 120-3ff */ + u32 deco_avail; /* DAR - DECO availability */ + u32 deco_reset; /* DRR - DECO reset */ + u32 rsvd6[182]; + + /* Key Encryption/Decryption Configuration 400-5ff */ + /* Read/Writable only while in Non-secure mode */ + u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */ + u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */ + u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */ + u32 rsvd7[32]; + u64 sknonce; /* SKNR - Secure Key Nonce */ + u32 rsvd8[70]; + + /* RNG Test/Verification/Debug Access 600-7ff */ + /* (Useful in Test/Debug modes only...) */ + union { + struct rngtst rtst[2]; + struct rng4tst r4tst[2]; + }; + + u32 rsvd9[448]; + + /* Performance Monitor f00-fff */ + struct caam_perfmon perfmon; +}; + +/* + * Controller master config register defs + */ +#define MCFGR_SWRESET 0x80000000 /* software reset */ +#define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */ +#define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */ +#define MCFGR_DMA_RESET 0x10000000 +#define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */ +#define SCFGR_RDBENABLE 0x00000400 +#define SCFGR_VIRT_EN 0x00008000 +#define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */ +#define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */ +#define DECORSR_VALID 0x80000000 +#define DECORR_DEN0 0x00010000 /* DECO0 available for access*/ + +/* AXI read cache control */ +#define MCFGR_ARCACHE_SHIFT 12 +#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) +#define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT) +#define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT) +#define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT) + +/* AXI write cache control */ +#define MCFGR_AWCACHE_SHIFT 8 +#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) +#define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT) +#define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT) +#define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT) + +/* AXI pipeline depth */ +#define MCFGR_AXIPIPE_SHIFT 4 +#define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT) + +#define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */ +#define MCFGR_BURST_64 0x00000001 /* Max burst size */ + +/* JRSTART register offsets */ +#define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */ +#define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */ +#define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */ +#define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */ + +/* + * caam_job_ring - direct job ring setup + * 1-4 possible per instantiation, base + 1000/2000/3000/4000 + * Padded out to 0x1000 + */ +struct caam_job_ring { + /* Input ring */ + u64 inpring_base; /* IRBAx - Input desc ring baseaddr */ + u32 rsvd1; + u32 inpring_size; /* IRSx - Input ring size */ + u32 rsvd2; + u32 inpring_avail; /* IRSAx - Input ring room remaining */ + u32 rsvd3; + u32 inpring_jobadd; /* IRJAx - Input ring jobs added */ + + /* Output Ring */ + u64 outring_base; /* ORBAx - Output status ring base addr */ + u32 rsvd4; + u32 outring_size; /* ORSx - Output ring size */ + u32 rsvd5; + u32 outring_rmvd; /* ORJRx - Output ring jobs removed */ + u32 rsvd6; + u32 outring_used; /* ORSFx - Output ring slots full */ + + /* Status/Configuration */ + u32 rsvd7; + u32 jroutstatus; /* JRSTAx - JobR output status */ + u32 rsvd8; + u32 jrintstatus; /* JRINTx - JobR interrupt status */ + u32 rconfig_hi; /* JRxCFG - Ring configuration */ + u32 rconfig_lo; + + /* Indices. CAAM maintains as "heads" of each queue */ + u32 rsvd9; + u32 inp_rdidx; /* IRRIx - Input ring read index */ + u32 rsvd10; + u32 out_wtidx; /* ORWIx - Output ring write index */ + + /* Command/control */ + u32 rsvd11; + u32 jrcommand; /* JRCRx - JobR command */ + + u32 rsvd12[33]; + + /* Secure Memory Configuration - if you have it */ + u32 sm_cmd; /* SMCJRx - Secure memory command */ + u32 rsvd13; + u32 sm_status; /* SMCSJRx - Secure memory status */ + u32 rsvd14; + u32 sm_perm; /* SMAPJRx - Secure memory access perms */ + u32 sm_group2; /* SMAP2JRx - Secure memory access group 2 */ + u32 sm_group1; /* SMAP1JRx - Secure memory access group 1 */ + + u32 rsvd15[891]; + + /* Performance Monitor f00-fff */ + struct caam_perfmon perfmon; +}; + +#define JR_RINGSIZE_MASK 0x03ff +/* + * jrstatus - Job Ring Output Status + * All values in lo word + * Also note, same values written out as status through QI + * in the command/status field of a frame descriptor + */ +#define JRSTA_SSRC_SHIFT 28 +#define JRSTA_SSRC_MASK 0xf0000000 + +#define JRSTA_SSRC_NONE 0x00000000 +#define JRSTA_SSRC_CCB_ERROR 0x20000000 +#define JRSTA_SSRC_JUMP_HALT_USER 0x30000000 +#define JRSTA_SSRC_DECO 0x40000000 +#define JRSTA_SSRC_JRERROR 0x60000000 +#define JRSTA_SSRC_JUMP_HALT_CC 0x70000000 + +#define JRSTA_DECOERR_JUMP 0x08000000 +#define JRSTA_DECOERR_INDEX_SHIFT 8 +#define JRSTA_DECOERR_INDEX_MASK 0xff00 +#define JRSTA_DECOERR_ERROR_MASK 0x00ff + +#define JRSTA_DECOERR_NONE 0x00 +#define JRSTA_DECOERR_LINKLEN 0x01 +#define JRSTA_DECOERR_LINKPTR 0x02 +#define JRSTA_DECOERR_JRCTRL 0x03 +#define JRSTA_DECOERR_DESCCMD 0x04 +#define JRSTA_DECOERR_ORDER 0x05 +#define JRSTA_DECOERR_KEYCMD 0x06 +#define JRSTA_DECOERR_LOADCMD 0x07 +#define JRSTA_DECOERR_STORECMD 0x08 +#define JRSTA_DECOERR_OPCMD 0x09 +#define JRSTA_DECOERR_FIFOLDCMD 0x0a +#define JRSTA_DECOERR_FIFOSTCMD 0x0b +#define JRSTA_DECOERR_MOVECMD 0x0c +#define JRSTA_DECOERR_JUMPCMD 0x0d +#define JRSTA_DECOERR_MATHCMD 0x0e +#define JRSTA_DECOERR_SHASHCMD 0x0f +#define JRSTA_DECOERR_SEQCMD 0x10 +#define JRSTA_DECOERR_DECOINTERNAL 0x11 +#define JRSTA_DECOERR_SHDESCHDR 0x12 +#define JRSTA_DECOERR_HDRLEN 0x13 +#define JRSTA_DECOERR_BURSTER 0x14 +#define JRSTA_DECOERR_DESCSIGNATURE 0x15 +#define JRSTA_DECOERR_DMA 0x16 +#define JRSTA_DECOERR_BURSTFIFO 0x17 +#define JRSTA_DECOERR_JRRESET 0x1a +#define JRSTA_DECOERR_JOBFAIL 0x1b +#define JRSTA_DECOERR_DNRERR 0x80 +#define JRSTA_DECOERR_UNDEFPCL 0x81 +#define JRSTA_DECOERR_PDBERR 0x82 +#define JRSTA_DECOERR_ANRPLY_LATE 0x83 +#define JRSTA_DECOERR_ANRPLY_REPLAY 0x84 +#define JRSTA_DECOERR_SEQOVF 0x85 +#define JRSTA_DECOERR_INVSIGN 0x86 +#define JRSTA_DECOERR_DSASIGN 0x87 + +#define JRSTA_CCBERR_JUMP 0x08000000 +#define JRSTA_CCBERR_INDEX_MASK 0xff00 +#define JRSTA_CCBERR_INDEX_SHIFT 8 +#define JRSTA_CCBERR_CHAID_MASK 0x00f0 +#define JRSTA_CCBERR_CHAID_SHIFT 4 +#define JRSTA_CCBERR_ERRID_MASK 0x000f + +#define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT) + +#define JRSTA_CCBERR_ERRID_NONE 0x00 +#define JRSTA_CCBERR_ERRID_MODE 0x01 +#define JRSTA_CCBERR_ERRID_DATASIZ 0x02 +#define JRSTA_CCBERR_ERRID_KEYSIZ 0x03 +#define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04 +#define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05 +#define JRSTA_CCBERR_ERRID_SEQUENCE 0x06 +#define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07 +#define JRSTA_CCBERR_ERRID_PKMODEVN 0x08 +#define JRSTA_CCBERR_ERRID_KEYPARIT 0x09 +#define JRSTA_CCBERR_ERRID_ICVCHK 0x0a +#define JRSTA_CCBERR_ERRID_HARDWARE 0x0b +#define JRSTA_CCBERR_ERRID_CCMAAD 0x0c +#define JRSTA_CCBERR_ERRID_INVCHA 0x0f + +#define JRINT_ERR_INDEX_MASK 0x3fff0000 +#define JRINT_ERR_INDEX_SHIFT 16 +#define JRINT_ERR_TYPE_MASK 0xf00 +#define JRINT_ERR_TYPE_SHIFT 8 +#define JRINT_ERR_HALT_MASK 0xc +#define JRINT_ERR_HALT_SHIFT 2 +#define JRINT_ERR_HALT_INPROGRESS 0x4 +#define JRINT_ERR_HALT_COMPLETE 0x8 +#define JRINT_JR_ERROR 0x02 +#define JRINT_JR_INT 0x01 + +#define JRINT_ERR_TYPE_WRITE 1 +#define JRINT_ERR_TYPE_BAD_INPADDR 3 +#define JRINT_ERR_TYPE_BAD_OUTADDR 4 +#define JRINT_ERR_TYPE_INV_INPWRT 5 +#define JRINT_ERR_TYPE_INV_OUTWRT 6 +#define JRINT_ERR_TYPE_RESET 7 +#define JRINT_ERR_TYPE_REMOVE_OFL 8 +#define JRINT_ERR_TYPE_ADD_OFL 9 + +#define JRCFG_SOE 0x04 +#define JRCFG_ICEN 0x02 +#define JRCFG_IMSK 0x01 +#define JRCFG_ICDCT_SHIFT 8 +#define JRCFG_ICTT_SHIFT 16 + +#define JRCR_RESET 0x01 + +/* secure memory command */ +#define SMC_PAGE_SHIFT 16 +#define SMC_PAGE_MASK (0xffff << SMC_PAGE_SHIFT) +#define SMC_PART_SHIFT 8 +#define SMC_PART_MASK (0x0f << SMC_PART_SHIFT) +#define SMC_CMD_SHIFT 0 +#define SMC_CMD_MASK (0x0f << SMC_CMD_SHIFT) + +#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */ +#define SMC_CMD_DEALLOC_PAGE 0x02 /* deallocate page from partition */ +#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */ +#define SMC_CMD_PAGE_INQUIRY 0x05 /* find partition associate with page */ + +/* secure memory (command) status */ +#define SMCS_PAGE_SHIFT 16 +#define SMCS_PAGE_MASK (0x0fff << SMCS_PAGE_SHIFT) +#define SMCS_CMDERR_SHIFT 14 +#define SMCS_CMDERR_MASK (3 << SMCS_CMDERR_SHIFT) +#define SMCS_ALCERR_SHIFT 12 +#define SMCS_ALCERR_MASK (3 << SMCS_ALCERR_SHIFT) +#define SMCS_PGOWN_SHIFT 6 +#define SMCS_PGWON_MASK (3 << SMCS_PGOWN_SHIFT) +#define SMCS_PART_SHIFT 0 +#define SMCS_PART_MASK (0xf << SMCS_PART_SHIFT) + +#define SMCS_CMDERR_NONE 0 +#define SMCS_CMDERR_INCOMP 1 /* Command not yet complete */ +#define SMCS_CMDERR_SECFAIL 2 /* Security failure occurred */ +#define SMCS_CMDERR_OVERFLOW 3 /* Command overflow */ + +#define SMCS_ALCERR_NONE 0 +#define SMCS_ALCERR_PSPERR 1 /* Partion marked PSP (dealloc only) */ +#define SMCS_ALCERR_PAGEAVAIL 2 /* Page not available */ +#define SMCS_ALCERR_PARTOWN 3 /* Partition ownership error */ + +#define SMCS_PGOWN_AVAIL 0 /* Page is available */ +#define SMCS_PGOWN_NOEXIST 1 /* Page initializing or nonexistent */ +#define SMCS_PGOWN_NOOWN 2 /* Page owned by another processor */ +#define SMCS_PGOWN_OWNED 3 /* Page belongs to this processor */ + +/* secure memory access permissions */ +#define SMCS_PERM_KEYMOD_SHIFT 16 +#define SMCA_PERM_KEYMOD_MASK (0xff << SMCS_PERM_KEYMOD_SHIFT) +#define SMCA_PERM_CSP_ZERO 0x8000 /* Zero when deallocated or released */ +#define SMCA_PERM_PSP_LOCK 0x4000 /* Part./pages can't be deallocated */ +#define SMCA_PERM_PERM_LOCK 0x2000 /* Lock permissions */ +#define SMCA_PERM_GRP_LOCK 0x1000 /* Lock access groups */ +#define SMCA_PERM_RINGID_SHIFT 10 +#define SMCA_PERM_RINGID_MASK (3 << SMCA_PERM_RINGID_SHIFT) +#define SMCA_PERM_G2_BLOB 0x0080 /* Group 2 blob import/export */ +#define SMCA_PERM_G2_WRITE 0x0020 /* Group 2 write */ +#define SMCA_PERM_G2_READ 0x0010 /* Group 2 read */ +#define SMCA_PERM_G1_BLOB 0x0008 /* Group 1... */ +#define SMCA_PERM_G1_WRITE 0x0002 +#define SMCA_PERM_G1_READ 0x0001 + +/* + * caam_assurance - Assurance Controller View + * base + 0x6000 padded out to 0x1000 + */ + +struct rtic_element { + u64 address; + u32 rsvd; + u32 length; +}; + +struct rtic_block { + struct rtic_element element[2]; +}; + +struct rtic_memhash { + u32 memhash_be[32]; + u32 memhash_le[32]; +}; + +struct caam_assurance { + /* Status/Command/Watchdog */ + u32 rsvd1; + u32 status; /* RSTA - Status */ + u32 rsvd2; + u32 cmd; /* RCMD - Command */ + u32 rsvd3; + u32 ctrl; /* RCTL - Control */ + u32 rsvd4; + u32 throttle; /* RTHR - Throttle */ + u32 rsvd5[2]; + u64 watchdog; /* RWDOG - Watchdog Timer */ + u32 rsvd6; + u32 rend; /* REND - Endian corrections */ + u32 rsvd7[50]; + + /* Block access/configuration @ 100/110/120/130 */ + struct rtic_block memblk[4]; /* Memory Blocks A-D */ + u32 rsvd8[32]; + + /* Block hashes @ 200/300/400/500 */ + struct rtic_memhash hash[4]; /* Block hash values A-D */ + u32 rsvd_3[640]; +}; + +/* + * caam_queue_if - QI configuration and control + * starts base + 0x7000, padded out to 0x1000 long + */ + +struct caam_queue_if { + u32 qi_control_hi; /* QICTL - QI Control */ + u32 qi_control_lo; + u32 rsvd1; + u32 qi_status; /* QISTA - QI Status */ + u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */ + u32 qi_deq_cfg_lo; + u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */ + u32 qi_enq_cfg_lo; + u32 rsvd2[1016]; +}; + +/* QI control bits - low word */ +#define QICTL_DQEN 0x01 /* Enable frame pop */ +#define QICTL_STOP 0x02 /* Stop dequeue/enqueue */ +#define QICTL_SOE 0x04 /* Stop on error */ + +/* QI control bits - high word */ +#define QICTL_MBSI 0x01 +#define QICTL_MHWSI 0x02 +#define QICTL_MWSI 0x04 +#define QICTL_MDWSI 0x08 +#define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */ +#define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */ +#define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */ +#define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */ +#define QICTL_MBSO 0x0100 +#define QICTL_MHWSO 0x0200 +#define QICTL_MWSO 0x0400 +#define QICTL_MDWSO 0x0800 +#define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */ +#define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */ +#define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */ +#define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */ +#define QICTL_DMBS 0x010000 +#define QICTL_EPO 0x020000 + +/* QI status bits */ +#define QISTA_PHRDERR 0x01 /* PreHeader Read Error */ +#define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */ +#define QISTA_OFWRERR 0x04 /* Output Frame Read Error */ +#define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */ +#define QISTA_BTSERR 0x10 /* Buffer Undersize */ +#define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */ +#define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */ + +/* deco_sg_table - DECO view of scatter/gather table */ +struct deco_sg_table { + u64 addr; /* Segment Address */ + u32 elen; /* E, F bits + 30-bit length */ + u32 bpid_offset; /* Buffer Pool ID + 16-bit length */ +}; + +/* + * caam_deco - descriptor controller - CHA cluster block + * + * Only accessible when direct DECO access is turned on + * (done in DECORR, via MID programmed in DECOxMID + * + * 5 typical, base + 0x8000/9000/a000/b000 + * Padded out to 0x1000 long + */ +struct caam_deco { + u32 rsvd1; + u32 cls1_mode; /* CxC1MR - Class 1 Mode */ + u32 rsvd2; + u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */ + u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */ + u32 cls1_datasize_lo; + u32 rsvd3; + u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */ + u32 rsvd4[5]; + u32 cha_ctrl; /* CCTLR - CHA control */ + u32 rsvd5; + u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */ + u32 rsvd6; + u32 clr_written; /* CxCWR - Clear-Written */ + u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */ + u32 ccb_status_lo; + u32 rsvd7[3]; + u32 aad_size; /* CxAADSZR - Current AAD Size */ + u32 rsvd8; + u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */ + u32 rsvd9[7]; + u32 pkha_a_size; /* PKASZRx - Size of PKHA A */ + u32 rsvd10; + u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */ + u32 rsvd11; + u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */ + u32 rsvd12; + u32 pkha_e_size; /* PKESZRx - Size of PKHA E */ + u32 rsvd13[24]; + u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */ + u32 rsvd14[48]; + u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */ + u32 rsvd15[121]; + u32 cls2_mode; /* CxC2MR - Class 2 Mode */ + u32 rsvd16; + u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */ + u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */ + u32 cls2_datasize_lo; + u32 rsvd17; + u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */ + u32 rsvd18[56]; + u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */ + u32 rsvd19[46]; + u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */ + u32 rsvd20[84]; + u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */ + u32 inp_infofifo_lo; + u32 rsvd21[2]; + u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */ + u32 rsvd22[2]; + u64 out_datafifo; /* CxOFIFO - Output Data FIFO */ + u32 rsvd23[2]; + u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */ + u32 jr_ctl_lo; + u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */ +#define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF + u32 op_status_hi; /* DxOPSTA - DECO Operation Status */ + u32 op_status_lo; + u32 rsvd24[2]; + u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */ + u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */ + u32 rsvd26[6]; + u64 math[4]; /* DxMTH - Math register */ + u32 rsvd27[8]; + struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */ + u32 rsvd28[16]; + struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */ + u32 rsvd29[48]; + u32 descbuf[64]; /* DxDESB - Descriptor buffer */ + u32 rscvd30[193]; +#define DESC_DBG_DECO_STAT_HOST_ERR 0x00D00000 +#define DESC_DBG_DECO_STAT_VALID 0x80000000 +#define DESC_DBG_DECO_STAT_MASK 0x00F00000 + u32 desc_dbg; /* DxDDR - DECO Debug Register */ + u32 rsvd31[126]; +}; + +#define DECO_JQCR_WHL 0x20000000 +#define DECO_JQCR_FOUR 0x10000000 + +#define JR_BLOCK_NUMBER 1 +#define ASSURE_BLOCK_NUMBER 6 +#define QI_BLOCK_NUMBER 7 +#define DECO_BLOCK_NUMBER 8 +#define PG_SIZE_4K 0x1000 +#define PG_SIZE_64K 0x10000 +#endif /* REGS_H */ diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index bd0017b6c1..64f4326514 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -588,6 +588,7 @@ int mxs_dma_go(int chan) */ static int apbh_dma_probe(struct device_d *dev) { + struct resource *iores; struct apbh_dma *apbh; struct mxs_dma_chan *pchan; enum mxs_dma_id id; @@ -598,9 +599,10 @@ static int apbh_dma_probe(struct device_d *dev) return ret; apbh_dma = apbh = xzalloc(sizeof(*apbh)); - apbh->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(apbh->regs)) - return PTR_ERR(apbh->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + apbh->regs = IOMEM(iores->start); apbh->id = id; diff --git a/drivers/eeprom/at25.c b/drivers/eeprom/at25.c index 3e75b56519..9f054d00b4 100644 --- a/drivers/eeprom/at25.c +++ b/drivers/eeprom/at25.c @@ -356,6 +356,7 @@ static int at25_probe(struct device_d *dev) dev_dbg(dev, "%s probed\n", at25->cdev.name); devfs_create(&at25->cdev); + of_parse_partitions(&at25->cdev, dev->device_node); return 0; fail: diff --git a/drivers/firmware/socfpga.c b/drivers/firmware/socfpga.c index 159644bbfb..a0cd2011cb 100644 --- a/drivers/firmware/socfpga.c +++ b/drivers/firmware/socfpga.c @@ -395,6 +395,7 @@ static int programmed_get(struct param_d *p, void *priv) static int fpgamgr_probe(struct device_d *dev) { + struct resource *iores; struct fpgamgr *mgr; struct firmware_handler *fh; const char *alias = of_alias_get(dev->device_node); @@ -407,17 +408,19 @@ static int fpgamgr_probe(struct device_d *dev) mgr = xzalloc(sizeof(*mgr)); fh = &mgr->fh; - mgr->regs = dev_request_mem_region(dev, 0); - if (!mgr->regs) { - ret = -EBUSY; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto out; } + mgr->regs = IOMEM(iores->start); - mgr->regs_data = dev_request_mem_region(dev, 1); - if (!mgr->regs_data) { - ret = -EBUSY; + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto out; } + mgr->regs_data = IOMEM(iores->start); if (alias) fh->id = xstrdup(alias); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d839d7a426..ab919c95f5 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -87,17 +87,17 @@ config GPIO_PCA953X SMBus I/O expanders, made mostly by NXP or TI. Compatible models include: - 4 bits: pca9536, pca9537 + 4 bits: pca9536, pca9537 - 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554, - pca9556, pca9557, pca9574, tca6408, xra1202 + 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554, + pca9556, pca9557, pca9574, tca6408, xra1202 - 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575, - tca6416 + 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575, + tca6416 - 24 bits: tca6424 + 24 bits: tca6424 - 40 bits: pca9505, pca9698 + 40 bits: pca9505, pca9698 config GPIO_PL061 bool "PrimeCell PL061 GPIO support" diff --git a/drivers/gpio/gpio-ath79.c b/drivers/gpio/gpio-ath79.c index a1e42c417d..d08d743b54 100644 --- a/drivers/gpio/gpio-ath79.c +++ b/drivers/gpio/gpio-ath79.c @@ -107,6 +107,7 @@ static const struct of_device_id ath79_gpio_of_match[] = { static int ath79_gpio_probe(struct device_d *dev) { + struct resource *iores; struct device_node *np = dev->device_node; int err; @@ -125,11 +126,12 @@ static int ath79_gpio_probe(struct device_d *dev) return -EINVAL; } - ath79_gpio_base = dev_request_mem_region(dev, 0); - if (IS_ERR(ath79_gpio_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(ath79_gpio_base); + return PTR_ERR(iores); } + ath79_gpio_base = IOMEM(iores->start); ath79_gpio_chip.dev = dev; ath79_gpio_chip.ngpio = ath79_gpio_count; diff --git a/drivers/gpio/gpio-bcm2835.c b/drivers/gpio/gpio-bcm2835.c index cec15c98b1..1802ab7ccb 100644 --- a/drivers/gpio/gpio-bcm2835.c +++ b/drivers/gpio/gpio-bcm2835.c @@ -112,11 +112,15 @@ static struct gpio_ops bcm2835_gpio_ops = { static int bcm2835_gpio_probe(struct device_d *dev) { + struct resource *iores; struct bcm2835_gpio_chip *bcmgpio; int ret; bcmgpio = xzalloc(sizeof(*bcmgpio)); - bcmgpio->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + bcmgpio->base = IOMEM(iores->start); bcmgpio->chip.ops = &bcm2835_gpio_ops; bcmgpio->chip.base = 0; bcmgpio->chip.ngpio = 54; diff --git a/drivers/gpio/gpio-clps711x.c b/drivers/gpio/gpio-clps711x.c index 43268b6bbf..d71c606690 100644 --- a/drivers/gpio/gpio-clps711x.c +++ b/drivers/gpio/gpio-clps711x.c @@ -15,6 +15,7 @@ static int clps711x_gpio_probe(struct device_d *dev) { + struct resource *iores; int err, id = dev->id; void __iomem *dat, *dir = NULL, *dir_inv = NULL; struct bgpio_chip *bgc; @@ -25,20 +26,23 @@ static int clps711x_gpio_probe(struct device_d *dev) if (id < 0 || id > 4) return -ENODEV; - dat = dev_request_mem_region(dev, 0); - if (IS_ERR(dat)) - return PTR_ERR(dat); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + dat = IOMEM(iores->start); switch (id) { case 3: - dir_inv = dev_request_mem_region(dev, 1); - if (IS_ERR(dir_inv)) - return PTR_ERR(dir_inv); + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + dir_inv = IOMEM(iores->start); break; default: - dir = dev_request_mem_region(dev, 1); - if (IS_ERR(dir)) - return PTR_ERR(dir); + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + dir = IOMEM(iores->start); break; } diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index 61c6e7e68c..7c060a09b1 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -142,6 +142,7 @@ static struct gpio_ops davinci_gpio_ops = { static int davinci_gpio_probe(struct device_d *dev) { + struct resource *iores; void __iomem *gpio_base; int ret; u32 val; @@ -162,11 +163,12 @@ static int davinci_gpio_probe(struct device_d *dev) chips = xzalloc((ngpio / 32 + 1) * sizeof(*chips)); - gpio_base = dev_request_mem_region(dev, 0); - if (IS_ERR(gpio_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(gpio_base); + return PTR_ERR(iores); } + gpio_base = IOMEM(iores->start); for (i = 0, base = 0; base < ngpio; i++, base += 32) { struct davinci_gpio_regs __iomem *regs; diff --git a/drivers/gpio/gpio-digic.c b/drivers/gpio/gpio-digic.c index 468aaa79ab..714e3b4a1d 100644 --- a/drivers/gpio/gpio-digic.c +++ b/drivers/gpio/gpio-digic.c @@ -122,6 +122,7 @@ static struct gpio_ops digic_gpio_ops = { static int digic_gpio_probe(struct device_d *dev) { + struct resource *iores; struct digic_gpio_chip *chip; struct resource *res; resource_size_t rsize; @@ -136,7 +137,10 @@ static int digic_gpio_probe(struct device_d *dev) rsize = resource_size(res); chip->gc.ngpio = rsize / sizeof(int32_t); - chip->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + chip->base = IOMEM(iores->start); chip->gc.ops = &digic_gpio_ops; chip->gc.base = 0; diff --git a/drivers/gpio/gpio-dw.c b/drivers/gpio/gpio-dw.c index 258e43b84e..f145c01232 100644 --- a/drivers/gpio/gpio-dw.c +++ b/drivers/gpio/gpio-dw.c @@ -164,14 +164,16 @@ static int dw_gpio_add_port(struct device_d *dev, struct device_node *node, static int dw_gpio_probe(struct device_d *dev) { + struct resource *iores; struct dw_gpio *gpio; struct device_node *node; gpio = xzalloc(sizeof(*gpio)); - gpio->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(gpio->regs)) - return PTR_ERR(gpio->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + gpio->regs = IOMEM(iores->start); for_each_child_of_node(dev->device_node, node) dw_gpio_add_port(dev, node, gpio); diff --git a/drivers/gpio/gpio-imx.c b/drivers/gpio/gpio-imx.c index 6311db22fe..bfb0119c84 100644 --- a/drivers/gpio/gpio-imx.c +++ b/drivers/gpio/gpio-imx.c @@ -132,6 +132,7 @@ static struct gpio_ops imx_gpio_ops = { static int imx_gpio_probe(struct device_d *dev) { + struct resource *iores; struct imx_gpio_chip *imxgpio; struct imx_gpio_regs *regs; int ret; @@ -141,7 +142,10 @@ static int imx_gpio_probe(struct device_d *dev) return ret; imxgpio = xzalloc(sizeof(*imxgpio)); - imxgpio->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + imxgpio->base = IOMEM(iores->start); imxgpio->chip.ops = &imx_gpio_ops; if (dev->id < 0) { imxgpio->chip.base = of_alias_get_id(dev->device_node, "gpio"); diff --git a/drivers/gpio/gpio-jz4740.c b/drivers/gpio/gpio-jz4740.c index f7e6781dc1..87e0716b06 100644 --- a/drivers/gpio/gpio-jz4740.c +++ b/drivers/gpio/gpio-jz4740.c @@ -90,15 +90,17 @@ static struct gpio_ops jz4740_gpio_ops = { static int jz4740_gpio_probe(struct device_d *dev) { + struct resource *iores; void __iomem *base; struct jz4740_gpio_chip *jz4740_gpio; int ret; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(base); + return PTR_ERR(iores); } + base = IOMEM(iores->start); jz4740_gpio = xzalloc(sizeof(*jz4740_gpio)); jz4740_gpio->base = base; diff --git a/drivers/gpio/gpio-malta-fpga-i2c.c b/drivers/gpio/gpio-malta-fpga-i2c.c index ff77b8c7ef..0188e51af2 100644 --- a/drivers/gpio/gpio-malta-fpga-i2c.c +++ b/drivers/gpio/gpio-malta-fpga-i2c.c @@ -133,15 +133,17 @@ static struct gpio_ops malta_i2c_gpio_ops = { static int malta_i2c_gpio_probe(struct device_d *dev) { + struct resource *iores; void __iomem *gpio_base; struct malta_i2c_gpio *sc; int ret; - gpio_base = dev_request_mem_region(dev, 0); - if (IS_ERR(gpio_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(gpio_base); + return PTR_ERR(iores); } + gpio_base = IOMEM(iores->start); sc = xzalloc(sizeof(*sc)); sc->base = gpio_base; diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 43449df45b..b00766a6aa 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -141,15 +141,17 @@ static struct gpio_ops omap_gpio_ops = { static int omap_gpio_probe(struct device_d *dev) { + struct resource *iores; struct omap_gpio_chip *omapgpio; struct omap_gpio_drvdata *drvdata = NULL; dev_get_drvdata(dev, (const void **)&drvdata); omapgpio = xzalloc(sizeof(*omapgpio)); - omapgpio->base = dev_request_mem_region(dev, 0); - if (IS_ERR(omapgpio->base)) - return PTR_ERR(omapgpio->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + omapgpio->base = IOMEM(iores->start); if (drvdata) omapgpio->base += drvdata->regofs; diff --git a/drivers/gpio/gpio-orion.c b/drivers/gpio/gpio-orion.c index 3deeac126f..63ef966edf 100644 --- a/drivers/gpio/gpio-orion.c +++ b/drivers/gpio/gpio-orion.c @@ -89,6 +89,7 @@ static struct gpio_ops orion_gpio_ops = { static int orion_gpio_probe(struct device_d *dev) { + struct resource *iores; struct orion_gpio_chip *gpio; dev->id = of_alias_get_id(dev->device_node, "gpio"); @@ -96,11 +97,12 @@ static int orion_gpio_probe(struct device_d *dev) return dev->id; gpio = xzalloc(sizeof(*gpio)); - gpio->regs = dev_request_mem_region(dev, 0); - if (!gpio->regs) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { free(gpio); - return -EINVAL; + return PTR_ERR(iores); } + gpio->regs = IOMEM(iores->start); gpio->chip.dev = dev; gpio->chip.ops = &orion_gpio_ops; gpio->chip.base = dev->id * 32; diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c index e2cc3f4a8c..56808b57e4 100644 --- a/drivers/gpio/gpio-tegra.c +++ b/drivers/gpio/gpio-tegra.c @@ -140,6 +140,7 @@ static struct gpio_chip tegra_gpio_chip = { static int tegra_gpio_probe(struct device_d *dev) { + struct resource *iores; int i, j, ret; ret = dev_get_drvdata(dev, (const void **)&config); @@ -148,11 +149,12 @@ static int tegra_gpio_probe(struct device_d *dev) return ret; } - gpio_base = dev_request_mem_region(dev, 0); - if (IS_ERR(gpio_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(gpio_base); + return PTR_ERR(iores); } + gpio_base = IOMEM(iores->start); for (i = 0; i < config->bank_count; i++) { for (j = 0; j < 4; j++) { diff --git a/drivers/hab/habv3.c b/drivers/hab/habv3.c index 70f31a3c4d..82ae245f8a 100644 --- a/drivers/hab/habv3.c +++ b/drivers/hab/habv3.c @@ -20,35 +20,39 @@ struct hab_status { }; static struct hab_status hab_status[] = { - { 0x8d, "data specified is out of bounds" }, - { 0x55, "error during assert verification" }, - { 0x36, "hash verification failed" }, - { 0x33, "certificate parsing failed or the certificate contained an unsupported key" }, - { 0x35, "signature verification failed" }, - { 0x4B, "CSF command sequence contains unsupported command identifier" }, - { 0x4e, "absence of expected CSF header" }, - { 0x4d, "CSF length is unsupported" }, - { 0x2e, "CSF TYPE does not match processor TYPE" }, - { 0x2d, "CSF UID does not match either processor UID or generic UID" }, - { 0x3a, "CSF customer/product code does not match processor customer/product code" }, - { 0x87, "key indexis either unsupported, or an attempt is made to overwrite the SRK from a CSF command" }, + { 0x12, "Download code can't be executed, please check the HAB type" }, { 0x17, "SCC unexpectedly not in secure state" }, - { 0x1e, "secureRAM secret key invalid" }, - { 0x1d, "secureRAM initialization failure" }, { 0x1b, "secureRAM self test failure" }, - { 0x2b, "secureRAM internal failure" }, + { 0x1d, "secureRAM initialization failure" }, + { 0x1e, "secureRAM secret key invalid" }, { 0x27, "secureRAM secrect key unexpectedly in use" }, - { 0x8b, "an attempt is made to read a key from the list of subordinate public keys at a location " - "where no key is installed" }, - { 0x8e, "algorithm type is either invalid or ortherwise unsupported" }, - { 0x66, "write operation to register failed" }, + { 0x2b, "secureRAM internal failure" }, + { 0x2d, "CSF UID does not match either processor UID or generic UID" }, + { 0x2e, "CSF TYPE does not match processor TYPE" }, + { 0x33, "certificate parsing failed or the certificate contained an unsupported key" }, + { 0x35, "signature verification failed" }, + { 0x36, "hash verification failed" }, + { 0x39, "Failure not matching any other description" }, + { 0x3a, "CSF customer/product code does not match processor customer/product code" }, + { 0x47, "installation or comparison of SRKs failed" }, + { 0x4b, "CSF command sequence contains unsupported command identifier" }, + { 0x4d, "CSF length is unsupported" }, + { 0x4e, "absence of expected CSF header" }, + { 0x55, "error during assert verification" }, + { 0x56, "Download code can't be executed, please check the HAB type" }, { 0x63, "DCD invalid" }, - { 0x6f, "RAM application pointer is NULL or ERASED_FLASH" }, + { 0x66, "write operation to register failed" }, + { 0x67, "INT_BOOT fuse is blown but BOOT pins are set for external boot" }, { 0x69, "CSF missing when HAB TYPE is not HAB-disabled" }, { 0x6a, "NANDFC boot buffer load failed" }, { 0x6c, "Exception has occured" }, - { 0x67, "INT_BOOT fuse is blown but BOOT pins are set for external boot" }, + { 0x6f, "RAM application pointer is NULL or ERASED_FLASH" }, + { 0x87, "key indexis either unsupported, or an attempt is made to overwrite the SRK from a CSF command" }, { 0x88, "Successful download completion" }, + { 0x8b, "an attempt is made to read a key from the list of subordinate public keys at a location " + "where no key is installed" }, + { 0x8d, "data specified is out of bounds" }, + { 0x8e, "algorithm type is either invalid or ortherwise unsupported" }, }; int imx_habv3_get_status(uint32_t status) @@ -75,4 +79,4 @@ int imx_habv3_get_status(uint32_t status) int imx25_hab_get_status(void) { return imx_habv3_get_status(readl(IOMEM(0x780018d4))); -}
\ No newline at end of file +} diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c index 622c56d97b..76bb51bf30 100644 --- a/drivers/i2c/busses/i2c-at91.c +++ b/drivers/i2c/busses/i2c-at91.c @@ -410,6 +410,7 @@ static struct of_device_id at91_twi_dt_ids[] = { static int at91_twi_probe(struct device_d *dev) { + struct resource *iores; struct at91_twi_dev *i2c_at91; struct at91_twi_pdata *i2c_data; int rc = 0; @@ -425,10 +426,13 @@ static int at91_twi_probe(struct device_d *dev) i2c_at91->pdata = i2c_data; - i2c_at91->base = dev_request_mem_region(dev, 0); - if (!i2c_at91->base) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + i2c_at91->base = IOMEM(iores->start); + if (IS_ERR(i2c_at91->base)) { dev_err(dev, "could not get memory region\n"); - rc = -ENODEV; + rc = PTR_ERR(i2c_at91->base); goto out_free; } diff --git a/drivers/i2c/busses/i2c-designware.c b/drivers/i2c/busses/i2c-designware.c index a51439f2d5..0b022afd30 100644 --- a/drivers/i2c/busses/i2c-designware.c +++ b/drivers/i2c/busses/i2c-designware.c @@ -472,6 +472,7 @@ static int i2c_dw_xfer(struct i2c_adapter *adapter, static int i2c_dw_probe(struct device_d *pdev) { + struct resource *iores; struct dw_i2c_dev *dw; struct i2c_platform_data *pdata; int ret, bitrate; @@ -494,11 +495,12 @@ static int i2c_dw_probe(struct device_d *pdev) dw->adapter.dev.parent = pdev; dw->adapter.dev.device_node = pdev->device_node; - dw->base = dev_request_mem_region(pdev, 0); - if (IS_ERR(dw->base)) { - ret = PTR_ERR(dw->base); + iores = dev_request_mem_resource(pdev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto fail; } + dw->base = IOMEM(iores->start); ic_comp_type_value = readl(dw->base + DW_IC_COMP_TYPE); if (ic_comp_type_value != DW_IC_COMP_TYPE_VALUE) { diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index affc277164..e407896394 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c @@ -584,6 +584,7 @@ static void i2c_fsl_init_recovery(struct fsl_i2c_struct *i2c_fsl, struct device_ static int __init i2c_fsl_probe(struct device_d *pdev) { + struct resource *iores; struct fsl_i2c_struct *i2c_fsl; struct i2c_platform_data *pdata; int ret; @@ -604,11 +605,12 @@ static int __init i2c_fsl_probe(struct device_d *pdev) i2c_fsl->adapter.nr = pdev->id; i2c_fsl->adapter.dev.parent = pdev; i2c_fsl->adapter.dev.device_node = pdev->device_node; - i2c_fsl->base = dev_request_mem_region(pdev, 0); - if (IS_ERR(i2c_fsl->base)) { - ret = PTR_ERR(i2c_fsl->base); + iores = dev_request_mem_resource(pdev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto fail; } + i2c_fsl->base = IOMEM(iores->start); i2c_fsl_init_recovery(i2c_fsl, pdev); diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c index 0c38e64145..9b9e6c953f 100644 --- a/drivers/i2c/busses/i2c-mv64xxx.c +++ b/drivers/i2c/busses/i2c-mv64xxx.c @@ -595,6 +595,7 @@ out: static int mv64xxx_i2c_probe(struct device_d *pd) { + struct resource *iores; struct mv64xxx_i2c_data *drv_data; int rc; @@ -603,9 +604,10 @@ mv64xxx_i2c_probe(struct device_d *pd) drv_data = xzalloc(sizeof(*drv_data)); - drv_data->reg_base = dev_request_mem_region(pd, 0); - if (IS_ERR(drv_data->reg_base)) - return PTR_ERR(drv_data->reg_base); + iores = dev_request_mem_resource(pd, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + drv_data->reg_base = IOMEM(iores->start); drv_data->clk = clk_get(pd, NULL); if (IS_ERR(drv_data->clk)) diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 48c55daeda..bdb34ca1b4 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -1070,6 +1070,7 @@ static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = { static int __init i2c_omap_probe(struct device_d *pdev) { + struct resource *iores; struct omap_i2c_struct *i2c_omap; struct omap_i2c_driver_data *i2c_data; int r; @@ -1109,9 +1110,10 @@ i2c_omap_probe(struct device_d *pdev) speed = 100; /* Default speed */ i2c_omap->speed = speed; - i2c_omap->base = dev_request_mem_region(pdev, 0); - if (IS_ERR(i2c_omap->base)) - return PTR_ERR(i2c_omap->base); + iores = dev_request_mem_resource(pdev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + i2c_omap->base = IOMEM(iores->start); /* * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2. diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index f6a4b227f4..d56c0def65 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -605,16 +605,18 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { static int tegra_i2c_probe(struct device_d *dev) { + struct resource *iores; struct tegra_i2c_dev *i2c_dev; struct clk *div_clk, *fast_clk; void __iomem *base; int ret = 0; - base = dev_request_mem_region(dev, 0); - if (!base) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get iomem region\n"); - return -ENODEV; + return PTR_ERR(iores); } + base = IOMEM(iores->start); div_clk = clk_get(dev, "div-clk"); if (IS_ERR(div_clk)) { diff --git a/drivers/i2c/busses/i2c-versatile.c b/drivers/i2c/busses/i2c-versatile.c index bfabc78312..6a00c2a2eb 100644 --- a/drivers/i2c/busses/i2c-versatile.c +++ b/drivers/i2c/busses/i2c-versatile.c @@ -66,6 +66,7 @@ static struct i2c_algo_bit_data i2c_versatile_algo = { static int i2c_versatile_probe(struct device_d *dev) { + struct resource *iores; struct i2c_versatile *i2c; int ret; @@ -75,11 +76,12 @@ static int i2c_versatile_probe(struct device_d *dev) goto err_release; } - i2c->base = dev_request_mem_region(dev, 0); - if (IS_ERR(i2c->base)) { - ret = PTR_ERR(i2c->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto err_free; } + i2c->base = IOMEM(iores->start); writel(SCL | SDA, i2c->base + I2C_CONTROLS); diff --git a/drivers/input/imx_keypad.c b/drivers/input/imx_keypad.c index 000e17626b..44ff9b7856 100644 --- a/drivers/input/imx_keypad.c +++ b/drivers/input/imx_keypad.c @@ -364,6 +364,7 @@ static void imx_keypad_inhibit(struct imx_keypad *keypad) static int __init imx_keypad_probe(struct device_d *dev) { + struct resource *iores; struct imx_keypad *keypad; const struct matrix_keymap_data *keymap_data = dev->platform_data; int i, ret, row, col; @@ -371,9 +372,10 @@ static int __init imx_keypad_probe(struct device_d *dev) keypad = xzalloc(sizeof(struct imx_keypad)); keypad->dev = dev; - keypad->mmio_base = dev_request_mem_region(dev, 0); - if (IS_ERR(keypad->mmio_base)) - return PTR_ERR(keypad->mmio_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + keypad->mmio_base = IOMEM(iores->start); ret = matrix_keypad_build_keymap(dev, keymap_data, MATRIX_ROW_SHIFT, keypad->keycodes); diff --git a/drivers/input/usb_kbd.c b/drivers/input/usb_kbd.c index 74bc11f3bb..2acc95d9fd 100644 --- a/drivers/input/usb_kbd.c +++ b/drivers/input/usb_kbd.c @@ -46,13 +46,10 @@ struct usb_kbd_pdata; struct usb_kbd_pdata { - uint64_t last_report; uint8_t *new; uint8_t old[USB_KBD_BOOT_REPORT_SIZE]; - uint8_t flags; - struct poller_struct poller; + struct poller_async poller; struct usb_device *usbdev; - int lock; unsigned long intpipe; int intpktsize; int intinterval; @@ -94,23 +91,17 @@ static const unsigned char usb_kbd_keycode[256] = { 150,158,159,128,136,177,178,176,142,152,173,140 }; -static void usb_kbd_poll(struct poller_struct *poller) +static void usb_kbd_poll(void *arg) { - struct usb_kbd_pdata *data = container_of(poller, - struct usb_kbd_pdata, poller); + struct usb_kbd_pdata *data = arg; struct usb_device *usbdev = data->usbdev; int ret, i; - if (data->lock) - return; - - data->lock = 1; - ret = data->do_poll(data); if (ret == -EAGAIN) goto exit; if (ret < 0) { - /* exit and lock forever */ + /* exit with noreturn */ dev_err(&usbdev->dev, "usb_submit_int_msg() failed. Keyboard disconnect?\n"); return; @@ -125,7 +116,6 @@ static void usb_kbd_poll(struct poller_struct *poller) input_report_key_event(&data->input, usb_kbd_keycode[i + 224], (data->new[0] >> i) & 1); for (i = 2; i < 8; i++) { - if (data->old[i] > 3 && memscan(data->new + 2, data->old[i], 6) == data->new + 8) { if (usb_kbd_keycode[data->old[i]]) input_report_key_event(&data->input, usb_kbd_keycode[data->old[i]], 0); @@ -145,10 +135,10 @@ static void usb_kbd_poll(struct poller_struct *poller) } } - memcpy(data->old, data->new, 8); + memcpy(data->old, data->new, USB_KBD_BOOT_REPORT_SIZE); exit: - data->lock = 0; + poller_call_async(&data->poller, data->intinterval * MSECOND, usb_kbd_poll, data); } static int usb_kbd_probe(struct usb_device *usbdev, @@ -173,7 +163,6 @@ static int usb_kbd_probe(struct usb_device *usbdev, data->new = dma_alloc(USB_KBD_BOOT_REPORT_SIZE); data->usbdev = usbdev; - data->last_report = get_time_ns(); data->ep = &iface->ep_desc[0]; data->intpipe = usb_rcvintpipe(usbdev, data->ep->bEndpointAddress); @@ -199,18 +188,28 @@ static int usb_kbd_probe(struct usb_device *usbdev, } else dev_dbg(&usbdev->dev, "poll keyboard via int ep\n"); - input_device_register(&data->input); + ret = input_device_register(&data->input); + if (ret) { + dev_err(&usbdev->dev, "can't register input\n"); + return ret; + } + + ret = poller_async_register(&data->poller); + if (ret) { + dev_err(&usbdev->dev, "can't setup poller\n"); + return ret; + } - data->poller.func = usb_kbd_poll; + poller_call_async(&data->poller, data->intinterval * MSECOND, usb_kbd_poll, data); - return poller_register(&data->poller); + return 0; } static void usb_kbd_disconnect(struct usb_device *usbdev) { struct usb_kbd_pdata *data = usbdev->drv_data; - poller_unregister(&data->poller); + poller_async_unregister(&data->poller); input_device_unregister(&data->input); dma_free(data->new); free(data); diff --git a/drivers/mci/atmel_mci.c b/drivers/mci/atmel_mci.c index 10e769ea13..2a0ddb052b 100644 --- a/drivers/mci/atmel_mci.c +++ b/drivers/mci/atmel_mci.c @@ -533,6 +533,7 @@ static void atmci_get_cap(struct atmel_mci *host) static int atmci_probe(struct device_d *hw_dev) { + struct resource *iores; struct atmel_mci *host; struct atmel_mci_platform_data *pd = hw_dev->platform_data; int ret; @@ -572,9 +573,10 @@ static int atmci_probe(struct device_d *hw_dev) host->mci.host_caps |= MMC_CAP_8_BIT_DATA; host->slot_b = pd->slot_b; - host->regs = dev_request_mem_region(hw_dev, 0); - if (IS_ERR(host->regs)) - return PTR_ERR(host->regs); + iores = dev_request_mem_resource(hw_dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->regs = IOMEM(iores->start); host->hw_dev = hw_dev; hw_dev->priv = host; host->clk = clk_get(hw_dev, "mci_clk"); diff --git a/drivers/mci/dw_mmc.c b/drivers/mci/dw_mmc.c index cbd3f00646..0e004abe31 100644 --- a/drivers/mci/dw_mmc.c +++ b/drivers/mci/dw_mmc.c @@ -675,6 +675,7 @@ static int dw_mmc_detect(struct device_d *dev) static int dw_mmc_probe(struct device_d *dev) { + struct resource *iores; struct dwmci_host *host; struct dw_mmc_platform_data *pdata = dev->platform_data; @@ -692,9 +693,10 @@ static int dw_mmc_probe(struct device_d *dev) clk_enable(host->clk_ciu); host->dev = dev; - host->ioaddr = dev_request_mem_region(dev, 0); - if (IS_ERR(host->ioaddr)) - return PTR_ERR(host->ioaddr); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->ioaddr = IOMEM(iores->start); host->idmac = dma_alloc_coherent(sizeof(*host->idmac) * DW_MMC_NUM_IDMACS, DMA_ADDRESS_BROKEN); diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c index 6caf165616..282887ba78 100644 --- a/drivers/mci/imx-esdhc.c +++ b/drivers/mci/imx-esdhc.c @@ -545,6 +545,7 @@ static int fsl_esdhc_detect(struct device_d *dev) static int fsl_esdhc_probe(struct device_d *dev) { + struct resource *iores; struct fsl_esdhc_host *host; struct mci_host *mci; u32 caps; @@ -560,9 +561,10 @@ static int fsl_esdhc_probe(struct device_d *dev) return PTR_ERR(host->clk); host->dev = dev; - host->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(host->regs)) - return PTR_ERR(host->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->regs = IOMEM(iores->start); /* First reset the eSDHC controller */ ret = esdhc_reset(host); diff --git a/drivers/mci/imx.c b/drivers/mci/imx.c index 9c8c1b1e27..2788fb9d9d 100644 --- a/drivers/mci/imx.c +++ b/drivers/mci/imx.c @@ -492,6 +492,7 @@ static int mxcmci_init(struct mci_host *mci, struct device_d *dev) static int mxcmci_probe(struct device_d *dev) { + struct resource *iores; struct mxcmci_host *host; unsigned long rate; @@ -507,9 +508,10 @@ static int mxcmci_probe(struct device_d *dev) host->mci.host_caps = MMC_CAP_4_BIT_DATA; host->mci.hw_dev = dev; - host->base = dev_request_mem_region(dev, 0); - if (IS_ERR(host->base)) - return PTR_ERR(host->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->base = IOMEM(iores->start); host->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; diff --git a/drivers/mci/mci-bcm2835.c b/drivers/mci/mci-bcm2835.c index 59c667f5c9..c7a8cf972a 100644 --- a/drivers/mci/mci-bcm2835.c +++ b/drivers/mci/mci-bcm2835.c @@ -480,6 +480,7 @@ static int bcm2835_mci_detect(struct device_d *dev) static int bcm2835_mci_probe(struct device_d *hw_dev) { + struct resource *iores; struct bcm2835_mci_host *host; static struct clk *clk; int ret; @@ -505,11 +506,12 @@ static int bcm2835_mci_probe(struct device_d *hw_dev) host->mci.hw_dev = hw_dev; host->hw_dev = hw_dev; host->max_clock = clk_get_rate(clk); - host->regs = dev_request_mem_region(hw_dev, 0); - if (IS_ERR(host->regs)) { + iores = dev_request_mem_resource(hw_dev, 0); + if (IS_ERR(iores)) { dev_err(host->hw_dev, "Failed request mem region, aborting...\n"); - return PTR_ERR(host->regs); + return PTR_ERR(iores); } + host->regs = IOMEM(iores->start); host->mci.host_caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; diff --git a/drivers/mci/mxs.c b/drivers/mci/mxs.c index b36fb13254..2355651022 100644 --- a/drivers/mci/mxs.c +++ b/drivers/mci/mxs.c @@ -544,6 +544,7 @@ static void mxs_mci_info(struct device_d *hw_dev) static int mxs_mci_probe(struct device_d *hw_dev) { + struct resource *iores; struct mxs_mci_platform_data *pd = hw_dev->platform_data; struct mxs_mci_host *mxs_mci; struct mci_host *host; @@ -557,9 +558,10 @@ static int mxs_mci_probe(struct device_d *hw_dev) host->send_cmd = mxs_mci_request; host->set_ios = mxs_mci_set_ios; host->init = mxs_mci_initialize; - mxs_mci->regs = dev_request_mem_region(hw_dev, 0); - if (IS_ERR(mxs_mci->regs)) - return PTR_ERR(mxs_mci->regs); + iores = dev_request_mem_resource(hw_dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mxs_mci->regs = IOMEM(iores->start); /* feed forward the platform specific values */ if (pd) { diff --git a/drivers/mci/omap_hsmmc.c b/drivers/mci/omap_hsmmc.c index 752787aa43..180afb16c9 100644 --- a/drivers/mci/omap_hsmmc.c +++ b/drivers/mci/omap_hsmmc.c @@ -584,6 +584,7 @@ static int omap_mmc_detect(struct device_d *dev) static int omap_mmc_probe(struct device_d *dev) { + struct resource *iores; struct omap_hsmmc *hsmmc; struct omap_hsmmc_platform_data *pdata; struct omap_mmc_driver_data *drvdata; @@ -604,9 +605,10 @@ static int omap_mmc_probe(struct device_d *dev) MMC_CAP_MMC_HIGHSPEED | MMC_CAP_8_BIT_DATA; hsmmc->mci.hw_dev = dev; - hsmmc->iobase = dev_request_mem_region(dev, 0); - if (IS_ERR(hsmmc->iobase)) - return PTR_ERR(hsmmc->iobase); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + hsmmc->iobase = IOMEM(iores->start); hsmmc->base = hsmmc->iobase + reg_ofs; hsmmc->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; diff --git a/drivers/mci/pxamci.c b/drivers/mci/pxamci.c index 6b14aba509..1a33661d0f 100644 --- a/drivers/mci/pxamci.c +++ b/drivers/mci/pxamci.c @@ -334,14 +334,16 @@ static int pxamci_init(struct mci_host *mci, struct device_d *dev) static int pxamci_probe(struct device_d *dev) { + struct resource *iores; struct pxamci_host *host; int gpio_power = -1; clk_enable(); host = xzalloc(sizeof(*host)); - host->base = dev_request_mem_region(dev, 0); - if (IS_ERR(host->base)) - return PTR_ERR(host->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->base = IOMEM(iores->start); host->mci.init = pxamci_init; host->mci.send_cmd = pxamci_request; diff --git a/drivers/mci/s3c.c b/drivers/mci/s3c.c index 3afd61e491..86a83b63fa 100644 --- a/drivers/mci/s3c.c +++ b/drivers/mci/s3c.c @@ -723,6 +723,7 @@ static void s3c_info(struct device_d *hw_dev) static int s3c_mci_probe(struct device_d *hw_dev) { + struct resource *iores; struct s3c_mci_host *s3c_host; struct s3c_mci_platform_data *pd = hw_dev->platform_data; @@ -741,9 +742,10 @@ static int s3c_mci_probe(struct device_d *hw_dev) } hw_dev->priv = s3c_host; - s3c_host->base = dev_request_mem_region(hw_dev, 0); - if (IS_ERR(s3c_host->base)) - return PTR_ERR(s3c_host->base); + iores = dev_request_mem_resource(hw_dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + s3c_host->base = IOMEM(iores->start); s3c_host->host.hw_dev = hw_dev; diff --git a/drivers/mci/tegra-sdmmc.c b/drivers/mci/tegra-sdmmc.c index 14c230483f..e465d891a2 100644 --- a/drivers/mci/tegra-sdmmc.c +++ b/drivers/mci/tegra-sdmmc.c @@ -422,6 +422,7 @@ static void tegra_sdmmc_parse_dt(struct tegra_sdmmc_host *host) static int tegra_sdmmc_probe(struct device_d *dev) { + struct resource *iores; struct tegra_sdmmc_host *host; struct mci_host *mci; int ret; @@ -437,11 +438,12 @@ static int tegra_sdmmc_probe(struct device_d *dev) if (IS_ERR(host->reset)) return PTR_ERR(host->reset); - host->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(host->regs)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get iomem region\n"); - return PTR_ERR(host->regs); + return PTR_ERR(iores); } + host->regs = IOMEM(iores->start); mci->hw_dev = dev; mci->f_max = 48000000; diff --git a/drivers/misc/sram.c b/drivers/misc/sram.c index 9769325338..58b574157a 100644 --- a/drivers/misc/sram.c +++ b/drivers/misc/sram.c @@ -34,14 +34,16 @@ static struct file_operations memops = { static int sram_probe(struct device_d *dev) { + struct resource *iores; struct sram *sram; struct resource *res; void __iomem *base; int ret; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); sram = xzalloc(sizeof(*sram)); diff --git a/drivers/mtd/core.c b/drivers/mtd/core.c index 62307db709..161c6ad874 100644 --- a/drivers/mtd/core.c +++ b/drivers/mtd/core.c @@ -67,14 +67,13 @@ int mtd_all_ff(const void *buf, unsigned int len) } static ssize_t mtd_op_read(struct cdev *cdev, void* buf, size_t count, - loff_t _offset, ulong flags) + loff_t offset, ulong flags) { struct mtd_info *mtd = cdev->priv; size_t retlen; int ret; - unsigned long offset = _offset; - dev_dbg(cdev->dev, "read ofs: 0x%08lx count: 0x%08zx\n", + dev_dbg(cdev->dev, "read ofs: 0x%08llx count: 0x%08zx\n", offset, count); ret = mtd_read(mtd, offset, count, &retlen, buf); @@ -115,13 +114,13 @@ static struct mtd_erase_region_info *mtd_find_erase_region(struct mtd_info *mtd, return NULL; } -static int mtd_erase_align(struct mtd_info *mtd, size_t *count, loff_t *offset) +static int mtd_erase_align(struct mtd_info *mtd, loff_t *count, loff_t *offset) { struct mtd_erase_region_info *e; loff_t ofs; if (mtd->numeraseregions == 0) { - ofs = *offset & ~(mtd->erasesize - 1); + ofs = *offset & ~(loff_t)(mtd->erasesize - 1); *count += (*offset - ofs); *count = ALIGN(*count, mtd->erasesize); *offset = ofs; @@ -145,11 +144,11 @@ static int mtd_erase_align(struct mtd_info *mtd, size_t *count, loff_t *offset) return 0; } -static int mtd_op_erase(struct cdev *cdev, size_t count, loff_t offset) +static int mtd_op_erase(struct cdev *cdev, loff_t count, loff_t offset) { struct mtd_info *mtd = cdev->priv; struct erase_info erase; - uint32_t addr; + loff_t addr; int ret; ret = mtd_erase_align(mtd, &count, &offset); @@ -169,7 +168,7 @@ static int mtd_op_erase(struct cdev *cdev, size_t count, loff_t offset) erase.len = mtd->erasesize; while (count > 0) { - dev_dbg(cdev->dev, "erase %d %d\n", addr, erase.len); + dev_dbg(cdev->dev, "erase 0x%08llx len: 0x%08llx\n", addr, erase.len); if (mtd->allow_erasebad || (mtd->master && mtd->master->allow_erasebad)) ret = 0; @@ -179,7 +178,7 @@ static int mtd_op_erase(struct cdev *cdev, size_t count, loff_t offset) erase.addr = addr; if (ret > 0) { - printf("Skipping bad block at 0x%08x\n", addr); + printf("Skipping bad block at 0x%08llx\n", addr); } else { ret = mtd_erase(mtd, &erase); if (ret) @@ -310,6 +309,9 @@ int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs) { int ret; + if (ofs < 0 || ofs >= mtd->size) + return -EINVAL; + if (mtd->block_markbad) ret = mtd->block_markbad(mtd, ofs); else @@ -324,6 +326,11 @@ int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, int ret_code; *retlen = 0; + if (from < 0 || from >= mtd->size || len > mtd->size - from) + return -EINVAL; + if (!len) + return 0; + /* * In the absence of an error, drivers return a non-negative integer * representing the maximum number of bitflips that were corrected on @@ -342,11 +349,28 @@ int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, { *retlen = 0; + if (to < 0 || to >= mtd->size || len > mtd->size - to) + return -EINVAL; + if (!mtd->write || !(mtd->flags & MTD_WRITEABLE)) + return -EROFS; + if (!len) + return 0; + return mtd->write(mtd, to, len, retlen, buf); } int mtd_erase(struct mtd_info *mtd, struct erase_info *instr) { + if (instr->addr >= mtd->size || instr->len > mtd->size - instr->addr) + return -EINVAL; + if (!(mtd->flags & MTD_WRITEABLE)) + return -EROFS; + instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN; + if (!instr->len) { + instr->state = MTD_ERASE_DONE; + mtd_erase_callback(instr); + return 0; + } return mtd->erase(mtd, instr); } diff --git a/drivers/mtd/devices/docg3.c b/drivers/mtd/devices/docg3.c index 9ae606b3d8..3ff7ddfb09 100644 --- a/drivers/mtd/devices/docg3.c +++ b/drivers/mtd/devices/docg3.c @@ -1146,11 +1146,15 @@ nomem1: static int __init docg3_probe(struct device_d *dev) { + struct resource *iores; struct mtd_info *mtd; void __iomem *base; int ret, floor, found = 0; - base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); ret = -ENOMEM; docg3_bch = init_bch(DOC_ECC_BCH_M, DOC_ECC_BCH_T, diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index d627690080..656a7f5ef0 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -298,6 +298,8 @@ static __maybe_unused struct of_device_id m25p80_dt_ids[] = { { .compatible = "m25p80", }, { + .compatible = "jedec,spi-nor", + }, { /* sentinel */ } }; diff --git a/drivers/mtd/devices/mtdram.c b/drivers/mtd/devices/mtdram.c index d1eaafdab5..acaf002258 100644 --- a/drivers/mtd/devices/mtdram.c +++ b/drivers/mtd/devices/mtdram.c @@ -49,6 +49,7 @@ static int ram_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retle static int mtdram_probe(struct device_d *dev) { + struct resource *iores; void __iomem *base; int device_id; struct mtd_info *mtd; @@ -70,11 +71,12 @@ static int mtdram_probe(struct device_d *dev) mtd->name = "mtdram"; } - base = dev_request_mem_region(dev, 0); - if (!base) { - ret = -EBUSY; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto nobase; } + base = IOMEM(iores->start); res = dev_get_resource(dev, IORESOURCE_MEM, 0); size = (unsigned long) resource_size(res); diff --git a/drivers/mtd/mtdoob.c b/drivers/mtd/mtdoob.c index 6160ddba08..4dcf2f5915 100644 --- a/drivers/mtd/mtdoob.c +++ b/drivers/mtd/mtdoob.c @@ -79,7 +79,7 @@ static int add_mtdoob_device(struct mtd_info *mtd, const char *devname, void **p mtdoob = xzalloc(sizeof(*mtdoob)); mtdoob->cdev.ops = &mtd_ops_oob; mtdoob->cdev.size = mtd_div_by_wb(mtd->size, mtd) * mtd->oobsize; - mtdoob->cdev.name = asprintf("%s_oob%d", devname, mtd->class_dev.id); + mtdoob->cdev.name = asprintf("%s.oob", mtd->cdev.name); mtdoob->cdev.priv = mtdoob; mtdoob->cdev.dev = &mtd->class_dev; mtdoob->mtd = mtd; diff --git a/drivers/mtd/mtdraw.c b/drivers/mtd/mtdraw.c index ae4bec2a4c..4d6ac72bd9 100644 --- a/drivers/mtd/mtdraw.c +++ b/drivers/mtd/mtdraw.c @@ -83,6 +83,20 @@ static struct mtd_info *to_mtd(struct cdev *cdev) return mtdraw->mtd; } +static unsigned int mtdraw_offset_to_block(struct mtd_info *mtd, loff_t offset) +{ + u64 ofs64 = offset; + + do_div(ofs64, mtd->writesize + mtd->oobsize); + + return ofs64; +} + +static loff_t mtdraw_raw_to_mtd_offset(struct mtd_info *mtd, loff_t offset) +{ + return (loff_t)mtdraw_offset_to_block(mtd, offset) * mtd->writesize; +} + static ssize_t mtdraw_read_unaligned(struct mtd_info *mtd, void *dst, size_t count, int skip, ulong offset) { @@ -117,22 +131,21 @@ err: } static ssize_t mtdraw_read(struct cdev *cdev, void *buf, size_t count, - loff_t _offset, ulong flags) + loff_t offset, ulong flags) { struct mtd_info *mtd = to_mtd(cdev); ssize_t retlen = 0, ret = 1, toread; - ulong numpage; + ulong numblock; int skip; - unsigned long offset = _offset; - numpage = offset / (mtd->writesize + mtd->oobsize); - skip = offset % (mtd->writesize + mtd->oobsize); + numblock = mtdraw_offset_to_block(mtd, offset); + skip = offset - numblock * (mtd->writesize + mtd->oobsize); while (ret > 0 && count > 0) { toread = min_t(int, count, mtd->writesize + mtd->oobsize - skip); ret = mtdraw_read_unaligned(mtd, buf, toread, - skip, numpage++ * mtd->writesize); + skip, numblock++ * mtd->writesize); buf += ret; skip = 0; count -= ret; @@ -171,20 +184,21 @@ static void mtdraw_fillbuf(struct mtdraw *mtdraw, const void *src, int nbbytes) } static ssize_t mtdraw_write(struct cdev *cdev, const void *buf, size_t count, - loff_t _offset, ulong flags) + loff_t offset, ulong flags) { struct mtdraw *mtdraw = to_mtdraw(cdev); struct mtd_info *mtd = to_mtd(cdev); int bsz = mtd->writesize + mtd->oobsize; - ulong numpage; + ulong numblock; size_t retlen = 0, tofill; - unsigned long offset = _offset; int ret = 0; + numblock = mtdraw_offset_to_block(mtd, offset); + if (mtdraw->write_fill && mtdraw->write_ofs + mtdraw->write_fill != offset) return -EINVAL; - if (mtdraw->write_fill == 0 && offset % bsz) + if (mtdraw->write_fill == 0 && offset - numblock * mtd->writesize != 0) return -EINVAL; if (mtdraw->write_fill) { @@ -196,16 +210,16 @@ static ssize_t mtdraw_write(struct cdev *cdev, const void *buf, size_t count, } if (mtdraw->write_fill == bsz) { - numpage = mtdraw->write_ofs / (mtd->writesize + mtd->oobsize); + numblock = mtdraw_offset_to_block(mtd, mtdraw->write_ofs); ret = mtdraw_blkwrite(mtd, mtdraw->writebuf, - mtd->writesize * numpage); + mtd->writesize * numblock); mtdraw->write_fill = 0; } - numpage = offset / (mtd->writesize + mtd->oobsize); + numblock = mtdraw_offset_to_block(mtd, offset); while (ret >= 0 && count >= bsz) { ret = mtdraw_blkwrite(mtd, buf + retlen, - mtd->writesize * numpage++); + mtd->writesize * numblock++); count -= ret; retlen += ret; offset += ret; @@ -225,15 +239,14 @@ static ssize_t mtdraw_write(struct cdev *cdev, const void *buf, size_t count, } } -static int mtdraw_erase(struct cdev *cdev, size_t count, loff_t _offset) +static int mtdraw_erase(struct cdev *cdev, loff_t count, loff_t offset) { struct mtd_info *mtd = to_mtd(cdev); struct erase_info erase; - unsigned long offset = _offset; int ret; - offset = offset / (mtd->writesize + mtd->oobsize) * mtd->writesize; - count = count / (mtd->writesize + mtd->oobsize) * mtd->writesize; + offset = mtdraw_raw_to_mtd_offset(mtd, offset); + count = mtdraw_raw_to_mtd_offset(mtd, count); memset(&erase, 0, sizeof(erase)); erase.mtd = mtd; @@ -241,7 +254,7 @@ static int mtdraw_erase(struct cdev *cdev, size_t count, loff_t _offset) erase.len = mtd->erasesize; while (count > 0) { - debug("erase %d %d\n", erase.addr, erase.len); + debug("erase 0x%08llx len: 0x%08llx\n", erase.addr, erase.len); if (!mtd->allow_erasebad) ret = mtd_block_isbad(mtd, erase.addr); @@ -249,7 +262,7 @@ static int mtdraw_erase(struct cdev *cdev, size_t count, loff_t _offset) ret = 0; if (ret > 0) { - printf("Skipping bad block at 0x%08x\n", erase.addr); + printf("Skipping bad block at 0x%08llx\n", erase.addr); } else { ret = mtd_erase(mtd, &erase); if (ret) diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 4ddabda572..299cc15c3d 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -862,6 +862,7 @@ static int pmecc_build_galois_table(unsigned int mm, int16_t *index_of, static int __init atmel_pmecc_nand_init_params(struct device_d *dev, struct atmel_nand_host *host) { + struct resource *iores; struct mtd_info *mtd = &host->mtd; struct nand_chip *nand_chip = &host->nand_chip; int cap, sector_size, err_no; @@ -872,21 +873,28 @@ static int __init atmel_pmecc_nand_init_params(struct device_d *dev, dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n", cap, sector_size); - host->ecc = dev_request_mem_region(dev, 1); - if (host->ecc == NULL) { + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->ecc = IOMEM(iores->start); + if (IS_ERR(host->ecc)) { dev_err(host->dev, "ioremap failed\n"); return -EIO; } - host->pmerrloc_base = dev_request_mem_region(dev, 2); - if (!host->pmerrloc_base) { + iores = dev_request_mem_resource(dev, 2); + if (IS_ERR(iores)) { dev_err(host->dev, "Can not get I/O resource for PMECC ERRLOC controller!\n"); - return -EIO; + return PTR_ERR(iores); } + host->pmerrloc_base = IOMEM(iores->start); - host->pmecc_rom_base = dev_request_mem_region(dev, 3); - if (!host->pmecc_rom_base) { + iores = dev_request_mem_resource(dev, 3); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->pmecc_rom_base = IOMEM(iores->start); + if (IS_ERR(host->pmecc_rom_base)) { /* Set pmecc_rom_base as the begin of gf table */ int size = sector_size == 512 ? 0x2000 : 0x4000; pmecc_galois_table = xzalloc(2 * size * sizeof(uint16_t)); @@ -1245,11 +1253,15 @@ static int atmel_nand_of_init(struct atmel_nand_host *host, struct device_node * static int atmel_hw_nand_init_params(struct device_d *dev, struct atmel_nand_host *host) { + struct resource *iores; struct mtd_info *mtd = &host->mtd; struct nand_chip *nand_chip = &host->nand_chip; - host->ecc = dev_request_mem_region(dev, 1); - if (host->ecc == NULL) { + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->ecc = IOMEM(iores->start); + if (IS_ERR(host->ecc)) { dev_err(host->dev, "ioremap failed\n"); return -EIO; } @@ -1297,6 +1309,7 @@ static int atmel_hw_nand_init_params(struct device_d *dev, */ static int __init atmel_nand_probe(struct device_d *dev) { + struct resource *iores; struct atmel_nand_data *pdata = NULL; struct atmel_nand_host *host; struct mtd_info *mtd; @@ -1312,9 +1325,10 @@ static int __init atmel_nand_probe(struct device_d *dev) if (!pdata) return -ENOMEM; - host->io_base = dev_request_mem_region(dev, 0); - if (IS_ERR(host->io_base)) - return PTR_ERR(host->io_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->io_base = IOMEM(iores->start); mtd = &host->mtd; nand_chip = &host->nand_chip; diff --git a/drivers/mtd/nand/nand-bb.c b/drivers/mtd/nand/nand-bb.c index 8e4600ab03..e6d42772b3 100644 --- a/drivers/mtd/nand/nand-bb.c +++ b/drivers/mtd/nand/nand-bb.c @@ -88,7 +88,7 @@ static ssize_t nand_bb_read(struct cdev *cdev, void *buf, size_t count, } /* Must be a multiple of the largest NAND page size */ -#define BB_WRITEBUF_SIZE 4096 +#define BB_WRITEBUF_SIZE 8192 #ifdef CONFIG_MTD_WRITE static int nand_bb_write_buf(struct nand_bb *bb, size_t count) @@ -157,7 +157,7 @@ static ssize_t nand_bb_write(struct cdev *cdev, const void *buf, size_t count, return bytes; } -static int nand_bb_erase(struct cdev *cdev, size_t count, loff_t offset) +static int nand_bb_erase(struct cdev *cdev, loff_t count, loff_t offset) { struct nand_bb *bb = cdev->priv; struct erase_info erase = {}; diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 554d3d2f96..ec5a8b757c 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -3718,7 +3718,7 @@ int nand_scan_tail(struct mtd_info *mtd) * properly set. */ if (!mtd->bitflip_threshold) - mtd->bitflip_threshold = mtd->ecc_strength; + mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); /* Check, if we should skip the bad block table scan */ if (chip->options & NAND_SKIP_BBTSCAN) diff --git a/drivers/mtd/nand/nand_denali_dt.c b/drivers/mtd/nand/nand_denali_dt.c index 6a3aee1415..2c6b188094 100644 --- a/drivers/mtd/nand/nand_denali_dt.c +++ b/drivers/mtd/nand/nand_denali_dt.c @@ -36,6 +36,7 @@ struct denali_dt { static int denali_dt_probe(struct device_d *ofdev) { + struct resource *iores; struct denali_dt *dt; struct denali_nand_info *denali; int ret; @@ -51,12 +52,15 @@ static int denali_dt_probe(struct device_d *ofdev) denali->platform = DT; denali->dev = ofdev; - denali->flash_mem = dev_request_mem_region(ofdev, 0); - if (IS_ERR(denali->flash_mem)) - return PTR_ERR(denali->flash_mem); - denali->flash_reg = dev_request_mem_region(ofdev, 1); - if (IS_ERR(denali->flash_reg)) - return PTR_ERR(denali->flash_reg); + iores = dev_request_mem_resource(ofdev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + denali->flash_mem = IOMEM(iores->start); + + iores = dev_request_mem_resource(ofdev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + denali->flash_reg = IOMEM(iores->start); dt->clk = clk_get(ofdev, NULL); if (IS_ERR(dt->clk)) { diff --git a/drivers/mtd/nand/nand_imx.c b/drivers/mtd/nand/nand_imx.c index 00c05d00af..6ea82a110d 100644 --- a/drivers/mtd/nand/nand_imx.c +++ b/drivers/mtd/nand/nand_imx.c @@ -1105,6 +1105,7 @@ static int __init mxcnd_probe_dt(struct imx_nand_host *host) static int __init imxnd_probe(struct device_d *dev) { + struct resource *iores; struct nand_chip *this; struct mtd_info *mtd; struct imx_nand_host *host; @@ -1146,7 +1147,10 @@ static int __init imxnd_probe(struct device_d *dev) } if (nfc_is_v21()) { - host->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->base = IOMEM(iores->start); host->main_area0 = host->base; host->regs = host->base + 0x1e00; host->spare0 = host->base + 0x1000; @@ -1155,7 +1159,10 @@ static int __init imxnd_probe(struct device_d *dev) oob_largepage = &nandv2_hw_eccoob_largepage; oob_4kpage = &nandv2_hw_eccoob_4k; /* FIXME : to check */ } else if (nfc_is_v1()) { - host->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->base = IOMEM(iores->start); host->main_area0 = host->base; host->regs = host->base + 0xe00; host->spare0 = host->base + 0x800; @@ -1164,13 +1171,20 @@ static int __init imxnd_probe(struct device_d *dev) oob_largepage = &nandv1_hw_eccoob_largepage; oob_4kpage = &nandv1_hw_eccoob_smallpage; /* FIXME : to check */ } else if (nfc_is_v3_2()) { - host->regs_ip = dev_request_mem_region(dev, 0); - host->base = dev_request_mem_region(dev, 1); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->regs_ip = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->base = IOMEM(iores->start); host->main_area0 = host->base; - if (!host->regs_ip) { + if (IS_ERR(host->regs_ip)) { dev_err(dev, "no second mem region\n"); - err = -ENODEV; + err = PTR_ERR(host->regs_ip); goto escan; } diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c index f160d15ab5..578790da26 100644 --- a/drivers/mtd/nand/nand_mrvl_nfc.c +++ b/drivers/mtd/nand/nand_mrvl_nfc.c @@ -1105,6 +1105,7 @@ static int mrvl_nand_scan(struct mtd_info *mtd) static struct mrvl_nand_host *alloc_nand_resource(struct device_d *dev) { + struct resource *iores; struct mrvl_nand_platform_data *pdata; struct mrvl_nand_host *host; struct nand_chip *chip = NULL; @@ -1135,7 +1136,10 @@ static struct mrvl_nand_host *alloc_nand_resource(struct device_d *dev) chip->chip_delay = CHIP_DELAY_TIMEOUT_US; host->dev = dev; - host->mmio_base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->mmio_base = IOMEM(iores->start); if (IS_ERR(host->mmio_base)) { free(host); return host->mmio_base; diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c index 7635e2a418..20bda14b62 100644 --- a/drivers/mtd/nand/nand_mxs.c +++ b/drivers/mtd/nand/nand_mxs.c @@ -1274,6 +1274,7 @@ static void mxs_nand_probe_dt(struct device_d *dev, struct mxs_nand_info *nand_i static int mxs_nand_probe(struct device_d *dev) { + struct resource *iores; struct mxs_nand_info *nand_info; struct nand_chip *nand; struct mtd_info *mtd; @@ -1293,13 +1294,15 @@ static int mxs_nand_probe(struct device_d *dev) mxs_nand_probe_dt(dev, nand_info); nand_info->type = type; - nand_info->io_base = dev_request_mem_region(dev, 0); - if (IS_ERR(nand_info->io_base)) - return PTR_ERR(nand_info->io_base); - - nand_info->bch_base = dev_request_mem_region(dev, 1); - if (IS_ERR(nand_info->bch_base)) - return PTR_ERR(nand_info->bch_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + nand_info->io_base = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + nand_info->bch_base = IOMEM(iores->start); nand_info->clk = clk_get(dev, NULL); if (IS_ERR(nand_info->clk)) diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c index 9d9d27e964..a920522939 100644 --- a/drivers/mtd/nand/nand_omap_gpmc.c +++ b/drivers/mtd/nand/nand_omap_gpmc.c @@ -846,6 +846,7 @@ static int gpmc_set_buswidth(struct nand_chip *chip, int buswidth) */ static int gpmc_nand_probe(struct device_d *pdev) { + struct resource *iores; struct gpmc_nand_info *oinfo; struct gpmc_nand_platform_data *pdata; struct nand_chip *nand; @@ -881,7 +882,10 @@ static int gpmc_nand_probe(struct device_d *pdev) } /* Setup register specific data */ oinfo->gpmc_cs = pdata->cs; - oinfo->gpmc_base = dev_request_mem_region(pdev, 0); + iores = dev_request_mem_resource(pdev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + oinfo->gpmc_base = IOMEM(iores->start); cs_base = oinfo->gpmc_base + GPMC_CONFIG1_0 + (pdata->cs * GPMC_CONFIG_CS_SIZE); oinfo->gpmc_command = (void *)(cs_base + GPMC_CS_NAND_COMMAND); diff --git a/drivers/mtd/nand/nand_orion.c b/drivers/mtd/nand/nand_orion.c index fe06ef7912..881ffeec05 100644 --- a/drivers/mtd/nand/nand_orion.c +++ b/drivers/mtd/nand/nand_orion.c @@ -80,6 +80,7 @@ static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) static int orion_nand_probe(struct device_d *dev) { + struct resource *iores; struct device_node *dev_node = dev->device_node; struct orion_nand *priv; struct mtd_info *mtd; @@ -93,9 +94,10 @@ static int orion_nand_probe(struct device_d *dev) mtd = &priv->mtd; chip = &priv->chip; - io_base = dev_request_mem_region(dev, 0); - if (IS_ERR(io_base)) - return PTR_ERR(io_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + io_base = IOMEM(iores->start); if (!of_property_read_u32(dev_node, "cle", &val)) priv->cle = (u8)val; diff --git a/drivers/mtd/nand/nand_s3c24xx.c b/drivers/mtd/nand/nand_s3c24xx.c index 37bba39260..83d45172b1 100644 --- a/drivers/mtd/nand/nand_s3c24xx.c +++ b/drivers/mtd/nand/nand_s3c24xx.c @@ -408,6 +408,7 @@ static int s3c24x0_nand_inithw(struct s3c24x0_nand_host *host) static int s3c24x0_nand_probe(struct device_d *dev) { + struct resource *iores; struct nand_chip *chip; struct s3c24x0_nand_platform_data *pdata = dev->platform_data; struct mtd_info *mtd; @@ -420,7 +421,10 @@ static int s3c24x0_nand_probe(struct device_d *dev) return -ENOMEM; host->dev = dev; - host->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->base = IOMEM(iores->start); /* structures must be linked */ chip = &host->nand; diff --git a/drivers/mtd/nor/cfi_flash.c b/drivers/mtd/nor/cfi_flash.c index feffbd04ac..e50f0e667f 100644 --- a/drivers/mtd/nor/cfi_flash.c +++ b/drivers/mtd/nor/cfi_flash.c @@ -966,13 +966,15 @@ static void cfi_init_mtd(struct flash_info *info) static int cfi_probe_one(struct flash_info *info, int num) { + struct resource *iores; int ret; info->flash_id = FLASH_UNKNOWN; info->cmd_reset = FLASH_CMD_RESET; - info->base = dev_request_mem_region(info->dev, num); - if (IS_ERR(info->base)) - return PTR_ERR(info->base); + iores = dev_request_mem_resource(info->dev, num); + if (IS_ERR(iores)) + return PTR_ERR(iores); + info->base = IOMEM(iores->start); ret = flash_detect_size(info); if (ret) { diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index ff7bb7a5d8..680f30f707 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -1109,6 +1109,7 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) static int cqspi_probe(struct device_d *dev) { + struct resource *iores; struct device_node *np = dev->device_node; struct cqspi_st *cqspi; struct cadence_qspi_platform_data *pdata = dev->platform_data; @@ -1142,14 +1143,20 @@ static int cqspi_probe(struct device_d *dev) clk_enable(cqspi->qspi_clk); - cqspi->iobase = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + cqspi->iobase = IOMEM(iores->start); if (IS_ERR(cqspi->iobase)) { dev_err(dev, "dev_request_mem_region 0 failed\n"); ret = PTR_ERR(cqspi->iobase); goto probe_failed; } - cqspi->ahb_base = dev_request_mem_region(dev, 1); + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + cqspi->ahb_base = IOMEM(iores->start); if (IS_ERR(cqspi->ahb_base)) { dev_err(dev, "dev_request_mem_region 0 failed\n"); ret = PTR_ERR(cqspi->ahb_base); diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 908aacb6a2..4b55b0c3d8 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -571,6 +571,7 @@ static const struct spi_device_id spi_nor_ids[] = { { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) }, { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, + { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K) }, { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, 0) }, { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K) }, diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c index a1863655fa..1e67c7a8e7 100644 --- a/drivers/net/altera_tse.c +++ b/drivers/net/altera_tse.c @@ -492,6 +492,7 @@ static int tse_init_dev(struct eth_device *edev) static int tse_probe(struct device_d *dev) { + struct resource *iores; struct altera_tse_priv *priv; struct mii_bus *miibus; struct eth_device *edev; @@ -516,9 +517,10 @@ static int tse_probe(struct device_d *dev) edev->parent = dev; #ifdef CONFIG_TSE_USE_DEDICATED_DESC_MEM - tx_desc = dev_request_mem_region(dev, 3); - if (IS_ERR(tx_desc)) - return PTR_ERR(tx_desc); + iores = dev_request_mem_resource(dev, 3); + if (IS_ERR(iores)) + return PTR_ERR(iores); + tx_desc = IOMEM(iores->start); rx_desc = tx_desc + 2; #else tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX), (dma_addr_t *)&dma_handle); @@ -534,15 +536,19 @@ static int tse_probe(struct device_d *dev) memset(rx_desc, 0, (sizeof *rx_desc) * (PKTBUFSRX + 1)); memset(tx_desc, 0, (sizeof *tx_desc) * 2); - priv->tse_regs = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->tse_regs)) - return PTR_ERR(priv->tse_regs); - priv->sgdma_rx_regs = dev_request_mem_region(dev, 1); - if (IS_ERR(priv->sgdma_rx_regs)) - return PTR_ERR(priv->sgdma_rx_regs); - priv->sgdma_tx_regs = dev_request_mem_region(dev, 2); - if (IS_ERR(priv->sgdma_tx_regs)) - return PTR_ERR(priv->sgdma_tx_regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->tse_regs = IOMEM(iores->start); + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->sgdma_rx_regs = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 2); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->sgdma_tx_regs = IOMEM(iores->start); priv->rx_desc = rx_desc; priv->tx_desc = tx_desc; diff --git a/drivers/net/ar231x.c b/drivers/net/ar231x.c index 7447c4484d..1ef9ce8154 100644 --- a/drivers/net/ar231x.c +++ b/drivers/net/ar231x.c @@ -363,6 +363,7 @@ static int ar231x_mdiibus_reset(struct mii_bus *bus) static int ar231x_eth_probe(struct device_d *dev) { + struct resource *iores; struct ar231x_eth_priv *priv; struct eth_device *edev; struct mii_bus *miibus; @@ -384,20 +385,22 @@ static int ar231x_eth_probe(struct device_d *dev) priv->mac = pdata->mac; priv->reset_bit = pdata->reset_bit; - priv->eth_regs = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->eth_regs)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "No eth_regs!!\n"); - return PTR_ERR(priv->eth_regs); + return PTR_ERR(iores); } + priv->eth_regs = IOMEM(iores->start); /* we have 0x100000 for eth, part of it are dma regs. * So they are already requested */ priv->dma_regs = (void *)(priv->eth_regs + 0x1000); - priv->phy_regs = dev_request_mem_region(dev, 1); - if (IS_ERR(priv->phy_regs)) { + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) { dev_err(dev, "No phy_regs!!\n"); - return PTR_ERR(priv->phy_regs); + return PTR_ERR(iores); } + priv->phy_regs = IOMEM(iores->start); priv->cfg = pdata; edev->init = ar231x_eth_init; diff --git a/drivers/net/arc_emac.c b/drivers/net/arc_emac.c index 3dc54cd22b..2155349e21 100644 --- a/drivers/net/arc_emac.c +++ b/drivers/net/arc_emac.c @@ -391,6 +391,7 @@ static int arc_emac_mdio_write(struct mii_bus *bus, int phy_addr, int reg_num, static int arc_emac_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct arc_emac_priv *priv; unsigned long clock_frequency; @@ -406,9 +407,10 @@ static int arc_emac_probe(struct device_d *dev) miibus = xzalloc(sizeof(struct mii_bus)); priv = edev->priv; - priv->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->regs)) - return PTR_ERR(priv->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); priv->bus = miibus; priv->clk = clk_get(dev, "hclk"); diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 4d6b7b2e78..d11ca33f70 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -1126,6 +1126,7 @@ static int cpsw_probe_dt(struct cpsw_priv *priv) int cpsw_probe(struct device_d *dev) { + struct resource *iores; struct cpsw_platform_data *data = (struct cpsw_platform_data *)dev->platform_data; struct cpsw_priv *priv; void __iomem *regs; @@ -1136,9 +1137,10 @@ int cpsw_probe(struct device_d *dev) dev_dbg(dev, "* %s\n", __func__); - regs = dev_request_mem_region(dev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + regs = IOMEM(iores->start); priv = xzalloc(sizeof(*priv)); priv->dev = dev; diff --git a/drivers/net/cs8900.c b/drivers/net/cs8900.c index a4a5dcaf7f..1be49e86fe 100644 --- a/drivers/net/cs8900.c +++ b/drivers/net/cs8900.c @@ -435,13 +435,17 @@ static int cs8900_check_id(struct cs8900_priv *priv) static int cs8900_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct cs8900_priv *priv; debug("cs8900_init()\n"); priv = (struct cs8900_priv *)xmalloc(sizeof(*priv)); - priv->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); if (cs8900_check_id(priv)) { free(priv); return -1; diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 9f8f0e1fa7..3dc4b16b67 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -516,6 +516,7 @@ out: static int davinci_emac_probe(struct device_d *dev) { + struct resource *iores; struct davinci_emac_platform_data *pdata; struct davinci_emac_priv *priv; uint64_t start; @@ -534,10 +535,25 @@ static int davinci_emac_probe(struct device_d *dev) priv->dev = dev; - priv->adap_emac = dev_request_mem_region(dev, 0); - priv->adap_ewrap = dev_request_mem_region(dev, 1); - priv->adap_mdio = dev_request_mem_region(dev, 2); - priv->emac_desc_base = dev_request_mem_region(dev, 3); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->adap_emac = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->adap_ewrap = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 2); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->adap_mdio = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 3); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->emac_desc_base = IOMEM(iores->start); /* EMAC descriptors */ priv->emac_rx_desc = priv->emac_desc_base + EMAC_RX_DESC_BASE; diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 966f64f7b6..3b21244478 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -445,6 +445,7 @@ static int dwc_probe_dt(struct device_d *dev, struct dw_eth_dev *priv) static int dwc_ether_probe(struct device_d *dev) { + struct resource *iores; struct dw_eth_dev *priv; struct eth_device *edev; struct mii_bus *miibus; @@ -471,9 +472,10 @@ static int dwc_ether_probe(struct device_d *dev) return ret; } - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); priv->mac_regs_p = base; dwc_version(dev, readl(&priv->mac_regs_p->version)); diff --git a/drivers/net/dm9k.c b/drivers/net/dm9k.c index 1f1938d977..ad402e3efc 100644 --- a/drivers/net/dm9k.c +++ b/drivers/net/dm9k.c @@ -785,6 +785,7 @@ static int dm9000_parse_pdata(struct device_d *dev, struct dm9k *priv) static int dm9k_probe(struct device_d *dev) { + struct resource *iores; unsigned io_mode; struct eth_device *edev; struct dm9k *priv; @@ -808,17 +809,19 @@ static int dm9k_probe(struct device_d *dev) if (ret) goto err; - priv->iodata = dev_request_mem_region(dev, 1); - if (!priv->iodata) { - ret = -EBUSY; + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto err; } + priv->iodata = IOMEM(iores->start); - priv->iobase = dev_request_mem_region(dev, 0); - if (!priv->iobase) { - ret = -EBUSY; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto err; } + priv->iobase = IOMEM(iores->start); edev->init = dm9k_init_dev; edev->open = dm9k_eth_open; diff --git a/drivers/net/efi-snp.c b/drivers/net/efi-snp.c index 5b96fbf462..963d539db3 100644 --- a/drivers/net/efi-snp.c +++ b/drivers/net/efi-snp.c @@ -238,7 +238,7 @@ static int efi_snp_get_ethaddr(struct eth_device *edev, unsigned char *adr) return 0; } -static int efi_snp_set_ethaddr(struct eth_device *edev, unsigned char *adr) +static int efi_snp_set_ethaddr(struct eth_device *edev, const unsigned char *adr) { return 0; } diff --git a/drivers/net/ep93xx.c b/drivers/net/ep93xx.c index 90c12fce75..0acb9b692f 100644 --- a/drivers/net/ep93xx.c +++ b/drivers/net/ep93xx.c @@ -38,6 +38,7 @@ #include <linux/types.h> #include <mach/ep93xx-regs.h> #include <linux/phy.h> +#include <net/ep93xx_eth.h> #include "ep93xx.h" #define EP93XX_MAX_PKT_SIZE 1536 @@ -203,8 +204,8 @@ static int ep93xx_eth_open(struct eth_device *edev) pr_debug("+ep93xx_eth_open\n"); - ret = phy_device_connect(edev, &priv->miibus, 0, NULL, - 0, PHY_INTERFACE_MODE_NA); + ret = phy_device_connect(edev, &priv->miibus, priv->phy_addr, NULL, + 0, priv->interface); if (ret) return ret; @@ -482,6 +483,7 @@ static int ep93xx_eth_set_ethaddr(struct eth_device *edev, static int ep93xx_eth_probe(struct device_d *dev) { + struct ep93xx_eth_platform_data *pdata = (struct ep93xx_eth_platform_data *)dev->platform_data; struct eth_device *edev; struct ep93xx_eth_priv *priv; int ret = -1; @@ -504,6 +506,14 @@ static int ep93xx_eth_probe(struct device_d *dev) edev->set_ethaddr = ep93xx_eth_set_ethaddr; edev->parent = dev; + if (pdata) { + priv->interface = pdata->xcv_type; + priv->phy_addr = pdata->phy_addr; + } else { + priv->interface = PHY_INTERFACE_MODE_NA; + priv->phy_addr = 0; + } + priv->miibus.read = ep93xx_phy_read; priv->miibus.write = ep93xx_phy_write; priv->miibus.parent = dev; @@ -589,14 +599,12 @@ static int ep93xx_phy_read(struct mii_bus *bus, int phy_addr, int phy_reg) pr_debug("+ep93xx_phy_read\n"); /* - * Save the current SelfCTL register value. Set MAC to suppress + * Save the current SelfCTL register value. Set MAC to send * preamble bits. Wait for any previous MII command to complete * before issuing the new command. */ self_ctl = readl(®s->selfctl); -#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) /* TODO */ writel(self_ctl & ~(1 << 8), ®s->selfctl); -#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ while (readl(®s->miists) & MIISTS_BUSY) ; /* noop */ @@ -632,14 +640,12 @@ static int ep93xx_phy_write(struct mii_bus *bus, int phy_addr, pr_debug("+ep93xx_phy_write\n"); /* - * Save the current SelfCTL register value. Set MAC to suppress + * Save the current SelfCTL register value. Set MAC to send * preamble bits. Wait for any previous MII command to complete * before issuing the new command. */ self_ctl = readl(®s->selfctl); -#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) /* TODO */ writel(self_ctl & ~(1 << 8), ®s->selfctl); -#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ while (readl(®s->miists) & MIISTS_BUSY) ; /* noop */ diff --git a/drivers/net/ep93xx.h b/drivers/net/ep93xx.h index 89451b8a5f..32ae57f9f2 100644 --- a/drivers/net/ep93xx.h +++ b/drivers/net/ep93xx.h @@ -137,6 +137,8 @@ struct ep93xx_eth_priv { struct tx_descriptor_queue tx_dq; struct tx_status_queue tx_sq; + int phy_addr; + phy_interface_t interface; struct mii_bus miibus; }; diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index 6bae7d68a6..1cb9fc2859 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -534,6 +534,7 @@ static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) static int ethoc_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct ethoc *priv; @@ -542,9 +543,10 @@ static int ethoc_probe(struct device_d *dev) edev->priv = (struct ethoc *)(edev + 1); priv = edev->priv; - priv->iobase = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->iobase)) - return PTR_ERR(priv->iobase); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->iobase = IOMEM(iores->start); priv->miibus.read = ethoc_mdio_read; priv->miibus.write = ethoc_mdio_write; diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c index 5418034129..de31ec48bd 100644 --- a/drivers/net/fec_imx.c +++ b/drivers/net/fec_imx.c @@ -647,6 +647,7 @@ static int fec_probe_dt(struct device_d *dev, struct fec_priv *fec) #endif static int fec_probe(struct device_d *dev) { + struct resource *iores; struct fec_platform_data *pdata = (struct fec_platform_data *)dev->platform_data; struct eth_device *edev; struct fec_priv *fec; @@ -681,7 +682,10 @@ static int fec_probe(struct device_d *dev) clk_enable(fec->clk); - fec->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + fec->regs = IOMEM(iores->start); phy_reset = of_get_named_gpio(dev->device_node, "phy-reset-gpios", 0); if (gpio_is_valid(phy_reset)) { diff --git a/drivers/net/fec_mpc5200.c b/drivers/net/fec_mpc5200.c index 30be8f77dc..bb57c34502 100644 --- a/drivers/net/fec_mpc5200.c +++ b/drivers/net/fec_mpc5200.c @@ -638,6 +638,7 @@ static int mpc5xxx_fec_recv(struct eth_device *dev) int mpc5xxx_fec_probe(struct device_d *dev) { + struct resource *iores; struct fec_platform_data *pdata = dev->platform_data; struct eth_device *edev; mpc5xxx_fec_priv *fec; @@ -655,9 +656,10 @@ int mpc5xxx_fec_probe(struct device_d *dev) edev->set_ethaddr = mpc5xxx_fec_set_ethaddr; edev->parent = dev; - fec->eth = dev_request_mem_region(dev, 0); - if (IS_ERR(fec->eth)) - return PTR_ERR(fec->eth); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + fec->eth = IOMEM(iores->start); fec->tbdBase = (FEC_TBD *)FEC_BD_BASE; fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD)); diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c index 854a666bfc..39e1654ca6 100644 --- a/drivers/net/ks8851_mll.c +++ b/drivers/net/ks8851_mll.c @@ -809,6 +809,7 @@ static void ks8851_eth_halt(struct eth_device *edev) static int ks8851_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct ks_net *ks; u16 id; @@ -823,13 +824,16 @@ static int ks8851_probe(struct device_d *dev) return -ENODEV; } - ks->hw_addr = dev_request_mem_region(dev, 0); - if (IS_ERR(ks->hw_addr)) - return PTR_ERR(ks->hw_addr); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ks->hw_addr = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ks->hw_addr_cmd = IOMEM(iores->start); - ks->hw_addr_cmd = dev_request_mem_region(dev, 1); - if (IS_ERR(ks->hw_addr_cmd)) - return PTR_ERR(ks->hw_addr_cmd); ks->bus_width = dev->resource[0].flags & IORESOURCE_MEM_TYPE_MASK; edev->init = ks8851_init_dev; diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 6d4973fa2f..5f2e5e5131 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -612,6 +612,7 @@ static void macb_init_rx_buffer_size(struct macb_device *bp, size_t size) static int macb_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct macb_device *macb; u32 ncfgr; @@ -649,9 +650,10 @@ static int macb_probe(struct device_d *dev) macb->phy_flags = pdata->phy_flags; - macb->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(macb->regs)) - return PTR_ERR(macb->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + macb->regs = IOMEM(iores->start); /* * Do some basic initialization so that we at least can talk diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c index 1199b372b6..b7055910eb 100644 --- a/drivers/net/smc91111.c +++ b/drivers/net/smc91111.c @@ -1444,6 +1444,7 @@ static int smc91c111_init_dev(struct eth_device *edev) static int smc91c111_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct smc91c111_priv *priv; @@ -1481,9 +1482,10 @@ static int smc91c111_probe(struct device_d *dev) priv->miibus.write = smc91c111_phy_write; priv->miibus.priv = priv; priv->miibus.parent = dev; - priv->base = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->base = IOMEM(iores->start); smc91c111_reset(edev); diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 60cf36ea4a..9b1a38ae21 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -494,6 +494,7 @@ static int smc911x_init_dev(struct eth_device *edev) static int smc911x_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct smc911x_priv *priv; uint32_t val; @@ -506,7 +507,10 @@ static int smc911x_probe(struct device_d *dev) is_32bit = 1; else is_32bit = is_32bit == IORESOURCE_MEM_32BIT; - priv->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->base = IOMEM(iores->start); if (pdata) { priv->shift = pdata->shift; diff --git a/drivers/net/xgmac.c b/drivers/net/xgmac.c index 7cc4d4888f..47ab6e72eb 100644 --- a/drivers/net/xgmac.c +++ b/drivers/net/xgmac.c @@ -689,11 +689,15 @@ static int xgmac_set_ethaddr(struct eth_device *dev, const unsigned char *addr) static int hb_xgmac_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct xgmac_priv *priv; void __iomem *base; - base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); /* check hardware version */ if (readl(base + XGMAC_VERSION) != 0x1012) diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c index d32bd2b4ce..46483b4cc8 100644 --- a/drivers/pci/pci-imx6.c +++ b/drivers/pci/pci-imx6.c @@ -555,6 +555,7 @@ static int __init imx6_add_pcie_port(struct pcie_port *pp, static int __init imx6_pcie_probe(struct device_d *dev) { + struct resource *iores; struct imx6_pcie *imx6_pcie; struct pcie_port *pp; struct device_node *np = dev->device_node; @@ -567,9 +568,10 @@ static int __init imx6_pcie_probe(struct device_d *dev) pp = &imx6_pcie->pp; pp->dev = dev; - pp->dbi_base = dev_request_mem_region(dev, 0); - if (IS_ERR(pp->dbi_base)) - return PTR_ERR(pp->dbi_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + pp->dbi_base = IOMEM(iores->start); /* Fetch GPIOs */ imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); diff --git a/drivers/pinctrl/imx-iomux-v2.c b/drivers/pinctrl/imx-iomux-v2.c index 1e0e8e9fd6..0c985a69d3 100644 --- a/drivers/pinctrl/imx-iomux-v2.c +++ b/drivers/pinctrl/imx-iomux-v2.c @@ -118,9 +118,11 @@ int imx_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count) static int imx_iomux_probe(struct device_d *dev) { - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + struct resource *iores; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); return 0; } diff --git a/drivers/pinctrl/imx-iomux-v3.c b/drivers/pinctrl/imx-iomux-v3.c index 62a352ba50..66443b7e7b 100644 --- a/drivers/pinctrl/imx-iomux-v3.c +++ b/drivers/pinctrl/imx-iomux-v3.c @@ -171,12 +171,16 @@ static int imx_pinctrl_dt(struct device_d *dev, void __iomem *base) static int imx_iomux_v3_probe(struct device_d *dev) { + struct resource *iores; int ret = 0; if (iomuxv3_base) return -EBUSY; - iomuxv3_base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + iomuxv3_base = IOMEM(iores->start); iomuxv3_dev = dev; if (IS_ENABLED(CONFIG_PINCTRL) && dev->device_node) diff --git a/drivers/pinctrl/mvebu/armada-370.c b/drivers/pinctrl/mvebu/armada-370.c index b7901f8c6d..1c79bd62af 100644 --- a/drivers/pinctrl/mvebu/armada-370.c +++ b/drivers/pinctrl/mvebu/armada-370.c @@ -391,14 +391,16 @@ static struct of_device_id armada_370_pinctrl_of_match[] = { static int armada_370_pinctrl_probe(struct device_d *dev) { + struct resource *iores; const struct of_device_id *match = of_match_node(armada_370_pinctrl_of_match, dev->device_node); struct mvebu_pinctrl_soc_info *soc = (struct mvebu_pinctrl_soc_info *)match->data; - mpp_base = dev_request_mem_region(dev, 0); - if (!mpp_base) - return -EBUSY; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mpp_base = IOMEM(iores->start); return mvebu_pinctrl_probe(dev, soc); } diff --git a/drivers/pinctrl/mvebu/armada-xp.c b/drivers/pinctrl/mvebu/armada-xp.c index 51db35d068..f1bc8b498a 100644 --- a/drivers/pinctrl/mvebu/armada-xp.c +++ b/drivers/pinctrl/mvebu/armada-xp.c @@ -370,13 +370,15 @@ static struct of_device_id armada_xp_pinctrl_of_match[] = { static int armada_xp_pinctrl_probe(struct device_d *dev) { + struct resource *iores; const struct of_device_id *match = of_match_node(armada_xp_pinctrl_of_match, dev->device_node); struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info; - mpp_base = dev_request_mem_region(dev, 0); - if (IS_ERR(mpp_base)) - return PTR_ERR(mpp_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mpp_base = IOMEM(iores->start); soc->variant = (enum armada_xp_variant)match->data; diff --git a/drivers/pinctrl/mvebu/dove.c b/drivers/pinctrl/mvebu/dove.c index d1848a79d3..8de01e74d6 100644 --- a/drivers/pinctrl/mvebu/dove.c +++ b/drivers/pinctrl/mvebu/dove.c @@ -696,6 +696,7 @@ static struct of_device_id dove_pinctrl_of_match[] = { static int dove_pinctrl_probe(struct device_d *dev) { + struct resource *iores; const struct of_device_id *match = of_match_node(dove_pinctrl_of_match, dev->device_node); struct mvebu_pinctrl_soc_info *soc = @@ -706,10 +707,15 @@ static int dove_pinctrl_probe(struct device_d *dev) clk = clk_get(dev, NULL); clk_enable(clk); - mpp_base = dev_request_mem_region(dev, 0); - mpp4_base = dev_request_mem_region(dev, 1); - if (!mpp_base || !mpp4_base) - return -EBUSY; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mpp_base = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mpp4_base = IOMEM(iores->start); /* * Dove PMU does not have a stable binding, yet. diff --git a/drivers/pinctrl/mvebu/kirkwood.c b/drivers/pinctrl/mvebu/kirkwood.c index e2ac559668..4b2618cd2e 100644 --- a/drivers/pinctrl/mvebu/kirkwood.c +++ b/drivers/pinctrl/mvebu/kirkwood.c @@ -432,14 +432,16 @@ static struct of_device_id kirkwood_pinctrl_of_match[] = { static int kirkwood_pinctrl_probe(struct device_d *dev) { + struct resource *iores; const struct of_device_id *match = of_match_node(kirkwood_pinctrl_of_match, dev->device_node); struct mvebu_pinctrl_soc_info *soc = (struct mvebu_pinctrl_soc_info *)match->data; - mpp_base = dev_request_mem_region(dev, 0); - if (IS_ERR(mpp_base)) - return PTR_ERR(mpp_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mpp_base = IOMEM(iores->start); return mvebu_pinctrl_probe(dev, soc); } diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 5c60c70b17..15b74cc1df 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -98,12 +98,16 @@ static struct pinctrl_ops pcs_ops = { static int pcs_probe(struct device_d *dev) { + struct resource *iores; struct pinctrl_single *pcs; struct device_node *np = dev->device_node; int ret = 0; pcs = xzalloc(sizeof(*pcs)); - pcs->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + pcs->base = IOMEM(iores->start); pcs->pinctrl.dev = dev; pcs->pinctrl.ops = &pcs_ops; diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c index d567754fd7..a7a75bb9c5 100644 --- a/drivers/pinctrl/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/pinctrl-tegra-xusb.c @@ -378,6 +378,7 @@ static struct pinctrl_ops pinctrl_tegra_xusb_ops = { static int pinctrl_tegra_xusb_probe(struct device_d *dev) { + struct resource *iores; struct tegra_xusb_padctl *padctl; struct phy *phy; int err; @@ -389,11 +390,12 @@ static int pinctrl_tegra_xusb_probe(struct device_d *dev) dev_get_drvdata(dev, (const void **)&padctl->soc); - padctl->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(padctl->regs)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "Could not get iomem region\n"); - return PTR_ERR(padctl->regs); + return PTR_ERR(iores); } + padctl->regs = IOMEM(iores->start); padctl->rst = reset_control_get(dev, NULL); if (IS_ERR(padctl->rst)) diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c index be9d8a996d..eaaba9e7a7 100644 --- a/drivers/pinctrl/pinctrl-tegra20.c +++ b/drivers/pinctrl/pinctrl-tegra20.c @@ -295,6 +295,7 @@ static struct pinctrl_ops pinctrl_tegra20_ops = { static int pinctrl_tegra20_probe(struct device_d *dev) { + struct resource *iores; struct pinctrl_tegra20 *ctrl; int i, ret; u32 **regs; @@ -309,11 +310,12 @@ static int pinctrl_tegra20_probe(struct device_d *dev) */ regs = (u32 **)&ctrl->regs; for (i = 0; i <= 2; i++) { - regs[i] = dev_request_mem_region(dev, i); - if (IS_ERR(regs[i])) { + iores = dev_request_mem_resource(dev, i); + if (IS_ERR(iores)) { dev_err(dev, "Could not get iomem region %d\n", i); - return PTR_ERR(regs[i]); + return PTR_ERR(iores); } + regs[i] = IOMEM(iores->start); } ctrl->pinctrl.dev = dev; diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c index 145a1a821e..4b271dd0b6 100644 --- a/drivers/pinctrl/pinctrl-tegra30.c +++ b/drivers/pinctrl/pinctrl-tegra30.c @@ -870,6 +870,7 @@ static struct pinctrl_ops pinctrl_tegra30_ops = { static int pinctrl_tegra30_probe(struct device_d *dev) { + struct resource *iores; struct pinctrl_tegra30 *ctrl; int i, ret; u32 **regs; @@ -884,11 +885,12 @@ static int pinctrl_tegra30_probe(struct device_d *dev) */ regs = (u32 **)&ctrl->regs; for (i = 0; i <= 1; i++) { - regs[i] = dev_request_mem_region(dev, i); - if (IS_ERR(regs[i])) { + iores = dev_request_mem_resource(dev, i); + if (IS_ERR(iores)) { dev_err(dev, "Could not get iomem region %d\n", i); - return PTR_ERR(regs[i]); + return PTR_ERR(iores); } + regs[i] = IOMEM(iores->start); } dev_get_drvdata(dev, (const void **)&ctrl->drvdata); diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index bd99cf3198..0845c234fe 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -212,6 +212,7 @@ static struct of_device_id imx_pwm_dt_ids[] = { static int imx_pwm_probe(struct device_d *dev) { + struct resource *iores; const struct imx_pwm_data *data; struct imx_chip *imx; int ret = 0; @@ -226,9 +227,10 @@ static int imx_pwm_probe(struct device_d *dev) if (IS_ERR(imx->clk_per)) return PTR_ERR(imx->clk_per); - imx->mmio_base = dev_request_mem_region(dev, 0); - if (IS_ERR(imx->mmio_base)) - return PTR_ERR(imx->mmio_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + imx->mmio_base = IOMEM(iores->start); imx->chip.ops = &imx_pwm_ops; if (dev->device_node) { diff --git a/drivers/pwm/pwm-mxs.c b/drivers/pwm/pwm-mxs.c index e66744288b..011d9002ba 100644 --- a/drivers/pwm/pwm-mxs.c +++ b/drivers/pwm/pwm-mxs.c @@ -110,6 +110,7 @@ static struct pwm_ops mxs_pwm_ops = { static int mxs_pwm_probe(struct device_d *dev) { + struct resource *iores; struct device_node *np = dev->device_node; struct mxs_pwm *mxs; int ret, i; @@ -117,9 +118,10 @@ static int mxs_pwm_probe(struct device_d *dev) mxs = xzalloc(sizeof(*mxs)); - mxs->base = dev_request_mem_region(dev, 0); - if (IS_ERR(mxs->base)) - return PTR_ERR(mxs->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mxs->base = IOMEM(iores->start); mxs->clk = clk_get(dev, NULL); if (IS_ERR(mxs->clk)) diff --git a/drivers/pwm/pxa_pwm.c b/drivers/pwm/pxa_pwm.c index 8b2ebe4f6f..e399d03efd 100644 --- a/drivers/pwm/pxa_pwm.c +++ b/drivers/pwm/pxa_pwm.c @@ -130,12 +130,16 @@ static struct pwm_ops pxa_pwm_ops = { static int pxa_pwm_probe(struct device_d *dev) { + struct resource *iores; struct pxa_pwm_chip *chip; chip = xzalloc(sizeof(*chip)); chip->chip.devname = asprintf("pwm%d", dev->id); chip->chip.ops = &pxa_pwm_ops; - chip->iobase = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + chip->iobase = IOMEM(iores->start); chip->id = dev->id; dev->priv = chip; diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c index 8194050e7f..95885357d9 100644 --- a/drivers/rtc/rtc-jz4740.c +++ b/drivers/rtc/rtc-jz4740.c @@ -113,16 +113,18 @@ static struct rtc_class_ops jz4740_rtc_ops = { static int jz4740_rtc_probe(struct device_d *dev) { + struct resource *iores; int ret; struct jz4740_rtc *rtc; uint32_t scratchpad; void __iomem *base; - base = dev_request_mem_region(dev, 0); - if (!base) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return -ENODEV; + return PTR_ERR(iores); } + base = IOMEM(iores->start); rtc = xzalloc(sizeof(*rtc)); diff --git a/drivers/serial/serial_altera.c b/drivers/serial/serial_altera.c index d519a87928..10d1506bca 100644 --- a/drivers/serial/serial_altera.c +++ b/drivers/serial/serial_altera.c @@ -78,13 +78,17 @@ static int altera_serial_getc(struct console_device *cdev) static int altera_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; struct altera_serial_priv *priv; priv = xzalloc(sizeof(*priv)); cdev = &priv->cdev; - priv->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = altera_serial_tstc; cdev->putc = altera_serial_putc; diff --git a/drivers/serial/serial_altera_jtag.c b/drivers/serial/serial_altera_jtag.c index 4219a4bbb9..0164ea5eff 100644 --- a/drivers/serial/serial_altera_jtag.c +++ b/drivers/serial/serial_altera_jtag.c @@ -82,6 +82,7 @@ static int altera_serial_jtag_getc(struct console_device *cdev) } static int altera_serial_jtag_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; struct altera_serial_jtag_priv *priv; @@ -89,7 +90,10 @@ static int altera_serial_jtag_probe(struct device_d *dev) { priv = xzalloc(sizeof(*priv)); cdev = &priv->cdev; - priv->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = altera_serial_jtag_tstc; cdev->putc = altera_serial_jtag_putc; diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c index 59bb5b2ecf..676b9fadf8 100644 --- a/drivers/serial/serial_ar933x.c +++ b/drivers/serial/serial_ar933x.c @@ -156,15 +156,17 @@ static int ar933x_serial_getc(struct console_device *cdev) static int ar933x_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; struct ar933x_uart_priv *priv; u32 uart_cs; cdev = xzalloc(sizeof(struct console_device)); priv = xzalloc(sizeof(struct ar933x_uart_priv)); - priv->base = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->base = IOMEM(iores->start); dev->priv = priv; diff --git a/drivers/serial/serial_auart.c b/drivers/serial/serial_auart.c index 87b2e33ca3..9bef576cd7 100644 --- a/drivers/serial/serial_auart.c +++ b/drivers/serial/serial_auart.c @@ -180,6 +180,7 @@ static void auart_serial_init_port(struct auart_priv *priv) static int auart_serial_probe(struct device_d *dev) { + struct resource *iores; struct auart_priv *priv; struct console_device *cdev; @@ -194,9 +195,10 @@ static int auart_serial_probe(struct device_d *dev) cdev->dev = dev; dev->priv = priv; - priv->base = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->base = IOMEM(iores->start); priv->clk = clk_get(dev, NULL); if (IS_ERR(priv->clk)) return PTR_ERR(priv->clk); diff --git a/drivers/serial/serial_cadence.c b/drivers/serial/serial_cadence.c index 6b48a48d1f..36dfa20841 100644 --- a/drivers/serial/serial_cadence.c +++ b/drivers/serial/serial_cadence.c @@ -216,6 +216,7 @@ static int cadence_clocksource_clock_change(struct notifier_block *nb, static int cadence_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; struct cadence_serial_priv *priv; struct cadence_serial_devtype_data *devtype; @@ -239,11 +240,12 @@ static int cadence_serial_probe(struct device_d *dev) if (devtype->mode & CADENCE_MODE_CLK_REF_DIV) clk_set_rate(priv->clk, clk_get_rate(priv->clk) / 8); - priv->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->regs)) { - ret = PTR_ERR(priv->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto err_free; } + priv->regs = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = cadence_serial_tstc; diff --git a/drivers/serial/serial_digic.c b/drivers/serial/serial_digic.c index 235ea0ff47..06b6e15e0c 100644 --- a/drivers/serial/serial_digic.c +++ b/drivers/serial/serial_digic.c @@ -101,10 +101,14 @@ static int digic_serial_tstc(struct console_device *cdev) static int digic_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; cdev = xzalloc(sizeof(struct console_device)); - dev->priv = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + dev->priv = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = &digic_serial_tstc; cdev->putc = &digic_serial_putc; diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c index 68b438b0bb..f140310fdc 100644 --- a/drivers/serial/serial_imx.c +++ b/drivers/serial/serial_imx.c @@ -55,6 +55,7 @@ static struct imx_serial_devtype_data imx21_data = { struct imx_serial_priv { struct console_device cdev; int baudrate; + int dte_mode; struct notifier_block notify; void __iomem *regs; struct clk *clk; @@ -93,9 +94,12 @@ static int imx_serial_init_port(struct console_device *cdev) writel(0, regs + UBMR); writel(0, regs + priv->devtype->uts); - /* Configure FIFOs */ - writel(0xa81, regs + UFCR); + val = 0xa81; + if (priv->dte_mode) + val |= UFCR_DCEDTE; + + writel(val, regs + UFCR); if (priv->devtype->onems) @@ -202,6 +206,7 @@ static int imx_clocksource_clock_change(struct notifier_block *nb, static int imx_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; struct imx_serial_priv *priv; uint32_t val; @@ -224,7 +229,10 @@ static int imx_serial_probe(struct device_d *dev) goto err_free; } - priv->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = imx_serial_tstc; cdev->putc = imx_serial_putc; @@ -240,6 +248,9 @@ static int imx_serial_probe(struct device_d *dev) } } + if (of_property_read_bool(dev->device_node, "fsl,dte-mode")) + priv->dte_mode = 1; + imx_serial_init_port(cdev); /* Enable UART */ diff --git a/drivers/serial/serial_mpc5xxx.c b/drivers/serial/serial_mpc5xxx.c index 711163cefd..cc63a84c68 100644 --- a/drivers/serial/serial_mpc5xxx.c +++ b/drivers/serial/serial_mpc5xxx.c @@ -145,12 +145,14 @@ static int mpc5xxx_serial_tstc (struct console_device *cdev) static int mpc5xxx_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; cdev = xzalloc(sizeof(struct console_device)); - dev->priv = dev_request_mem_region(dev, 0); - if (IS_ERR(dev->priv)) - return PTR_ERR(dev->priv); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + dev->priv = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = mpc5xxx_serial_tstc; cdev->putc = mpc5xxx_serial_putc; diff --git a/drivers/serial/serial_netx.c b/drivers/serial/serial_netx.c index c659cfaaf3..55ed89bf92 100644 --- a/drivers/serial/serial_netx.c +++ b/drivers/serial/serial_netx.c @@ -133,10 +133,14 @@ static int netx_serial_tstc(struct console_device *cdev) static int netx_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; cdev = xzalloc(sizeof(struct console_device)); - dev->priv = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + dev->priv = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = netx_serial_tstc; cdev->putc = netx_serial_putc; diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index 1af226a76a..4ad52ea79c 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -321,6 +321,7 @@ static __maybe_unused struct ns16550_drvdata tegra_drvdata = { static int ns16550_init_iomem(struct device_d *dev, struct ns16550_priv *priv) { + struct resource *iores; struct resource *res; int width; @@ -328,9 +329,10 @@ static int ns16550_init_iomem(struct device_d *dev, struct ns16550_priv *priv) if (IS_ERR(res)) return PTR_ERR(res); - priv->mmiobase = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->mmiobase)) - return PTR_ERR(priv->mmiobase); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->mmiobase = IOMEM(iores->start); width = res->flags & IORESOURCE_MEM_TYPE_MASK; switch (width) { diff --git a/drivers/serial/serial_pl010.c b/drivers/serial/serial_pl010.c index 81cea776a6..06f9d2dcdc 100644 --- a/drivers/serial/serial_pl010.c +++ b/drivers/serial/serial_pl010.c @@ -135,10 +135,14 @@ static int pl010_tstc(struct console_device *cdev) static int pl010_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; cdev = xzalloc(sizeof(struct console_device)); - dev->priv = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + dev->priv = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = pl010_tstc; cdev->putc = pl010_putc; diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c index 20ac4beb96..1a4d7b4303 100644 --- a/drivers/serial/serial_pxa.c +++ b/drivers/serial/serial_pxa.c @@ -161,12 +161,16 @@ static int pxa_serial_setbaudrate(struct console_device *cdev, int baudrate) static int pxa_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; struct pxa_serial_priv *priv; priv = xzalloc(sizeof(*priv)); cdev = &priv->cdev; - priv->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); dev->priv = priv; cdev->dev = dev; diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c index 038193dcf4..0a6e22d971 100644 --- a/drivers/serial/serial_s3c.c +++ b/drivers/serial/serial_s3c.c @@ -176,12 +176,16 @@ static void s3c_serial_flush(struct console_device *cdev) static int s3c_serial_probe(struct device_d *dev) { + struct resource *iores; struct s3c_uart *priv; struct console_device *cdev; priv = xzalloc(sizeof(struct s3c_uart)); cdev = &priv->cdev; - priv->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); dev->priv = priv; cdev->dev = dev; cdev->tstc = s3c_serial_tstc; diff --git a/drivers/serial/stm-serial.c b/drivers/serial/stm-serial.c index 8bb242b14d..83328f4550 100644 --- a/drivers/serial/stm-serial.c +++ b/drivers/serial/stm-serial.c @@ -145,6 +145,7 @@ static int stm_serial_init_port(struct stm_priv *priv) static int stm_serial_probe(struct device_d *dev) { + struct resource *iores; struct stm_priv *priv; struct console_device *cdev; @@ -160,9 +161,10 @@ static int stm_serial_probe(struct device_d *dev) cdev->dev = dev; dev->priv = priv; - priv->base = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->base = IOMEM(iores->start); priv->clk = clk_get(dev, NULL); if (IS_ERR(priv->clk)) return PTR_ERR(priv->clk); diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index bf1add81fe..4506e2741d 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -206,6 +206,7 @@ static int altera_spi_transfer(struct spi_device *spi, struct spi_message *mesg) static int altera_spi_probe(struct device_d *dev) { + struct resource *iores; struct spi_master *master; struct altera_spi *altera_spi; struct spi_altera_master *pdata = dev->platform_data; @@ -221,9 +222,10 @@ static int altera_spi_probe(struct device_d *dev) master->num_chipselect = pdata->num_chipselect; master->bus_num = pdata->bus_num; - altera_spi->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(altera_spi->regs)) - return PTR_ERR(altera_spi->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + altera_spi->regs = IOMEM(iores->start); altera_spi->databits = pdata->databits; altera_spi->speed = pdata->speed; diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c index bdb39ef0cb..68b4c7c48e 100644 --- a/drivers/spi/ath79_spi.c +++ b/drivers/spi/ath79_spi.c @@ -233,6 +233,7 @@ static void ath79_spi_disable(struct ath79_spi *sp) static int ath79_spi_probe(struct device_d *dev) { + struct resource *iores; struct spi_master *master; struct ath79_spi *ath79_spi; @@ -263,7 +264,10 @@ static int ath79_spi_probe(struct device_d *dev) master->num_chipselect = num_cs; } - ath79_spi->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ath79_spi->regs = IOMEM(iores->start); /* enable gpio mode */ ath79_spi_enable(ath79_spi); diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index 0bf9d08b83..3f2c527d14 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -371,6 +371,7 @@ err: static int atmel_spi_probe(struct device_d *dev) { + struct resource *iores; int ret = 0; int i; struct spi_master *master; @@ -399,7 +400,10 @@ static int atmel_spi_probe(struct device_d *dev) master->transfer = atmel_spi_transfer; master->num_chipselect = pdata->num_chipselect; as->cs_pins = pdata->chipselect; - as->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + as->regs = IOMEM(iores->start); for (i = 0; i < master->num_chipselect; i++) { ret = gpio_request(as->cs_pins[i], dev_name(dev)); diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c index 2e489674d8..5bd1845fbb 100644 --- a/drivers/spi/imx_spi.c +++ b/drivers/spi/imx_spi.c @@ -538,6 +538,7 @@ static int imx_spi_dt_probe(struct imx_spi *imx) static int imx_spi_probe(struct device_d *dev) { + struct resource *iores; struct spi_master *master; struct imx_spi *imx; struct spi_imx_master *pdata = dev->platform_data; @@ -574,7 +575,10 @@ static int imx_spi_probe(struct device_d *dev) imx->chipselect = devdata->chipselect; imx->xchg_single = devdata->xchg_single; imx->do_transfer = devdata->do_transfer; - imx->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + imx->regs = IOMEM(iores->start); if (devdata->init) devdata->init(imx); diff --git a/drivers/spi/mvebu_spi.c b/drivers/spi/mvebu_spi.c index bc0655f6a0..c679e64c42 100644 --- a/drivers/spi/mvebu_spi.c +++ b/drivers/spi/mvebu_spi.c @@ -332,6 +332,7 @@ static struct of_device_id mvebu_spi_dt_ids[] = { static int mvebu_spi_probe(struct device_d *dev) { + struct resource *iores; struct spi_master *master; struct mvebu_spi *priv; const struct of_device_id *match; @@ -342,11 +343,12 @@ static int mvebu_spi_probe(struct device_d *dev) return -EINVAL; priv = xzalloc(sizeof(*priv)); - priv->base = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->base)) { - ret = PTR_ERR(priv->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto err_free; } + priv->base = IOMEM(iores->start); priv->set_baudrate = (void *)match->data; priv->clk = clk_get(dev, NULL); if (IS_ERR(priv->clk)) { diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 9fe2fd4eaf..420d122b55 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -250,6 +250,7 @@ static int mxs_spi_transfer(struct spi_device *spi, struct spi_message *mesg) static int mxs_spi_probe(struct device_d *dev) { + struct resource *iores; struct spi_master *master; struct mxs_spi *mxs; @@ -264,9 +265,10 @@ static int mxs_spi_probe(struct device_d *dev) master->num_chipselect = 3; mxs->mode = SPI_CPOL | SPI_CPHA; - mxs->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(mxs->regs)) - return PTR_ERR(mxs->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mxs->regs = IOMEM(iores->start); mxs->clk = clk_get(dev, NULL); if (IS_ERR(mxs->clk)) diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 8e29fde0bb..f63039718f 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -358,6 +358,7 @@ static int omap3_spi_probe_dt(struct device_d *dev, struct omap3_spi_master *oma static int omap3_spi_probe(struct device_d *dev) { + struct resource *iores; struct spi_master *master; struct omap3_spi_master *omap3_master; struct omap_spi_drvdata *devtype; @@ -399,7 +400,10 @@ static int omap3_spi_probe(struct device_d *dev) master->setup = omap3_spi_setup; master->transfer = omap3_spi_transfer; - omap3_master->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + omap3_master->base = IOMEM(iores->start); omap3_master->regs = omap3_master->base; omap3_master->regs += devtype->register_offset; diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c index b36ef19c8a..5f6bebc733 100644 --- a/drivers/usb/gadget/at91_udc.c +++ b/drivers/usb/gadget/at91_udc.c @@ -1379,6 +1379,7 @@ static void at91_udc_gadget_poll(struct usb_gadget *gadget) static int __init at91udc_probe(struct device_d *dev) { + struct resource *iores; struct at91_udc *udc = &controller; int retval; @@ -1422,7 +1423,10 @@ static int __init at91udc_probe(struct device_d *dev) udc->ep[3].maxpacket = 64; } - udc->udp_baseaddr = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + udc->udp_baseaddr = IOMEM(iores->start); if (IS_ERR(udc->udp_baseaddr)) { retval = PTR_ERR(udc->udp_baseaddr); goto fail0a; diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index bf28f7c22a..0df08c9a2b 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -23,6 +23,7 @@ #include <clock.h> #include <ioctl.h> #include <libbb.h> +#include <bbu.h> #include <boot.h> #include <dma.h> #include <fs.h> @@ -686,7 +687,21 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req, const char *cmd } if (filetype == filetype_ubi) { - char *cmd = asprintf("ubiformat -y -f %s %s", FASTBOOT_TMPFILE, filename); + char *cmd; + int fd; + struct mtd_info_user meminfo; + + fd = open(filename, O_RDONLY); + if (fd < 0) + goto copy; + + ret = ioctl(fd, MEMGETINFO, &meminfo); + close(fd); + /* Not a MTD device, ubiformat is not a valid operation */ + if (ret) + goto copy; + + cmd = asprintf("ubiformat -y -f %s %s", FASTBOOT_TMPFILE, filename); fastboot_tx_print(f_fb, "INFOThis is an UBI image..."); @@ -702,6 +717,37 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req, const char *cmd goto out; } + if (IS_ENABLED(CONFIG_BAREBOX_UPDATE) && filetype_is_barebox_image(filetype)) { + struct bbu_data data = { + .devicefile = filename, + .imagefile = FASTBOOT_TMPFILE, + .flags = BBU_FLAG_YES, + }; + + if (!barebox_update_handler_exists(&data)) + goto copy; + + fastboot_tx_print(f_fb, "INFOThis is a barebox image..."); + + data.image = read_file(data.imagefile, &data.len); + if (!data.image) { + fastboot_tx_print(f_fb, "FAILreading barebox"); + return; + } + + ret = barebox_update(&data); + + free(data.image); + + if (ret) { + fastboot_tx_print(f_fb, "FAILupdate barebox: %s", strerror(-ret)); + return; + } + + goto out; + } + +copy: ret = copy_file(FASTBOOT_TMPFILE, filename, 1); if (ret) { fastboot_tx_print(f_fb, "FAILwrite partition: %s", strerror(-ret)); diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c index 3db3480cad..372c07b418 100644 --- a/drivers/usb/gadget/pxa27x_udc.c +++ b/drivers/usb/gadget/pxa27x_udc.c @@ -1449,12 +1449,14 @@ static struct pxa_udc memory = { static int __init pxa_udc_probe(struct device_d *dev) { + struct resource *iores; struct pxa_udc *udc = &memory; int gpio, ret; - udc->regs = dev_request_mem_region(dev, 0); - if (!udc->regs) - return -ENXIO; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + udc->regs = IOMEM(iores->start); udc->dev = dev; udc->mach = dev->platform_data; diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c index 11b1a894e1..cc9636c4b7 100644 --- a/drivers/usb/host/ehci-atmel.c +++ b/drivers/usb/host/ehci-atmel.c @@ -46,6 +46,7 @@ static void atmel_stop_clock(void) static int atmel_ehci_probe(struct device_d *dev) { + struct resource *iores; struct ehci_data data; iclk = clk_get(dev, "ehci_clk"); @@ -67,7 +68,10 @@ static int atmel_ehci_probe(struct device_d *dev) data.flags = 0; - data.hccr = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + data.hccr = IOMEM(iores->start); ehci_register(dev, &data); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 91c6d73c30..b0bf9225ec 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1005,7 +1005,7 @@ static struct int_queue *ehci_create_int_queue(struct usb_device *dev, struct usb_host *host = dev->host; struct ehci_priv *ehci = to_ehci(host); struct int_queue *result = NULL; - uint32_t i, toggle; + uint32_t i; struct QH *list = ehci->periodic_queue; /* @@ -1057,8 +1057,6 @@ static struct int_queue *ehci_create_int_queue(struct usb_device *dev, memset(result->first, 0, sizeof(struct QH) * queuesize); memset(result->tds, 0, sizeof(struct qTD) * queuesize); - toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); - for (i = 0; i < queuesize; i++) { struct QH *qh = result->first + i; struct qTD *td = result->tds + i; @@ -1073,7 +1071,6 @@ static struct int_queue *ehci_create_int_queue(struct usb_device *dev, qh->qh_endpt1 = cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */ (usb_maxpacket(dev, pipe) << 16) | /* MPS */ - (1 << 14) | QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */ (usb_pipedevice(pipe) << 0)); @@ -1092,7 +1089,6 @@ static struct int_queue *ehci_create_int_queue(struct usb_device *dev, "communication direction is '%s'\n", usb_pipein(pipe) ? "in" : "out"); td->qt_token = cpu_to_hc32( - QT_TOKEN_DT(toggle) | (elementsize << 16) | ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */ 0x80); /* active */ @@ -1108,7 +1104,6 @@ static struct int_queue *ehci_create_int_queue(struct usb_device *dev, cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff); *buf = buffer + i * elementsize; - toggle ^= 1; } if (ehci->periodic_schedules > 0) { @@ -1144,8 +1139,7 @@ static void *ehci_poll_int_queue(struct usb_device *dev, { struct QH *cur = queue->current; struct qTD *cur_td; - uint32_t token, toggle; - unsigned long pipe = queue->pipe; + uint32_t token; /* depleted queue */ if (cur == NULL) { @@ -1162,9 +1156,6 @@ static void *ehci_poll_int_queue(struct usb_device *dev, return NULL; } - toggle = QT_TOKEN_GET_DT(token); - usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle); - if (!(cur->qh_link & QH_LINK_TERMINATE)) queue->current++; else @@ -1183,7 +1174,6 @@ static int ehci_destroy_int_queue(struct usb_device *dev, struct usb_host *host = dev->host; struct ehci_priv *ehci = to_ehci(host); struct QH *cur = ehci->periodic_queue; - uint64_t start; if (disable_periodic(ehci) < 0) { dev_err(&dev->dev, @@ -1192,7 +1182,6 @@ static int ehci_destroy_int_queue(struct usb_device *dev, } ehci->periodic_schedules--; - start = get_time_ns(); while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) { dev_dbg(&dev->dev, "considering %p, with qh_link %x\n", @@ -1205,12 +1194,6 @@ static int ehci_destroy_int_queue(struct usb_device *dev, break; } cur = NEXT_QH(cur); - if (is_timeout_non_interruptible(start, 500 * MSECOND)) { - dev_err(&dev->dev, - "Timeout destroying interrupt endpoint queue\n"); - result = -ETIMEDOUT; - goto out; - } } if (ehci->periodic_schedules > 0) { @@ -1334,6 +1317,7 @@ int ehci_register(struct device_d *dev, struct ehci_data *data) static int ehci_probe(struct device_d *dev) { + struct resource *iores; struct ehci_data data = {}; struct ehci_platform_data *pdata = dev->platform_data; struct device_node *dn = dev->device_node; @@ -1350,12 +1334,17 @@ static int ehci_probe(struct device_d *dev) */ data.flags = EHCI_HAS_TT; - data.hccr = dev_request_mem_region(dev, 0); - if (IS_ERR(data.hccr)) - return PTR_ERR(data.hccr); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + data.hccr = IOMEM(iores->start); - if (dev->num_resources > 1) - data.hcor = dev_request_mem_region(dev, 1); + if (dev->num_resources > 1) { + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + data.hcor = IOMEM(iores->start); + } else data.hcor = NULL; diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 1d511b7563..612c3a1033 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1793,6 +1793,7 @@ static int ohci_init(struct usb_host *host) static int ohci_probe(struct device_d *dev) { + struct resource *iores; struct usb_host *host; struct ohci *ohci; @@ -1818,9 +1819,10 @@ static int ohci_probe(struct device_d *dev) usb_register_host(host); - ohci->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(ohci->regs)) - return PTR_ERR(ohci->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ohci->regs = IOMEM(iores->start); return 0; } diff --git a/drivers/usb/host/xhci-hcd.c b/drivers/usb/host/xhci-hcd.c index a44a1a4dff..2b808cc875 100644 --- a/drivers/usb/host/xhci-hcd.c +++ b/drivers/usb/host/xhci-hcd.c @@ -1509,9 +1509,13 @@ int xhci_register(struct device_d *dev, struct xhci_data *data) static int xhci_probe(struct device_d *dev) { + struct resource *iores; struct xhci_data data = {}; - data.regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + data.regs = IOMEM(iores->start); return xhci_register(dev, &data); } diff --git a/drivers/usb/imx/chipidea-imx.c b/drivers/usb/imx/chipidea-imx.c index a1c36cf644..a799abe4ee 100644 --- a/drivers/usb/imx/chipidea-imx.c +++ b/drivers/usb/imx/chipidea-imx.c @@ -216,6 +216,7 @@ static int ci_register_otg_device(struct imx_chipidea *ci) static int imx_chipidea_probe(struct device_d *dev) { + struct resource *iores; struct imxusb_platformdata *pdata = dev->platform_data; int ret; void __iomem *base; @@ -245,9 +246,10 @@ static int imx_chipidea_probe(struct device_d *dev) if (!IS_ERR(ci->vbus)) regulator_enable(ci->vbus); - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); ci->base = base; diff --git a/drivers/usb/imx/imx-usb-misc.c b/drivers/usb/imx/imx-usb-misc.c index af1a32110c..d938a2cd87 100644 --- a/drivers/usb/imx/imx-usb-misc.c +++ b/drivers/usb/imx/imx-usb-misc.c @@ -545,6 +545,7 @@ int imx_usbmisc_port_post_init(int port, unsigned flags) static int imx_usbmisc_probe(struct device_d *dev) { + struct resource *iores; struct imx_usb_misc_data *devtype; int ret; @@ -552,9 +553,10 @@ static int imx_usbmisc_probe(struct device_d *dev) if (ret) return ret; - usbmisc_base = dev_request_mem_region(dev, 0); - if (!usbmisc_base) - return -ENOMEM; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + usbmisc_base = IOMEM(iores->start); imxusbmisc_data = devtype; diff --git a/drivers/usb/imx/imx-usb-phy.c b/drivers/usb/imx/imx-usb-phy.c index 837c1b5176..1aa12be29d 100644 --- a/drivers/usb/imx/imx-usb-phy.c +++ b/drivers/usb/imx/imx-usb-phy.c @@ -65,20 +65,23 @@ static int imx_usbphy_enable(struct imx_usbphy *imxphy) static int imx_usbphy_probe(struct device_d *dev) { + struct resource *iores; int ret; struct imx_usbphy *imxphy; imxphy = xzalloc(sizeof(*imxphy)); - imxphy->base = dev_request_mem_region(dev, 0); - if (!imxphy->base) { - ret = -ENODEV; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto err_free; } + imxphy->base = IOMEM(iores->start); imxphy->clk = clk_get(dev, NULL); if (IS_ERR(imxphy->clk)) { dev_err(dev, "could not get clk: %s\n", strerrorp(imxphy->clk)); + ret = PTR_ERR(imxphy->clk); goto err_clk; } diff --git a/drivers/usb/musb/musb_dsps.c b/drivers/usb/musb/musb_dsps.c index 958aeec685..431b97ea9b 100644 --- a/drivers/usb/musb/musb_dsps.c +++ b/drivers/usb/musb/musb_dsps.c @@ -349,6 +349,7 @@ static int dsps_register_otg_device(struct dsps_glue *glue) static int dsps_probe(struct device_d *dev) { + struct resource *iores; struct musb_hdrc_platform_data *pdata; struct musb_hdrc_config *config; struct device_node *dn = dev->device_node; @@ -378,13 +379,15 @@ static int dsps_probe(struct device_d *dev) pdata = &glue->pdata; - glue->musb.mregs = dev_request_mem_region(dev, 0); - if (IS_ERR(glue->musb.mregs)) - return PTR_ERR(glue->musb.mregs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + glue->musb.mregs = IOMEM(iores->start); - glue->musb.ctrl_base = dev_request_mem_region(dev, 1); - if (IS_ERR(glue->musb.ctrl_base)) - return PTR_ERR(glue->musb.ctrl_base); + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + glue->musb.ctrl_base = IOMEM(iores->start); glue->musb.controller = dev; diff --git a/drivers/usb/musb/phy-am335x-control.c b/drivers/usb/musb/phy-am335x-control.c index 809c5182c0..5fd8802b3a 100644 --- a/drivers/usb/musb/phy-am335x-control.c +++ b/drivers/usb/musb/phy-am335x-control.c @@ -129,6 +129,7 @@ EXPORT_SYMBOL(am335x_get_phy_control); static int am335x_control_usb_probe(struct device_d *dev) { + struct resource *iores; /*struct resource *res;*/ struct am335x_control_usb *ctrl_usb; const struct phy_control *phy_ctrl; @@ -146,13 +147,15 @@ static int am335x_control_usb_probe(struct device_d *dev) ctrl_usb->dev = dev; - ctrl_usb->phy_reg = dev_request_mem_region(dev, 0); - if (IS_ERR(ctrl_usb->phy_reg)) - return PTR_ERR(ctrl_usb->phy_reg); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ctrl_usb->phy_reg = IOMEM(iores->start); - ctrl_usb->wkup = dev_request_mem_region(dev, 1); - if (IS_ERR(ctrl_usb->wkup)) - return PTR_ERR(ctrl_usb->wkup); + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ctrl_usb->wkup = IOMEM(iores->start); spin_lock_init(&ctrl_usb->lock); ctrl_usb->phy_ctrl = *phy_ctrl; diff --git a/drivers/usb/musb/phy-am335x.c b/drivers/usb/musb/phy-am335x.c index 2d58bbedb4..204e51054d 100644 --- a/drivers/usb/musb/phy-am335x.c +++ b/drivers/usb/musb/phy-am335x.c @@ -30,17 +30,19 @@ static int am335x_init(struct usb_phy *phy) static int am335x_phy_probe(struct device_d *dev) { + struct resource *iores; int ret; am_usbphy = xzalloc(sizeof(*am_usbphy)); if (!am_usbphy) return -ENOMEM; - am_usbphy->base = dev_request_mem_region(dev, 0); - if (!am_usbphy->base) { - ret = -ENODEV; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto err_free; } + am_usbphy->base = IOMEM(iores->start); am_usbphy->phy_ctrl = am335x_get_phy_control(dev); if (!am_usbphy->phy_ctrl) diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c index 76116af1da..555799ea4b 100644 --- a/drivers/video/atmel_lcdfb_core.c +++ b/drivers/video/atmel_lcdfb_core.c @@ -245,6 +245,7 @@ static struct fb_ops atmel_lcdc_ops = { int atmel_lcdc_register(struct device_d *dev, struct atmel_lcdfb_devdata *data) { + struct resource *iores; struct atmel_lcdfb_info *sinfo; struct atmel_lcdfb_platform_data *pdata = dev->platform_data; int ret = 0; @@ -257,9 +258,10 @@ int atmel_lcdc_register(struct device_d *dev, struct atmel_lcdfb_devdata *data) sinfo = xzalloc(sizeof(*sinfo)); sinfo->pdata = pdata; - sinfo->mmio = dev_request_mem_region(dev, 0); - if (IS_ERR(sinfo->mmio)) - return PTR_ERR(sinfo->mmio); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + sinfo->mmio = IOMEM(iores->start); sinfo->dev_data = data; diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c index 03d191a331..7c3a800149 100644 --- a/drivers/video/imx-ipu-fb.c +++ b/drivers/video/imx-ipu-fb.c @@ -988,6 +988,7 @@ static int sdc_fb_register_overlay(struct ipu_fb_info *fbi, void *fb) static int imxfb_probe(struct device_d *dev) { + struct resource *iores; struct ipu_fb_info *fbi; struct fb_info *info; const struct imx_ipu_fb_platform_data *pdata = dev->platform_data; @@ -1003,9 +1004,10 @@ static int imxfb_probe(struct device_d *dev) if (IS_ERR(fbi->clk)) return PTR_ERR(fbi->clk); - fbi->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(fbi->regs)) - return PTR_ERR(fbi->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + fbi->regs = IOMEM(iores->start); fbi->dev = dev; fbi->enable = pdata->enable; fbi->disp_data_fmt = pdata->disp_data_fmt; diff --git a/drivers/video/imx-ipu-v3/imx-hdmi.c b/drivers/video/imx-ipu-v3/imx-hdmi.c index 25fcb0c739..8b251a52ea 100644 --- a/drivers/video/imx-ipu-v3/imx-hdmi.c +++ b/drivers/video/imx-ipu-v3/imx-hdmi.c @@ -1271,6 +1271,7 @@ static int dw_hdmi_ioctl(struct vpl *vpl, unsigned int port, static int dw_hdmi_probe(struct device_d *dev) { + struct resource *iores; struct device_node *np = dev->device_node; struct dw_hdmi *hdmi; int ret; @@ -1293,9 +1294,10 @@ static int dw_hdmi_probe(struct device_d *dev) hdmi->ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); - hdmi->regs = dev_request_mem_region(dev, 0); - if (!hdmi->regs) - return -EBUSY; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + hdmi->regs = IOMEM(iores->start); hdmi->isfr_clk = clk_get(hdmi->dev, "isfr"); if (IS_ERR(hdmi->isfr_clk)) { diff --git a/drivers/video/imx-ipu-v3/ipu-common.c b/drivers/video/imx-ipu-v3/ipu-common.c index 70bb0e59b6..1811e50227 100644 --- a/drivers/video/imx-ipu-v3/ipu-common.c +++ b/drivers/video/imx-ipu-v3/ipu-common.c @@ -751,6 +751,7 @@ err_register: static int ipu_probe(struct device_d *dev) { + struct resource *iores; struct ipu_soc *ipu; void __iomem *ipu_base; int i, ret; @@ -760,9 +761,10 @@ static int ipu_probe(struct device_d *dev) if (ret) return ret; - ipu_base = dev_request_mem_region(dev, 0); - if (!ipu_base) - return -EBUSY; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ipu_base = IOMEM(iores->start); ipu = xzalloc(sizeof(*ipu)); diff --git a/drivers/video/imx.c b/drivers/video/imx.c index 11d49c6cfb..78cb5c0ca2 100644 --- a/drivers/video/imx.c +++ b/drivers/video/imx.c @@ -539,6 +539,7 @@ static int imxfb_register_overlay(struct imxfb_info *fbi, void *fb) static int imxfb_probe(struct device_d *dev) { + struct resource *iores; struct imxfb_info *fbi; struct fb_info *info; struct imx_fb_platform_data *pdata = dev->platform_data; @@ -573,9 +574,10 @@ static int imxfb_probe(struct device_d *dev) return PTR_ERR(fbi->ipg_clk); fbi->mode = pdata->mode; - fbi->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(fbi->regs)) - return PTR_ERR(fbi->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + fbi->regs = IOMEM(iores->start); fbi->pcr = pdata->mode->pcr; fbi->pwmr = pdata->pwmr; diff --git a/drivers/video/pxa.c b/drivers/video/pxa.c index e76404d9c9..d444e0981f 100644 --- a/drivers/video/pxa.c +++ b/drivers/video/pxa.c @@ -487,6 +487,7 @@ static struct fb_ops pxafb_ops = { static int pxafb_probe(struct device_d *dev) { + struct resource *iores; struct pxafb_platform_data *pdata = dev->platform_data; struct pxafb_info *fbi; struct fb_info *info; @@ -499,9 +500,10 @@ static int pxafb_probe(struct device_d *dev) info = &fbi->info; fbi->mode = pdata->mode; - fbi->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(fbi->regs)) - return PTR_ERR(fbi->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + fbi->regs = IOMEM(iores->start); fbi->dev = dev; fbi->lcd_power = pdata->lcd_power; diff --git a/drivers/video/s3c24xx.c b/drivers/video/s3c24xx.c index b1883e232c..84ed0aee39 100644 --- a/drivers/video/s3c24xx.c +++ b/drivers/video/s3c24xx.c @@ -358,13 +358,17 @@ static struct s3cfb_info fbi = { static int s3cfb_probe(struct device_d *hw_dev) { + struct resource *iores; struct s3c_fb_platform_data *pdata = hw_dev->platform_data; int ret; if (! pdata) return -ENODEV; - fbi.base = dev_request_mem_region(hw_dev, 0); + iores = dev_request_mem_resource(hw_dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + fbi.base = IOMEM(iores->start); writel(0, fbi.base + LCDCON1); writel(0, fbi.base + LCDCON5); /* FIXME not 0 for some displays */ diff --git a/drivers/video/stm.c b/drivers/video/stm.c index e5c1ef3974..0c190d36ae 100644 --- a/drivers/video/stm.c +++ b/drivers/video/stm.c @@ -505,6 +505,7 @@ static struct imxfb_info fbi = { static int stmfb_probe(struct device_d *hw_dev) { + struct resource *iores; struct imx_fb_platformdata *pdata = hw_dev->platform_data; int ret; @@ -513,7 +514,10 @@ static int stmfb_probe(struct device_d *hw_dev) /* add runtime hardware info */ fbi.hw_dev = hw_dev; - fbi.base = dev_request_mem_region(hw_dev, 0); + iores = dev_request_mem_resource(hw_dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + fbi.base = IOMEM(iores->start); fbi.clk = clk_get(hw_dev, NULL); if (IS_ERR(fbi.clk)) return PTR_ERR(fbi.clk); diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c index dfabee230c..03dc83408e 100644 --- a/drivers/watchdog/davinci_wdt.c +++ b/drivers/watchdog/davinci_wdt.c @@ -131,14 +131,16 @@ static int davinci_wdt_set_timeout(struct watchdog *wd, unsigned timeout) static int davinci_wdt_probe(struct device_d *dev) { + struct resource *iores; int ret = 0; struct davinci_wdt *davinci_wdt; davinci_wdt = xzalloc(sizeof(*davinci_wdt)); - davinci_wdt->base = dev_request_mem_region(dev, 0); - if (IS_ERR(davinci_wdt->base)) - return PTR_ERR(davinci_wdt->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + davinci_wdt->base = IOMEM(iores->start); davinci_wdt->clk = clk_get(dev, NULL); if (WARN_ON(IS_ERR(davinci_wdt->clk))) diff --git a/drivers/watchdog/im28wd.c b/drivers/watchdog/im28wd.c index 3510776a3a..1956fdb73d 100644 --- a/drivers/watchdog/im28wd.c +++ b/drivers/watchdog/im28wd.c @@ -189,13 +189,15 @@ static void __maybe_unused imx28_detect_reset_source(const struct imx28_wd *p) static int imx28_wd_probe(struct device_d *dev) { + struct resource *iores; struct imx28_wd *priv; int rc; priv = xzalloc(sizeof(struct imx28_wd)); - priv->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->regs)) - return PTR_ERR(priv->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); priv->wd.set_timeout = imx28_watchdog_set_timeout; priv->wd.dev = dev; diff --git a/drivers/watchdog/imxwd.c b/drivers/watchdog/imxwd.c index 1952548fa7..03e116ea20 100644 --- a/drivers/watchdog/imxwd.c +++ b/drivers/watchdog/imxwd.c @@ -173,6 +173,7 @@ static int imx21_wd_init(struct imx_wd *priv) static int imx_wd_probe(struct device_d *dev) { + struct resource *iores; struct imx_wd *priv; void *ops; int ret; @@ -182,11 +183,12 @@ static int imx_wd_probe(struct device_d *dev) return ret; priv = xzalloc(sizeof(struct imx_wd)); - priv->base = dev_request_mem_region(dev, 0); - if (!priv->base) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return -ENODEV; + return PTR_ERR(iores); } + priv->base = IOMEM(iores->start); priv->ops = ops; priv->wd.set_timeout = imx_watchdog_set_timeout; priv->wd.dev = dev; diff --git a/drivers/watchdog/jz4740.c b/drivers/watchdog/jz4740.c index 3d45b46ee2..f28bb9177a 100644 --- a/drivers/watchdog/jz4740.c +++ b/drivers/watchdog/jz4740.c @@ -67,14 +67,16 @@ static void __noreturn jz4740_reset_soc(struct restart_handler *rst) static int jz4740_wdt_probe(struct device_d *dev) { + struct resource *iores; struct jz4740_wdt_drvdata *priv; priv = xzalloc(sizeof(struct jz4740_wdt_drvdata)); - priv->base = dev_request_mem_region(dev, 0); - if (!priv->base) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return -ENODEV; + return PTR_ERR(iores); } + priv->base = IOMEM(iores->start); dev->priv = priv; diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 06301b3b9e..27fdfd13a0 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -154,6 +154,7 @@ static int omap_wdt_set_timeout(struct watchdog *wdog, static int omap_wdt_probe(struct device_d *dev) { + struct resource *iores; struct omap_wdt_dev *wdev; int ret; @@ -162,11 +163,12 @@ static int omap_wdt_probe(struct device_d *dev) wdev->wdt_trgr_pattern = 0x1234; /* reserve static register mappings */ - wdev->base = dev_request_mem_region(dev, 0); - if (IS_ERR(wdev->base)) { - ret = PTR_ERR(wdev->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto error; } + wdev->base = IOMEM(iores->start); wdev->timeout = TIMER_MARGIN_DEFAULT; |