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-rw-r--r--dts/Bindings/arc/archs-idu-intc.txt46
-rw-r--r--dts/Bindings/arc/archs-intc.txt22
-rw-r--r--dts/Bindings/arc/axs101.txt7
-rw-r--r--dts/Bindings/arc/axs103.txt8
4 files changed, 83 insertions, 0 deletions
diff --git a/dts/Bindings/arc/archs-idu-intc.txt b/dts/Bindings/arc/archs-idu-intc.txt
new file mode 100644
index 000000000..0dcb7c7d3
--- /dev/null
+++ b/dts/Bindings/arc/archs-idu-intc.txt
@@ -0,0 +1,46 @@
+* ARC-HS Interrupt Distribution Unit
+
+ This optional 2nd level interrupt controller can be used in SMP configurations for
+ dynamic IRQ routing, load balancing of common/external IRQs towards core intc.
+
+Properties:
+
+- compatible: "snps,archs-idu-intc"
+- interrupt-controller: This is an interrupt controller.
+- interrupt-parent: <reference to parent core intc>
+- #interrupt-cells: Must be <2>.
+- interrupts: <...> specifies the upstream core irqs
+
+ First cell specifies the "common" IRQ from peripheral to IDU
+ Second cell specifies the irq distribution mode to cores
+ 0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
+
+ intc accessed via the special ARC AUX register interface, hence "reg" property
+ is not specified.
+
+Example:
+ core_intc: core-interrupt-controller {
+ compatible = "snps,archs-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ idu_intc: idu-interrupt-controller {
+ compatible = "snps,archs-idu-intc";
+ interrupt-controller;
+ interrupt-parent = <&core_intc>;
+
+ /*
+ * <hwirq distribution>
+ * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
+ */
+ #interrupt-cells = <2>;
+
+ /* upstream core irqs: downstream these are "COMMON" irq 0,1.. */
+ interrupts = <24 25 26 27 28 29 30 31>;
+ };
+
+ some_device: serial@c0fc1000 {
+ interrupt-parent = <&idu_intc>;
+ interrupts = <0 0>; /* upstream idu IRQ #24, Round Robin */
+ };
diff --git a/dts/Bindings/arc/archs-intc.txt b/dts/Bindings/arc/archs-intc.txt
new file mode 100644
index 000000000..69f326d6a
--- /dev/null
+++ b/dts/Bindings/arc/archs-intc.txt
@@ -0,0 +1,22 @@
+* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)
+
+Properties:
+
+- compatible: "snps,archs-intc"
+- interrupt-controller: This is an interrupt controller.
+- #interrupt-cells: Must be <1>.
+
+ Single Cell "interrupts" property of a device specifies the IRQ number
+ between 16 to 256
+
+ intc accessed via the special ARC AUX register interface, hence "reg" property
+ is not specified.
+
+Example:
+
+ intc: interrupt-controller {
+ compatible = "snps,archs-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <16 17 18 19 20 21 22 23 24 25>;
+ };
diff --git a/dts/Bindings/arc/axs101.txt b/dts/Bindings/arc/axs101.txt
new file mode 100644
index 000000000..48290d517
--- /dev/null
+++ b/dts/Bindings/arc/axs101.txt
@@ -0,0 +1,7 @@
+Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings
+---------------------------------------------------------------------------
+
+SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon
+
+Required root node properties:
+ - compatible = "snps,axs101", "snps,arc-sdp";
diff --git a/dts/Bindings/arc/axs103.txt b/dts/Bindings/arc/axs103.txt
new file mode 100644
index 000000000..6eea862e7
--- /dev/null
+++ b/dts/Bindings/arc/axs103.txt
@@ -0,0 +1,8 @@
+Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings
+---------------------------------------------------------------------------
+
+SDP Main Board with an AXC003 FPGA Card which can contain various flavours of
+HS38x cores.
+
+Required root node properties:
+ - compatible = "snps,axs103", "snps,arc-sdp";