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Diffstat (limited to 'dts/Bindings/arm/arm,trace-buffer-extension.yaml')
| -rw-r--r-- | dts/Bindings/arm/arm,trace-buffer-extension.yaml | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/dts/Bindings/arm/arm,trace-buffer-extension.yaml b/dts/Bindings/arm/arm,trace-buffer-extension.yaml new file mode 100644 index 0000000000..87128e7b7d --- /dev/null +++ b/dts/Bindings/arm/arm,trace-buffer-extension.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright 2021, Arm Ltd +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Trace Buffer Extensions + +maintainers: + - Anshuman Khandual <anshuman.khandual@arm.com> + +description: | + Arm Trace Buffer Extension (TRBE) is a per CPU component + for storing trace generated on the CPU to memory. It is + accessed via CPU system registers. The software can verify + if it is permitted to use the component by checking the + TRBIDR register. + +properties: + $nodename: + const: trbe + + compatible: + items: + - const: arm,trace-buffer-extension + + interrupts: + description: | + Exactly 1 PPI must be listed. For heterogeneous systems where + TRBE is only supported on a subset of the CPUs, please consult + the arm,gic-v3 binding for details on describing a PPI partition. + maxItems: 1 + +required: + - compatible + - interrupts + +additionalProperties: false + +examples: + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + trbe { + compatible = "arm,trace-buffer-extension"; + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; + }; +... |