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-rw-r--r--dts/Bindings/arm/cpus.yaml219
1 files changed, 164 insertions, 55 deletions
diff --git a/dts/Bindings/arm/cpus.yaml b/dts/Bindings/arm/cpus.yaml
index cb30895e3b..cc5a21b47e 100644
--- a/dts/Bindings/arm/cpus.yaml
+++ b/dts/Bindings/arm/cpus.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/arm/cpus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: ARM CPUs bindings
+title: ARM CPUs
maintainers:
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
@@ -85,6 +85,10 @@ properties:
compatible:
enum:
+ - apple,avalanche
+ - apple,blizzard
+ - apple,icestorm
+ - apple,firestorm
- arm,arm710t
- arm,arm720t
- arm,arm740t
@@ -123,11 +127,26 @@ properties:
- arm,cortex-a12
- arm,cortex-a15
- arm,cortex-a17
+ - arm,cortex-a32
+ - arm,cortex-a34
+ - arm,cortex-a35
- arm,cortex-a53
- arm,cortex-a55
- arm,cortex-a57
+ - arm,cortex-a65
- arm,cortex-a72
- arm,cortex-a73
+ - arm,cortex-a75
+ - arm,cortex-a76
+ - arm,cortex-a77
+ - arm,cortex-a78
+ - arm,cortex-a78ae
+ - arm,cortex-a78c
+ - arm,cortex-a510
+ - arm,cortex-a520
+ - arm,cortex-a710
+ - arm,cortex-a715
+ - arm,cortex-a720
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
@@ -136,6 +155,16 @@ properties:
- arm,cortex-r4
- arm,cortex-r5
- arm,cortex-r7
+ - arm,cortex-r52
+ - arm,cortex-x1
+ - arm,cortex-x1c
+ - arm,cortex-x2
+ - arm,cortex-x3
+ - arm,cortex-x4
+ - arm,neoverse-e1
+ - arm,neoverse-n1
+ - arm,neoverse-n2
+ - arm,neoverse-v1
- brcm,brahma-b15
- brcm,brahma-b53
- brcm,vulcan
@@ -155,77 +184,99 @@ properties:
- nvidia,tegra194-carmel
- qcom,krait
- qcom,kryo
+ - qcom,kryo240
+ - qcom,kryo250
+ - qcom,kryo260
+ - qcom,kryo280
+ - qcom,kryo360
- qcom,kryo385
+ - qcom,kryo465
+ - qcom,kryo468
- qcom,kryo485
+ - qcom,kryo560
+ - qcom,kryo570
+ - qcom,kryo660
+ - qcom,kryo685
+ - qcom,kryo780
+ - qcom,oryon
- qcom,scorpion
enable-method:
- allOf:
- - $ref: '/schemas/types.yaml#/definitions/string'
- - oneOf:
- # On ARM v8 64-bit this property is required
- - enum:
- - psci
- - spin-table
- # On ARM 32-bit systems this property is optional
- - enum:
- - actions,s500-smp
- - allwinner,sun6i-a31
- - allwinner,sun8i-a23
- - allwinner,sun9i-a80-smp
- - allwinner,sun8i-a83t-smp
- - amlogic,meson8-smp
- - amlogic,meson8b-smp
- - arm,realview-smp
- - aspeed,ast2600-smp
- - brcm,bcm11351-cpu-method
- - brcm,bcm23550
- - brcm,bcm2836-smp
- - brcm,bcm63138
- - brcm,bcm-nsp-smp
- - brcm,brahma-b15
- - marvell,armada-375-smp
- - marvell,armada-380-smp
- - marvell,armada-390-smp
- - marvell,armada-xp-smp
- - marvell,98dx3236-smp
- - mediatek,mt6589-smp
- - mediatek,mt81xx-tz-smp
- - qcom,gcc-msm8660
- - qcom,kpss-acc-v1
- - qcom,kpss-acc-v2
- - renesas,apmu
- - renesas,r9a06g032-smp
- - rockchip,rk3036-smp
- - rockchip,rk3066-smp
- - socionext,milbeaut-m10v-smp
- - ste,dbx500-smp
+ $ref: /schemas/types.yaml#/definitions/string
+ oneOf:
+ # On ARM v8 64-bit this property is required
+ - enum:
+ - psci
+ - spin-table
+ # On ARM 32-bit systems this property is optional
+ - enum:
+ - actions,s500-smp
+ - allwinner,sun6i-a31
+ - allwinner,sun8i-a23
+ - allwinner,sun9i-a80-smp
+ - allwinner,sun8i-a83t-smp
+ - amlogic,meson8-smp
+ - amlogic,meson8b-smp
+ - arm,realview-smp
+ - aspeed,ast2600-smp
+ - brcm,bcm11351-cpu-method
+ - brcm,bcm23550
+ - brcm,bcm2836-smp
+ - brcm,bcm63138
+ - brcm,bcm-nsp-smp
+ - brcm,brahma-b15
+ - marvell,armada-375-smp
+ - marvell,armada-380-smp
+ - marvell,armada-390-smp
+ - marvell,armada-xp-smp
+ - marvell,98dx3236-smp
+ - marvell,mmp3-smp
+ - mediatek,mt6589-smp
+ - mediatek,mt81xx-tz-smp
+ - qcom,gcc-msm8660
+ - qcom,kpss-acc-v1
+ - qcom,kpss-acc-v2
+ - qcom,msm8226-smp
+ - qcom,msm8909-smp
+ # Only valid on ARM 32-bit, see above for ARM v8 64-bit
+ - qcom,msm8916-smp
+ - renesas,apmu
+ - renesas,r9a06g032-smp
+ - rockchip,rk3036-smp
+ - rockchip,rk3066-smp
+ - socionext,milbeaut-m10v-smp
+ - ste,dbx500-smp
+ - ti,am3352
+ - ti,am4372
cpu-release-addr:
- $ref: '/schemas/types.yaml#/definitions/uint64'
-
+ oneOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - $ref: /schemas/types.yaml#/definitions/uint64
description:
+ The DT specification defines this as 64-bit always, but some 32-bit Arm
+ systems have used a 32-bit value which must be supported.
Required for systems that have an "enable-method"
property value of "spin-table".
- On ARM v8 64-bit systems must be a two cell
- property identifying a 64-bit zero-initialised
- memory location.
cpu-idle-states:
- $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description: |
List of phandles to idle state nodes supported
- by this cpu (see ./idle-states.txt).
+ by this cpu (see ./idle-states.yaml).
capacity-dmips-mhz:
- $ref: '/schemas/types.yaml#/definitions/uint32'
description:
- u32 value representing CPU capacity (see ./cpu-capacity.txt) in
+ u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
DMIPS/MHz, relative to highest capacity-dmips-mhz
in the system.
+ cci-control-port: true
+
dynamic-power-coefficient:
- $ref: '/schemas/types.yaml#/definitions/uint32'
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
@@ -241,8 +292,30 @@ properties:
where voltage is in V, frequency is in MHz.
+ performance-domains:
+ maxItems: 1
+ description:
+ List of phandles and performance domain specifiers, as defined by
+ bindings of the performance domain provider. See also
+ dvfs/performance-domain.yaml.
+
+ power-domains:
+ description:
+ List of phandles and PM domain specifiers, as defined by bindings of the
+ PM domain provider (see also ../power_domain.txt).
+
+ power-domain-names:
+ description:
+ A list of power domain name strings sorted in the same order as the
+ power-domains property.
+
+ For PSCI based platforms, the name corresponding to the index of the PSCI
+ PM domain provider, must be "psci". For SCMI based platforms, the name
+ corresponding to the index of an SCMI performance domain provider, must be
+ "perf".
+
qcom,saw:
- $ref: '/schemas/types.yaml#/definitions/phandle'
+ $ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the SAW* node associated with this CPU.
@@ -252,17 +325,18 @@ properties:
* arm/msm/qcom,saw2.txt
qcom,acc:
- $ref: '/schemas/types.yaml#/definitions/phandle'
+ $ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the ACC* node associated with this CPU.
Required for systems that have an "enable-method" property
- value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
+ value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
+ "qcom,msm8916-smp".
* arm/msm/qcom,kpss-acc.txt
rockchip,pmu:
- $ref: '/schemas/types.yaml#/definitions/phandle'
+ $ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the syscon node controlling the cpu core power domains.
@@ -271,6 +345,39 @@ properties:
While optional, it is the preferred way to get access to
the cpu-core power-domains.
+ secondary-boot-reg:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Required for systems that have an "enable-method" property value of
+ "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
+
+ This includes the following SoCs: |
+ BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
+ BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+ The secondary-boot-reg property is a u32 value that specifies the
+ physical address of the register used to request the ROM holding pen
+ code release a secondary CPU. The value written to the register is
+ formed by encoding the target CPU id into the low bits of the
+ physical start address it should jump to.
+
+if:
+ # If the enable-method property contains one of those values
+ properties:
+ enable-method:
+ contains:
+ enum:
+ - brcm,bcm11351-cpu-method
+ - brcm,bcm23550
+ - brcm,bcm-nsp-smp
+ # and if enable-method is present
+ required:
+ - enable-method
+
+then:
+ required:
+ - secondary-boot-reg
+
required:
- device_type
- reg
@@ -279,6 +386,8 @@ required:
dependencies:
rockchip,pmu: [enable-method]
+additionalProperties: true
+
examples:
- |
cpus {