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-rw-r--r--dts/Bindings/arm/freescale/fsl,imx7ulp-sim.txt16
-rw-r--r--dts/Bindings/arm/freescale/fsl,scu.txt15
2 files changed, 27 insertions, 4 deletions
diff --git a/dts/Bindings/arm/freescale/fsl,imx7ulp-sim.txt b/dts/Bindings/arm/freescale/fsl,imx7ulp-sim.txt
new file mode 100644
index 0000000..7d0c7f0
--- /dev/null
+++ b/dts/Bindings/arm/freescale/fsl,imx7ulp-sim.txt
@@ -0,0 +1,16 @@
+Freescale i.MX7ULP System Integration Module
+----------------------------------------------
+The system integration module (SIM) provides system control and chip configuration
+registers. In this module, chip revision information is located in JTAG ID register,
+and a set of registers have been made available in DGO domain for SW use, with the
+objective to maintain its value between system resets.
+
+Required properties:
+- compatible: Should be "fsl,imx7ulp-sim".
+- reg: Specifies base physical address and size of the register sets.
+
+Example:
+sim: sim@410a3000 {
+ compatible = "fsl,imx7ulp-sim", "syscon";
+ reg = <0x410a3000 0x1000>;
+};
diff --git a/dts/Bindings/arm/freescale/fsl,scu.txt b/dts/Bindings/arm/freescale/fsl,scu.txt
index 27784b6..72d481c 100644
--- a/dts/Bindings/arm/freescale/fsl,scu.txt
+++ b/dts/Bindings/arm/freescale/fsl,scu.txt
@@ -58,7 +58,11 @@ This binding for the SCU power domain providers uses the generic power
domain binding[2].
Required properties:
-- compatible: Should be "fsl,imx8qxp-scu-pd".
+- compatible: Should be one of:
+ "fsl,imx8qm-scu-pd",
+ "fsl,imx8qxp-scu-pd"
+ followed by "fsl,scu-pd"
+
- #power-domain-cells: Must be 1. Contains the Resource ID used by
SCU commands.
See detailed Resource ID list from:
@@ -70,7 +74,10 @@ Clock bindings based on SCU Message Protocol
This binding uses the common clock binding[1].
Required properties:
-- compatible: Should be "fsl,imx8qxp-clock".
+- compatible: Should be one of:
+ "fsl,imx8qm-clock"
+ "fsl,imx8qxp-clock"
+ followed by "fsl,scu-clk"
- #clock-cells: Should be 1. Contains the Clock ID value.
- clocks: List of clock specifiers, must contain an entry for
each required entry in clock-names
@@ -137,7 +144,7 @@ firmware {
&lsio_mu1 1 3>;
clk: clk {
- compatible = "fsl,imx8qxp-clk";
+ compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
#clock-cells = <1>;
};
@@ -154,7 +161,7 @@ firmware {
};
pd: imx8qx-pd {
- compatible = "fsl,imx8qxp-scu-pd";
+ compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
#power-domain-cells = <1>;
};