diff options
Diffstat (limited to 'dts/Bindings/arm/freescale')
| -rw-r--r-- | dts/Bindings/arm/freescale/fsl,imx7ulp-pm.txt | 23 | ||||
| -rw-r--r-- | dts/Bindings/arm/freescale/fsl,scu.txt | 50 |
2 files changed, 44 insertions, 29 deletions
diff --git a/dts/Bindings/arm/freescale/fsl,imx7ulp-pm.txt b/dts/Bindings/arm/freescale/fsl,imx7ulp-pm.txt new file mode 100644 index 0000000000..75195bee11 --- /dev/null +++ b/dts/Bindings/arm/freescale/fsl,imx7ulp-pm.txt @@ -0,0 +1,23 @@ +Freescale i.MX7ULP Power Management Components +---------------------------------------------- + +The Multi-System Mode Controller (MSMC) is responsible for sequencing +the MCU into and out of all stop and run power modes. Specifically, it +monitors events to trigger transitions between power modes while +controlling the power, clocks, and memories of the MCU to achieve the +power consumption and functionality of that mode. + +The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or +Standby modes for either Cortex family. Run, Wait, and Stop are the +common terms used for the primary operating modes of Kinetis +microcontrollers. + +Required properties: +- compatible: Should be "fsl,imx7ulp-smc1". +- reg: Specifies base physical address and size of the register sets. + +Example: +smc1: smc1@40410000 { + compatible = "fsl,imx7ulp-smc1"; + reg = <0x40410000 0x1000>; +}; diff --git a/dts/Bindings/arm/freescale/fsl,scu.txt b/dts/Bindings/arm/freescale/fsl,scu.txt index 46d0af1f08..27784b6edf 100644 --- a/dts/Bindings/arm/freescale/fsl,scu.txt +++ b/dts/Bindings/arm/freescale/fsl,scu.txt @@ -58,19 +58,11 @@ This binding for the SCU power domain providers uses the generic power domain binding[2]. Required properties: -- compatible: Should be "fsl,scu-pd". -- #address-cells: Should be 1. -- #size-cells: Should be 0. - -Required properties for power domain sub nodes: -- #power-domain-cells: Must be 0. - -Optional Properties: -- reg: Resource ID of this power domain. - No exist means uncontrollable by user. +- compatible: Should be "fsl,imx8qxp-scu-pd". +- #power-domain-cells: Must be 1. Contains the Resource ID used by + SCU commands. See detailed Resource ID list from: - include/dt-bindings/power/imx-rsrc.h -- power-domains: phandle pointing to the parent power domain. + include/dt-bindings/firmware/imx/rsrc.h Clock bindings based on SCU Message Protocol ------------------------------------------------------------ @@ -96,13 +88,16 @@ Pinctrl bindings based on SCU Message Protocol This binding uses the i.MX common pinctrl binding[3]. Required properties: -- compatible: Should be "fsl,imx8qxp-iomuxc". +- compatible: Should be one of: + "fsl,imx8qm-iomuxc", + "fsl,imx8qxp-iomuxc". Required properties for Pinctrl sub nodes: - fsl,pins: Each entry consists of 3 integers which represents the mux and config setting for one pin. The first 2 integers <pin_id mux_mode> are specified using a PIN_FUNC_ID macro, which can be found in + <dt-bindings/pinctrl/pads-imx8qm.h>, <dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer CONFIG is the pad setting value like pull-up on this pin. @@ -114,6 +109,12 @@ Required properties for Pinctrl sub nodes: [2] Documentation/devicetree/bindings/power/power_domain.txt [3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt +RTC bindings based on SCU Message Protocol +------------------------------------------------------------ + +Required properties: +- compatible: should be "fsl,imx8qxp-sc-rtc"; + Example (imx8qxp): ------------- lsio_mu1: mailbox@5d1c0000 { @@ -152,22 +153,13 @@ firmware { ... }; - imx8qx-pm { - compatible = "fsl,scu-pd"; - #address-cells = <1>; - #size-cells = <0>; - - pd_dma: dma-power-domain { - #power-domain-cells = <0>; + pd: imx8qx-pd { + compatible = "fsl,imx8qxp-scu-pd"; + #power-domain-cells = <1>; + }; - pd_dma_lpuart0: dma-lpuart0@57 { - reg = <SC_R_UART_0>; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - ... - }; - ... + rtc: rtc { + compatible = "fsl,imx8qxp-sc-rtc"; }; }; }; @@ -179,5 +171,5 @@ serial@5a060000 { clocks = <&clk IMX8QXP_UART0_CLK>, <&clk IMX8QXP_UART0_IPG_CLK>; clock-names = "per", "ipg"; - power-domains = <&pd_dma_lpuart0>; + power-domains = <&pd IMX_SC_R_UART_0>; }; |