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-rw-r--r--dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt3
-rw-r--r--dts/Bindings/arm/freescale/m4if.txt12
-rw-r--r--dts/Bindings/arm/freescale/tigerp.txt12
3 files changed, 24 insertions, 3 deletions
diff --git a/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt b/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt
index 669808b..6dd6f39 100644
--- a/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt
+++ b/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt
@@ -18,9 +18,6 @@ Required properties:
assignment of the interrupt router is required.
Flags get passed only when using GIC as parent. Flags
encoding as documented by the GIC bindings.
-- interrupt-parent: Should be the phandle for the interrupt controller of
- the CPU the device tree is intended to be used on. This
- is either the node of the GIC or NVIC controller.
Example:
mscm_ir: interrupt-controller@40001800 {
diff --git a/dts/Bindings/arm/freescale/m4if.txt b/dts/Bindings/arm/freescale/m4if.txt
new file mode 100644
index 0000000..93bd7b8
--- /dev/null
+++ b/dts/Bindings/arm/freescale/m4if.txt
@@ -0,0 +1,12 @@
+* Freescale Multi Master Multi Memory Interface (M4IF) module
+
+Required properties:
+- compatible : Should be "fsl,imx51-m4if"
+- reg : Address and length of the register set for the device
+
+Example:
+
+m4if: m4if@83fd8000 {
+ compatible = "fsl,imx51-m4if";
+ reg = <0x83fd8000 0x1000>;
+};
diff --git a/dts/Bindings/arm/freescale/tigerp.txt b/dts/Bindings/arm/freescale/tigerp.txt
new file mode 100644
index 0000000..19e2aad
--- /dev/null
+++ b/dts/Bindings/arm/freescale/tigerp.txt
@@ -0,0 +1,12 @@
+* Freescale Tigerp platform module
+
+Required properties:
+- compatible : Should be "fsl,imx51-tigerp"
+- reg : Address and length of the register set for the device
+
+Example:
+
+tigerp: tigerp@83fa0000 {
+ compatible = "fsl,imx51-tigerp";
+ reg = <0x83fa0000 0x28>;
+};