diff options
Diffstat (limited to 'dts/Bindings/arm/l2c2x0.txt')
| -rw-r--r-- | dts/Bindings/arm/l2c2x0.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/dts/Bindings/arm/l2c2x0.txt b/dts/Bindings/arm/l2c2x0.txt index d9650c1788..fbe6cb21f4 100644 --- a/dts/Bindings/arm/l2c2x0.txt +++ b/dts/Bindings/arm/l2c2x0.txt @@ -4,8 +4,8 @@ ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/ PL310 and variants) based level 2 cache controller. All these various implementations of the L2 cache controller have compatible programming models (Note 1). Some of the properties that are just prefixed "cache-*" are taken from section -3.7.3 of the ePAPR v1.1 specification which can be found at: -https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf +3.7.3 of the Devicetree Specification which can be found at: +https://www.devicetree.org/specifications/ The ARM L2 cache representation in the device tree should be done as follows: |