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-rw-r--r--dts/Bindings/arm/exynos/power_domain.txt2
-rw-r--r--dts/Bindings/arm/sti.txt4
2 files changed, 6 insertions, 0 deletions
diff --git a/dts/Bindings/arm/exynos/power_domain.txt b/dts/Bindings/arm/exynos/power_domain.txt
index f4445e5a2b..1e09703734 100644
--- a/dts/Bindings/arm/exynos/power_domain.txt
+++ b/dts/Bindings/arm/exynos/power_domain.txt
@@ -22,6 +22,8 @@ Optional Properties:
- pclkN, clkN: Pairs of parent of input clock and input clock to the
devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
are supported currently.
+- power-domains: phandle pointing to the parent power domain, for more details
+ see Documentation/devicetree/bindings/power/power_domain.txt
Node of a device using power domains must have a power-domains property
defined with a phandle to respective power domain.
diff --git a/dts/Bindings/arm/sti.txt b/dts/Bindings/arm/sti.txt
index d70ec35873..8d27f6b084 100644
--- a/dts/Bindings/arm/sti.txt
+++ b/dts/Bindings/arm/sti.txt
@@ -13,6 +13,10 @@ Boards with the ST STiH407 SoC shall have the following properties:
Required root node property:
compatible = "st,stih407";
+Boards with the ST STiH410 SoC shall have the following properties:
+Required root node property:
+compatible = "st,stih410";
+
Boards with the ST STiH418 SoC shall have the following properties:
Required root node property:
compatible = "st,stih418";