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-rw-r--r--dts/Bindings/arm/amlogic.txt1
-rw-r--r--dts/Bindings/arm/armadeus.txt6
-rw-r--r--dts/Bindings/arm/atmel-sysregs.txt4
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm2835.txt4
-rw-r--r--dts/Bindings/arm/bhf.txt6
-rw-r--r--dts/Bindings/arm/bitmain.yaml18
-rw-r--r--dts/Bindings/arm/compulab-boards.txt25
-rw-r--r--dts/Bindings/arm/cpus.yaml1
-rw-r--r--dts/Bindings/arm/freescale/fsl,imx7ulp-sim.txt16
-rw-r--r--dts/Bindings/arm/freescale/fsl,scu.txt15
-rw-r--r--dts/Bindings/arm/fsl.txt237
-rw-r--r--dts/Bindings/arm/fsl.yaml232
-rw-r--r--dts/Bindings/arm/i2se.txt22
-rw-r--r--dts/Bindings/arm/l2c2x0.txt114
-rw-r--r--dts/Bindings/arm/l2c2x0.yaml248
-rw-r--r--dts/Bindings/arm/mediatek.txt14
-rw-r--r--dts/Bindings/arm/olimex.txt10
-rw-r--r--dts/Bindings/arm/pmu.txt70
-rw-r--r--dts/Bindings/arm/pmu.yaml87
-rw-r--r--dts/Bindings/arm/renesas.yaml238
-rw-r--r--dts/Bindings/arm/rockchip.yaml17
-rw-r--r--dts/Bindings/arm/shmobile.txt155
-rw-r--r--dts/Bindings/arm/socionext/milbeaut.yaml22
-rw-r--r--dts/Bindings/arm/technologic.txt23
-rw-r--r--dts/Bindings/arm/tegra.yaml2
25 files changed, 912 insertions, 675 deletions
diff --git a/dts/Bindings/arm/amlogic.txt b/dts/Bindings/arm/amlogic.txt
index 8dbc259..7f40cb5 100644
--- a/dts/Bindings/arm/amlogic.txt
+++ b/dts/Bindings/arm/amlogic.txt
@@ -109,6 +109,7 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,s400" (Meson axg a113d)
- "amlogic,u200" (Meson g12a s905d2)
+ - "amediatech,x96-max" (Meson g12a s905x2)
Amlogic Meson Firmware registers Interface
------------------------------------------
diff --git a/dts/Bindings/arm/armadeus.txt b/dts/Bindings/arm/armadeus.txt
deleted file mode 100644
index 9821283..0000000
--- a/dts/Bindings/arm/armadeus.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Armadeus i.MX Platforms Device Tree Bindings
------------------------------------------------
-
-APF51: i.MX51 based module.
-Required root node properties:
- - compatible = "armadeus,imx51-apf51", "fsl,imx51";
diff --git a/dts/Bindings/arm/atmel-sysregs.txt b/dts/Bindings/arm/atmel-sysregs.txt
index 14f319f..e61d00e 100644
--- a/dts/Bindings/arm/atmel-sysregs.txt
+++ b/dts/Bindings/arm/atmel-sysregs.txt
@@ -21,7 +21,8 @@ Its subnodes can be:
RSTC Reset Controller required properties:
- compatible: Should be "atmel,<chip>-rstc".
- <chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3"
+ <chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7"
+ it also can be "microchip,sam9x60-rstc"
- reg: Should contain registers location and length
- clocks: phandle to input clock.
@@ -147,6 +148,7 @@ required properties:
- compatible: Should be "atmel,<chip>-sfr", "syscon" or
"atmel,<chip>-sfrbu", "syscon"
<chip> can be "sama5d3", "sama5d4" or "sama5d2".
+ It also can be "microchip,sam9x60-sfr", "syscon".
- reg: Should contain registers location and length
sfr@f0038000 {
diff --git a/dts/Bindings/arm/bcm/brcm,bcm2835.txt b/dts/Bindings/arm/bcm/brcm,bcm2835.txt
index 0dcc3ea..245328f 100644
--- a/dts/Bindings/arm/bcm/brcm,bcm2835.txt
+++ b/dts/Bindings/arm/bcm/brcm,bcm2835.txt
@@ -30,6 +30,10 @@ Raspberry Pi 2 Model B
Required root node properties:
compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
+Raspberry Pi 3 Model A+
+Required root node properties:
+compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837";
+
Raspberry Pi 3 Model B
Required root node properties:
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
diff --git a/dts/Bindings/arm/bhf.txt b/dts/Bindings/arm/bhf.txt
deleted file mode 100644
index 886b503..0000000
--- a/dts/Bindings/arm/bhf.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Beckhoff Automation Platforms Device Tree Bindings
---------------------------------------------------
-
-CX9020 Embedded PC
-Required root node properties:
- - compatible = "bhf,cx9020", "fsl,imx53";
diff --git a/dts/Bindings/arm/bitmain.yaml b/dts/Bindings/arm/bitmain.yaml
new file mode 100644
index 0000000..0efdb4a
--- /dev/null
+++ b/dts/Bindings/arm/bitmain.yaml
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bitmain.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bitmain platform device tree bindings
+
+maintainers:
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - bitmain,sophon-edge
+ - const: bitmain,bm1880
+...
diff --git a/dts/Bindings/arm/compulab-boards.txt b/dts/Bindings/arm/compulab-boards.txt
deleted file mode 100644
index 42a1028..0000000
--- a/dts/Bindings/arm/compulab-boards.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-CompuLab SB-SOM is a multi-module baseboard capable of carrying:
- - CM-T43
- - CM-T54
- - CM-QS600
- - CL-SOM-AM57x
- - CL-SOM-iMX7
-modules with minor modifications to the SB-SOM assembly.
-
-Required root node properties:
- - compatible = should be "compulab,sb-som"
-
-Compulab CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on
-Freescale i.MX7 ARM Cortex-A7 System-on-Chip.
-
-Required root node properties:
- - compatible = "compulab,cl-som-imx7", "fsl,imx7d";
-
-Compulab SBC-iMX7 is a single board computer based on the
-Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with
-the CL-SOM-iMX7 System-on-Module providing most of the functions,
-and SB-SOM-iMX7 carrier board providing additional peripheral
-functions and connectors.
-
-Required root node properties:
- - compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d";
diff --git a/dts/Bindings/arm/cpus.yaml b/dts/Bindings/arm/cpus.yaml
index 298c17b..365dcf3 100644
--- a/dts/Bindings/arm/cpus.yaml
+++ b/dts/Bindings/arm/cpus.yaml
@@ -228,6 +228,7 @@ patternProperties:
- renesas,r9a06g032-smp
- rockchip,rk3036-smp
- rockchip,rk3066-smp
+ - socionext,milbeaut-m10v-smp
- ste,dbx500-smp
cpu-release-addr:
diff --git a/dts/Bindings/arm/freescale/fsl,imx7ulp-sim.txt b/dts/Bindings/arm/freescale/fsl,imx7ulp-sim.txt
new file mode 100644
index 0000000..7d0c7f0
--- /dev/null
+++ b/dts/Bindings/arm/freescale/fsl,imx7ulp-sim.txt
@@ -0,0 +1,16 @@
+Freescale i.MX7ULP System Integration Module
+----------------------------------------------
+The system integration module (SIM) provides system control and chip configuration
+registers. In this module, chip revision information is located in JTAG ID register,
+and a set of registers have been made available in DGO domain for SW use, with the
+objective to maintain its value between system resets.
+
+Required properties:
+- compatible: Should be "fsl,imx7ulp-sim".
+- reg: Specifies base physical address and size of the register sets.
+
+Example:
+sim: sim@410a3000 {
+ compatible = "fsl,imx7ulp-sim", "syscon";
+ reg = <0x410a3000 0x1000>;
+};
diff --git a/dts/Bindings/arm/freescale/fsl,scu.txt b/dts/Bindings/arm/freescale/fsl,scu.txt
index 27784b6..72d481c 100644
--- a/dts/Bindings/arm/freescale/fsl,scu.txt
+++ b/dts/Bindings/arm/freescale/fsl,scu.txt
@@ -58,7 +58,11 @@ This binding for the SCU power domain providers uses the generic power
domain binding[2].
Required properties:
-- compatible: Should be "fsl,imx8qxp-scu-pd".
+- compatible: Should be one of:
+ "fsl,imx8qm-scu-pd",
+ "fsl,imx8qxp-scu-pd"
+ followed by "fsl,scu-pd"
+
- #power-domain-cells: Must be 1. Contains the Resource ID used by
SCU commands.
See detailed Resource ID list from:
@@ -70,7 +74,10 @@ Clock bindings based on SCU Message Protocol
This binding uses the common clock binding[1].
Required properties:
-- compatible: Should be "fsl,imx8qxp-clock".
+- compatible: Should be one of:
+ "fsl,imx8qm-clock"
+ "fsl,imx8qxp-clock"
+ followed by "fsl,scu-clk"
- #clock-cells: Should be 1. Contains the Clock ID value.
- clocks: List of clock specifiers, must contain an entry for
each required entry in clock-names
@@ -137,7 +144,7 @@ firmware {
&lsio_mu1 1 3>;
clk: clk {
- compatible = "fsl,imx8qxp-clk";
+ compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
#clock-cells = <1>;
};
@@ -154,7 +161,7 @@ firmware {
};
pd: imx8qx-pd {
- compatible = "fsl,imx8qxp-scu-pd";
+ compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
#power-domain-cells = <1>;
};
diff --git a/dts/Bindings/arm/fsl.txt b/dts/Bindings/arm/fsl.txt
deleted file mode 100644
index 7fbc424..0000000
--- a/dts/Bindings/arm/fsl.txt
+++ /dev/null
@@ -1,237 +0,0 @@
-Freescale i.MX Platforms Device Tree Bindings
------------------------------------------------
-
-i.MX23 Evaluation Kit
-Required root node properties:
- - compatible = "fsl,imx23-evk", "fsl,imx23";
-
-i.MX25 Product Development Kit
-Required root node properties:
- - compatible = "fsl,imx25-pdk", "fsl,imx25";
-
-i.MX27 Product Development Kit
-Required root node properties:
- - compatible = "fsl,imx27-pdk", "fsl,imx27";
-
-i.MX28 Evaluation Kit
-Required root node properties:
- - compatible = "fsl,imx28-evk", "fsl,imx28";
-
-i.MX51 Babbage Board
-Required root node properties:
- - compatible = "fsl,imx51-babbage", "fsl,imx51";
-
-i.MX53 Automotive Reference Design Board
-Required root node properties:
- - compatible = "fsl,imx53-ard", "fsl,imx53";
-
-i.MX53 Evaluation Kit
-Required root node properties:
- - compatible = "fsl,imx53-evk", "fsl,imx53";
-
-i.MX53 Quick Start Board
-Required root node properties:
- - compatible = "fsl,imx53-qsb", "fsl,imx53";
-
-i.MX53 Smart Mobile Reference Design Board
-Required root node properties:
- - compatible = "fsl,imx53-smd", "fsl,imx53";
-
-i.MX6 Quad Armadillo2 Board
-Required root node properties:
- - compatible = "fsl,imx6q-arm2", "fsl,imx6q";
-
-i.MX6 Quad SABRE Lite Board
-Required root node properties:
- - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
-
-i.MX6 Quad SABRE Smart Device Board
-Required root node properties:
- - compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
-
-i.MX6 Quad SABRE Automotive Board
-Required root node properties:
- - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
-
-i.MX6SLL EVK board
-Required root node properties:
- - compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
-
-i.MX6 Quad Plus SABRE Smart Device Board
-Required root node properties:
- - compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
-
-i.MX6 Quad Plus SABRE Automotive Board
-Required root node properties:
- - compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
-
-i.MX6 DualLite SABRE Smart Device Board
-Required root node properties:
- - compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
-
-i.MX6 DualLite/Solo SABRE Automotive Board
-Required root node properties:
- - compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
-
-i.MX6 SoloLite EVK Board
-Required root node properties:
- - compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
-
-i.MX6 UltraLite 14x14 EVK Board
-Required root node properties:
- - compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
-
-i.MX6 UltraLiteLite 14x14 EVK Board
-Required root node properties:
- - compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
-
-i.MX6 ULZ 14x14 EVK Board
-Required root node properties:
- - compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz";
-
-i.MX6 SoloX SDB Board
-Required root node properties:
- - compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
-
-i.MX6 SoloX Sabre Auto Board
-Required root node properties:
- - compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
-
-i.MX7 SabreSD Board
-Required root node properties:
- - compatible = "fsl,imx7d-sdb", "fsl,imx7d";
-
-i.MX7ULP Evaluation Kit
-Required root node properties:
- - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
-
-Generic i.MX boards
--------------------
-
-No iomux setup is done for these boards, so this must have been configured
-by the bootloader for boards to work with the generic bindings.
-
-i.MX27 generic board
-Required root node properties:
- - compatible = "fsl,imx27";
-
-i.MX51 generic board
-Required root node properties:
- - compatible = "fsl,imx51";
-
-i.MX53 generic board
-Required root node properties:
- - compatible = "fsl,imx53";
-
-i.MX6q generic board
-Required root node properties:
- - compatible = "fsl,imx6q";
-
-i.MX7ULP generic board
-Required root node properties:
- - compatible = "fsl,imx7ulp";
-
-Freescale Vybrid Platform Device Tree Bindings
-----------------------------------------------
-
-For the Vybrid SoC familiy all variants with DDR controller are supported,
-which is the VF5xx and VF6xx series. Out of historical reasons, in most
-places the kernel uses vf610 to refer to the whole familiy.
-The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4
-core support.
-
-Required root node compatible property (one of them):
- - compatible = "fsl,vf500";
- - compatible = "fsl,vf510";
- - compatible = "fsl,vf600";
- - compatible = "fsl,vf610";
- - compatible = "fsl,vf610m4";
-
-Freescale LS1021A Platform Device Tree Bindings
-------------------------------------------------
-
-Required root node compatible properties:
- - compatible = "fsl,ls1021a";
-
-Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
-----------------------------------------------------------------
-
-LS1012A SoC
-Required root node properties:
- - compatible = "fsl,ls1012a";
-
-LS1012A ARMv8 based RDB Board
-Required root node properties:
- - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
-
-LS1012A ARMv8 based FRDM Board
-Required root node properties:
- - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
-
-LS1012A ARMv8 based QDS Board
-Required root node properties:
- - compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
-
-LS1043A SoC
-Required root node properties:
- - compatible = "fsl,ls1043a";
-
-LS1043A ARMv8 based RDB Board
-Required root node properties:
- - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
-
-LS1043A ARMv8 based QDS Board
-Required root node properties:
- - compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
-
-LS1046A SoC
-Required root node properties:
- - compatible = "fsl,ls1046a";
-
-LS1046A ARMv8 based QDS Board
-Required root node properties:
- - compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
-
-LS1046A ARMv8 based RDB Board
-Required root node properties:
- - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
-
-LS1088A SoC
-Required root node properties:
- - compatible = "fsl,ls1088a";
-
-LS1088A ARMv8 based QDS Board
-Required root node properties:
- - compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
-
-LS1088A ARMv8 based RDB Board
-Required root node properties:
- - compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
-
-LS2080A SoC
-Required root node properties:
- - compatible = "fsl,ls2080a";
-
-LS2080A ARMv8 based Simulator model
-Required root node properties:
- - compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
-
-LS2080A ARMv8 based QDS Board
-Required root node properties:
- - compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
-
-LS2080A ARMv8 based RDB Board
-Required root node properties:
- - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
-
-LS2088A SoC
-Required root node properties:
- - compatible = "fsl,ls2088a";
-
-LS2088A ARMv8 based QDS Board
-Required root node properties:
- - compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
-
-LS2088A ARMv8 based RDB Board
-Required root node properties:
- - compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
diff --git a/dts/Bindings/arm/fsl.yaml b/dts/Bindings/arm/fsl.yaml
new file mode 100644
index 0000000..7e2cd6a
--- /dev/null
+++ b/dts/Bindings/arm/fsl.yaml
@@ -0,0 +1,232 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/arm/fsl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX Platforms Device Tree Bindings
+
+maintainers:
+ - Shawn Guo <shawnguo@kernel.org>
+ - Li Yang <leoyang.li@nxp.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: i.MX23 based Boards
+ items:
+ - enum:
+ - fsl,imx23-evk
+ - olimex,imx23-olinuxino
+ - const: fsl,imx23
+
+ - description: i.MX25 Product Development Kit
+ items:
+ - enum:
+ - fsl,imx25-pdk
+ - const: fsl,imx25
+
+ - description: i.MX27 Product Development Kit
+ items:
+ - enum:
+ - fsl,imx27-pdk
+ - const: fsl,imx27
+
+ - description: i.MX28 based Boards
+ items:
+ - enum:
+ - fsl,imx28-evk
+ - i2se,duckbill
+ - i2se,duckbill-2
+ - technologic,imx28-ts4600
+ - const: fsl,imx28
+ - description: i.MX28 Duckbill 2 based Boards
+ items:
+ - enum:
+ - i2se,duckbill-2-485
+ - i2se,duckbill-2-enocean
+ - i2se,duckbill-2-spi
+ - const: i2se,duckbill-2
+ - const: fsl,imx28
+
+ - description: i.MX51 Babbage Board
+ items:
+ - enum:
+ - armadeus,imx51-apf51
+ - fsl,imx51-babbage
+ - technologic,imx51-ts4800
+ - const: fsl,imx51
+
+ - description: i.MX53 based Boards
+ items:
+ - enum:
+ - bhf,cx9020
+ - fsl,imx53-ard
+ - fsl,imx53-evk
+ - fsl,imx53-qsb
+ - fsl,imx53-smd
+ - const: fsl,imx53
+
+ - description: i.MX6Q based Boards
+ items:
+ - enum:
+ - fsl,imx6q-arm2
+ - fsl,imx6q-sabreauto
+ - fsl,imx6q-sabrelite
+ - fsl,imx6q-sabresd
+ - technologic,imx6q-ts4900
+ - technologic,imx6q-ts7970
+ - const: fsl,imx6q
+
+ - description: i.MX6QP based Boards
+ items:
+ - enum:
+ - fsl,imx6qp-sabreauto # i.MX6 Quad Plus SABRE Automotive Board
+ - fsl,imx6qp-sabresd # i.MX6 Quad Plus SABRE Smart Device Board
+ - const: fsl,imx6qp
+
+ - description: i.MX6DL based Boards
+ items:
+ - enum:
+ - fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
+ - fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
+ - technologic,imx6dl-ts4900
+ - technologic,imx6dl-ts7970
+ - ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board
+ - ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board
+ - ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board
+ - const: fsl,imx6dl
+
+ - description: i.MX6SL based Boards
+ items:
+ - enum:
+ - fsl,imx6sl-evk # i.MX6 SoloLite EVK Board
+ - const: fsl,imx6sl
+
+ - description: i.MX6SLL based Boards
+ items:
+ - enum:
+ - fsl,imx6sll-evk
+ - const: fsl,imx6sll
+
+ - description: i.MX6SX based Boards
+ items:
+ - enum:
+ - fsl,imx6sx-sabreauto # i.MX6 SoloX Sabre Auto Board
+ - fsl,imx6sx-sdb # i.MX6 SoloX SDB Board
+ - const: fsl,imx6sx
+
+ - description: i.MX6UL based Boards
+ items:
+ - enum:
+ - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
+ - const: fsl,imx6ul
+
+ - description: i.MX6ULL based Boards
+ items:
+ - enum:
+ - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
+ - const: fsl,imx6ull
+
+ - description: i.MX6ULZ based Boards
+ items:
+ - enum:
+ - fsl,imx6ulz-14x14-evk # i.MX6 ULZ 14x14 EVK Board
+ - const: fsl,imx6ull # This seems odd. Should be last?
+ - const: fsl,imx6ulz
+
+ - description: i.MX7D based Boards
+ items:
+ - enum:
+ - fsl,imx7d-sdb # i.MX7 SabreSD Board
+ - const: fsl,imx7d
+
+ - description:
+ Compulab SBC-iMX7 is a single board computer based on the
+ Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with
+ the CL-SOM-iMX7 System-on-Module providing most of the functions,
+ and SB-SOM-iMX7 carrier board providing additional peripheral
+ functions and connectors.
+ items:
+ - const: compulab,sbc-imx7
+ - const: compulab,cl-som-imx7
+ - const: fsl,imx7d
+
+ - description: i.MX8QXP based Boards
+ items:
+ - enum:
+ - fsl,imx8qxp-mek # i.MX8QXP MEK Board
+ - const: fsl,imx8qxp
+
+ - description:
+ Freescale Vybrid Platform Device Tree Bindings
+
+ For the Vybrid SoC familiy all variants with DDR controller are supported,
+ which is the VF5xx and VF6xx series. Out of historical reasons, in most
+ places the kernel uses vf610 to refer to the whole familiy.
+ The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4
+ core support.
+ items:
+ - enum:
+ - fsl,vf500
+ - fsl,vf510
+ - fsl,vf600
+ - fsl,vf610
+ - fsl,vf610m4
+
+ - description: LS1012A based Boards
+ items:
+ - enum:
+ - ebs-systart,oxalis
+ - fsl,ls1012a-rdb
+ - fsl,ls1012a-frdm
+ - fsl,ls1012a-qds
+ - const: fsl,ls1012a
+
+ - description: LS1021A based Boards
+ items:
+ - enum:
+ - fsl,ls1021a-moxa-uc-8410a
+ - fsl,ls1021a-qds
+ - fsl,ls1021a-twr
+ - const: fsl,ls1021a
+
+ - description: LS1043A based Boards
+ items:
+ - enum:
+ - fsl,ls1043a-rdb
+ - fsl,ls1043a-qds
+ - const: fsl,ls1043a
+
+ - description: LS1046A based Boards
+ items:
+ - enum:
+ - fsl,ls1046a-qds
+ - fsl,ls1046a-rdb
+ - const: fsl,ls1046a
+
+ - description: LS1088A based Boards
+ items:
+ - enum:
+ - fsl,ls1088a-qds
+ - fsl,ls1088a-rdb
+ - const: fsl,ls1088a
+
+ - description: LS2080A based Boards
+ items:
+ - enum:
+ - fsl,ls2080a-simu
+ - fsl,ls2080a-qds
+ - fsl,ls2080a-rdb
+ - const: fsl,ls2080a
+
+ - description: LS2088A based Boards
+ items:
+ - enum:
+ - fsl,ls2088a-qds
+ - fsl,ls2088a-rdb
+ - const: fsl,ls2088a
+
+...
diff --git a/dts/Bindings/arm/i2se.txt b/dts/Bindings/arm/i2se.txt
deleted file mode 100644
index dbd54a3..0000000
--- a/dts/Bindings/arm/i2se.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-I2SE Device Tree Bindings
--------------------------
-
-Duckbill Board
-Required root node properties:
- - compatible = "i2se,duckbill", "fsl,imx28";
-
-Duckbill 2 Board
-Required root node properties:
- - compatible = "i2se,duckbill-2", "fsl,imx28";
-
-Duckbill 2 485 Board
-Required root node properties:
- - compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28";
-
-Duckbill 2 EnOcean Board
-Required root node properties:
- - compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28";
-
-Duckbill 2 SPI Board
-Required root node properties:
- - compatible = "i2se,duckbill-2-spi", "i2se,duckbill-2", "fsl,imx28";
diff --git a/dts/Bindings/arm/l2c2x0.txt b/dts/Bindings/arm/l2c2x0.txt
deleted file mode 100644
index fbe6cb2..0000000
--- a/dts/Bindings/arm/l2c2x0.txt
+++ /dev/null
@@ -1,114 +0,0 @@
-* ARM L2 Cache Controller
-
-ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/
-PL310 and variants) based level 2 cache controller. All these various implementations
-of the L2 cache controller have compatible programming models (Note 1).
-Some of the properties that are just prefixed "cache-*" are taken from section
-3.7.3 of the Devicetree Specification which can be found at:
-https://www.devicetree.org/specifications/
-
-The ARM L2 cache representation in the device tree should be done as follows:
-
-Required properties:
-
-- compatible : should be one of:
- "arm,pl310-cache"
- "arm,l220-cache"
- "arm,l210-cache"
- "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
- "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
- offset needs to be added to the address before passing down to the L2
- cache controller
- "marvell,aurora-system-cache": Marvell Controller designed to be
- compatible with the ARM one, with system cache mode (meaning
- maintenance operations on L1 are broadcasted to the L2 and L2
- performs the same operation).
- "marvell,aurora-outer-cache": Marvell Controller designed to be
- compatible with the ARM one with outer cache mode.
- "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
- with arm,pl310-cache controller.
-- cache-unified : Specifies the cache is a unified cache.
-- cache-level : Should be set to 2 for a level 2 cache.
-- reg : Physical base address and size of cache controller's memory mapped
- registers.
-
-Optional properties:
-
-- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
- read, write and setup latencies. Minimum valid values are 1. Controllers
- without setup latency control should use a value of 0.
-- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
- read, write and setup latencies. Controllers without setup latency control
- should use 0. Controllers without separate read and write Tag RAM latency
- values should only use the first cell.
-- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
-- arm,filter-ranges : <start length> Starting address and length of window to
- filter. Addresses in the filter window are directed to the M1 port. Other
- addresses will go to the M0 port.
-- arm,io-coherent : indicates that the system is operating in an hardware
- I/O coherent mode. Valid only when the arm,pl310-cache compatible
- string is used.
-- interrupts : 1 combined interrupt.
-- cache-size : specifies the size in bytes of the cache
-- cache-sets : specifies the number of associativity sets of the cache
-- cache-block-size : specifies the size in bytes of a cache block
-- cache-line-size : specifies the size in bytes of a line in the cache,
- if this is not specified, the line size is assumed to be equal to the
- cache block size
-- cache-id-part: cache id part number to be used if it is not present
- on hardware
-- wt-override: If present then L2 is forced to Write through mode
-- arm,double-linefill : Override double linefill enable setting. Enable if
- non-zero, disable if zero.
-- arm,double-linefill-incr : Override double linefill on INCR read. Enable
- if non-zero, disable if zero.
-- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
- if non-zero, disable if zero.
-- arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero,
- disable if zero.
-- arm,prefetch-offset : Override prefetch offset value. Valid values are
- 0-7, 15, 23, and 31.
-- arm,shared-override : The default behavior of the L220 or PL310 cache
- controllers with respect to the shareable attribute is to transform "normal
- memory non-cacheable transactions" into "cacheable no allocate" (for reads)
- or "write through no write allocate" (for writes).
- On systems where this may cause DMA buffer corruption, this property must be
- specified to indicate that such transforms are precluded.
-- arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).
-- arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).
-- arm,outer-sync-disable : disable the outer sync operation on the L2 cache.
- Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
- will randomly hang unless outer sync operations are disabled.
-- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>
- (forcibly enable), property absent (retain settings set by firmware)
-- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
- <1> (forcibly enable), property absent (retain settings set by
- firmware)
-- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
- disable), <1> (forcibly enable), property absent (OS specific behavior,
- preferably retain firmware settings)
-- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
- <1> (forcibly enable), property absent (OS specific behavior,
- preferably retain firmware settings)
-- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310)
-- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero
- write (PL310)
-
-Example:
-
-L2: cache-controller {
- compatible = "arm,pl310-cache";
- reg = <0xfff12000 0x1000>;
- arm,data-latency = <1 1 1>;
- arm,tag-latency = <2 2 2>;
- arm,filter-ranges = <0x80000000 0x8000000>;
- cache-unified;
- cache-level = <2>;
- interrupts = <45>;
-};
-
-Note 1: The description in this document doesn't apply to integrated L2
- cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
- integrated L2 controllers are assumed to be all preconfigured by
- early secure boot code. Thus no need to deal with their configuration
- in the kernel at all.
diff --git a/dts/Bindings/arm/l2c2x0.yaml b/dts/Bindings/arm/l2c2x0.yaml
new file mode 100644
index 0000000..bfc5c18
--- /dev/null
+++ b/dts/Bindings/arm/l2c2x0.yaml
@@ -0,0 +1,248 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/l2c2x0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM L2 Cache Controller
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description: |+
+ ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
+ PL220/PL310 and variants) based level 2 cache controller. All these various
+ implementations of the L2 cache controller have compatible programming
+ models (Note 1). Some of the properties that are just prefixed "cache-*" are
+ taken from section 3.7.3 of the Devicetree Specification which can be found
+ at:
+ https://www.devicetree.org/specifications/
+
+ Note 1: The description in this document doesn't apply to integrated L2
+ cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
+ integrated L2 controllers are assumed to be all preconfigured by
+ early secure boot code. Thus no need to deal with their configuration
+ in the kernel at all.
+
+allOf:
+ - $ref: /schemas/cache-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - arm,pl310-cache
+ - arm,l220-cache
+ - arm,l210-cache
+ # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+ - bcm,bcm11351-a2-pl310-cache
+ # For Broadcom bcm11351 chipset where an
+ # offset needs to be added to the address before passing down to the L2
+ # cache controller
+ - brcm,bcm11351-a2-pl310-cache
+ # Marvell Controller designed to be
+ # compatible with the ARM one, with system cache mode (meaning
+ # maintenance operations on L1 are broadcasted to the L2 and L2
+ # performs the same operation).
+ - marvell,aurora-system-cache
+ # Marvell Controller designed to be
+ # compatible with the ARM one with outer cache mode.
+ - marvell,aurora-outer-cache
+ # Marvell Tauros3 cache controller, compatible
+ # with arm,pl310-cache controller.
+ - marvell,tauros3-cache
+
+ cache-level:
+ const: 2
+
+ cache-unified: true
+ cache-size: true
+ cache-sets: true
+ cache-block-size: true
+ cache-line-size: true
+
+ reg:
+ maxItems: 1
+
+ arm,data-latency:
+ description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
+ read, write and setup latencies. Minimum valid values are 1. Controllers
+ without setup latency control should use a value of 0.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - minItems: 2
+ maxItems: 3
+ items:
+ minimum: 0
+ maximum: 8
+
+ arm,tag-latency:
+ description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
+ read, write and setup latencies. Controllers without setup latency control
+ should use 0. Controllers without separate read and write Tag RAM latency
+ values should only use the first cell.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - minItems: 1
+ maxItems: 3
+ items:
+ minimum: 0
+ maximum: 8
+
+ arm,dirty-latency:
+ description: Cycles of latency for Dirty RAMs. This is a single cell.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 1
+ maximum: 8
+
+ arm,filter-ranges:
+ description: <start length> Starting address and length of window to
+ filter. Addresses in the filter window are directed to the M1 port. Other
+ addresses will go to the M0 port.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - items:
+ minItems: 2
+ maxItems: 2
+
+ arm,io-coherent:
+ description: indicates that the system is operating in an hardware
+ I/O coherent mode. Valid only when the arm,pl310-cache compatible
+ string is used.
+ type: boolean
+
+ interrupts:
+ # Either a single combined interrupt or up to 9 individual interrupts
+ minItems: 1
+ maxItems: 9
+
+ cache-id-part:
+ description: cache id part number to be used if it is not present
+ on hardware
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ wt-override:
+ description: If present then L2 is forced to Write through mode
+ type: boolean
+
+ arm,double-linefill:
+ description: Override double linefill enable setting. Enable if
+ non-zero, disable if zero.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 0, 1 ]
+
+ arm,double-linefill-incr:
+ description: Override double linefill on INCR read. Enable
+ if non-zero, disable if zero.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 0, 1 ]
+
+ arm,double-linefill-wrap:
+ description: Override double linefill on WRAP read. Enable
+ if non-zero, disable if zero.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 0, 1 ]
+
+ arm,prefetch-drop:
+ description: Override prefetch drop enable setting. Enable if non-zero,
+ disable if zero.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 0, 1 ]
+
+ arm,prefetch-offset:
+ description: Override prefetch offset value.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31 ]
+
+ arm,shared-override:
+ description: The default behavior of the L220 or PL310 cache
+ controllers with respect to the shareable attribute is to transform "normal
+ memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+ or "write through no write allocate" (for writes).
+ On systems where this may cause DMA buffer corruption, this property must
+ be specified to indicate that such transforms are precluded.
+ type: boolean
+
+ arm,parity-enable:
+ description: enable parity checking on the L2 cache (L220 or PL310).
+ type: boolean
+
+ arm,parity-disable:
+ description: disable parity checking on the L2 cache (L220 or PL310).
+ type: boolean
+
+ arm,outer-sync-disable:
+ description: disable the outer sync operation on the L2 cache.
+ Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
+ will randomly hang unless outer sync operations are disabled.
+ type: boolean
+
+ prefetch-data:
+ description: |
+ Data prefetch. Value: <0> (forcibly disable), <1>
+ (forcibly enable), property absent (retain settings set by firmware)
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 0, 1 ]
+
+ prefetch-instr:
+ description: |
+ Instruction prefetch. Value: <0> (forcibly disable),
+ <1> (forcibly enable), property absent (retain settings set by
+ firmware)
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 0, 1 ]
+
+ arm,dynamic-clock-gating:
+ description: |
+ L2 dynamic clock gating. Value: <0> (forcibly
+ disable), <1> (forcibly enable), property absent (OS specific behavior,
+ preferably retain firmware settings)
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 0, 1 ]
+
+ arm,standby-mode:
+ description: L2 standby mode enable. Value <0> (forcibly disable),
+ <1> (forcibly enable), property absent (OS specific behavior,
+ preferably retain firmware settings)
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 0, 1 ]
+
+ arm,early-bresp-disable:
+ description: Disable the CA9 optimization Early BRESP (PL310)
+ type: boolean
+
+ arm,full-line-zero-disable:
+ description: Disable the CA9 optimization Full line of zero
+ write (PL310)
+ type: boolean
+
+required:
+ - compatible
+ - cache-unified
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ cache-controller@fff12000 {
+ compatible = "arm,pl310-cache";
+ reg = <0xfff12000 0x1000>;
+ arm,data-latency = <1 1 1>;
+ arm,tag-latency = <2 2 2>;
+ arm,filter-ranges = <0x80000000 0x8000000>;
+ cache-unified;
+ cache-level = <2>;
+ interrupts = <45>;
+ };
+
+...
diff --git a/dts/Bindings/arm/mediatek.txt b/dts/Bindings/arm/mediatek.txt
index 8f260e5..56ac789 100644
--- a/dts/Bindings/arm/mediatek.txt
+++ b/dts/Bindings/arm/mediatek.txt
@@ -15,11 +15,12 @@ compatible: Must contain one of
"mediatek,mt6795"
"mediatek,mt6797"
"mediatek,mt7622"
- "mediatek,mt7623" which is referred to MT7623N SoC
- "mediatek,mt7623a"
+ "mediatek,mt7623"
+ "mediatek,mt7629"
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
+ "mediatek,mt8183"
Supported boards:
@@ -57,6 +58,9 @@ Supported boards:
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+- Bananapi BPI-R64 for MT7622:
+ Required root node properties:
+ - compatible = "bananapi,bpi-r64", "mediatek,mt7622";
- Reference board for MT7623a with eMMC:
Required root node properties:
- compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
@@ -68,6 +72,9 @@ Supported boards:
- compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
- Bananapi BPI-R2 board:
- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
+- Reference board for MT7629:
+ Required root node properties:
+ - compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
- MTK mt8127 tablet moose EVB:
Required root node properties:
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
@@ -77,3 +84,6 @@ Supported boards:
- MTK mt8173 tablet EVB:
Required root node properties:
- compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
+- Evaluation board for MT8183:
+ Required root node properties:
+ - compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
diff --git a/dts/Bindings/arm/olimex.txt b/dts/Bindings/arm/olimex.txt
deleted file mode 100644
index d726aec..0000000
--- a/dts/Bindings/arm/olimex.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-Olimex Device Tree Bindings
----------------------------
-
-SAM9-L9260 Board
-Required root node properties:
- - compatible = "olimex,sam9-l9260", "atmel,at91sam9260";
-
-i.MX23 Olinuxino Low Cost Board
-Required root node properties:
- - compatible = "olimex,imx23-olinuxino", "fsl,imx23";
diff --git a/dts/Bindings/arm/pmu.txt b/dts/Bindings/arm/pmu.txt
deleted file mode 100644
index 13611a8..0000000
--- a/dts/Bindings/arm/pmu.txt
+++ /dev/null
@@ -1,70 +0,0 @@
-* ARM Performance Monitor Units
-
-ARM cores often have a PMU for counting cpu and cache events like cache misses
-and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
-representation in the device tree should be done as under:-
-
-Required properties:
-
-- compatible : should be one of
- "apm,potenza-pmu"
- "arm,armv8-pmuv3"
- "arm,cortex-a73-pmu"
- "arm,cortex-a72-pmu"
- "arm,cortex-a57-pmu"
- "arm,cortex-a53-pmu"
- "arm,cortex-a35-pmu"
- "arm,cortex-a17-pmu"
- "arm,cortex-a15-pmu"
- "arm,cortex-a12-pmu"
- "arm,cortex-a9-pmu"
- "arm,cortex-a8-pmu"
- "arm,cortex-a7-pmu"
- "arm,cortex-a5-pmu"
- "arm,arm11mpcore-pmu"
- "arm,arm1176-pmu"
- "arm,arm1136-pmu"
- "brcm,vulcan-pmu"
- "cavium,thunder-pmu"
- "qcom,scorpion-pmu"
- "qcom,scorpion-mp-pmu"
- "qcom,krait-pmu"
-- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
- interrupt (PPI) then 1 interrupt should be specified.
-
-Optional properties:
-
-- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
- nodes corresponding directly to the affinity of
- the SPIs listed in the interrupts property.
-
- When using a PPI, specifies a list of phandles to CPU
- nodes corresponding to the set of CPUs which have
- a PMU of this type signalling the PPI listed in the
- interrupts property, unless this is already specified
- by the PPI interrupt specifier itself (in which case
- the interrupt-affinity property shouldn't be present).
-
- This property should be present when there is more than
- a single SPI.
-
-
-- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
- events.
-
-- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register
- (SDER) is accessible. This will cause the driver to do
- any setup required that is only possible in ARMv7 secure
- state. If not present the ARMv7 SDER will not be touched,
- which means the PMU may fail to operate unless external
- code (bootloader or security monitor) has performed the
- appropriate initialisation. Note that this property is
- not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
- in Non-secure state.
-
-Example:
-
-pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupts = <100 101>;
-};
diff --git a/dts/Bindings/arm/pmu.yaml b/dts/Bindings/arm/pmu.yaml
new file mode 100644
index 0000000..52ae094
--- /dev/null
+++ b/dts/Bindings/arm/pmu.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Performance Monitor Units
+
+maintainers:
+ - Mark Rutland <mark.rutland@arm.com>
+ - Will Deacon <will.deacon@arm.com>
+
+description: |+
+ ARM cores often have a PMU for counting cpu and cache events like cache misses
+ and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
+ representation in the device tree should be done as under:-
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - apm,potenza-pmu
+ - arm,armv8-pmuv3
+ - arm,cortex-a73-pmu
+ - arm,cortex-a72-pmu
+ - arm,cortex-a57-pmu
+ - arm,cortex-a53-pmu
+ - arm,cortex-a35-pmu
+ - arm,cortex-a17-pmu
+ - arm,cortex-a15-pmu
+ - arm,cortex-a12-pmu
+ - arm,cortex-a9-pmu
+ - arm,cortex-a8-pmu
+ - arm,cortex-a7-pmu
+ - arm,cortex-a5-pmu
+ - arm,arm11mpcore-pmu
+ - arm,arm1176-pmu
+ - arm,arm1136-pmu
+ - brcm,vulcan-pmu
+ - cavium,thunder-pmu
+ - qcom,scorpion-pmu
+ - qcom,scorpion-mp-pmu
+ - qcom,krait-pmu
+
+ interrupts:
+ # Don't know how many CPUs, so no constraints to specify
+ description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
+
+ interrupt-affinity:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ When using SPIs, specifies a list of phandles to CPU
+ nodes corresponding directly to the affinity of
+ the SPIs listed in the interrupts property.
+
+ When using a PPI, specifies a list of phandles to CPU
+ nodes corresponding to the set of CPUs which have
+ a PMU of this type signalling the PPI listed in the
+ interrupts property, unless this is already specified
+ by the PPI interrupt specifier itself (in which case
+ the interrupt-affinity property shouldn't be present).
+
+ This property should be present when there is more than
+ a single SPI.
+
+ qcom,no-pc-write:
+ type: boolean
+ description:
+ Indicates that this PMU doesn't support the 0xc and 0xd events.
+
+ secure-reg-access:
+ type: boolean
+ description:
+ Indicates that the ARMv7 Secure Debug Enable Register
+ (SDER) is accessible. This will cause the driver to do
+ any setup required that is only possible in ARMv7 secure
+ state. If not present the ARMv7 SDER will not be touched,
+ which means the PMU may fail to operate unless external
+ code (bootloader or security monitor) has performed the
+ appropriate initialisation. Note that this property is
+ not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
+ in Non-secure state.
+
+required:
+ - compatible
+
+...
diff --git a/dts/Bindings/arm/renesas.yaml b/dts/Bindings/arm/renesas.yaml
new file mode 100644
index 0000000..19f3798
--- /dev/null
+++ b/dts/Bindings/arm/renesas.yaml
@@ -0,0 +1,238 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/shmobile.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: Emma Mobile EV2
+ items:
+ - enum:
+ - renesas,kzm9d # Kyoto Microcomputer Co. KZM-A9-Dual
+ - const: renesas,emev2
+
+ - description: RZ/A1H (R7S72100)
+ items:
+ - enum:
+ - renesas,genmai # Genmai (RTK772100BC00000BR)
+ - renesas,gr-peach # GR-Peach (X28A-M01-E/F)
+ - renesas,rskrza1 # RSKRZA1 (YR0K77210C000BE)
+ - const: renesas,r7s72100
+
+ - description: RZ/A2 (R7S9210)
+ items:
+ - enum:
+ - renesas,rza2mevb # RZ/A2M Eval Board (RTK7921053S00000BE)
+ - const: renesas,r7s9210
+
+ - description: SH-Mobile AG5 (R8A73A00/SH73A0)
+ items:
+ - enum:
+ - renesas,kzm9g # Kyoto Microcomputer Co. KZM-A9-GT
+ - const: renesas,sh73a0
+
+ - description: R-Mobile APE6 (R8A73A40)
+ items:
+ - enum:
+ - renesas,ape6evm
+ - const: renesas,r8a73a4
+
+ - description: R-Mobile A1 (R8A77400)
+ items:
+ - enum:
+ - renesas,armadillo800eva # Atmark Techno Armadillo-800 EVA
+ - const: renesas,r8a7740
+
+ - description: RZ/G1H (R8A77420)
+ items:
+ - const: renesas,r8a7742
+
+ - description: RZ/G1M (R8A77430)
+ items:
+ - enum:
+ # iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
+ - iwave,g20d
+ - const: iwave,g20m
+ - const: renesas,r8a7743
+
+ - items:
+ - enum:
+ # iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
+ - iwave,g20m
+ - renesas,sk-rzg1m # SK-RZG1M (YR8A77430S000BE)
+ - const: renesas,r8a7743
+
+ - description: RZ/G1N (R8A77440)
+ items:
+ - enum:
+ # iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven)
+ - iwave,g20d
+ - const: iwave,g20m
+ - const: renesas,r8a7744
+
+ - items:
+ - enum:
+ # iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven)
+ - iwave,g20m
+ - const: renesas,r8a7744
+
+ - description: RZ/G1E (R8A77450)
+ items:
+ - enum:
+ - iwave,g22m # iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
+ - renesas,sk-rzg1e # SK-RZG1E (YR8A77450S000BE)
+ - const: renesas,r8a7745
+
+ - description: iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
+ items:
+ - const: iwave,g22d
+ - const: iwave,g22m
+ - const: renesas,r8a7745
+
+ - description: RZ/G1C (R8A77470)
+ items:
+ - enum:
+ - iwave,g23s #iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S)
+ - const: renesas,r8a77470
+
+ - description: RZ/G2M (R8A774A1)
+ items:
+ - const: renesas,r8a774a1
+
+ - description: RZ/G2E (R8A774C0)
+ items:
+ - enum:
+ - si-linux,cat874 # Silicon Linux RZ/G2E 96board platform (CAT874)
+ - const: renesas,r8a774c0
+
+ - items:
+ - enum:
+ - si-linux,cat875 # Silicon Linux sub board for CAT874 (CAT875)
+ - const: si-linux,cat874
+ - const: renesas,r8a774c0
+
+ - description: R-Car M1A (R8A77781)
+ items:
+ - enum:
+ - renesas,bockw
+ - const: renesas,r8a7778
+
+ - description: R-Car H1 (R8A77790)
+ items:
+ - enum:
+ - renesas,marzen # Marzen (R0P7779A00010S)
+ - const: renesas,r8a7779
+
+ - description: R-Car H2 (R8A77900)
+ items:
+ - enum:
+ - renesas,lager # Lager (RTP0RC7790SEB00010S)
+ - renesas,stout # Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
+ - const: renesas,r8a7790
+
+ - description: R-Car M2-W (R8A77910)
+ items:
+ - enum:
+ - renesas,henninger
+ - renesas,koelsch # Koelsch (RTP0RC7791SEB00010S)
+ - renesas,porter # Porter (M2-LCDP)
+ - const: renesas,r8a7791
+
+ - description: R-Car V2H (R8A77920)
+ items:
+ - enum:
+ - renesas,blanche # Blanche (RTP0RC7792SEB00010S)
+ - renesas,wheat # Wheat (RTP0RC7792ASKB0000JE)
+ - const: renesas,r8a7792
+
+ - description: R-Car M2-N (R8A77930)
+ items:
+ - enum:
+ - renesas,gose # Gose (RTP0RC7793SEB00010S)
+ - const: renesas,r8a7793
+
+ - description: R-Car E2 (R8A77940)
+ items:
+ - enum:
+ - renesas,alt # Alt (RTP0RC7794SEB00010S)
+ - renesas,silk # SILK (RTP0RC7794LCB00011S)
+ - const: renesas,r8a7794
+
+ - description: R-Car H3 (R8A77950)
+ items:
+ - enum:
+ # H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1))
+ # H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0))
+ - renesas,h3ulcb
+ - renesas,salvator-x # Salvator-X (RTP0RC7795SIPB0010S)
+ - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
+ - const: renesas,r8a7795
+
+ - description: R-Car M3-W (R8A77960)
+ items:
+ - enum:
+ - renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0))
+ - renesas,salvator-x # Salvator-X (RTP0RC7796SIPB0011S)
+ - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
+ - const: renesas,r8a7796
+
+ - description: Kingfisher (SBEV-RCAR-KF-M03)
+ items:
+ - const: shimafuji,kingfisher
+ - enum:
+ - renesas,h3ulcb
+ - renesas,m3ulcb
+ - enum:
+ - renesas,r8a7795
+ - renesas,r8a7796
+
+ - description: R-Car M3-N (R8A77965)
+ items:
+ - enum:
+ - renesas,m3nulcb # M3NULCB (R-Car Starter Kit Pro, RTP0RC77965SKBX010SA00 (M3-N ES1.1))
+ - renesas,salvator-x # Salvator-X (RTP0RC7796SIPB0011S (M3-N))
+ - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S)
+ - const: renesas,r8a77965
+
+ - description: R-Car V3M (R8A77970)
+ items:
+ - enum:
+ - renesas,eagle # Eagle (RTP0RC77970SEB0010S)
+ - renesas,v3msk # V3MSK (Y-ASK-RCAR-V3M-WS10)
+ - const: renesas,r8a77970
+
+ - description: R-Car V3H (R8A77980)
+ items:
+ - enum:
+ - renesas,condor # Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01)
+ - renesas,v3hsk # V3HSK (Y-ASK-RCAR-V3H-WS10)
+ - const: renesas,r8a77980
+
+ - description: R-Car E3 (R8A77990)
+ items:
+ - enum:
+ - renesas,ebisu # Ebisu (RTP0RC77990SEB0010S)
+ - const: renesas,r8a77990
+
+ - description: R-Car D3 (R8A77995)
+ items:
+ - enum:
+ - renesas,draak # Draak (RTP0RC77995SEB0010S)
+ - const: renesas,r8a77995
+
+ - description: RZ/N1D (R9A06G032)
+ items:
+ - enum:
+ - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
+ - const: renesas,r9a06g032
+
+...
diff --git a/dts/Bindings/arm/rockchip.yaml b/dts/Bindings/arm/rockchip.yaml
index b12958b..061a03e 100644
--- a/dts/Bindings/arm/rockchip.yaml
+++ b/dts/Bindings/arm/rockchip.yaml
@@ -60,6 +60,11 @@ properties:
- const: chipspark,rayeager-px2
- const: rockchip,rk3066a
+ - description: Elgin RV1108 R1
+ items:
+ - const: elgin,rv1108-r1
+ - const: rockchip,rv1108
+
- description: Firefly Firefly-RK3288
items:
- enum:
@@ -87,6 +92,13 @@ properties:
- const: firefly,roc-rk3399-pc
- const: rockchip,rk3399
+ - description: FriendlyElec NanoPi4 series boards
+ items:
+ - enum:
+ - friendlyarm,nanopc-t4
+ - friendlyarm,nanopi-m4
+ - const: rockchip,rk3399
+
- description: GeekBuying GeekBox
items:
- const: geekbuying,geekbox
@@ -317,6 +329,11 @@ properties:
- const: radxa,rock
- const: rockchip,rk3188
+ - description: Radxa ROCK Pi 4
+ items:
+ - const: radxa,rockpi4
+ - const: rockchip,rk3399
+
- description: Radxa Rock2 Square
items:
- const: radxa,rock2-square
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
deleted file mode 100644
index 7f91c2a..0000000
--- a/dts/Bindings/arm/shmobile.txt
+++ /dev/null
@@ -1,155 +0,0 @@
-Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
---------------------------------------------------------------------
-
-SoCs:
-
- - Emma Mobile EV2
- compatible = "renesas,emev2"
- - RZ/A1H (R7S72100)
- compatible = "renesas,r7s72100"
- - RZ/A2 (R7S9210)
- compatible = "renesas,r7s9210"
- - SH-Mobile AG5 (R8A73A00/SH73A0)
- compatible = "renesas,sh73a0"
- - R-Mobile APE6 (R8A73A40)
- compatible = "renesas,r8a73a4"
- - R-Mobile A1 (R8A77400)
- compatible = "renesas,r8a7740"
- - RZ/G1H (R8A77420)
- compatible = "renesas,r8a7742"
- - RZ/G1M (R8A77430)
- compatible = "renesas,r8a7743"
- - RZ/G1N (R8A77440)
- compatible = "renesas,r8a7744"
- - RZ/G1E (R8A77450)
- compatible = "renesas,r8a7745"
- - RZ/G1C (R8A77470)
- compatible = "renesas,r8a77470"
- - RZ/G2M (R8A774A1)
- compatible = "renesas,r8a774a1"
- - RZ/G2E (R8A774C0)
- compatible = "renesas,r8a774c0"
- - R-Car M1A (R8A77781)
- compatible = "renesas,r8a7778"
- - R-Car H1 (R8A77790)
- compatible = "renesas,r8a7779"
- - R-Car H2 (R8A77900)
- compatible = "renesas,r8a7790"
- - R-Car M2-W (R8A77910)
- compatible = "renesas,r8a7791"
- - R-Car V2H (R8A77920)
- compatible = "renesas,r8a7792"
- - R-Car M2-N (R8A77930)
- compatible = "renesas,r8a7793"
- - R-Car E2 (R8A77940)
- compatible = "renesas,r8a7794"
- - R-Car H3 (R8A77950)
- compatible = "renesas,r8a7795"
- - R-Car M3-W (R8A77960)
- compatible = "renesas,r8a7796"
- - R-Car M3-N (R8A77965)
- compatible = "renesas,r8a77965"
- - R-Car V3M (R8A77970)
- compatible = "renesas,r8a77970"
- - R-Car V3H (R8A77980)
- compatible = "renesas,r8a77980"
- - R-Car E3 (R8A77990)
- compatible = "renesas,r8a77990"
- - R-Car D3 (R8A77995)
- compatible = "renesas,r8a77995"
- - RZ/N1D (R9A06G032)
- compatible = "renesas,r9a06g032"
-
-Boards:
-
- - Alt (RTP0RC7794SEB00010S)
- compatible = "renesas,alt", "renesas,r8a7794"
- - APE6-EVM
- compatible = "renesas,ape6evm", "renesas,r8a73a4"
- - Atmark Techno Armadillo-800 EVA
- compatible = "renesas,armadillo800eva", "renesas,r8a7740"
- - Blanche (RTP0RC7792SEB00010S)
- compatible = "renesas,blanche", "renesas,r8a7792"
- - BOCK-W
- compatible = "renesas,bockw", "renesas,r8a7778"
- - Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01)
- compatible = "renesas,condor", "renesas,r8a77980"
- - Draak (RTP0RC77995SEB0010S)
- compatible = "renesas,draak", "renesas,r8a77995"
- - Eagle (RTP0RC77970SEB0010S)
- compatible = "renesas,eagle", "renesas,r8a77970"
- - Ebisu (RTP0RC77990SEB0010S)
- compatible = "renesas,ebisu", "renesas,r8a77990"
- - Genmai (RTK772100BC00000BR)
- compatible = "renesas,genmai", "renesas,r7s72100"
- - GR-Peach (X28A-M01-E/F)
- compatible = "renesas,gr-peach", "renesas,r7s72100"
- - Gose (RTP0RC7793SEB00010S)
- compatible = "renesas,gose", "renesas,r8a7793"
- - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1))
- H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0))
- compatible = "renesas,h3ulcb", "renesas,r8a7795"
- - Henninger
- compatible = "renesas,henninger", "renesas,r8a7791"
- - iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S)
- compatible = "iwave,g23s", "renesas,r8a77470"
- - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
- compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
- - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
- compatible = "iwave,g22m", "renesas,r8a7745"
- - iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
- compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
- - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
- compatible = "iwave,g20m", "renesas,r8a7743"
- - iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven)
- compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"
- - iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven)
- compatible = "iwave,g20m", "renesas,r8a7744"
- - Kingfisher (SBEV-RCAR-KF-M03)
- compatible = "shimafuji,kingfisher"
- - Koelsch (RTP0RC7791SEB00010S)
- compatible = "renesas,koelsch", "renesas,r8a7791"
- - Kyoto Microcomputer Co. KZM-A9-Dual
- compatible = "renesas,kzm9d", "renesas,emev2"
- - Kyoto Microcomputer Co. KZM-A9-GT
- compatible = "renesas,kzm9g", "renesas,sh73a0"
- - Lager (RTP0RC7790SEB00010S)
- compatible = "renesas,lager", "renesas,r8a7790"
- - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0))
- compatible = "renesas,m3ulcb", "renesas,r8a7796"
- - M3NULCB (R-Car Starter Kit Pro, RTP0RC77965SKBX010SA00 (M3-N ES1.1))
- compatible = "renesas,m3nulcb", "renesas,r8a77965"
- - Marzen (R0P7779A00010S)
- compatible = "renesas,marzen", "renesas,r8a7779"
- - Porter (M2-LCDP)
- compatible = "renesas,porter", "renesas,r8a7791"
- - RSKRZA1 (YR0K77210C000BE)
- compatible = "renesas,rskrza1", "renesas,r7s72100"
- - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
- compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"
- - Salvator-X (RTP0RC7795SIPB0010S)
- compatible = "renesas,salvator-x", "renesas,r8a7795"
- - Salvator-X (RTP0RC7796SIPB0011S)
- compatible = "renesas,salvator-x", "renesas,r8a7796"
- - Salvator-X (RTP0RC7796SIPB0011S (M3-N))
- compatible = "renesas,salvator-x", "renesas,r8a77965"
- - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
- compatible = "renesas,salvator-xs", "renesas,r8a7795"
- - Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
- compatible = "renesas,salvator-xs", "renesas,r8a7796"
- - Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S)
- compatible = "renesas,salvator-xs", "renesas,r8a77965"
- - SILK (RTP0RC7794LCB00011S)
- compatible = "renesas,silk", "renesas,r8a7794"
- - SK-RZG1E (YR8A77450S000BE)
- compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
- - SK-RZG1M (YR8A77430S000BE)
- compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
- - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
- compatible = "renesas,stout", "renesas,r8a7790"
- - V3HSK (Y-ASK-RCAR-V3H-WS10)
- compatible = "renesas,v3hsk", "renesas,r8a77980"
- - V3MSK (Y-ASK-RCAR-V3M-WS10)
- compatible = "renesas,v3msk", "renesas,r8a77970"
- - Wheat (RTP0RC7792ASKB0000JE)
- compatible = "renesas,wheat", "renesas,r8a7792"
diff --git a/dts/Bindings/arm/socionext/milbeaut.yaml b/dts/Bindings/arm/socionext/milbeaut.yaml
new file mode 100644
index 0000000..aae53fc
--- /dev/null
+++ b/dts/Bindings/arm/socionext/milbeaut.yaml
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/milbeaut.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Milbeaut platforms device tree bindings
+
+maintainers:
+ - Taichi Sugaya <sugaya.taichi@socionext.com>
+ - Takao Orito <orito.takao@socionext.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - socionext,milbeaut-m10v-evb
+ - const: socionext,sc2000a
+...
diff --git a/dts/Bindings/arm/technologic.txt b/dts/Bindings/arm/technologic.txt
deleted file mode 100644
index f1cedc0..0000000
--- a/dts/Bindings/arm/technologic.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Technologic Systems Platforms Device Tree Bindings
---------------------------------------------------
-
-TS-4600 is a System-on-Module based on the Freescale i.MX28 System-on-Chip.
-It can be mounted on a carrier board providing additional peripheral connectors.
-Required root node properties:
- - compatible = "technologic,imx28-ts4600", "fsl,imx28"
-
-TS-4800 board
-Required root node properties:
- - compatible = "technologic,imx51-ts4800", "fsl,imx51";
-
-TS-4900 is a System-on-Module based on the Freescale i.MX6 System-on-Chip.
-It can be mounted on a carrier board providing additional peripheral connectors.
-Required root node properties:
- - compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"
- - compatible = "technologic,imx6q-ts4900", "fsl,imx6q"
-
-TS-7970 is a System-on-Module based on the Freescale i.MX6 System-on-Chip.
-It can be mounted on a carrier board providing additional peripheral connectors.
-Required root node properties:
- - compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl"
- - compatible = "technologic,imx6q-ts7970", "fsl,imx6q"
diff --git a/dts/Bindings/arm/tegra.yaml b/dts/Bindings/arm/tegra.yaml
index fbcde8a..60b38eb 100644
--- a/dts/Bindings/arm/tegra.yaml
+++ b/dts/Bindings/arm/tegra.yaml
@@ -87,9 +87,11 @@ properties:
- const: nvidia,tegra124
- items:
- enum:
+ - nvidia,darcy
- nvidia,p2371-0000
- nvidia,p2371-2180
- nvidia,p2571
+ - nvidia,p2894-0050-a08
- const: nvidia,tegra210
- items:
- enum: