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-rw-r--r--dts/Bindings/arm/adapteva.txt7
-rw-r--r--dts/Bindings/arm/amlogic.txt13
-rw-r--r--dts/Bindings/arm/atmel-pmc.txt14
-rw-r--r--dts/Bindings/arm/bcm/brcm,brcmstb.txt4
-rw-r--r--dts/Bindings/arm/coresight.txt58
-rw-r--r--dts/Bindings/arm/cpu-capacity.txt2
-rw-r--r--dts/Bindings/arm/cpus.txt2
-rw-r--r--dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt3
-rw-r--r--dts/Bindings/arm/freescale/m4if.txt12
-rw-r--r--dts/Bindings/arm/freescale/tigerp.txt12
-rw-r--r--dts/Bindings/arm/fsl.txt4
-rw-r--r--dts/Bindings/arm/idle-states.txt4
-rw-r--r--dts/Bindings/arm/insignal-boards.txt8
-rw-r--r--dts/Bindings/arm/marvell/ap806-system-controller.txt48
-rw-r--r--dts/Bindings/arm/marvell/armada-37xx.txt15
-rw-r--r--dts/Bindings/arm/marvell/cp110-system-controller.txt (renamed from dts/Bindings/arm/marvell/cp110-system-controller0.txt)61
-rw-r--r--dts/Bindings/arm/mediatek.txt10
-rw-r--r--dts/Bindings/arm/msm/qcom,llcc.txt26
-rw-r--r--dts/Bindings/arm/omap/crossbar.txt1
-rw-r--r--dts/Bindings/arm/omap/l4.txt15
-rw-r--r--dts/Bindings/arm/rockchip.txt14
-rw-r--r--dts/Bindings/arm/samsung/pmu.txt3
-rw-r--r--dts/Bindings/arm/samsung/samsung-boards.txt5
-rw-r--r--dts/Bindings/arm/shmobile.txt5
-rw-r--r--dts/Bindings/arm/ti/k3.txt23
-rw-r--r--dts/Bindings/arm/xilinx.txt30
26 files changed, 330 insertions, 69 deletions
diff --git a/dts/Bindings/arm/adapteva.txt b/dts/Bindings/arm/adapteva.txt
deleted file mode 100644
index 1d8af9e..0000000
--- a/dts/Bindings/arm/adapteva.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Adapteva Platforms Device Tree Bindings
----------------------------------------
-
-Parallella board
-
-Required root node properties:
- - compatible = "adapteva,parallella";
diff --git a/dts/Bindings/arm/amlogic.txt b/dts/Bindings/arm/amlogic.txt
index 6988056..b5c2b5c 100644
--- a/dts/Bindings/arm/amlogic.txt
+++ b/dts/Bindings/arm/amlogic.txt
@@ -41,6 +41,14 @@ Boards with the Amlogic Meson GXL S905D SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s905d", "amlogic,meson-gxl";
+Boards with the Amlogic Meson GXL S805X SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,s805x", "amlogic,meson-gxl";
+
+Boards with the Amlogic Meson GXL S905W SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,s905w", "amlogic,meson-gxl";
+
Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s912", "amlogic,meson-gxm";
@@ -79,6 +87,11 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,p230" (Meson gxl s905d)
- "amlogic,p231" (Meson gxl s905d)
+ - "amlogic,p241" (Meson gxl s805x)
+
+ - "amlogic,p281" (Meson gxl s905w)
+ - "oranth,tx3-mini" (Meson gxl s905w)
+
- "amlogic,q200" (Meson gxm s912)
- "amlogic,q201" (Meson gxm s912)
- "khadas,vim2" (Meson gxm s912)
diff --git a/dts/Bindings/arm/atmel-pmc.txt b/dts/Bindings/arm/atmel-pmc.txt
deleted file mode 100644
index 795cc78..0000000
--- a/dts/Bindings/arm/atmel-pmc.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Power Management Controller (PMC)
-
-Required properties:
-- compatible: Should be "atmel,<chip>-pmc".
- <chip> can be: at91rm9200, at91sam9260, at91sam9g45, at91sam9n12,
- at91sam9x5, sama5d3
-
-- reg: Should contain PMC registers location and length
-
-Examples:
- pmc: pmc@fffffc00 {
- compatible = "atmel,at91rm9200-pmc";
- reg = <0xfffffc00 0x100>;
- };
diff --git a/dts/Bindings/arm/bcm/brcm,brcmstb.txt b/dts/Bindings/arm/bcm/brcm,brcmstb.txt
index c052caa..104cc9b 100644
--- a/dts/Bindings/arm/bcm/brcm,brcmstb.txt
+++ b/dts/Bindings/arm/bcm/brcm,brcmstb.txt
@@ -189,7 +189,11 @@ Power-Down (SRPD), among other things.
Required properties:
- compatible : should contain one of these
+ "brcm,brcmstb-memc-ddr-rev-b.2.1"
"brcm,brcmstb-memc-ddr-rev-b.2.2"
+ "brcm,brcmstb-memc-ddr-rev-b.2.3"
+ "brcm,brcmstb-memc-ddr-rev-b.3.0"
+ "brcm,brcmstb-memc-ddr-rev-b.3.1"
"brcm,brcmstb-memc-ddr"
- reg : the MEMC DDR register range
diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt
index 15ac8e8..5d1ad09 100644
--- a/dts/Bindings/arm/coresight.txt
+++ b/dts/Bindings/arm/coresight.txt
@@ -39,6 +39,8 @@ its hardware characteristcs.
- System Trace Macrocell:
"arm,coresight-stm", "arm,primecell"; [1]
+ - Coresight Address Translation Unit (CATU)
+ "arm,coresight-catu", "arm,primecell";
* reg: physical base address and length of the register
set(s) of the component.
@@ -84,8 +86,15 @@ its hardware characteristcs.
* Optional property for TMC:
* arm,buffer-size: size of contiguous buffer space for TMC ETR
- (embedded trace router)
+ (embedded trace router). This property is obsolete. The buffer size
+ can be configured dynamically via buffer_size property in sysfs.
+ * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
+ use the SG mode on this system.
+
+* Optional property for CATU :
+ * interrupts : Exactly one SPI may be listed for reporting the address
+ error
Example:
@@ -118,6 +127,35 @@ Example:
};
};
+ etr@20070000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x20070000 0 0x1000>;
+
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* input port */
+ port@0 {
+ reg = <0>;
+ etr_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator2_out_port0>;
+ };
+ };
+
+ /* CATU link represented by output port */
+ port@1 {
+ reg = <1>;
+ etr_out_port: endpoint {
+ remote-endpoint = <&catu_in_port>;
+ };
+ };
+ };
+ };
+
2. Links
replicator {
/* non-configurable replicators don't show up on the
@@ -247,5 +285,23 @@ Example:
};
};
+5. CATU
+
+ catu@207e0000 {
+ compatible = "arm,coresight-catu", "arm,primecell";
+ reg = <0 0x207e0000 0 0x1000>;
+
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ port {
+ catu_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&etr_out_port>;
+ };
+ };
+ };
+
[1]. There is currently two version of STM: STM32 and STM500. Both
have the same HW interface and as such don't need an explicit binding name.
diff --git a/dts/Bindings/arm/cpu-capacity.txt b/dts/Bindings/arm/cpu-capacity.txt
index 7809fbe..9b5685a 100644
--- a/dts/Bindings/arm/cpu-capacity.txt
+++ b/dts/Bindings/arm/cpu-capacity.txt
@@ -94,7 +94,7 @@ cpus {
};
idle-states {
- entry-method = "arm,psci";
+ entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt
index 29e1dc5..96dfccc 100644
--- a/dts/Bindings/arm/cpus.txt
+++ b/dts/Bindings/arm/cpus.txt
@@ -183,6 +183,7 @@ described below.
"marvell,sheeva-v5"
"nvidia,tegra132-denver"
"nvidia,tegra186-denver"
+ "nvidia,tegra194-carmel"
"qcom,krait"
"qcom,kryo"
"qcom,kryo385"
@@ -219,6 +220,7 @@ described below.
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
"renesas,apmu"
+ "renesas,r9a06g032-smp"
"rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"
diff --git a/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt b/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt
index 669808b..6dd6f39 100644
--- a/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt
+++ b/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt
@@ -18,9 +18,6 @@ Required properties:
assignment of the interrupt router is required.
Flags get passed only when using GIC as parent. Flags
encoding as documented by the GIC bindings.
-- interrupt-parent: Should be the phandle for the interrupt controller of
- the CPU the device tree is intended to be used on. This
- is either the node of the GIC or NVIC controller.
Example:
mscm_ir: interrupt-controller@40001800 {
diff --git a/dts/Bindings/arm/freescale/m4if.txt b/dts/Bindings/arm/freescale/m4if.txt
new file mode 100644
index 0000000..93bd7b8
--- /dev/null
+++ b/dts/Bindings/arm/freescale/m4if.txt
@@ -0,0 +1,12 @@
+* Freescale Multi Master Multi Memory Interface (M4IF) module
+
+Required properties:
+- compatible : Should be "fsl,imx51-m4if"
+- reg : Address and length of the register set for the device
+
+Example:
+
+m4if: m4if@83fd8000 {
+ compatible = "fsl,imx51-m4if";
+ reg = <0x83fd8000 0x1000>;
+};
diff --git a/dts/Bindings/arm/freescale/tigerp.txt b/dts/Bindings/arm/freescale/tigerp.txt
new file mode 100644
index 0000000..19e2aad
--- /dev/null
+++ b/dts/Bindings/arm/freescale/tigerp.txt
@@ -0,0 +1,12 @@
+* Freescale Tigerp platform module
+
+Required properties:
+- compatible : Should be "fsl,imx51-tigerp"
+- reg : Address and length of the register set for the device
+
+Example:
+
+tigerp: tigerp@83fa0000 {
+ compatible = "fsl,imx51-tigerp";
+ reg = <0x83fa0000 0x28>;
+};
diff --git a/dts/Bindings/arm/fsl.txt b/dts/Bindings/arm/fsl.txt
index cdb9dd7..8a1baa2 100644
--- a/dts/Bindings/arm/fsl.txt
+++ b/dts/Bindings/arm/fsl.txt
@@ -53,6 +53,10 @@ i.MX6 Quad SABRE Automotive Board
Required root node properties:
- compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+i.MX6SLL EVK board
+Required root node properties:
+ - compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
+
Generic i.MX boards
-------------------
diff --git a/dts/Bindings/arm/idle-states.txt b/dts/Bindings/arm/idle-states.txt
index 7a59133..2c73847 100644
--- a/dts/Bindings/arm/idle-states.txt
+++ b/dts/Bindings/arm/idle-states.txt
@@ -237,8 +237,8 @@ processor idle states, defined as device tree nodes, are listed.
Value type: <stringlist>
Usage and definition depend on ARM architecture version.
# On ARM v8 64-bit this property is required and must
- be one of:
- - "psci" (see bindings in [2])
+ be:
+ - "psci"
# On ARM 32-bit systems this property is optional
The nodes describing the idle states (state) can only be defined within the
diff --git a/dts/Bindings/arm/insignal-boards.txt b/dts/Bindings/arm/insignal-boards.txt
deleted file mode 100644
index 524c3dc..0000000
--- a/dts/Bindings/arm/insignal-boards.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-* Insignal's Exynos4210 based Origen evaluation board
-
-Origen low-cost evaluation board is based on Samsung's Exynos4210 SoC.
-
-Required root node properties:
- - compatible = should be one or more of the following.
- (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
- (b) "samsung,exynos4210" - for boards based on Exynos4210 SoC.
diff --git a/dts/Bindings/arm/marvell/ap806-system-controller.txt b/dts/Bindings/arm/marvell/ap806-system-controller.txt
index 0b88744..3fd21bb 100644
--- a/dts/Bindings/arm/marvell/ap806-system-controller.txt
+++ b/dts/Bindings/arm/marvell/ap806-system-controller.txt
@@ -2,14 +2,17 @@ Marvell Armada AP806 System Controller
======================================
The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
-SoCs. It contains a system controller, which provides a number
-registers giving access to numerous features: clocks, pin-muxing and
-many other SoC configuration items. This DT binding allows to describe
-this system controller.
+SoCs. It contains system controllers, which provide several registers
+giving access to numerous features: clocks, pin-muxing and many other
+SoC configuration items. This DT binding allows to describe these
+system controllers.
For the top level node:
- compatible: must be: "syscon", "simple-mfd";
- - reg: register area of the AP806 system controller
+ - reg: register area of the AP806 system controller
+
+SYSTEM CONTROLLER 0
+===================
Clocks:
-------
@@ -98,3 +101,38 @@ ap_syscon: system-controller@6f4000 {
gpio-ranges = <&ap_pinctrl 0 0 19>;
};
};
+
+SYSTEM CONTROLLER 1
+===================
+
+Thermal:
+--------
+
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/thermal/thermal.txt
+
+The thermal IP can probe the temperature all around the processor. It
+may feature several channels, each of them wired to one sensor.
+
+Required properties:
+- compatible: must be one of:
+ * marvell,armada-ap806-thermal
+- reg: register range associated with the thermal functions.
+
+Optional properties:
+- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
+ to this IP and represents the channel ID. There is one sensor per
+ channel. O refers to the thermal IP internal channel, while positive
+ IDs refer to each CPU.
+
+Example:
+ap_syscon1: system-controller@6f8000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f8000 0x1000>;
+
+ ap_thermal: thermal-sensor@80 {
+ compatible = "marvell,armada-ap806-thermal";
+ reg = <0x80 0x10>;
+ #thermal-sensor-cells = <1>;
+ };
+};
diff --git a/dts/Bindings/arm/marvell/armada-37xx.txt b/dts/Bindings/arm/marvell/armada-37xx.txt
index 35c3c34..eddde4f 100644
--- a/dts/Bindings/arm/marvell/armada-37xx.txt
+++ b/dts/Bindings/arm/marvell/armada-37xx.txt
@@ -33,3 +33,18 @@ nb_pm: syscon@14000 {
compatible = "marvell,armada-3700-nb-pm", "syscon";
reg = <0x14000 0x60>;
}
+
+AVS
+---
+
+For AVS an other component is needed:
+
+Required properties:
+- compatible : should contain "marvell,armada-3700-avs", "syscon";
+- reg : the register start and length for the AVS
+
+Example:
+avs: avs@11500 {
+ compatible = "marvell,armada-3700-avs", "syscon";
+ reg = <0x11500 0x40>;
+}
diff --git a/dts/Bindings/arm/marvell/cp110-system-controller0.txt b/dts/Bindings/arm/marvell/cp110-system-controller.txt
index 29cdbae..81ce742 100644
--- a/dts/Bindings/arm/marvell/cp110-system-controller0.txt
+++ b/dts/Bindings/arm/marvell/cp110-system-controller.txt
@@ -1,15 +1,18 @@
-Marvell Armada CP110 System Controller 0
-========================================
+Marvell Armada CP110 System Controller
+======================================
The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
-SoCs. It contains two sets of system control registers, System
-Controller 0 and System Controller 1. This Device Tree binding allows
-to describe the first system controller, which provides registers to
-configure various aspects of the SoC.
+SoCs. It contains system controllers, which provide several registers
+giving access to numerous features: clocks, pin-muxing and many other
+SoC configuration items. This DT binding allows to describe these
+system controllers.
For the top level node:
- compatible: must be: "syscon", "simple-mfd";
- - reg: register area of the CP110 system controller 0
+ - reg: register area of the CP110 system controller
+
+SYSTEM CONTROLLER 0
+===================
Clocks:
-------
@@ -163,26 +166,60 @@ Required properties:
Example:
-cpm_syscon0: system-controller@440000 {
+CP110_LABEL(syscon0): system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
- cpm_clk: clock {
+ CP110_LABEL(clk): clock {
compatible = "marvell,cp110-clock";
#clock-cells = <2>;
};
- cpm_pinctrl: pinctrl {
+ CP110_LABEL(pinctrl): pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
};
- cpm_gpio1: gpio@100 {
+ CP110_LABEL(gpio1): gpio@100 {
compatible = "marvell,armada-8k-gpio";
offset = <0x100>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&cpm_pinctrl 0 0 32>;
+ gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
};
};
+
+SYSTEM CONTROLLER 1
+===================
+
+Thermal:
+--------
+
+The thermal IP can probe the temperature all around the processor. It
+may feature several channels, each of them wired to one sensor.
+
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/thermal/thermal.txt
+
+Required properties:
+- compatible: must be one of:
+ * marvell,armada-cp110-thermal
+- reg: register range associated with the thermal functions.
+
+Optional properties:
+- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
+ to this IP and represents the channel ID. There is one sensor per
+ channel. O refers to the thermal IP internal channel.
+
+Example:
+CP110_LABEL(syscon1): system-controller@6f8000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f8000 0x1000>;
+
+ CP110_LABEL(thermal): thermal-sensor@70 {
+ compatible = "marvell,armada-cp110-thermal";
+ reg = <0x70 0x10>;
+ #thermal-sensor-cells = <1>;
+ };
+};
diff --git a/dts/Bindings/arm/mediatek.txt b/dts/Bindings/arm/mediatek.txt
index 7d21ab3..8f260e5 100644
--- a/dts/Bindings/arm/mediatek.txt
+++ b/dts/Bindings/arm/mediatek.txt
@@ -11,6 +11,7 @@ compatible: Must contain one of
"mediatek,mt6589"
"mediatek,mt6592"
"mediatek,mt6755"
+ "mediatek,mt6765"
"mediatek,mt6795"
"mediatek,mt6797"
"mediatek,mt7622"
@@ -41,12 +42,18 @@ Supported boards:
- Evaluation phone for MT6755(Helio P10):
Required root node properties:
- compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
+- Evaluation board for MT6765(Helio P22):
+ Required root node properties:
+ - compatible = "mediatek,mt6765-evb", "mediatek,mt6765";
- Evaluation board for MT6795(Helio X10):
Required root node properties:
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
- Evaluation board for MT6797(Helio X20):
Required root node properties:
- compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
+- Mediatek X20 Development Board:
+ Required root node properties:
+ - compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
@@ -59,9 +66,6 @@ Supported boards:
- Reference board for MT7623n with eMMC:
Required root node properties:
- compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
-- Reference board for MT7623n with NAND:
- Required root node properties:
- - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
- Bananapi BPI-R2 board:
- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
- MTK mt8127 tablet moose EVB:
diff --git a/dts/Bindings/arm/msm/qcom,llcc.txt b/dts/Bindings/arm/msm/qcom,llcc.txt
new file mode 100644
index 0000000..5e85749
--- /dev/null
+++ b/dts/Bindings/arm/msm/qcom,llcc.txt
@@ -0,0 +1,26 @@
+== Introduction==
+
+LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
+that can be shared by multiple clients. Clients here are different cores in the
+SOC, the idea is to minimize the local caches at the clients and migrate to
+common pool of memory. Cache memory is divided into partitions called slices
+which are assigned to clients. Clients can query the slice details, activate
+and deactivate them.
+
+Properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,sdm845-llcc"
+
+- reg:
+ Usage: required
+ Value Type: <prop-encoded-array>
+ Definition: Start address and the the size of the register region.
+
+Example:
+
+ cache-controller@1100000 {
+ compatible = "qcom,sdm845-llcc";
+ reg = <0x1100000 0x250000>;
+ };
diff --git a/dts/Bindings/arm/omap/crossbar.txt b/dts/Bindings/arm/omap/crossbar.txt
index ecb360e..4cd5d87 100644
--- a/dts/Bindings/arm/omap/crossbar.txt
+++ b/dts/Bindings/arm/omap/crossbar.txt
@@ -10,7 +10,6 @@ Required properties:
- compatible : Should be "ti,irq-crossbar"
- reg: Base address and the size of the crossbar registers.
- interrupt-controller: indicates that this block is an interrupt controller.
-- interrupt-parent: the interrupt controller this block is connected to.
- ti,max-irqs: Total number of irqs available at the parent interrupt controller.
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
- ti,reg-size: Size of a individual register in bytes. Every individual
diff --git a/dts/Bindings/arm/omap/l4.txt b/dts/Bindings/arm/omap/l4.txt
index b4f8a16..6816adc 100644
--- a/dts/Bindings/arm/omap/l4.txt
+++ b/dts/Bindings/arm/omap/l4.txt
@@ -7,6 +7,7 @@ Required properties:
Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
+ Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus
Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
@@ -15,11 +16,21 @@ Required properties:
Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus
Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus
- ranges : contains the IO map range for the bus
+- reg : registers link agent and interconnect agent and access protection
+- reg-names : "la" for link agent, "ia0" to "ia3" for one to three
+ interconnect agent instances, "ap" for access if it exists
Examples:
-l4: l4@48000000 {
- compatible "ti,omap2-l4", "simple-bus";
+l4: interconnect@48000000 {
+ compatible "ti,omap4-l4-per", "simple-bus";
+ reg = <0x48000000 0x800>,
+ <0x48000800 0x800>,
+ <0x48001000 0x400>,
+ <0x48001400 0x400>,
+ <0x48001800 0x400>,
+ <0x48001c00 0x400>;
+ reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48000000 0x100000>;
diff --git a/dts/Bindings/arm/rockchip.txt b/dts/Bindings/arm/rockchip.txt
index 1c1d62d..acfd3c7 100644
--- a/dts/Bindings/arm/rockchip.txt
+++ b/dts/Bindings/arm/rockchip.txt
@@ -1,5 +1,10 @@
Rockchip platforms device tree bindings
---------------------------------------
+
+- 96boards RK3399 Ficus (ROCK960 Enterprise Edition)
+ Required root node properties:
+ - compatible = "vamrs,ficus", "rockchip,rk3399";
+
- Amarula Vyasa RK3288 board
Required root node properties:
- compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
@@ -66,6 +71,15 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "geekbuying,geekbox", "rockchip,rk3368";
+- Google Bob (Asus Chromebook Flip C101PA):
+ Required root node properties:
+ compatible = "google,bob-rev13", "google,bob-rev12",
+ "google,bob-rev11", "google,bob-rev10",
+ "google,bob-rev9", "google,bob-rev8",
+ "google,bob-rev7", "google,bob-rev6",
+ "google,bob-rev5", "google,bob-rev4",
+ "google,bob", "google,gru", "rockchip,rk3399";
+
- Google Brain (dev-board):
Required root node properties:
- compatible = "google,veyron-brain-rev0", "google,veyron-brain",
diff --git a/dts/Bindings/arm/samsung/pmu.txt b/dts/Bindings/arm/samsung/pmu.txt
index 1668578..433bfd7 100644
--- a/dts/Bindings/arm/samsung/pmu.txt
+++ b/dts/Bindings/arm/samsung/pmu.txt
@@ -40,9 +40,6 @@ following properties:
- #interrupt-cells: must be identical to the that of the parent interrupt
controller.
-- interrupt-parent: a phandle indicating which interrupt controller
- this PMU signals interrupts to.
-
Optional nodes:
diff --git a/dts/Bindings/arm/samsung/samsung-boards.txt b/dts/Bindings/arm/samsung/samsung-boards.txt
index 6970f30..56021bf 100644
--- a/dts/Bindings/arm/samsung/samsung-boards.txt
+++ b/dts/Bindings/arm/samsung/samsung-boards.txt
@@ -1,7 +1,10 @@
-* Samsung's Exynos SoC based boards
+* Samsung's Exynos and S5P SoC based boards
Required root node properties:
- compatible = should be one or more of the following.
+ - "samsung,aries" - for S5PV210-based Samsung Aries board.
+ - "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board.
+ - "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board.
- "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
- "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
- "samsung,monk" - for Exynos3250-based Samsung Simband board.
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
index d8cf740..89b4a38 100644
--- a/dts/Bindings/arm/shmobile.txt
+++ b/dts/Bindings/arm/shmobile.txt
@@ -51,7 +51,8 @@ SoCs:
compatible = "renesas,r8a77990"
- R-Car D3 (R8A77995)
compatible = "renesas,r8a77995"
-
+ - RZ/N1D (R9A06G032)
+ compatible = "renesas,r9a06g032"
Boards:
@@ -112,6 +113,8 @@ Boards:
compatible = "renesas,porter", "renesas,r8a7791"
- RSKRZA1 (YR0K77210C000BE)
compatible = "renesas,rskrza1", "renesas,r7s72100"
+ - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
+ compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"
- Salvator-X (RTP0RC7795SIPB0010S)
compatible = "renesas,salvator-x", "renesas,r8a7795"
- Salvator-X (RTP0RC7796SIPB0011S)
diff --git a/dts/Bindings/arm/ti/k3.txt b/dts/Bindings/arm/ti/k3.txt
new file mode 100644
index 0000000..6a059ca
--- /dev/null
+++ b/dts/Bindings/arm/ti/k3.txt
@@ -0,0 +1,23 @@
+Texas Instruments K3 Multicore SoC architecture device tree bindings
+--------------------------------------------------------------------
+
+Platforms based on Texas Instruments K3 Multicore SoC architecture
+shall follow the following scheme:
+
+SoCs
+----
+
+Each device tree root node must specify which exact SoC in K3 Multicore SoC
+architecture it uses, using one of the following compatible values:
+
+- AM654
+ compatible = "ti,am654";
+
+Boards
+------
+
+In addition, each device tree root node must specify which one or more
+of the following board-specific compatible values:
+
+- AM654 EVM
+ compatible = "ti,am654-evm", "ti,am654";
diff --git a/dts/Bindings/arm/xilinx.txt b/dts/Bindings/arm/xilinx.txt
index b9043bc..26fe5ec 100644
--- a/dts/Bindings/arm/xilinx.txt
+++ b/dts/Bindings/arm/xilinx.txt
@@ -8,18 +8,38 @@ Required root node properties:
Additional compatible strings:
-- Xilinx internal board cc108
+- Adapteva Parallella board
+ "adapteva,parallella"
+
+- Avnet MicroZed board
+ "avnet,zynq-microzed"
+ "xlnx,zynq-microzed"
+
+- Avnet ZedBoard board
+ "avnet,zynq-zed"
+ "xlnx,zynq-zed"
+
+- Digilent Zybo board
+ "digilent,zynq-zybo"
+
+- Digilent Zybo Z7 board
+ "digilent,zynq-zybo-z7"
+
+- Xilinx CC108 internal board
"xlnx,zynq-cc108"
-- Xilinx internal board zc770 with different FMC cards
+- Xilinx ZC702 internal board
+ "xlnx,zynq-zc702"
+
+- Xilinx ZC706 internal board
+ "xlnx,zynq-zc706"
+
+- Xilinx ZC770 internal board, with different FMC cards
"xlnx,zynq-zc770-xm010"
"xlnx,zynq-zc770-xm011"
"xlnx,zynq-zc770-xm012"
"xlnx,zynq-zc770-xm013"
-- Digilent Zybo Z7 board
- "digilent,zynq-zybo-z7"
-
---------------------------------------------------------------
Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings