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-rw-r--r--dts/Bindings/arm/actions.txt16
-rw-r--r--dts/Bindings/arm/arm-dsu-pmu.txt27
-rw-r--r--dts/Bindings/arm/atmel-at91.txt32
-rw-r--r--dts/Bindings/arm/axentia.txt9
-rw-r--r--dts/Bindings/arm/bcm/brcm,brcmstb.txt22
-rw-r--r--dts/Bindings/arm/cpus.txt1
-rw-r--r--dts/Bindings/arm/firmware/sdei.txt42
-rw-r--r--dts/Bindings/arm/marvell/armada-37xx.txt19
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,ethsys.txt1
-rw-r--r--dts/Bindings/arm/samsung/exynos-adc.txt6
-rw-r--r--dts/Bindings/arm/samsung/samsung-boards.txt2
-rw-r--r--dts/Bindings/arm/shmobile.txt4
-rw-r--r--dts/Bindings/arm/stm32.txt9
-rw-r--r--dts/Bindings/arm/technologic.txt11
14 files changed, 155 insertions, 46 deletions
diff --git a/dts/Bindings/arm/actions.txt b/dts/Bindings/arm/actions.txt
index ced764a854..d54f33c4e0 100644
--- a/dts/Bindings/arm/actions.txt
+++ b/dts/Bindings/arm/actions.txt
@@ -21,10 +21,26 @@ Boards:
Root node property compatible must contain, depending on board:
+ - Allo.com Sparky: "allo,sparky"
- Cubietech CubieBoard6: "cubietech,cubieboard6"
- LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", "lemaker,guitar"
+S700 SoC
+========
+
+Required root node properties:
+
+- compatible : must contain "actions,s700"
+
+
+Boards:
+
+Root node property compatible must contain, depending on board:
+
+ - Cubietech CubieBoard7: "cubietech,cubieboard7"
+
+
S900 SoC
========
diff --git a/dts/Bindings/arm/arm-dsu-pmu.txt b/dts/Bindings/arm/arm-dsu-pmu.txt
new file mode 100644
index 0000000000..6efabba530
--- /dev/null
+++ b/dts/Bindings/arm/arm-dsu-pmu.txt
@@ -0,0 +1,27 @@
+* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
+
+ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
+with a shared L3 memory system, control logic and external interfaces to
+form a multicore cluster. The PMU enables to gather various statistics on
+the operations of the DSU. The PMU provides independent 32bit counters that
+can count any of the supported events, along with a 64bit cycle counter.
+The PMU is accessed via CPU system registers and has no MMIO component.
+
+** DSU PMU required properties:
+
+- compatible : should be one of :
+
+ "arm,dsu-pmu"
+
+- interrupts : Exactly 1 SPI must be listed.
+
+- cpus : List of phandles for the CPUs connected to this DSU instance.
+
+
+** Example:
+
+dsu-pmu-0 {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&cpu_0>, <&cpu_1>;
+};
diff --git a/dts/Bindings/arm/atmel-at91.txt b/dts/Bindings/arm/atmel-at91.txt
index 91cb8e4f2a..31220b54d8 100644
--- a/dts/Bindings/arm/atmel-at91.txt
+++ b/dts/Bindings/arm/atmel-at91.txt
@@ -90,38 +90,6 @@ System Timer (ST) required properties:
Its subnodes can be:
- watchdog: compatible should be "atmel,at91rm9200-wdt"
-TC/TCLIB Timer required properties:
-- compatible: Should be "atmel,<chip>-tcb".
- <chip> can be "at91rm9200" or "at91sam9x5"
-- reg: Should contain registers location and length
-- interrupts: Should contain all interrupts for the TC block
- Note that you can specify several interrupt cells if the TC
- block has one interrupt per channel.
-- clock-names: tuple listing input clock names.
- Required elements: "t0_clk", "slow_clk"
- Optional elements: "t1_clk", "t2_clk"
-- clocks: phandles to input clocks.
-
-Examples:
-
-One interrupt per TC block:
- tcb0: timer@fff7c000 {
- compatible = "atmel,at91rm9200-tcb";
- reg = <0xfff7c000 0x100>;
- interrupts = <18 4>;
- clocks = <&tcb0_clk>;
- clock-names = "t0_clk";
- };
-
-One interrupt per TC channel in a TC block:
- tcb1: timer@fffdc000 {
- compatible = "atmel,at91rm9200-tcb";
- reg = <0xfffdc000 0x100>;
- interrupts = <26 4 27 4 28 4>;
- clocks = <&tcb1_clk>;
- clock-names = "t0_clk";
- };
-
RSTC Reset Controller required properties:
- compatible: Should be "atmel,<chip>-rstc".
<chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3"
diff --git a/dts/Bindings/arm/axentia.txt b/dts/Bindings/arm/axentia.txt
index ea3fb96ae4..de58f24638 100644
--- a/dts/Bindings/arm/axentia.txt
+++ b/dts/Bindings/arm/axentia.txt
@@ -10,6 +10,15 @@ compatible = "axentia,linea",
and following the rules from atmel-at91.txt for a sama5d31 SoC.
+Nattis v2 board with Natte v2 power board
+-----------------------------------------
+
+Required root node properties:
+compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
+ "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
+and following the rules from above for the axentia,linea CPU module.
+
+
TSE-850 v3 board
----------------
diff --git a/dts/Bindings/arm/bcm/brcm,brcmstb.txt b/dts/Bindings/arm/bcm/brcm,brcmstb.txt
index 790e6b0b83..c052caad36 100644
--- a/dts/Bindings/arm/bcm/brcm,brcmstb.txt
+++ b/dts/Bindings/arm/bcm/brcm,brcmstb.txt
@@ -17,21 +17,23 @@ Further, syscon nodes that map platform-specific registers used for general
system control is required:
- compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
- - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
+ - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
+ "brcm,brcmstb-cpu-biu-ctrl",
+ "syscon"
- compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
-hif-cpubiuctrl node
+cpu-biu-ctrl node
-------------------
-SoCs with Broadcom Brahma15 ARM-based CPUs have a specific Bus Interface Unit
-(BIU) block which controls and interfaces the CPU complex to the different
-Memory Controller Ports (MCP), one per memory controller (MEMC). This BIU block
-offers a feature called Write Pairing which consists in collapsing two adjacent
-cache lines into a single (bursted) write transaction towards the memory
-controller (MEMC) to maximize write bandwidth.
+SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
+specific Bus Interface Unit (BIU) block which controls and interfaces the CPU
+complex to the different Memory Controller Ports (MCP), one per memory
+controller (MEMC). This BIU block offers a feature called Write Pairing which
+consists in collapsing two adjacent cache lines into a single (bursted) write
+transaction towards the memory controller (MEMC) to maximize write bandwidth.
Required properties:
- - compatible: must be "brcm,bcm7445-hif-cpubiuctrl", "syscon"
+ - compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"
Optional properties:
@@ -52,7 +54,7 @@ example:
};
hif_cpubiuctrl: syscon@3e2400 {
- compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
+ compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon";
reg = <0x3e2400 0x5b4>;
brcm,write-pairing;
};
diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt
index a0009b72e9..f4a777039f 100644
--- a/dts/Bindings/arm/cpus.txt
+++ b/dts/Bindings/arm/cpus.txt
@@ -169,6 +169,7 @@ described below.
"arm,cortex-r5"
"arm,cortex-r7"
"brcm,brahma-b15"
+ "brcm,brahma-b53"
"brcm,vulcan"
"cavium,thunder"
"cavium,thunder2"
diff --git a/dts/Bindings/arm/firmware/sdei.txt b/dts/Bindings/arm/firmware/sdei.txt
new file mode 100644
index 0000000000..ee3f0ff498
--- /dev/null
+++ b/dts/Bindings/arm/firmware/sdei.txt
@@ -0,0 +1,42 @@
+* Software Delegated Exception Interface (SDEI)
+
+Firmware implementing the SDEI functions described in ARM document number
+ARM DEN 0054A ("Software Delegated Exception Interface") can be used by
+Linux to receive notification of events such as those generated by
+firmware-first error handling, or from an IRQ that has been promoted to
+a firmware-assisted NMI.
+
+The interface provides a number of API functions for registering callbacks
+and enabling/disabling events. Functions are invoked by trapping to the
+privilege level of the SDEI firmware (specified as part of the binding
+below) and passing arguments in a manner specified by the "SMC Calling
+Convention (ARM DEN 0028B):
+
+ r0 => 32-bit Function ID / return value
+ {r1 - r3} => Parameters
+
+Note that the immediate field of the trapping instruction must be set
+to #0.
+
+The SDEI_EVENT_REGISTER function registers a callback in the kernel
+text to handle the specified event number.
+
+The sdei node should be a child node of '/firmware' and have required
+properties:
+
+ - compatible : should contain:
+ * "arm,sdei-1.0" : For implementations complying to SDEI version 1.x.
+
+ - method : The method of calling the SDEI firmware. Permitted
+ values are:
+ * "smc" : SMC #0, with the register assignments specified in this
+ binding.
+ * "hvc" : HVC #0, with the register assignments specified in this
+ binding.
+Example:
+ firmware {
+ sdei {
+ compatible = "arm,sdei-1.0";
+ method = "smc";
+ };
+ };
diff --git a/dts/Bindings/arm/marvell/armada-37xx.txt b/dts/Bindings/arm/marvell/armada-37xx.txt
index 51336e5fc7..35c3c3460d 100644
--- a/dts/Bindings/arm/marvell/armada-37xx.txt
+++ b/dts/Bindings/arm/marvell/armada-37xx.txt
@@ -14,3 +14,22 @@ following property before the previous one:
Example:
compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
+
+
+Power management
+----------------
+
+For power management (particularly DVFS and AVS), the North Bridge
+Power Management component is needed:
+
+Required properties:
+- compatible : should contain "marvell,armada-3700-nb-pm", "syscon";
+- reg : the register start and length for the North Bridge
+ Power Management
+
+Example:
+
+nb_pm: syscon@14000 {
+ compatible = "marvell,armada-3700-nb-pm", "syscon";
+ reg = <0x14000 0x60>;
+}
diff --git a/dts/Bindings/arm/mediatek/mediatek,ethsys.txt b/dts/Bindings/arm/mediatek/mediatek,ethsys.txt
index 7aa3fa1676..6cc7840ff3 100644
--- a/dts/Bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,ethsys.txt
@@ -20,4 +20,5 @@ ethsys: clock-controller@1b000000 {
compatible = "mediatek,mt2701-ethsys", "syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
diff --git a/dts/Bindings/arm/samsung/exynos-adc.txt b/dts/Bindings/arm/samsung/exynos-adc.txt
index ccaaec6014..6c49db7f8a 100644
--- a/dts/Bindings/arm/samsung/exynos-adc.txt
+++ b/dts/Bindings/arm/samsung/exynos-adc.txt
@@ -55,7 +55,7 @@ Note: child nodes can be added for auto probing from device tree.
Example: adding device info in dtsi file
-adc: adc@12D10000 {
+adc: adc@12d10000 {
compatible = "samsung,exynos-adc-v1";
reg = <0x12D10000 0x100>;
interrupts = <0 106 0>;
@@ -71,7 +71,7 @@ adc: adc@12D10000 {
Example: adding device info in dtsi file for Exynos3250 with additional sclk
-adc: adc@126C0000 {
+adc: adc@126c0000 {
compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
reg = <0x126C0000 0x100>;
interrupts = <0 137 0>;
@@ -87,7 +87,7 @@ adc: adc@126C0000 {
Example: Adding child nodes in dts file
-adc@12D10000 {
+adc@12d10000 {
/* NTC thermistor is a hwmon device */
ncp15wb473@0 {
diff --git a/dts/Bindings/arm/samsung/samsung-boards.txt b/dts/Bindings/arm/samsung/samsung-boards.txt
index e134596185..469ac98ecf 100644
--- a/dts/Bindings/arm/samsung/samsung-boards.txt
+++ b/dts/Bindings/arm/samsung/samsung-boards.txt
@@ -72,7 +72,7 @@ Optional nodes:
- compatible: only "samsung,secure-firmware" is currently supported
- reg: address of non-secure SYSRAM used for communication with firmware
- firmware@203F000 {
+ firmware@203f000 {
compatible = "samsung,secure-firmware";
reg = <0x0203F000 0x1000>;
};
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
index 020d758fc0..5c3af7ef07 100644
--- a/dts/Bindings/arm/shmobile.txt
+++ b/dts/Bindings/arm/shmobile.txt
@@ -104,12 +104,16 @@ Boards:
compatible = "renesas,salvator-x", "renesas,r8a7796"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
compatible = "renesas,salvator-xs", "renesas,r8a7795"
+ - Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
+ compatible = "renesas,salvator-xs", "renesas,r8a7796"
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
- SK-RZG1E (YR8A77450S000BE)
compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
- SK-RZG1M (YR8A77430S000BE)
compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
+ - V3MSK
+ compatible = "renesas,v3msk", "renesas,r8a77970"
- Wheat
compatible = "renesas,wheat", "renesas,r8a7792"
diff --git a/dts/Bindings/arm/stm32.txt b/dts/Bindings/arm/stm32.txt
new file mode 100644
index 0000000000..05762b08a7
--- /dev/null
+++ b/dts/Bindings/arm/stm32.txt
@@ -0,0 +1,9 @@
+STMicroelectronics STM32 Platforms Device Tree Bindings
+
+Each device tree must specify which STM32 SoC it uses,
+using one of the following compatible strings:
+
+ st,stm32f429
+ st,stm32f469
+ st,stm32f746
+ st,stm32h743
diff --git a/dts/Bindings/arm/technologic.txt b/dts/Bindings/arm/technologic.txt
index 33797acad8..f1cedc00dc 100644
--- a/dts/Bindings/arm/technologic.txt
+++ b/dts/Bindings/arm/technologic.txt
@@ -1,6 +1,11 @@
Technologic Systems Platforms Device Tree Bindings
--------------------------------------------------
+TS-4600 is a System-on-Module based on the Freescale i.MX28 System-on-Chip.
+It can be mounted on a carrier board providing additional peripheral connectors.
+Required root node properties:
+ - compatible = "technologic,imx28-ts4600", "fsl,imx28"
+
TS-4800 board
Required root node properties:
- compatible = "technologic,imx51-ts4800", "fsl,imx51";
@@ -10,3 +15,9 @@ It can be mounted on a carrier board providing additional peripheral connectors.
Required root node properties:
- compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"
- compatible = "technologic,imx6q-ts4900", "fsl,imx6q"
+
+TS-7970 is a System-on-Module based on the Freescale i.MX6 System-on-Chip.
+It can be mounted on a carrier board providing additional peripheral connectors.
+Required root node properties:
+ - compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl"
+ - compatible = "technologic,imx6q-ts7970", "fsl,imx6q"
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-24 04:00:30 +0000