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-rw-r--r--dts/Bindings/bus/qcom,ssc-block-bus.yaml25
1 files changed, 11 insertions, 14 deletions
diff --git a/dts/Bindings/bus/qcom,ssc-block-bus.yaml b/dts/Bindings/bus/qcom,ssc-block-bus.yaml
index 5b97050790..8e9e6ff35d 100644
--- a/dts/Bindings/bus/qcom,ssc-block-bus.yaml
+++ b/dts/Bindings/bus/qcom,ssc-block-bus.yaml
@@ -28,11 +28,9 @@ properties:
- const: qcom,ssc-block-bus
reg:
- description: |
- Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1
- registers
- minItems: 2
- maxItems: 2
+ items:
+ - description: SSCAON_CONFIG0 registers
+ - description: SSCAON_CONFIG1 registers
reg-names:
items:
@@ -48,7 +46,6 @@ properties:
ranges: true
clocks:
- minItems: 6
maxItems: 6
clock-names:
@@ -61,9 +58,9 @@ properties:
- const: ssc_ahbs
power-domains:
- description: Power domain phandles for the ssc_cx and ssc_mx power domains
- minItems: 2
- maxItems: 2
+ items:
+ - description: CX power domain
+ - description: MX power domain
power-domain-names:
items:
@@ -71,11 +68,11 @@ properties:
- const: ssc_mx
resets:
- description: |
- Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the
- branch control register associated with the ssc_xo and ssc_ahbs clocks)
- minItems: 2
- maxItems: 2
+ items:
+ - description: Main reset
+ - description:
+ SSC Branch Control Register reset (associated with the ssc_xo and
+ ssc_ahbs clocks)
reset-names:
items: