diff options
Diffstat (limited to 'dts/Bindings/clock/exynos5433-clock.txt')
| -rw-r--r-- | dts/Bindings/clock/exynos5433-clock.txt | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/dts/Bindings/clock/exynos5433-clock.txt b/dts/Bindings/clock/exynos5433-clock.txt index 63379b04e0..1dc80f8811 100644 --- a/dts/Bindings/clock/exynos5433-clock.txt +++ b/dts/Bindings/clock/exynos5433-clock.txt @@ -79,7 +79,7 @@ Required Properties: Input clocks for fsys clock controller: - oscclk - sclk_ufs_mphy - - div_aclk_fsys_200 + - aclk_fsys_200 - sclk_pcie_100_fsys - sclk_ufsunipro_fsys - sclk_mmc2_fsys @@ -104,6 +104,10 @@ Required Properties: - sclk_decon_tv_vclk_disp - aclk_disp_333 + Input clocks for audio clock controller: + - oscclk + - fout_aud_pll + Input clocks for bus0 clock controller: - aclk_bus0_400 @@ -235,7 +239,7 @@ Example 2: Examples of clock controller nodes are listed below. clock-names = "oscclk", "sclk_ufs_mphy", - "div_aclk_fsys_200", + "aclk_fsys_200", "sclk_pcie_100_fsys", "sclk_ufsunipro_fsys", "sclk_mmc2_fsys", @@ -245,7 +249,7 @@ Example 2: Examples of clock controller nodes are listed below. "sclk_usbdrd30_fsys"; clocks = <&xxti>, <&cmu_cpif CLK_SCLK_UFS_MPHY>, - <&cmu_top CLK_DIV_ACLK_FSYS_200>, + <&cmu_top CLK_ACLK_FSYS_200>, <&cmu_top CLK_SCLK_PCIE_100_FSYS>, <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, <&cmu_top CLK_SCLK_MMC2_FSYS>, @@ -297,6 +301,9 @@ Example 2: Examples of clock controller nodes are listed below. compatible = "samsung,exynos5433-cmu-aud"; reg = <0x114c0000 0x0b04>; #clock-cells = <1>; + + clock-names = "oscclk", "fout_aud_pll"; + clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; }; cmu_bus0: clock-controller@13600000 { |