summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/clock/qcom,a53pll.yaml
diff options
context:
space:
mode:
Diffstat (limited to 'dts/Bindings/clock/qcom,a53pll.yaml')
-rw-r--r--dts/Bindings/clock/qcom,a53pll.yaml40
1 files changed, 40 insertions, 0 deletions
diff --git a/dts/Bindings/clock/qcom,a53pll.yaml b/dts/Bindings/clock/qcom,a53pll.yaml
new file mode 100644
index 0000000000..20d2638b4c
--- /dev/null
+++ b/dts/Bindings/clock/qcom,a53pll.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,a53pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm A53 PLL Binding
+
+maintainers:
+ - Sivaprakash Murugesan <sivaprak@codeaurora.org>
+
+description:
+ The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for
+ frequencies above 1GHz.
+
+properties:
+ compatible:
+ const: qcom,msm8916-a53pll
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ #Example 1 - A53 PLL found on MSM8916 devices
+ - |
+ a53pll: clock@b016000 {
+ compatible = "qcom,msm8916-a53pll";
+ reg = <0xb016000 0x40>;
+ #clock-cells = <0>;
+ };