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-rw-r--r--dts/Bindings/clock/qcom,a7pll.yaml4
1 files changed, 2 insertions, 2 deletions
diff --git a/dts/Bindings/clock/qcom,a7pll.yaml b/dts/Bindings/clock/qcom,a7pll.yaml
index 8666e99572..809c34eb7d 100644
--- a/dts/Bindings/clock/qcom,a7pll.yaml
+++ b/dts/Bindings/clock/qcom,a7pll.yaml
@@ -4,13 +4,13 @@
$id: http://devicetree.org/schemas/clock/qcom,a7pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm A7 PLL Binding
+title: Qualcomm A7 PLL clock
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
- The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
+ The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
frequency clock to the CPU.
properties: