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Diffstat (limited to 'dts/Bindings/clock/qcom,gcc-ipq8074.yaml')
-rw-r--r-- | dts/Bindings/clock/qcom,gcc-ipq8074.yaml | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/dts/Bindings/clock/qcom,gcc-ipq8074.yaml b/dts/Bindings/clock/qcom,gcc-ipq8074.yaml new file mode 100644 index 0000000000..2d44ddc45a --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-ipq8074.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ8074 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ8074. + + See also:: include/dt-bindings/clock/qcom,gcc-ipq8074.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,gcc-ipq8074 + + clocks: + items: + - description: board XO clock + - description: sleep clock + - description: Gen3 QMP PCIe PHY PIPE clock + - description: Gen2 QMP PCIe PHY PIPE clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: pcie0_pipe + - const: pcie1_pipe + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,gcc-ipq8074"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; +... |