diff options
Diffstat (limited to 'dts/Bindings/clock/qcom,gcc-ipq8074.yaml')
| -rw-r--r-- | dts/Bindings/clock/qcom,gcc-ipq8074.yaml | 43 |
1 files changed, 22 insertions, 21 deletions
diff --git a/dts/Bindings/clock/qcom,gcc-ipq8074.yaml b/dts/Bindings/clock/qcom,gcc-ipq8074.yaml index 98572b4a9b..2d44ddc45a 100644 --- a/dts/Bindings/clock/qcom,gcc-ipq8074.yaml +++ b/dts/Bindings/clock/qcom,gcc-ipq8074.yaml @@ -4,43 +4,43 @@ $id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Global Clock & Reset Controller Bindingfor IPQ8074 +title: Qualcomm Global Clock & Reset Controller on IPQ8074 maintainers: - Stephen Boyd <sboyd@kernel.org> - - Taniya Das <tdas@codeaurora.org> + - Taniya Das <quic_tdas@quicinc.com> description: | - Qualcomm global clock control module which supports the clocks, resets and - power domains on IPQ8074. + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ8074. - See also: - - dt-bindings/clock/qcom,gcc-ipq8074.h + See also:: include/dt-bindings/clock/qcom,gcc-ipq8074.h + +allOf: + - $ref: qcom,gcc.yaml# properties: compatible: const: qcom,gcc-ipq8074 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - reg: - maxItems: 1 + clocks: + items: + - description: board XO clock + - description: sleep clock + - description: Gen3 QMP PCIe PHY PIPE clock + - description: Gen2 QMP PCIe PHY PIPE clock - protected-clocks: - description: - Protected clock specifier list as per common clock binding. + clock-names: + items: + - const: xo + - const: sleep_clk + - const: pcie0_pipe + - const: pcie1_pipe required: - compatible - - reg - - '#clock-cells' - - '#reset-cells' -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -48,6 +48,7 @@ examples: compatible = "qcom,gcc-ipq8074"; reg = <0x01800000 0x80000>; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; }; ... |