diff options
Diffstat (limited to 'dts/Bindings/clock/renesas,rzg2l-cpg.yaml')
| -rw-r--r-- | dts/Bindings/clock/renesas,rzg2l-cpg.yaml | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/dts/Bindings/clock/renesas,rzg2l-cpg.yaml b/dts/Bindings/clock/renesas,rzg2l-cpg.yaml index 8880b834f2..80a8c7114c 100644 --- a/dts/Bindings/clock/renesas,rzg2l-cpg.yaml +++ b/dts/Bindings/clock/renesas,rzg2l-cpg.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode @@ -24,9 +24,10 @@ description: | properties: compatible: enum: - - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} + - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-cpg # RZ/G2{L,LC} - renesas,r9a07g054-cpg # RZ/V2L + - renesas,r9a08g045-cpg # RZ/G3S - renesas,r9a09g011-cpg # RZ/V2M reg: @@ -45,10 +46,9 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - <dt-bindings/clock/r9a0*-cpg.h> + <dt-bindings/clock/r9a0*-cpg.h>, - For module clocks, the two clock specifier cells must be "CPG_MOD" and - a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or - <dt-bindings/clock/r9a09g011-cpg.h>. + a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>. const: 2 '#power-domain-cells': @@ -62,7 +62,7 @@ properties: '#reset-cells': description: The single reset specifier cell must be the module number, as defined in - the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>. + <dt-bindings/clock/r9a0*-cpg.h>. const: 1 required: |