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-rw-r--r--dts/Bindings/display/msm/dsi.txt12
1 files changed, 8 insertions, 4 deletions
diff --git a/dts/Bindings/display/msm/dsi.txt b/dts/Bindings/display/msm/dsi.txt
index f344b9e491..e7423bea14 100644
--- a/dts/Bindings/display/msm/dsi.txt
+++ b/dts/Bindings/display/msm/dsi.txt
@@ -14,17 +14,20 @@ Required properties:
- clocks: device clocks
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required:
+ * "mdp_core_clk"
+ * "iface_clk"
* "bus_clk"
- * "byte_clk"
- * "core_clk"
* "core_mmss_clk"
- * "iface_clk"
- * "mdp_core_clk"
+ * "byte_clk"
* "pixel_clk"
+ * "core_clk"
+ For DSIv2, we need an additional clock:
+ * "src_clk"
- vdd-supply: phandle to vdd regulator device node
- vddio-supply: phandle to vdd-io regulator device node
- vdda-supply: phandle to vdda regulator device node
- qcom,dsi-phy: phandle to DSI PHY device node
+- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
Optional properties:
- panel@0: Node of panel connected to this DSI controller.
@@ -51,6 +54,7 @@ Required properties:
* "qcom,dsi-phy-28nm-hpm"
* "qcom,dsi-phy-28nm-lp"
* "qcom,dsi-phy-20nm"
+ * "qcom,dsi-phy-28nm-8960"
- reg: Physical base address and length of the registers of PLL, PHY and PHY
regulator
- reg-names: The names of register regions. The following regions are required: