diff options
Diffstat (limited to 'dts/Bindings/display')
292 files changed, 16676 insertions, 3821 deletions
diff --git a/dts/Bindings/display/allwinner,sun4i-a10-display-backend.yaml b/dts/Bindings/display/allwinner,sun4i-a10-display-backend.yaml index 3d8ea3c2d8..ba06d1857b 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-display-backend.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-display-backend.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Display Engine Backend Device Tree Bindings +title: Allwinner A10 Display Engine Backend maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml b/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml index c388ae5da1..e6088f379f 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Display Engine Pipeline Device Tree Bindings +title: Allwinner A10 Display Engine Pipeline maintainers: - Chen-Yu Tsai <wens@csie.org> @@ -94,6 +94,7 @@ if: - allwinner,sun8i-a83t-display-engine - allwinner,sun8i-r40-display-engine - allwinner,sun9i-a80-display-engine + - allwinner,sun20i-d1-display-engine - allwinner,sun50i-a64-display-engine then: diff --git a/dts/Bindings/display/allwinner,sun4i-a10-display-frontend.yaml b/dts/Bindings/display/allwinner,sun4i-a10-display-frontend.yaml index 055157fbf3..98e8240a05 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-display-frontend.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-display-frontend.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Display Engine Frontend Device Tree Bindings +title: Allwinner A10 Display Engine Frontend maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun4i-a10-hdmi.yaml b/dts/Bindings/display/allwinner,sun4i-a10-hdmi.yaml index 7f11452539..55703caacb 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-hdmi.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-hdmi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 HDMI Controller Device Tree Bindings +title: Allwinner A10 HDMI Controller description: | The HDMI Encoder supports the HDMI video and audio outputs, and does diff --git a/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml b/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml index 4a92a4c7dc..724d93b919 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tcon.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Timings Controller (TCON) Device Tree Bindings +title: Allwinner A10 Timings Controller (TCON) maintainers: - Chen-Yu Tsai <wens@csie.org> @@ -233,6 +233,7 @@ allOf: - allwinner,sun8i-a83t-tcon-lcd - allwinner,sun8i-v3s-tcon - allwinner,sun9i-a80-tcon-lcd + - allwinner,sun20i-d1-tcon-lcd then: properties: @@ -252,6 +253,7 @@ allOf: - allwinner,sun8i-a83t-tcon-tv - allwinner,sun8i-r40-tcon-tv - allwinner,sun9i-a80-tcon-tv + - allwinner,sun20i-d1-tcon-tv then: properties: @@ -278,6 +280,7 @@ allOf: - allwinner,sun9i-a80-tcon-lcd - allwinner,sun4i-a10-tcon - allwinner,sun8i-a83t-tcon-lcd + - allwinner,sun20i-d1-tcon-lcd then: required: @@ -294,6 +297,7 @@ allOf: - allwinner,sun8i-a23-tcon - allwinner,sun8i-a33-tcon - allwinner,sun8i-a83t-tcon-lcd + - allwinner,sun20i-d1-tcon-lcd then: properties: diff --git a/dts/Bindings/display/allwinner,sun4i-a10-tv-encoder.yaml b/dts/Bindings/display/allwinner,sun4i-a10-tv-encoder.yaml index afc0ed799e..c39e90a594 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-tv-encoder.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-tv-encoder.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tv-encoder.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 TV Encoder Device Tree Bindings +title: Allwinner A10 TV Encoder maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun6i-a31-drc.yaml b/dts/Bindings/display/allwinner,sun6i-a31-drc.yaml index 71cce56875..895506d93f 100644 --- a/dts/Bindings/display/allwinner,sun6i-a31-drc.yaml +++ b/dts/Bindings/display/allwinner,sun6i-a31-drc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-drc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 Dynamic Range Controller Device Tree Bindings +title: Allwinner A31 Dynamic Range Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml b/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml index bf0bdf54e5..c731fbdc2f 100644 --- a/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml +++ b/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 MIPI-DSI Controller Device Tree Bindings +title: Allwinner A31 MIPI-DSI Controller maintainers: - Chen-Yu Tsai <wens@csie.org> @@ -12,9 +12,14 @@ maintainers: properties: compatible: - enum: - - allwinner,sun6i-a31-mipi-dsi - - allwinner,sun50i-a64-mipi-dsi + oneOf: + - enum: + - allwinner,sun6i-a31-mipi-dsi + - allwinner,sun50i-a64-mipi-dsi + - allwinner,sun50i-a100-mipi-dsi + - items: + - const: allwinner,sun20i-d1-mipi-dsi + - const: allwinner,sun50i-a100-mipi-dsi reg: maxItems: 1 @@ -59,7 +64,6 @@ required: - phys - phy-names - resets - - vcc-dsi-supply - port allOf: @@ -68,7 +72,9 @@ allOf: properties: compatible: contains: - const: allwinner,sun6i-a31-mipi-dsi + enum: + - allwinner,sun6i-a31-mipi-dsi + - allwinner,sun50i-a100-mipi-dsi then: properties: @@ -78,16 +84,22 @@ allOf: required: - clock-names + else: + properties: + clocks: + maxItems: 1 + - if: properties: compatible: contains: - const: allwinner,sun50i-a64-mipi-dsi + enum: + - allwinner,sun6i-a31-mipi-dsi + - allwinner,sun50i-a64-mipi-dsi then: - properties: - clocks: - minItems: 1 + required: + - vcc-dsi-supply unevaluatedProperties: false diff --git a/dts/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml b/dts/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml index cb243bc58e..b75c1ec686 100644 --- a/dts/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml +++ b/dts/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-de2-mixer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner Display Engine 2.0 Mixer Device Tree Bindings +title: Allwinner Display Engine 2.0 Mixer maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml b/dts/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml index 4951b5ef5c..60fd927b5a 100644 --- a/dts/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml +++ b/dts/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A83t DWC HDMI TX Encoder Device Tree Bindings +title: Allwinner A83t DWC HDMI TX Encoder description: | The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller diff --git a/dts/Bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml b/dts/Bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml index a97366aaf9..1b47f3d99a 100644 --- a/dts/Bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml +++ b/dts/Bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A83t HDMI PHY Device Tree Bindings +title: Allwinner A83t HDMI PHY maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml b/dts/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml index 845e226d7a..7d849c4095 100644 --- a/dts/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml +++ b/dts/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner R40 TCON TOP Device Tree Bindings +title: Allwinner R40 TCON TOP maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun9i-a80-deu.yaml b/dts/Bindings/display/allwinner,sun9i-a80-deu.yaml index 637372ec46..193afee2c3 100644 --- a/dts/Bindings/display/allwinner,sun9i-a80-deu.yaml +++ b/dts/Bindings/display/allwinner,sun9i-a80-deu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun9i-a80-deu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A80 Detail Enhancement Unit Device Tree Bindings +title: Allwinner A80 Detail Enhancement Unit maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml b/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml index 2e208d2fc9..0c85894648 100644 --- a/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml +++ b/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml @@ -2,16 +2,16 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic specific extensions to the Synopsys Designware HDMI Controller maintainers: - - Neil Armstrong <narmstrong@baylibre.com> + - Neil Armstrong <neil.armstrong@linaro.org> allOf: - - $ref: /schemas/sound/name-prefix.yaml# + - $ref: /schemas/sound/dai-common.yaml# description: | The Amlogic Meson Synopsys Designware Integration is composed of diff --git a/dts/Bindings/display/amlogic,meson-g12a-dw-mipi-dsi.yaml b/dts/Bindings/display/amlogic,meson-g12a-dw-mipi-dsi.yaml new file mode 100644 index 0000000000..a3428f0120 --- /dev/null +++ b/dts/Bindings/display/amlogic,meson-g12a-dw-mipi-dsi.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 BayLibre, SAS +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/amlogic,meson-g12a-dw-mipi-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +description: | + The Amlogic Meson Synopsys Designware Integration is composed of + - A Synopsys DesignWare MIPI DSI Host Controller IP + - A TOP control block controlling the Clocks & Resets of the IP + +allOf: + - $ref: dsi-controller.yaml# + +properties: + compatible: + enum: + - amlogic,meson-g12a-dw-mipi-dsi + + reg: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 4 + + clock-names: + minItems: 3 + items: + - const: pclk + - const: bit + - const: px + - const: meas + + resets: + maxItems: 1 + + reset-names: + items: + - const: top + + phys: + maxItems: 1 + + phy-names: + items: + - const: dphy + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input node to receive pixel data. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DSI output node to panel. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - ports + +unevaluatedProperties: false + +examples: + - | + dsi@6000 { + compatible = "amlogic,meson-g12a-dw-mipi-dsi"; + reg = <0x6000 0x400>; + resets = <&reset_top>; + reset-names = "top"; + clocks = <&clk_pclk>, <&bit_clk>, <&clk_px>; + clock-names = "pclk", "bit", "px"; + phys = <&mipi_dphy>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VPU VENC Input */ + mipi_dsi_venc_port: port@0 { + reg = <0>; + + mipi_dsi_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + /* DSI Output */ + mipi_dsi_panel_port: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/amlogic,meson-vpu.yaml b/dts/Bindings/display/amlogic,meson-vpu.yaml index 047fd69e03..cb0a90f023 100644 --- a/dts/Bindings/display/amlogic,meson-vpu.yaml +++ b/dts/Bindings/display/amlogic,meson-vpu.yaml @@ -2,13 +2,13 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson Display Controller maintainers: - - Neil Armstrong <narmstrong@baylibre.com> + - Neil Armstrong <neil.armstrong@linaro.org> description: | The Amlogic Meson Display controller is composed of several components @@ -96,6 +96,11 @@ properties: description: A port node pointing to the HDMI-TX port node. + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + A port node pointing to the DPI port node (e.g. DSI or LVDS transceiver). + "#address-cells": const: 1 diff --git a/dts/Bindings/display/arm,hdlcd.yaml b/dts/Bindings/display/arm,hdlcd.yaml index a2670258c4..9a30e9005e 100644 --- a/dts/Bindings/display/arm,hdlcd.yaml +++ b/dts/Bindings/display/arm,hdlcd.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/arm,hdlcd.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Arm HDLCD display controller binding +title: Arm HDLCD display controller maintainers: - Liviu Dudau <Liviu.Dudau@arm.com> diff --git a/dts/Bindings/display/arm,komeda.yaml b/dts/Bindings/display/arm,komeda.yaml index 9f4aade97f..3ad3eef89c 100644 --- a/dts/Bindings/display/arm,komeda.yaml +++ b/dts/Bindings/display/arm,komeda.yaml @@ -58,6 +58,7 @@ properties: patternProperties: '^pipeline@[01]$': type: object + additionalProperties: false description: clocks diff --git a/dts/Bindings/display/arm,malidp.yaml b/dts/Bindings/display/arm,malidp.yaml index 2a17ec6fc9..91812573fd 100644 --- a/dts/Bindings/display/arm,malidp.yaml +++ b/dts/Bindings/display/arm,malidp.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/arm,malidp.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Arm Mali Display Processor (Mali-DP) binding +title: Arm Mali Display Processor (Mali-DP) maintainers: - Liviu Dudau <Liviu.Dudau@arm.com> diff --git a/dts/Bindings/display/arm,pl11x.yaml b/dts/Bindings/display/arm,pl11x.yaml index b545c6d203..6cc9045e5c 100644 --- a/dts/Bindings/display/arm,pl11x.yaml +++ b/dts/Bindings/display/arm,pl11x.yaml @@ -159,25 +159,12 @@ examples: }; panel { - compatible = "arm,rtsm-display", "panel-dpi"; - power-supply = <&vcc_supply>; + compatible = "arm,rtsm-display"; port { clcd_panel: endpoint { remote-endpoint = <&clcd_pads>; }; }; - - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <40>; - hfront-porch = <24>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <2>; - }; }; ... diff --git a/dts/Bindings/display/atmel,lcdc.txt b/dts/Bindings/display/atmel,lcdc.txt index acb5a01321..b5e355ada2 100644 --- a/dts/Bindings/display/atmel,lcdc.txt +++ b/dts/Bindings/display/atmel,lcdc.txt @@ -9,7 +9,6 @@ Required properties: "atmel,at91sam9g45-lcdc" , "atmel,at91sam9g45es-lcdc" , "atmel,at91sam9rl-lcdc" , - "atmel,at32ap-lcdc" - reg : Should contain 1 register ranges(address and length). Can contain an additional register range(address and length) for fixed framebuffer memory. Useful for dedicated memories. diff --git a/dts/Bindings/display/atmel/hlcdc-dc.txt b/dts/Bindings/display/atmel/hlcdc-dc.txt index 0398aec488..923aea2534 100644 --- a/dts/Bindings/display/atmel/hlcdc-dc.txt +++ b/dts/Bindings/display/atmel/hlcdc-dc.txt @@ -12,7 +12,7 @@ Required properties: Required children nodes: Children nodes are encoding available output ports and their connections - to external devices using the OF graph reprensentation (see ../graph.txt). + to external devices using the OF graph representation (see ../graph.txt). At least one port node is required. Optional properties in grandchild nodes: diff --git a/dts/Bindings/display/brcm,bcm2711-hdmi.yaml b/dts/Bindings/display/brcm,bcm2711-hdmi.yaml index a9d34dd7bb..5b35adf34c 100644 --- a/dts/Bindings/display/brcm,bcm2711-hdmi.yaml +++ b/dts/Bindings/display/brcm,bcm2711-hdmi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/brcm,bcm2711-hdmi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM2711 HDMI Controller Device Tree Bindings +title: Broadcom BCM2711 HDMI Controller maintainers: - Eric Anholt <eric@anholt.net> diff --git a/dts/Bindings/display/bridge/adi,adv7511.yaml b/dts/Bindings/display/bridge/adi,adv7511.yaml index f08a01dfed..5bbe81862c 100644 --- a/dts/Bindings/display/bridge/adi,adv7511.yaml +++ b/dts/Bindings/display/bridge/adi,adv7511.yaml @@ -117,23 +117,21 @@ properties: ports: description: - The ADV7511(W)/13 has two video ports and one audio port. This node - models their connections as documented in - Documentation/devicetree/bindings/media/video-interfaces.txt - Documentation/devicetree/bindings/graph.txt - type: object + The ADV7511(W)/13 has two video ports and one audio port. + $ref: /schemas/graph.yaml#/properties/ports + properties: port@0: description: Video port for the RGB or YUV input. - type: object + $ref: /schemas/graph.yaml#/properties/port port@1: description: Video port for the HDMI output. - type: object + $ref: /schemas/graph.yaml#/properties/port port@2: description: Audio port for the HDMI output. - type: object + $ref: /schemas/graph.yaml#/properties/port # adi,input-colorspace and adi,input-clock are required except in # "rgb 1x" and "yuv444 1x" modes, in which case they must not be diff --git a/dts/Bindings/display/bridge/adi,adv7533.yaml b/dts/Bindings/display/bridge/adi,adv7533.yaml index f36209137c..df20a3c9c7 100644 --- a/dts/Bindings/display/bridge/adi,adv7533.yaml +++ b/dts/Bindings/display/bridge/adi,adv7533.yaml @@ -9,6 +9,9 @@ title: Analog Devices ADV7533/35 HDMI Encoders maintainers: - Laurent Pinchart <laurent.pinchart@ideasonboard.com> +allOf: + - $ref: /schemas/sound/dai-common.yaml# + description: | The ADV7533 and ADV7535 are HDMI audio and video transmitters compatible with HDMI 1.4 and DVI 1.0. They support color space @@ -89,27 +92,28 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 1, 2, 3, 4 ] + "#sound-dai-cells": + const: 0 + ports: description: - The ADV7533/35 has two video ports and one audio port. This node - models their connections as documented in - Documentation/devicetree/bindings/media/video-interfaces.txt - Documentation/devicetree/bindings/graph.txt - type: object + The ADV7533/35 has two video ports and one audio port. + $ref: /schemas/graph.yaml#/properties/ports + properties: port@0: description: Video port for the DSI input. The remote endpoint phandle should be a reference to a valid mipi_dsi_host_device. - type: object + $ref: /schemas/graph.yaml#/properties/port port@1: description: Video port for the HDMI output. - type: object + $ref: /schemas/graph.yaml#/properties/port port@2: description: Audio port for the HDMI output. - type: object + $ref: /schemas/graph.yaml#/properties/port required: - compatible diff --git a/dts/Bindings/display/bridge/analogix,anx7625.yaml b/dts/Bindings/display/bridge/analogix,anx7625.yaml index 35a4851583..a1ed100465 100644 --- a/dts/Bindings/display/bridge/analogix,anx7625.yaml +++ b/dts/Bindings/display/bridge/analogix,anx7625.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Analogix Semiconductor, Inc. %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/bridge/analogix,anx7625.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/bridge/analogix,anx7625.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Analogix ANX7625 SlimPort (4K Mobile HD Transmitter) @@ -16,8 +16,7 @@ description: | properties: compatible: - items: - - const: analogix,anx7625 + const: analogix,anx7625 reg: maxItems: 1 @@ -94,7 +93,22 @@ properties: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: - Video port for MIPI DSI input. + MIPI DSI/DPI input. + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + type: object + additionalProperties: false + + properties: + remote-endpoint: true + + bus-type: + enum: [7] + default: 1 + + data-lanes: true port@1: $ref: /schemas/graph.yaml#/properties/port @@ -119,7 +133,7 @@ examples: - | #include <dt-bindings/gpio/gpio.h> - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; @@ -143,6 +157,8 @@ examples: reg = <0>; anx7625_in: endpoint { remote-endpoint = <&mipi_dsi>; + bus-type = <7>; + data-lanes = <0 1 2 3>; }; }; diff --git a/dts/Bindings/display/bridge/analogix,anx7814.yaml b/dts/Bindings/display/bridge/analogix,anx7814.yaml index bce96b5b0d..4509c49673 100644 --- a/dts/Bindings/display/bridge/analogix,anx7814.yaml +++ b/dts/Bindings/display/bridge/analogix,anx7814.yaml @@ -8,7 +8,7 @@ title: Analogix ANX7814 SlimPort (Full-HD Transmitter) maintainers: - Andrzej Hajda <andrzej.hajda@intel.com> - - Neil Armstrong <narmstrong@baylibre.com> + - Neil Armstrong <neil.armstrong@linaro.org> - Robert Foss <robert.foss@linaro.org> properties: @@ -17,6 +17,7 @@ properties: - analogix,anx7808 - analogix,anx7812 - analogix,anx7814 + - analogix,anx7816 - analogix,anx7818 reg: diff --git a/dts/Bindings/display/bridge/analogix,dp.yaml b/dts/Bindings/display/bridge/analogix,dp.yaml new file mode 100644 index 0000000000..62f0521b09 --- /dev/null +++ b/dts/Bindings/display/bridge/analogix,dp.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/analogix,dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analogix Display Port bridge + +maintainers: + - Rob Herring <robh@kernel.org> + +properties: + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: true + + clock-names: true + + phys: true + + phy-names: + const: dp + + force-hpd: + type: boolean + description: + Indicate driver need force hpd when hpd detect failed, this + is used for some eDP screen which don not have a hpd signal. + + hpd-gpios: + description: + Hotplug detect GPIO. + Indicates which GPIO should be used for hotplug detection + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Input node to receive pixel data. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Port node with one endpoint connected to a dp-connector node. + + required: + - port@0 + - port@1 + +required: + - reg + - interrupts + - clock-names + - clocks + - ports + +additionalProperties: true diff --git a/dts/Bindings/display/bridge/analogix_dp.txt b/dts/Bindings/display/bridge/analogix_dp.txt deleted file mode 100644 index 027d76c27a..0000000000 --- a/dts/Bindings/display/bridge/analogix_dp.txt +++ /dev/null @@ -1,51 +0,0 @@ -Analogix Display Port bridge bindings - -Required properties for dp-controller: - -compatible: - platform specific such as: - * "samsung,exynos5-dp" - * "rockchip,rk3288-dp" - * "rockchip,rk3399-edp" - -reg: - physical base address of the controller and length - of memory mapped region. - -interrupts: - interrupt combiner values. - -clocks: - from common clock binding: handle to dp clock. - -clock-names: - from common clock binding: Shall be "dp". - -phys: - from general PHY binding: the phandle for the PHY device. - -phy-names: - from general PHY binding: Should be "dp". - -Optional properties for dp-controller: - -force-hpd: - Indicate driver need force hpd when hpd detect failed, this - is used for some eDP screen which don't have hpd signal. - -hpd-gpios: - Hotplug detect GPIO. - Indicates which GPIO should be used for hotplug detection - -port@[X]: SoC specific port nodes with endpoint definitions as defined - in Documentation/devicetree/bindings/media/video-interfaces.txt, - please refer to the SoC specific binding document: - * Documentation/devicetree/bindings/display/exynos/exynos_dp.txt - * Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt -------------------------------------------------------------------------------- - -Example: - - dp-controller { - compatible = "samsung,exynos5-dp"; - reg = <0x145b0000 0x10000>; - interrupts = <10 3>; - interrupt-parent = <&combiner>; - clocks = <&clock 342>; - clock-names = "dp"; - - phys = <&dp_phy>; - phy-names = "dp"; - }; diff --git a/dts/Bindings/display/bridge/anx6345.yaml b/dts/Bindings/display/bridge/anx6345.yaml index 1c0406c38f..514f588529 100644 --- a/dts/Bindings/display/bridge/anx6345.yaml +++ b/dts/Bindings/display/bridge/anx6345.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/bridge/anx6345.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Analogix ANX6345 eDP Transmitter Device Tree Bindings +title: Analogix ANX6345 eDP Transmitter maintainers: - Torsten Duwe <duwe@lst.de> @@ -61,7 +61,7 @@ additionalProperties: false examples: - | - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/display/bridge/cdns,dsi.txt b/dts/Bindings/display/bridge/cdns,dsi.txt deleted file mode 100644 index 525a4bfd86..0000000000 --- a/dts/Bindings/display/bridge/cdns,dsi.txt +++ /dev/null @@ -1,112 +0,0 @@ -Cadence DSI bridge -================== - -The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes. - -Required properties: -- compatible: should be set to "cdns,dsi". -- reg: physical base address and length of the controller's registers. -- interrupts: interrupt line connected to the DSI bridge. -- clocks: DSI bridge clocks. -- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk". -- phys: phandle link to the MIPI D-PHY controller. -- phy-names: must contain "dphy". -- #address-cells: must be set to 1. -- #size-cells: must be set to 0. - -Optional properties: -- resets: DSI reset lines. -- reset-names: can contain "dsi_p_rst". - -Required subnodes: -- ports: Ports as described in Documentation/devicetree/bindings/graph.txt. - 2 ports are available: - * port 0: this port is only needed if some of your DSI devices are - controlled through an external bus like I2C or SPI. Can have at - most 4 endpoints. The endpoint number is directly encoding the - DSI virtual channel used by this device. - * port 1: represents the DPI input. - Other ports will be added later to support the new kind of inputs. - -- one subnode per DSI device connected on the DSI bus. Each DSI device should - contain a reg property encoding its virtual channel. - -Example: - dsi0: dsi@fd0c0000 { - compatible = "cdns,dsi"; - reg = <0x0 0xfd0c0000 0x0 0x1000>; - clocks = <&pclk>, <&sysclk>; - clock-names = "dsi_p_clk", "dsi_sys_clk"; - interrupts = <1>; - phys = <&dphy0>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi0_dpi_input: endpoint { - remote-endpoint = <&xxx_dpi_output>; - }; - }; - }; - - panel: dsi-dev@0 { - compatible = "<vendor,panel>"; - reg = <0>; - }; - }; - -or - - dsi0: dsi@fd0c0000 { - compatible = "cdns,dsi"; - reg = <0x0 0xfd0c0000 0x0 0x1000>; - clocks = <&pclk>, <&sysclk>; - clock-names = "dsi_p_clk", "dsi_sys_clk"; - interrupts = <1>; - phys = <&dphy1>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dsi0_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi_panel_input>; - }; - }; - - port@1 { - reg = <1>; - dsi0_dpi_input: endpoint { - remote-endpoint = <&xxx_dpi_output>; - }; - }; - }; - }; - - i2c@xxx { - panel: panel@59 { - compatible = "<vendor,panel>"; - reg = <0x59>; - - port { - dsi_panel_input: endpoint { - remote-endpoint = <&dsi0_output>; - }; - }; - }; - }; diff --git a/dts/Bindings/display/bridge/cdns,dsi.yaml b/dts/Bindings/display/bridge/cdns,dsi.yaml new file mode 100644 index 0000000000..23060324d1 --- /dev/null +++ b/dts/Bindings/display/bridge/cdns,dsi.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/cdns,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DSI bridge + +maintainers: + - Boris Brezillon <boris.brezillon@bootlin.com> + +description: | + CDNS DSI is a bridge device which converts DPI to DSI + +properties: + compatible: + enum: + - cdns,dsi + - ti,j721e-dsi + + reg: + minItems: 1 + items: + - description: + Register block for controller's registers. + - description: + Register block for wrapper settings registers in case of TI J7 SoCs. + + clocks: + items: + - description: PSM clock, used by the IP + - description: sys clock, used by the IP + + clock-names: + items: + - const: dsi_p_clk + - const: dsi_sys_clk + + phys: + maxItems: 1 + + phy-names: + const: dphy + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: dsi_p_rst + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port representing the DSI output. It can have + at most 4 endpoints. The endpoint number is directly encoding + the DSI virtual channel used by this device. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Input port representing the DPI input. + + required: + - port@1 + +allOf: + - $ref: ../dsi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: ti,j721e-dsi + then: + properties: + reg: + minItems: 2 + maxItems: 2 + power-domains: + maxItems: 1 + else: + properties: + reg: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + - ports + +unevaluatedProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + dsi@fd0c0000 { + compatible = "cdns,dsi"; + reg = <0x0 0xfd0c0000 0x0 0x1000>; + clocks = <&pclk>, <&sysclk>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + interrupts = <1>; + phys = <&dphy0>; + phy-names = "dphy"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&xxx_dpi_output>; + }; + }; + }; + + panel@0 { + compatible = "panasonic,vvx10f034n00"; + reg = <0>; + power-supply = <&vcc_lcd_reg>; + }; + }; + }; + + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + dsi@fd0c0000 { + compatible = "cdns,dsi"; + reg = <0x0 0xfd0c0000 0x0 0x1000>; + clocks = <&pclk>, <&sysclk>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + interrupts = <1>; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_panel_input>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&xxx_dpi_output>; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/cdns,mhdp8546.yaml b/dts/Bindings/display/bridge/cdns,mhdp8546.yaml index b2e8bc6da9..c2b369456e 100644 --- a/dts/Bindings/display/bridge/cdns,mhdp8546.yaml +++ b/dts/Bindings/display/bridge/cdns,mhdp8546.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence MHDP8546 bridge diff --git a/dts/Bindings/display/bridge/chipone,icn6211.yaml b/dts/Bindings/display/bridge/chipone,icn6211.yaml index 4f0b7c7131..5fb54375ae 100644 --- a/dts/Bindings/display/bridge/chipone,icn6211.yaml +++ b/dts/Bindings/display/bridge/chipone,icn6211.yaml @@ -24,6 +24,15 @@ properties: maxItems: 1 description: virtual channel number of a DSI peripheral + clock-names: + const: refclk + + clocks: + maxItems: 1 + description: | + Optional external clock connected to REF_CLK input. + The clock rate must be in 10..154 MHz range. + enable-gpios: description: Bridge EN pin, chip is reset when EN is low. diff --git a/dts/Bindings/display/bridge/chrontel,ch7033.yaml b/dts/Bindings/display/bridge/chrontel,ch7033.yaml index bb6289c7d3..b0589fa167 100644 --- a/dts/Bindings/display/bridge/chrontel,ch7033.yaml +++ b/dts/Bindings/display/bridge/chrontel,ch7033.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/display/bridge/chrontel,ch7033.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Chrontel CH7033 Video Encoder Device Tree Bindings +title: Chrontel CH7033 Video Encoder maintainers: - Lubomir Rintel <lkundrak@v3.sk> diff --git a/dts/Bindings/display/bridge/fsl,imx8qxp-ldb.yaml b/dts/Bindings/display/bridge/fsl,imx8qxp-ldb.yaml new file mode 100644 index 0000000000..94543006f5 --- /dev/null +++ b/dts/Bindings/display/bridge/fsl,imx8qxp-ldb.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp LVDS Display Bridge + +maintainers: + - Liu Ying <victor.liu@nxp.com> + +description: | + The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels. + + The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module. + The CSR module, as a system controller, contains the LDB's configuration + registers. + + For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color + format and can map the input to VESA or JEIDA standards. The two channels + cannot be used simultaneously, that is to say, the user should pick one of + them to use. Two LDB channels from two LDB instances can work together in + LDB split mode to support a dual link LVDS display. The channel indexes + have to be different. Channel0 outputs odd pixels and channel1 outputs + even pixels. + + For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel + input color format. The two channels can be used simultaneously, either + in dual mode or split mode. In dual mode, the two channels output identical + data. In split mode, channel0 outputs odd pixels and channel1 outputs even + pixels. + + A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in + the SoC reference manuals. The pixel mapper uses logic of LDBs embedded in + i.MX6qdl/sx SoCs, i.e., it is essentially based on them. To keep the naming + consistency, this binding calls it LDB. + +properties: + compatible: + enum: + - fsl,imx8qm-ldb + - fsl,imx8qxp-ldb + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: + items: + - description: pixel clock + - description: bypass clock + + clock-names: + items: + - const: pixel + - const: bypass + + power-domains: + maxItems: 1 + + fsl,companion-ldb: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle which points to companion LDB which is used in LDB split mode. + +patternProperties: + "^channel@[0-1]$": + type: object + description: Represents a channel of LDB. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + description: The channel index. + enum: [ 0, 1 ] + + phys: + description: A phandle to the phy module representing the LVDS PHY. + maxItems: 1 + + phy-names: + const: lvds_phy + + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input port of the channel. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output port of the channel. + + required: + - "#address-cells" + - "#size-cells" + - reg + - phys + - phy-names + + additionalProperties: false + +required: + - compatible + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + - power-domains + - channel@0 + - channel@1 + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8qm-ldb + then: + properties: + fsl,companion-ldb: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/firmware/imx/rsrc.h> + ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>; + }; + }; + }; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml b/dts/Bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml new file mode 100644 index 0000000000..50bae21221 --- /dev/null +++ b/dts/Bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Pixel Combiner + +maintainers: + - Liu Ying <victor.liu@nxp.com> + +description: | + The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a + single display controller and manipulates the two streams to support a number + of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as + either one screen, two screens, or virtual screens. The pixel combiner is + also responsible for generating some of the control signals for the pixel link + output channel. + +properties: + compatible: + enum: + - fsl,imx8qm-pixel-combiner + - fsl,imx8qxp-pixel-combiner + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: apb + + power-domains: + maxItems: 1 + +patternProperties: + "^channel@[0-1]$": + type: object + description: Represents a display stream of pixel combiner. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + description: The display stream index. + enum: [ 0, 1 ] + + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input endpoint of the display stream. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output endpoint of the display stream. + + required: + - "#address-cells" + - "#size-cells" + - reg + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - "#address-cells" + - "#size-cells" + - reg + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8-lpcg.h> + #include <dt-bindings/firmware/imx/rsrc.h> + pixel-combiner@56020000 { + compatible = "fsl,imx8qxp-pixel-combiner"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x56020000 0x10000>; + clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>; + clock-names = "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + port@0 { + reg = <0>; + + dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint { + remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>; + }; + }; + + port@1 { + reg = <1>; + + dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint { + remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>; + }; + }; + }; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + port@0 { + reg = <0>; + + dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint { + remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>; + }; + }; + + port@1 { + reg = <1>; + + dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint { + remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/dts/Bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml new file mode 100644 index 0000000000..38ecc7926f --- /dev/null +++ b/dts/Bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Pixel Link + +maintainers: + - Liu Ying <victor.liu@nxp.com> + +description: | + The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard + asynchronous linkage between pixel sources(display controller or + camera module) and pixel consumers(imaging or displays). + It consists of two distinct functions, a pixel transfer function and a + control interface. Multiple pixel channels can exist per one control channel. + This binding documentation is only for pixel links whose pixel sources are + display controllers. + + The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU) + firmware. + +properties: + compatible: + enum: + - fsl,imx8qm-dc-pixel-link + - fsl,imx8qxp-dc-pixel-link + + fsl,dc-id: + $ref: /schemas/types.yaml#/definitions/uint8 + description: | + u8 value representing the display controller index that the pixel link + connects to. + + fsl,dc-stream-id: + $ref: /schemas/types.yaml#/definitions/uint8 + description: | + u8 value representing the display controller stream index that the pixel + link connects to. + enum: [0, 1] + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: The pixel link input port node from upstream video source. + + patternProperties: + "^port@[1-4]$": + $ref: /schemas/graph.yaml#/properties/port + description: The pixel link output port node to downstream bridge. + + required: + - port@0 + - port@1 + - port@2 + - port@3 + - port@4 + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8qxp-dc-pixel-link + then: + properties: + fsl,dc-id: + const: 0 + + - if: + properties: + compatible: + contains: + const: fsl,imx8qm-dc-pixel-link + then: + properties: + fsl,dc-id: + enum: [0, 1] + +required: + - compatible + - fsl,dc-id + - fsl,dc-stream-id + - ports + +additionalProperties: false + +examples: + - | + dc0-pixel-link0 { + compatible = "fsl,imx8qxp-dc-pixel-link"; + fsl,dc-id = /bits/ 8 <0>; + fsl,dc-stream-id = /bits/ 8 <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* from dc0 pixel combiner channel0 */ + port@0 { + reg = <0>; + + dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint { + remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>; + }; + }; + + /* to PXL2DPIs in MIPI/LVDS combo subsystems */ + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>; + }; + + dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>; + }; + }; + + /* unused */ + port@2 { + reg = <2>; + }; + + /* unused */ + port@3 { + reg = <3>; + }; + + /* to imaging subsystem */ + port@4 { + reg = <4>; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml b/dts/Bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml new file mode 100644 index 0000000000..e4e77fad05 --- /dev/null +++ b/dts/Bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface + +maintainers: + - Liu Ying <victor.liu@nxp.com> + +description: | + The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI) + interfaces the pixel link 36-bit data output and the DSI controller’s + MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module + used in LVDS mode, to remap the pixel color codings between those modules. + This module is purely combinatorial. + + The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module. + The CSR module, as a system controller, contains the PXL2DPI's configuration + register. + +properties: + compatible: + const: fsl,imx8qxp-pxl2dpi + + fsl,sc-resource: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The SCU resource ID associated with this PXL2DPI instance. + + power-domains: + maxItems: 1 + + fsl,companion-pxl2dpi: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle which points to companion PXL2DPI which is used by downstream + LVDS Display Bridge(LDB) in split mode. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: The PXL2DPI input port node from pixel link. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: The PXL2DPI output port node to downstream bridge. + + required: + - port@0 + - port@1 + +required: + - compatible + - fsl,sc-resource + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/firmware/imx/rsrc.h> + pxl2dpi { + compatible = "fsl,imx8qxp-pxl2dpi"; + fsl,sc-resource = <IMX_SC_R_MIPI_0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>; + }; + + mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>; + }; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/fsl,imx93-mipi-dsi.yaml b/dts/Bindings/display/bridge/fsl,imx93-mipi-dsi.yaml new file mode 100644 index 0000000000..d6e51d0cf5 --- /dev/null +++ b/dts/Bindings/display/bridge/fsl,imx93-mipi-dsi.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx93-mipi-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX93 specific extensions to Synopsys Designware MIPI DSI + +maintainers: + - Liu Ying <victor.liu@nxp.com> + +description: | + There is a Synopsys Designware MIPI DSI Host Controller and a Synopsys + Designware MIPI DPHY embedded in Freescale i.MX93 SoC. Some configurations + and extensions to them are controlled by i.MX93 media blk-ctrl. + +allOf: + - $ref: snps,dw-mipi-dsi.yaml# + +properties: + compatible: + const: fsl,imx93-mipi-dsi + + clocks: + items: + - description: apb clock + - description: pixel clock + - description: PHY configuration clock + - description: PHY reference clock + + clock-names: + items: + - const: pclk + - const: pix + - const: phy_cfg + - const: phy_ref + + interrupts: + maxItems: 1 + + fsl,media-blk-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + i.MX93 media blk-ctrl, as a syscon, controls pixel component bit map + configurations from LCDIF display controller to the MIPI DSI host + controller and MIPI DPHY PLL related configurations through PLL SoC + interface. + + power-domains: + maxItems: 1 + +required: + - compatible + - interrupts + - fsl,media-blk-ctrl + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/imx93-clock.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/fsl,imx93-power.h> + + dsi@4ae10000 { + compatible = "fsl,imx93-mipi-dsi"; + reg = <0x4ae10000 0x10000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MIPI_DSI_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_MIPI_PHY_CFG>, + <&clk IMX93_CLK_24M>; + clock-names = "pclk", "pix", "phy_cfg", "phy_ref"; + fsl,media-blk-ctrl = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&adp5585gpio 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_to_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsi>; + }; + }; + + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/fsl,ldb.yaml b/dts/Bindings/display/bridge/fsl,ldb.yaml index 77f174eee4..07388bf2b9 100644 --- a/dts/Bindings/display/bridge/fsl,ldb.yaml +++ b/dts/Bindings/display/bridge/fsl,ldb.yaml @@ -16,7 +16,10 @@ description: | properties: compatible: - const: fsl,imx8mp-ldb + enum: + - fsl,imx6sx-ldb + - fsl,imx8mp-ldb + - fsl,imx93-ldb clocks: maxItems: 1 @@ -24,6 +27,14 @@ properties: clock-names: const: ldb + reg: + maxItems: 2 + + reg-names: + items: + - const: ldb + - const: lvds + ports: $ref: /schemas/graph.yaml#/properties/ports @@ -49,6 +60,20 @@ required: - clocks - ports +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6sx-ldb + - fsl,imx93-ldb + then: + properties: + ports: + properties: + port@2: false + additionalProperties: false examples: @@ -56,10 +81,15 @@ examples: #include <dt-bindings/clock/imx8mp-clock.h> blk-ctrl { - bridge { + #address-cells = <1>; + #size-cells = <1>; + + bridge@5c { compatible = "fsl,imx8mp-ldb"; clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; clock-names = "ldb"; + reg = <0x5c 0x4>, <0x128 0x4>; + reg-names = "ldb", "lvds"; ports { #address-cells = <1>; diff --git a/dts/Bindings/display/bridge/ingenic,jz4780-hdmi.yaml b/dts/Bindings/display/bridge/ingenic,jz4780-hdmi.yaml index b8219eab44..0b27df429b 100644 --- a/dts/Bindings/display/bridge/ingenic,jz4780-hdmi.yaml +++ b/dts/Bindings/display/bridge/ingenic,jz4780-hdmi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/bridge/ingenic,jz4780-hdmi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Bindings for Ingenic JZ4780 HDMI Transmitter +title: Ingenic JZ4780 HDMI Transmitter maintainers: - H. Nikolaus Schaller <hns@goldelico.com> @@ -55,7 +55,6 @@ examples: compatible = "ingenic,jz4780-dw-hdmi"; reg = <0x10180000 0x8000>; reg-io-width = <4>; - ddc-i2c-bus = <&i2c4>; interrupt-parent = <&intc>; interrupts = <3>; clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>; diff --git a/dts/Bindings/display/bridge/intel,keembay-dsi.yaml b/dts/Bindings/display/bridge/intel,keembay-dsi.yaml index dcb1336ee2..958a073f4f 100644 --- a/dts/Bindings/display/bridge/intel,keembay-dsi.yaml +++ b/dts/Bindings/display/bridge/intel,keembay-dsi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/bridge/intel,keembay-dsi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Devicetree bindings for Intel Keem Bay mipi dsi controller +title: Intel Keem Bay mipi dsi controller maintainers: - Anitha Chrisanthus <anitha.chrisanthus@intel.com> diff --git a/dts/Bindings/display/bridge/ite,it6505.yaml b/dts/Bindings/display/bridge/ite,it6505.yaml index 833d11b230..c9a882ee6d 100644 --- a/dts/Bindings/display/bridge/ite,it6505.yaml +++ b/dts/Bindings/display/bridge/ite,it6505.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/bridge/ite,it6505.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ITE it6505 Device Tree Bindings +title: ITE it6505 maintainers: - Allen Chen <allen.chen@ite.com.tw> @@ -52,9 +52,49 @@ properties: maxItems: 1 description: extcon specifier for the Power Delivery - port: - $ref: /schemas/graph.yaml#/properties/port - description: A port node pointing to DPI host port node + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: A port node pointing to DPI host port node + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + properties: + link-frequencies: + minItems: 1 + maxItems: 1 + description: Allowed max link frequencies in Hz + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Video port for DP output + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + uniqueItems: true + items: + - enum: [ 0, 1 ] + - const: 1 + - const: 2 + - const: 3 + + required: + - port@0 + - port@1 required: - compatible @@ -63,6 +103,7 @@ required: - interrupts - reset-gpios - extcon + - ports additionalProperties: false @@ -85,9 +126,24 @@ examples: reset-gpios = <&pio 179 1>; extcon = <&usbc_extcon>; - port { - it6505_in: endpoint { - remote-endpoint = <&dpi_out>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + it6505_in: endpoint { + remote-endpoint = <&dpi_out>; + link-frequencies = /bits/ 64 <150000000>; + }; + }; + + port@1 { + reg = <1>; + it6505_out: endpoint { + remote-endpoint = <&dp_in>; + data-lanes = <0 1>; + }; }; }; }; diff --git a/dts/Bindings/display/bridge/ite,it66121.yaml b/dts/Bindings/display/bridge/ite,it66121.yaml index c6e81f5322..a7eb260369 100644 --- a/dts/Bindings/display/bridge/ite,it66121.yaml +++ b/dts/Bindings/display/bridge/ite,it66121.yaml @@ -4,11 +4,11 @@ $id: http://devicetree.org/schemas/display/bridge/ite,it66121.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ITE it66121 HDMI bridge Device Tree Bindings +title: ITE it66121 HDMI bridge maintainers: - Phong LE <ple@baylibre.com> - - Neil Armstrong <narmstrong@baylibre.com> + - Neil Armstrong <neil.armstrong@linaro.org> description: | The IT66121 is a high-performance and low-power single channel HDMI @@ -17,7 +17,9 @@ description: | properties: compatible: - const: ite,it66121 + enum: + - ite,it66121 + - ite,it6610 reg: maxItems: 1 diff --git a/dts/Bindings/display/bridge/lontium,lt8912b.yaml b/dts/Bindings/display/bridge/lontium,lt8912b.yaml index 674891ee2f..2cef252157 100644 --- a/dts/Bindings/display/bridge/lontium,lt8912b.yaml +++ b/dts/Bindings/display/bridge/lontium,lt8912b.yaml @@ -55,6 +55,27 @@ properties: - port@0 - port@1 + vcchdmipll-supply: + description: A 1.8V supply that powers the HDMI PLL. + + vcchdmitx-supply: + description: A 1.8V supply that powers the HDMI TX part. + + vcclvdspll-supply: + description: A 1.8V supply that powers the LVDS PLL. + + vcclvdstx-supply: + description: A 1.8V supply that powers the LVDS TX part. + + vccmipirx-supply: + description: A 1.8V supply that powers the MIPI RX part. + + vccsysclk-supply: + description: A 1.8V supply that powers the SYSCLK. + + vdd-supply: + description: A 1.8V supply that powers the digital part. + required: - compatible - reg @@ -67,7 +88,7 @@ examples: - | #include <dt-bindings/gpio/gpio.h> - i2c4 { + i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/display/bridge/lvds-codec.yaml b/dts/Bindings/display/bridge/lvds-codec.yaml index 3a8614e0f6..84aafcbf09 100644 --- a/dts/Bindings/display/bridge/lvds-codec.yaml +++ b/dts/Bindings/display/bridge/lvds-codec.yaml @@ -51,6 +51,7 @@ properties: properties: port@0: $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: | For LVDS encoders, port 0 is the parallel input For LVDS decoders, port 0 is the LVDS input diff --git a/dts/Bindings/display/bridge/nxp,ptn3460.yaml b/dts/Bindings/display/bridge/nxp,ptn3460.yaml index 107dd138e6..70ec70922c 100644 --- a/dts/Bindings/display/bridge/nxp,ptn3460.yaml +++ b/dts/Bindings/display/bridge/nxp,ptn3460.yaml @@ -18,7 +18,7 @@ properties: maxItems: 1 edid-emulation: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: The EDID emulation entry to use Value Resolution Description @@ -71,7 +71,7 @@ examples: - | #include <dt-bindings/gpio/gpio.h> - i2c1 { + i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/display/bridge/nxp,tda998x.yaml b/dts/Bindings/display/bridge/nxp,tda998x.yaml new file mode 100644 index 0000000000..b8e9cf6ce4 --- /dev/null +++ b/dts/Bindings/display/bridge/nxp,tda998x.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/nxp,tda998x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP TDA998x HDMI transmitter + +maintainers: + - Russell King <linux@armlinux.org.uk> + +properties: + compatible: + const: nxp,tda998x + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + video-ports: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0x230145 + maximum: 0xffffff + description: + 24 bits value which defines how the video controller output is wired to + the TDA998x input. + + audio-ports: + description: + Array of 2 values per DAI (Documentation/sound/soc/dai.rst). + The implementation allows one or two DAIs. + If two DAIs are defined, they must be of different type. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 2 + items: + items: + - description: | + The first value defines the DAI type: TDA998x_SPDIF or TDA998x_I2S + (see include/dt-bindings/display/tda998x.h). + enum: [ 1, 2 ] + - description: + The second value defines the tda998x AP_ENA reg content when the + DAI in question is used. + maximum: 0xff + + '#sound-dai-cells': + enum: [ 0, 1 ] + + nxp,calib-gpios: + maxItems: 1 + description: + Calibration GPIO, which must correspond with the gpio used for the + TDA998x interrupt pin. + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Parallel input port + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + type: object + description: Parallel input port + + port@1: + type: object + description: HDMI output port + +required: + - compatible + - reg + +oneOf: + - required: + - port + - required: + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/display/tda998x.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + tda998x: hdmi-encoder@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + interrupt-parent = <&gpio0>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + video-ports = <0x230145>; + + #sound-dai-cells = <1>; + /* DAI-format / AP_ENA reg value */ + audio-ports = <TDA998x_SPDIF 0x04>, + <TDA998x_I2S 0x03>; + + port { + tda998x_in: endpoint { + remote-endpoint = <&lcdc_0>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/parade,ps8622.yaml b/dts/Bindings/display/bridge/parade,ps8622.yaml new file mode 100644 index 0000000000..e6397ac204 --- /dev/null +++ b/dts/Bindings/display/bridge/parade,ps8622.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/parade,ps8622.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Parade PS8622/PS8625 DisplayPort to LVDS Converter + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +properties: + compatible: + enum: + - parade,ps8622 + - parade,ps8625 + + reg: + maxItems: 1 + + lane-count: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + description: Number of DP lanes to use. + + use-external-pwm: + type: boolean + description: Backlight will be controlled by an external PWM. + + reset-gpios: + maxItems: 1 + description: GPIO connected to RST_ pin. + + sleep-gpios: + maxItems: 1 + description: GPIO connected to PD_ pin. + + vdd12-supply: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for LVDS output. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for DisplayPort input. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - reset-gpios + - sleep-gpios + - ports + +allOf: + - if: + properties: + compatible: + const: parade,ps8622 + then: + properties: + lane-count: + const: 1 + else: + properties: + lane-count: + const: 2 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + lvds-bridge@48 { + compatible = "parade,ps8625"; + reg = <0x48>; + sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>; + lane-count = <2>; + use-external-pwm; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + port@1 { + reg = <1>; + + bridge_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/ps8622.txt b/dts/Bindings/display/bridge/ps8622.txt deleted file mode 100644 index c989c3807f..0000000000 --- a/dts/Bindings/display/bridge/ps8622.txt +++ /dev/null @@ -1,31 +0,0 @@ -ps8622-bridge bindings - -Required properties: - - compatible: "parade,ps8622" or "parade,ps8625" - - reg: first i2c address of the bridge - - sleep-gpios: OF device-tree gpio specification for PD_ pin. - - reset-gpios: OF device-tree gpio specification for RST_ pin. - -Optional properties: - - lane-count: number of DP lanes to use - - use-external-pwm: backlight will be controlled by an external PWM - - video interfaces: Device node can contain video interface port - nodes for panel according to [1]. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - lvds-bridge@48 { - compatible = "parade,ps8622"; - reg = <0x48>; - sleep-gpios = <&gpc3 6 1 0 0>; - reset-gpios = <&gpc3 1 1 0 0>; - lane-count = <1>; - ports { - port@0 { - bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; diff --git a/dts/Bindings/display/bridge/ps8640.yaml b/dts/Bindings/display/bridge/ps8640.yaml index 8ab156e0a8..5856450c5d 100644 --- a/dts/Bindings/display/bridge/ps8640.yaml +++ b/dts/Bindings/display/bridge/ps8640.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/bridge/ps8640.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MIPI DSI to eDP Video Format Converter Device Tree Bindings +title: MIPI DSI to eDP Video Format Converter maintainers: - Nicolas Boichat <drinkcat@chromium.org> @@ -73,7 +73,7 @@ additionalProperties: false examples: - | #include <dt-bindings/gpio/gpio.h> - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml b/dts/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml index afeeb96739..d33026f85e 100644 --- a/dts/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml +++ b/dts/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml @@ -11,13 +11,14 @@ maintainers: description: | This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas - R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up + R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up to four data lanes. properties: compatible: enum: - renesas,r8a779a0-dsi-csi2-tx # for V3U + - renesas,r8a779g0-dsi-csi2-tx # for V4H reg: maxItems: 1 diff --git a/dts/Bindings/display/bridge/renesas,dsi.yaml b/dts/Bindings/display/bridge/renesas,dsi.yaml new file mode 100644 index 0000000000..e08c246339 --- /dev/null +++ b/dts/Bindings/display/bridge/renesas,dsi.yaml @@ -0,0 +1,183 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L MIPI DSI Encoder + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +description: | + This binding describes the MIPI DSI encoder embedded in the Renesas + RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with + up to four data lanes. + +allOf: + - $ref: /schemas/display/dsi-controller.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} + - renesas,r9a07g054-mipi-dsi # RZ/V2L + - const: renesas,rzg2l-mipi-dsi + + reg: + maxItems: 1 + + interrupts: + items: + - description: Sequence operation channel 0 interrupt + - description: Sequence operation channel 1 interrupt + - description: Video-Input operation channel 1 interrupt + - description: DSI Packet Receive interrupt + - description: DSI Fatal Error interrupt + - description: DSI D-PHY PPI interrupt + - description: Debug interrupt + + interrupt-names: + items: + - const: seq0 + - const: seq1 + - const: vin1 + - const: rcv + - const: ferr + - const: ppi + - const: debug + + clocks: + items: + - description: DSI D-PHY PLL multiplied clock + - description: DSI D-PHY system clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock + + clock-names: + items: + - const: pllclk + - const: sysclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk + + resets: + items: + - description: MIPI_DSI_CMN_RSTB + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N + + reset-names: + items: + - const: rst + - const: arst + - const: prst + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Parallel input port + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: DSI output port + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + required: + - data-lanes + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a07g044-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + dsi0: dsi@10850000 { + compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi"; + reg = <0x10850000 0x20000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>; + clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>, + <&cpg R9A07G044_MIPI_DSI_ARESET_N>, + <&cpg R9A07G044_MIPI_DSI_PRESET_N>; + reset-names = "rst", "arst", "prst"; + power-domains = <&cpg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7535_in>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/bridge/renesas,dw-hdmi.yaml b/dts/Bindings/display/bridge/renesas,dw-hdmi.yaml index 0c9785c8db..e3ec697f89 100644 --- a/dts/Bindings/display/bridge/renesas,dw-hdmi.yaml +++ b/dts/Bindings/display/bridge/renesas,dw-hdmi.yaml @@ -38,6 +38,9 @@ properties: clock-names: maxItems: 2 + resets: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports @@ -67,6 +70,7 @@ required: - reg - clocks - clock-names + - resets - interrupts - ports @@ -85,6 +89,7 @@ examples: clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>; clock-names = "iahb", "isfr"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 729>; ports { #address-cells = <1>; diff --git a/dts/Bindings/display/bridge/samsung,mipi-dsim.yaml b/dts/Bindings/display/bridge/samsung,mipi-dsim.yaml new file mode 100644 index 0000000000..4ed7a799ba --- /dev/null +++ b/dts/Bindings/display/bridge/samsung,mipi-dsim.yaml @@ -0,0 +1,280 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung MIPI DSIM bridge controller + +maintainers: + - Inki Dae <inki.dae@samsung.com> + - Jagan Teki <jagan@amarulasolutions.com> + - Marek Szyprowski <m.szyprowski@samsung.com> + +description: | + Samsung MIPI DSIM bridge controller can be found it on Exynos + and i.MX8M Mini/Nano/Plus SoC's. + +properties: + compatible: + oneOf: + - enum: + - samsung,exynos3250-mipi-dsi + - samsung,exynos4210-mipi-dsi + - samsung,exynos5410-mipi-dsi + - samsung,exynos5422-mipi-dsi + - samsung,exynos5433-mipi-dsi + - fsl,imx8mm-mipi-dsim + - fsl,imx8mp-mipi-dsim + - items: + - const: fsl,imx8mn-mipi-dsim + - const: fsl,imx8mm-mipi-dsim + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + clocks: + minItems: 2 + maxItems: 5 + + clock-names: + minItems: 2 + maxItems: 5 + + samsung,phy-type: + $ref: /schemas/types.yaml#/definitions/uint32 + description: phandle to the samsung phy-type + + power-domains: + maxItems: 1 + + samsung,power-domain: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the associated samsung power domain + + vddcore-supply: + description: MIPI DSIM Core voltage supply (e.g. 1.1V) + + vddio-supply: + description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) + + samsung,burst-clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + DSIM high speed burst mode frequency. If absent, + the pixel clock from the attached device or bridge + will be used instead. + + samsung,esc-clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + DSIM escape mode frequency. + + samsung,pll-clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + DSIM oscillator clock frequency. If absent, the clock frequency + of sclk_mipi will be used instead. + + phys: + maxItems: 1 + + phy-names: + const: dsim + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Input port node to receive pixel data from the + display controller. Exactly one endpoint must be + specified. + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + DSI output port node to the panel or the next bridge + in the chain. + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + uniqueItems: true + items: + enum: [ 1, 2, 3, 4 ] + + lane-polarities: + minItems: 1 + maxItems: 5 + description: + The Samsung MIPI DSI IP requires that all the data lanes have + the same polarity. + + dependencies: + lane-polarities: [data-lanes] + +required: + - clock-names + - clocks + - compatible + - interrupts + - reg + - samsung,esc-clock-frequency + +allOf: + - $ref: ../dsi-controller.yaml# + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-mipi-dsi + + then: + properties: + clocks: + minItems: 5 + + clock-names: + items: + - const: bus_clk + - const: phyclk_mipidphy0_bitclkdiv8 + - const: phyclk_mipidphy0_rxclkesc0 + - const: sclk_rgb_vclk_to_dsim0 + - const: sclk_mipi + + ports: + required: + - port@0 + + required: + - ports + - vddcore-supply + - vddio-supply + + - if: + properties: + compatible: + contains: + const: samsung,exynos5410-mipi-dsi + + then: + properties: + clocks: + minItems: 2 + + clock-names: + items: + - const: bus_clk + - const: pll_clk + + required: + - vddcore-supply + - vddio-supply + + - if: + properties: + compatible: + contains: + const: samsung,exynos4210-mipi-dsi + + then: + properties: + clocks: + minItems: 2 + + clock-names: + items: + - const: bus_clk + - const: sclk_mipi + + required: + - vddcore-supply + - vddio-supply + + - if: + properties: + compatible: + contains: + const: samsung,exynos3250-mipi-dsi + + then: + properties: + clocks: + minItems: 2 + + clock-names: + items: + - const: bus_clk + - const: pll_clk + + required: + - vddcore-supply + - vddio-supply + - samsung,phy-type + +additionalProperties: + type: object + +examples: + - | + #include <dt-bindings/clock/exynos5433.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + dsi@13900000 { + compatible = "samsung,exynos5433-mipi-dsi"; + reg = <0x13900000 0xC0>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + phys = <&mipi_phy 1>; + phy-names = "dsim"; + clocks = <&cmu_disp CLK_PCLK_DSIM0>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>, + <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>, + <&cmu_disp CLK_SCLK_DSIM0>; + clock-names = "bus_clk", + "phyclk_mipidphy0_bitclkdiv8", + "phyclk_mipidphy0_rxclkesc0", + "sclk_rgb_vclk_to_dsim0", + "sclk_mipi"; + power-domains = <&pd_disp>; + vddcore-supply = <&ldo6_reg>; + vddio-supply = <&ldo7_reg>; + samsung,burst-clock-frequency = <512000000>; + samsung,esc-clock-frequency = <16000000>; + samsung,pll-clock-frequency = <24000000>; + pinctrl-names = "default"; + pinctrl-0 = <&te_irq>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_to_mic: endpoint { + remote-endpoint = <&mic_to_dsi>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/sii902x.txt b/dts/Bindings/display/bridge/sii902x.txt deleted file mode 100644 index 3bc760cc31..0000000000 --- a/dts/Bindings/display/bridge/sii902x.txt +++ /dev/null @@ -1,78 +0,0 @@ -sii902x HDMI bridge bindings - -Required properties: - - compatible: "sil,sii9022" - - reg: i2c address of the bridge - -Optional properties: - - interrupts: describe the interrupt line used to inform the host - about hotplug events. - - reset-gpios: OF device-tree gpio specification for RST_N pin. - - iovcc-supply: I/O Supply Voltage (1.8V or 3.3V) - - cvcc12-supply: Digital Core Supply Voltage (1.2V) - - HDMI audio properties: - - #sound-dai-cells: <0> or <1>. <0> if only i2s or spdif pin - is wired, <1> if the both are wired. HDMI audio is - configured only if this property is found. - - sil,i2s-data-lanes: Array of up to 4 integers with values of 0-3 - Each integer indicates which i2s pin is connected to which - audio fifo. The first integer selects i2s audio pin for the - first audio fifo#0 (HDMI channels 1&2), second for fifo#1 - (HDMI channels 3&4), and so on. There is 4 fifos and 4 i2s - pins (SD0 - SD3). Any i2s pin can be connected to any fifo, - but there can be no gaps. E.g. an i2s pin must be mapped to - fifo#0 and fifo#1 before mapping a channel to fifo#2. Default - value is <0>, describing SD0 pin beiging routed to hdmi audio - fifo #0. - - clocks: phandle and clock specifier for each clock listed in - the clock-names property - - clock-names: "mclk" - Describes SII902x MCLK input. MCLK can be used to produce - HDMI audio CTS values. This property follows - Documentation/devicetree/bindings/clock/clock-bindings.txt - consumer binding. - - If HDMI audio is configured the sii902x device becomes an I2S - and/or spdif audio codec component (e.g a digital audio sink), - that can be used in configuring a full audio devices with - simple-card or audio-graph-card binding. See their binding - documents on how to describe the way the sii902x device is - connected to the rest of the audio system: - Documentation/devicetree/bindings/sound/simple-card.yaml - Documentation/devicetree/bindings/sound/audio-graph-card.yaml - Note: In case of the audio-graph-card binding the used port - index should be 3. - -Optional subnodes: - - video input: this subnode can contain a video input port node - to connect the bridge to a display controller output (See this - documentation [1]). - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - hdmi-bridge@39 { - compatible = "sil,sii9022"; - reg = <0x39>; - reset-gpios = <&pioA 1 0>; - iovcc-supply = <&v3v3_hdmi>; - cvcc12-supply = <&v1v2_hdmi>; - - #sound-dai-cells = <0>; - sil,i2s-data-lanes = < 0 1 2 >; - clocks = <&mclk>; - clock-names = "mclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - bridge_in: endpoint { - remote-endpoint = <&dc_out>; - }; - }; - }; - }; diff --git a/dts/Bindings/display/bridge/sil,sii8620.yaml b/dts/Bindings/display/bridge/sil,sii8620.yaml new file mode 100644 index 0000000000..6d1a36b76f --- /dev/null +++ b/dts/Bindings/display/bridge/sil,sii8620.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/sil,sii8620.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Image SiI8620 HDMI/MHL bridge + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +properties: + compatible: + const: sil,sii8620 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xtal + + cvcc10-supply: + description: Digital Core Supply Voltage (1.0V) + + interrupts: + maxItems: 1 + + iovcc18-supply: + description: I/O Supply Voltage (1.8V) + + reset-gpios: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + unevaluatedProperties: false + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for HDMI (encoder) input + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + MHL to connector port + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - cvcc10-supply + - interrupts + - iovcc18-supply + - reset-gpios + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@39 { + reg = <0x39>; + compatible = "sil,sii8620"; + cvcc10-supply = <&ldo36_reg>; + iovcc18-supply = <&ldo34_reg>; + interrupt-parent = <&gpf0>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>; + clocks = <&pmu_system_controller 0>; + clock-names = "xtal"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mhl_to_hdmi: endpoint { + remote-endpoint = <&hdmi_to_mhl>; + }; + }; + + port@1 { + reg = <1>; + mhl_to_musb_con: endpoint { + remote-endpoint = <&musb_con_to_mhl>; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/sil,sii9022.yaml b/dts/Bindings/display/bridge/sil,sii9022.yaml new file mode 100644 index 0000000000..5a69547ad3 --- /dev/null +++ b/dts/Bindings/display/bridge/sil,sii9022.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/sil,sii9022.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Image sii902x HDMI bridge + +maintainers: + - Boris Brezillon <bbrezillon@kernel.org> + +properties: + compatible: + oneOf: + - items: + - enum: + - sil,sii9022-cpi # CEC Programming Interface + - sil,sii9022-tpi # Transmitter Programming Interface + - const: sil,sii9022 + - const: sil,sii9022 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + description: Interrupt line used to inform the host about hotplug events. + + reset-gpios: + maxItems: 1 + + iovcc-supply: + description: I/O Supply Voltage (1.8V or 3.3V) + + cvcc12-supply: + description: Digital Core Supply Voltage (1.2V) + + '#sound-dai-cells': + enum: [ 0, 1 ] + description: | + <0> if only I2S or S/PDIF pin is wired, + <1> if both are wired. + HDMI audio is configured only if this property is found. + If HDMI audio is configured, the sii902x device becomes an I2S and/or + S/PDIF audio codec component (e.g. a digital audio sink), that can be + used in configuring full audio devices with simple-card or + audio-graph-card bindings. See their binding documents on how to describe + the way the + sii902x device is connected to the rest of the audio system: + Documentation/devicetree/bindings/sound/simple-card.yaml + Documentation/devicetree/bindings/sound/audio-graph-card.yaml + Note: In case of the audio-graph-card binding the used port index should + be 3. + + sil,i2s-data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + uniqueItems: true + items: + enum: [ 0, 1, 2, 3 ] + description: + Each integer indicates which I2S pin is connected to which audio FIFO. + The first integer selects the I2S audio pin for the first audio FIFO#0 + (HDMI channels 1&2), the second for FIFO#1 (HDMI channels 3&4), and so + on. There are 4 FIFOs and 4 I2S pins (SD0 - SD3). Any I2S pin can be + connected to any FIFO, but there can be no gaps. E.g. an I2S pin must be + mapped to FIFO#0 and FIFO#1 before mapping a channel to FIFO#2. The + default value is <0>, describing SD0 pin being routed to HDMI audio + FIFO#0. + + clocks: + maxItems: 1 + description: MCLK input. MCLK can be used to produce HDMI audio CTS values. + + clock-names: + const: mclk + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Parallel RGB input port + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI output port + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Sound input port + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + hdmi-bridge@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + reset-gpios = <&pioA 1 0>; + iovcc-supply = <&v3v3_hdmi>; + cvcc12-supply = <&v1v2_hdmi>; + + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 1 2 >; + clocks = <&mclk>; + clock-names = "mclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dc_out>; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/sil,sii9234.yaml b/dts/Bindings/display/bridge/sil,sii9234.yaml index f88ddfe481..176181d255 100644 --- a/dts/Bindings/display/bridge/sil,sii9234.yaml +++ b/dts/Bindings/display/bridge/sil,sii9234.yaml @@ -71,7 +71,7 @@ examples: #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> - i2c1 { + i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/display/bridge/sil-sii8620.txt b/dts/Bindings/display/bridge/sil-sii8620.txt deleted file mode 100644 index b05052f7d6..0000000000 --- a/dts/Bindings/display/bridge/sil-sii8620.txt +++ /dev/null @@ -1,33 +0,0 @@ -Silicon Image SiI8620 HDMI/MHL bridge bindings - -Required properties: - - compatible: "sil,sii8620" - - reg: i2c address of the bridge - - cvcc10-supply: Digital Core Supply Voltage (1.0V) - - iovcc18-supply: I/O Supply Voltage (1.8V) - - interrupts: interrupt specifier of INT pin - - reset-gpios: gpio specifier of RESET pin - - clocks, clock-names: specification and name of "xtal" clock - - video interfaces: Device node can contain video interface port - node for HDMI encoder according to [1]. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - sii8620@39 { - reg = <0x39>; - compatible = "sil,sii8620"; - cvcc10-supply = <&ldo36_reg>; - iovcc18-supply = <&ldo34_reg>; - interrupt-parent = <&gpf0>; - interrupts = <2 0>; - reset-gpio = <&gpv7 0 0>; - clocks = <&pmu_system_controller 0>; - clock-names = "xtal"; - - port { - mhl_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_mhl>; - }; - }; - }; diff --git a/dts/Bindings/display/bridge/snps,dw-mipi-dsi.yaml b/dts/Bindings/display/bridge/snps,dw-mipi-dsi.yaml index 11fd68a70d..8747b95ec2 100644 --- a/dts/Bindings/display/bridge/snps,dw-mipi-dsi.yaml +++ b/dts/Bindings/display/bridge/snps,dw-mipi-dsi.yaml @@ -11,7 +11,7 @@ maintainers: description: | This document defines device tree properties for the Synopsys DesignWare MIPI - DSI host controller. It doesn't constitue a device tree binding specification + DSI host controller. It doesn't constitute a device tree binding specification by itself but is meant to be referenced by platform-specific device tree bindings. @@ -26,19 +26,9 @@ properties: reg: maxItems: 1 - clocks: - items: - - description: Module clock - - description: DSI bus clock for either AHB and APB - - description: Pixel clock for the DPI/RGB input - minItems: 2 - - clock-names: - items: - - const: ref - - const: pclk - - const: px_clk - minItems: 2 + clocks: true + + clock-names: true resets: maxItems: 1 diff --git a/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml b/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml index b00246faea..4b7e54a8f0 100644 --- a/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml +++ b/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml @@ -26,7 +26,6 @@ properties: reg-io-width: description: Width (in bytes) of the registers specified by the reg property. - $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 4] default: 1 diff --git a/dts/Bindings/display/bridge/tda998x.txt b/dts/Bindings/display/bridge/tda998x.txt deleted file mode 100644 index f5a02f61dd..0000000000 --- a/dts/Bindings/display/bridge/tda998x.txt +++ /dev/null @@ -1,54 +0,0 @@ -Device-Tree bindings for the NXP TDA998x HDMI transmitter - -Required properties; - - compatible: must be "nxp,tda998x" - - - reg: I2C address - -Required node: - - port: Input port node with endpoint definition, as described - in Documentation/devicetree/bindings/graph.txt - -Optional properties: - - interrupts: interrupt number and trigger type - default: polling - - - pinctrl-0: pin control group to be used for - screen plug/unplug interrupt. - - - pinctrl-names: must contain a "default" entry. - - - video-ports: 24 bits value which defines how the video controller - output is wired to the TDA998x input - default: <0x230145> - - - audio-ports: array of 8-bit values, 2 values per one DAI[1]. - The first value defines the DAI type: TDA998x_SPDIF or TDA998x_I2S[2]. - The second value defines the tda998x AP_ENA reg content when the DAI - in question is used. The implementation allows one or two DAIs. If two - DAIs are defined, they must be of different type. - - - nxp,calib-gpios: calibration GPIO, which must correspond with the - gpio used for the TDA998x interrupt pin. - -[1] Documentation/sound/soc/dai.rst -[2] include/dt-bindings/display/tda998x.h - -Example: - -#include <dt-bindings/display/tda998x.h> - - tda998x: hdmi-encoder { - compatible = "nxp,tda998x"; - reg = <0x70>; - interrupt-parent = <&gpio0>; - interrupts = <27 2>; /* falling edge */ - pinctrl-0 = <&pmx_camera>; - pinctrl-names = "default"; - video-ports = <0x230145>; - - #sound-dai-cells = <2>; - /* DAI-format AP_ENA reg value */ - audio-ports = < TDA998x_SPDIF 0x04 - TDA998x_I2S 0x03>; - - }; diff --git a/dts/Bindings/display/bridge/ti,dlpc3433.yaml b/dts/Bindings/display/bridge/ti,dlpc3433.yaml new file mode 100644 index 0000000000..d3f84d2207 --- /dev/null +++ b/dts/Bindings/display/bridge/ti,dlpc3433.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ti,dlpc3433.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DLPC3433 MIPI DSI to DMD bridge + +maintainers: + - Jagan Teki <jagan@amarulasolutions.com> + - Christopher Vollo <chris@renewoutreach.org> + +description: | + TI DLPC3433 is a MIPI DSI based display controller bridge + for processing high resolution DMD based projectors. + + It has a flexible configuration of MIPI DSI and DPI signal + input that produces a DMD output in RGB565, RGB666, RGB888 + formats. + + It supports upto 720p resolution with 60 and 120 Hz refresh + rates. + +properties: + compatible: + const: ti,dlpc3433 + + reg: + enum: + - 0x1b + - 0x1d + + enable-gpios: + description: PROJ_ON pin, chip powers up PROJ_ON is high. + + vcc_intf-supply: + description: A 1.8V/3.3V supply that power the Host I/O. + + vcc_flsh-supply: + description: A 1.8V/3.3V supply that power the Flash I/O. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Video port for MIPI DSI input. + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for DMD output. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - enable-gpios + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@1b { + compatible = "ti,dlpc3433"; + reg = <0x1b>; + enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_in_dsi: endpoint { + remote-endpoint = <&dsi_out_bridge>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + + bridge_out_panel: endpoint { + remote-endpoint = <&panel_out_bridge>; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/ti,sn65dsi86.yaml b/dts/Bindings/display/bridge/ti,sn65dsi86.yaml index 911564468c..6ec6d287bf 100644 --- a/dts/Bindings/display/bridge/ti,sn65dsi86.yaml +++ b/dts/Bindings/display/bridge/ti,sn65dsi86.yaml @@ -90,7 +90,7 @@ properties: properties: endpoint: - $ref: /schemas/graph.yaml#/$defs/endpoint-base + $ref: /schemas/media/video-interfaces.yaml# unevaluatedProperties: false properties: @@ -106,7 +106,6 @@ properties: description: If you have 1 logical lane the bridge supports routing to either port 0 or port 1. Port 0 is suggested. - See ../../media/video-interface.txt for details. - minItems: 2 maxItems: 2 @@ -118,7 +117,6 @@ properties: description: If you have 2 logical lanes the bridge supports reordering but only on physical ports 0 and 1. - See ../../media/video-interface.txt for details. - minItems: 4 maxItems: 4 @@ -132,7 +130,6 @@ properties: description: If you have 4 logical lanes the bridge supports reordering in any way. - See ../../media/video-interface.txt for details. lane-polarities: minItems: 1 @@ -141,7 +138,6 @@ properties: enum: - 0 - 1 - description: See ../../media/video-interface.txt dependencies: lane-polarities: [data-lanes] diff --git a/dts/Bindings/display/bridge/toshiba,tc358762.yaml b/dts/Bindings/display/bridge/toshiba,tc358762.yaml index a412a1da95..6c1de0b217 100644 --- a/dts/Bindings/display/bridge/toshiba,tc358762.yaml +++ b/dts/Bindings/display/bridge/toshiba,tc358762.yaml @@ -21,6 +21,9 @@ properties: maxItems: 1 description: virtual channel number of a DSI peripheral + reset-gpios: + maxItems: 1 + vddc-supply: description: Regulator for 1.2V internal core power. @@ -51,7 +54,7 @@ additionalProperties: false examples: - | - i2c1 { + i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/display/bridge/toshiba,tc358764.txt b/dts/Bindings/display/bridge/toshiba,tc358764.txt deleted file mode 100644 index 8f9abf28a8..0000000000 --- a/dts/Bindings/display/bridge/toshiba,tc358764.txt +++ /dev/null @@ -1,35 +0,0 @@ -TC358764 MIPI-DSI to LVDS panel bridge - -Required properties: - - compatible: "toshiba,tc358764" - - reg: the virtual channel number of a DSI peripheral - - vddc-supply: core voltage supply, 1.2V - - vddio-supply: I/O voltage supply, 1.8V or 3.3V - - vddlvds-supply: LVDS1/2 voltage supply, 3.3V - - reset-gpios: a GPIO spec for the reset pin - -The device node can contain following 'port' child nodes, -according to the OF graph bindings defined in [1]: - 0: DSI Input, not required, if the bridge is DSI controlled - 1: LVDS Output, mandatory - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - - bridge@0 { - reg = <0>; - compatible = "toshiba,tc358764"; - vddc-supply = <&vcc_1v2_reg>; - vddio-supply = <&vcc_1v8_reg>; - vddlvds-supply = <&vcc_3v3_reg>; - reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>; - #address-cells = <1>; - #size-cells = <0>; - port@1 { - reg = <1>; - lvds_ep: endpoint { - remote-endpoint = <&panel_ep>; - }; - }; - }; diff --git a/dts/Bindings/display/bridge/toshiba,tc358764.yaml b/dts/Bindings/display/bridge/toshiba,tc358764.yaml new file mode 100644 index 0000000000..8666074005 --- /dev/null +++ b/dts/Bindings/display/bridge/toshiba,tc358764.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358764.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba TC358764 MIPI-DSI to LVDS bridge + +maintainers: + - Andrzej Hajda <andrzej.hajda@intel.com> + +properties: + compatible: + const: toshiba,tc358764 + + reg: + description: Virtual channel number of a DSI peripheral + maxItems: 1 + + reset-gpios: + maxItems: 1 + + vddc-supply: + description: Core voltage supply, 1.2V + + vddio-supply: + description: I/O voltage supply, 1.8V or 3.3V + + vddlvds-supply: + description: LVDS1/2 voltage supply, 3.3V + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for MIPI DSI input, if the bridge DSI controlled + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for LVDS output (panel or connector). + + required: + - port@1 + +required: + - compatible + - reg + - reset-gpios + - vddc-supply + - vddio-supply + - vddlvds-supply + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@0 { + compatible = "toshiba,tc358764"; + reg = <0>; + + reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>; + vddc-supply = <&vcc_1v2_reg>; + vddio-supply = <&vcc_1v8_reg>; + vddlvds-supply = <&vcc_3v3_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_ep: endpoint { + remote-endpoint = <&panel_ep>; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/toshiba,tc358767.yaml b/dts/Bindings/display/bridge/toshiba,tc358767.yaml index ed280053ec..ae894d996d 100644 --- a/dts/Bindings/display/bridge/toshiba,tc358767.yaml +++ b/dts/Bindings/display/bridge/toshiba,tc358767.yaml @@ -4,16 +4,24 @@ $id: http://devicetree.org/schemas/display/bridge/toshiba,tc358767.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Toshiba TC358767 eDP bridge bindings +title: Toshiba TC358767/TC358867/TC9595 DSI/DPI/eDP bridge maintainers: - Andrey Gusakov <andrey.gusakov@cogentembedded.com> -description: The TC358767 is bridge device which converts DSI/DPI to eDP/DP +description: | + The TC358767/TC358867/TC9595 is bridge device which + converts DSI/DPI to eDP/DP . properties: compatible: - const: toshiba,tc358767 + oneOf: + - items: + - enum: + - toshiba,tc358867 + - toshiba,tc9595 + - const: toshiba,tc358767 + - const: toshiba,tc358767 reg: enum: @@ -23,7 +31,7 @@ properties: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins clock-names: - const: "ref" + const: ref clocks: maxItems: 1 @@ -41,6 +49,9 @@ properties: description: | OF device-tree gpio specification for RSTX pin(active low system reset) + interrupts: + maxItems: 1 + toshiba,hpd-pin: $ref: /schemas/types.yaml#/definitions/uint32 enum: diff --git a/dts/Bindings/display/bridge/toshiba,tc358768.yaml b/dts/Bindings/display/bridge/toshiba,tc358768.yaml index 0b6f5bef12..779d8c57f8 100644 --- a/dts/Bindings/display/bridge/toshiba,tc358768.yaml +++ b/dts/Bindings/display/bridge/toshiba,tc358768.yaml @@ -87,7 +87,7 @@ examples: - | #include <dt-bindings/gpio/gpio.h> - i2c1 { + i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/display/bridge/toshiba,tc358775.yaml b/dts/Bindings/display/bridge/toshiba,tc358775.yaml index 10471c6c1f..d879c70059 100644 --- a/dts/Bindings/display/bridge/toshiba,tc358775.yaml +++ b/dts/Bindings/display/bridge/toshiba,tc358775.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/bridge/toshiba,tc358775.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Toshiba TC358775 DSI to LVDS bridge bindings +title: Toshiba TC358775 DSI to LVDS bridge maintainers: - Vinay Simha BN <simhavcs@gmail.com> diff --git a/dts/Bindings/display/cirrus,clps711x-fb.txt b/dts/Bindings/display/cirrus,clps711x-fb.txt index 0ab5f06636..84c75f8498 100644 --- a/dts/Bindings/display/cirrus,clps711x-fb.txt +++ b/dts/Bindings/display/cirrus,clps711x-fb.txt @@ -1,4 +1,4 @@ -* Currus Logic CLPS711X Framebuffer +* Cirrus Logic CLPS711X Framebuffer Required properties: - compatible: Shall contain "cirrus,ep7209-fb". diff --git a/dts/Bindings/display/connector/hdmi-connector.yaml b/dts/Bindings/display/connector/hdmi-connector.yaml index 83c0d00826..3ee8f92259 100644 --- a/dts/Bindings/display/connector/hdmi-connector.yaml +++ b/dts/Bindings/display/connector/hdmi-connector.yaml @@ -36,6 +36,9 @@ properties: description: GPIO signal to enable DDC bus maxItems: 1 + hdmi-pwr-supply: + description: Power supply for the HDMI +5V Power pin + port: $ref: /schemas/graph.yaml#/properties/port description: Connection to controller providing HDMI signals diff --git a/dts/Bindings/display/dp-aux-bus.yaml b/dts/Bindings/display/dp-aux-bus.yaml index 5e4afe9f98..0ece7b0179 100644 --- a/dts/Bindings/display/dp-aux-bus.yaml +++ b/dts/Bindings/display/dp-aux-bus.yaml @@ -26,7 +26,7 @@ description: properties: $nodename: - const: "aux-bus" + const: aux-bus panel: $ref: panel/panel-common.yaml# diff --git a/dts/Bindings/display/dsi-controller.yaml b/dts/Bindings/display/dsi-controller.yaml index ca21671f6b..67ce10307e 100644 --- a/dts/Bindings/display/dsi-controller.yaml +++ b/dts/Bindings/display/dsi-controller.yaml @@ -30,6 +30,15 @@ properties: $nodename: pattern: "^dsi(@.*)?$" + clock-master: + type: boolean + description: + Should be enabled if the host is being used in conjunction with + another DSI host to drive the same peripheral. Hardware supporting + such a configuration generally requires the data on both the busses + to be driven by the same clock. Only the DSI host instance + controlling this clock should contain this property. + "#address-cells": const: 1 @@ -52,15 +61,6 @@ patternProperties: case the reg property can take multiple entries, one for each virtual channel that the peripheral responds to. - clock-master: - type: boolean - description: - Should be enabled if the host is being used in conjunction with - another DSI host to drive the same peripheral. Hardware supporting - such a configuration generally requires the data on both the busses - to be driven by the same clock. Only the DSI host instance - controlling this clock should contain this property. - enforce-video-mode: type: boolean description: diff --git a/dts/Bindings/display/exynos/exynos_dp.txt b/dts/Bindings/display/exynos/exynos_dp.txt index 9b6cba3f82..3a40159032 100644 --- a/dts/Bindings/display/exynos/exynos_dp.txt +++ b/dts/Bindings/display/exynos/exynos_dp.txt @@ -50,7 +50,7 @@ Optional properties for dp-controller: Documentation/devicetree/bindings/display/panel/display-timing.txt For the below properties, please refer to Analogix DP binding document: - * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt + * Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml -phys (required) -phy-names (required) -hpd-gpios (optional) diff --git a/dts/Bindings/display/exynos/exynos_dsim.txt b/dts/Bindings/display/exynos/exynos_dsim.txt deleted file mode 100644 index be377786e8..0000000000 --- a/dts/Bindings/display/exynos/exynos_dsim.txt +++ /dev/null @@ -1,90 +0,0 @@ -Exynos MIPI DSI Master - -Required properties: - - compatible: value should be one of the following - "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */ - "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */ - "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */ - "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */ - "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */ - - reg: physical base address and length of the registers set for the device - - interrupts: should contain DSI interrupt - - clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names - - clock-names: should include "bus_clk"and "sclk_mipi" entries - the use of "pll_clk" is deprecated - - phys: list of phy specifiers, must contain an entry for each required - entry in phy-names - - phy-names: should include "dsim" entry - - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V) - - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) - - samsung,pll-clock-frequency: specifies frequency of the oscillator clock - - #address-cells, #size-cells: should be set respectively to <1> and <0> - according to DSI host bindings (see MIPI DSI bindings [1]) - - samsung,burst-clock-frequency: specifies DSI frequency in high-speed burst - mode - - samsung,esc-clock-frequency: specifies DSI frequency in escape mode - -Optional properties: - - power-domains: a phandle to DSIM power domain node - -Child nodes: - Should contain DSI peripheral nodes (see MIPI DSI bindings [1]). - -Video interfaces: - Device node can contain following video interface port nodes according to [2]: - 0: RGB input, - 1: DSI output - -[1]: Documentation/devicetree/bindings/display/mipi-dsi-bus.txt -[2]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - - dsi@11c80000 { - compatible = "samsung,exynos4210-mipi-dsi"; - reg = <0x11C80000 0x10000>; - interrupts = <0 79 0>; - clocks = <&clock 286>, <&clock 143>; - clock-names = "bus_clk", "sclk_mipi"; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - vddcore-supply = <&vusb_reg>; - vddio-supply = <&vmipi_reg>; - power-domains = <&pd_lcd0>; - #address-cells = <1>; - #size-cells = <0>; - samsung,pll-clock-frequency = <24000000>; - - panel@1 { - reg = <0>; - ... - port { - panel_ep: endpoint { - remote-endpoint = <&dsi_ep>; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - decon_to_mic: endpoint { - remote-endpoint = <&mic_to_decon>; - }; - }; - - port@1 { - reg = <1>; - dsi_ep: endpoint { - reg = <0>; - samsung,burst-clock-frequency = <500000000>; - samsung,esc-clock-frequency = <20000000>; - remote-endpoint = <&panel_ep>; - }; - }; - }; - }; diff --git a/dts/Bindings/display/fsl,lcdif.yaml b/dts/Bindings/display/fsl,lcdif.yaml index 900a56cae8..1c2be8d6f6 100644 --- a/dts/Bindings/display/fsl,lcdif.yaml +++ b/dts/Bindings/display/fsl,lcdif.yaml @@ -20,6 +20,8 @@ properties: - fsl,imx23-lcdif - fsl,imx28-lcdif - fsl,imx6sx-lcdif + - fsl,imx8mp-lcdif + - fsl,imx93-lcdif - items: - enum: - fsl,imx6sl-lcdif @@ -49,6 +51,12 @@ properties: minItems: 1 interrupts: + items: + - description: LCDIF DMA interrupt + - description: LCDIF Error interrupt + minItems: 1 + + power-domains: maxItems: 1 port: @@ -80,12 +88,67 @@ allOf: maxItems: 3 required: - clock-names - else: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mp-lcdif + - fsl,imx93-lcdif + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + minItems: 3 + maxItems: 3 + required: + - clock-names + - if: + not: + properties: + compatible: + contains: + enum: + - fsl,imx6sx-lcdif + - fsl,imx8mp-lcdif + - fsl,imx93-lcdif + then: properties: clocks: maxItems: 1 clock-names: maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6sl-lcdif + - fsl,imx6sx-lcdif + - fsl,imx8mm-lcdif + - fsl,imx8mn-lcdif + - fsl,imx8mp-lcdif + - fsl,imx93-lcdif + then: + required: + - power-domains + - if: + properties: + compatible: + contains: + enum: + - fsl,imx23-lcdif + then: + properties: + interrupts: + minItems: 2 + maxItems: 2 + else: + properties: + interrupts: + maxItems: 1 examples: - | @@ -100,6 +163,7 @@ examples: <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pix", "axi", "disp_axi"; + power-domains = <&pd_disp>; port { endpoint { diff --git a/dts/Bindings/display/ilitek,ili9341.txt b/dts/Bindings/display/ilitek,ili9341.txt deleted file mode 100644 index 169b32e4ee..0000000000 --- a/dts/Bindings/display/ilitek,ili9341.txt +++ /dev/null @@ -1,27 +0,0 @@ -Ilitek ILI9341 display panels - -This binding is for display panels using an Ilitek ILI9341 controller in SPI -mode. - -Required properties: -- compatible: "adafruit,yx240qv29", "ilitek,ili9341" -- dc-gpios: D/C pin -- reset-gpios: Reset pin - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in ../spi/spi-bus.txt must be specified. - -Optional properties: -- rotation: panel rotation in degrees counter clockwise (0,90,180,270) -- backlight: phandle of the backlight device attached to the panel - -Example: - display@0{ - compatible = "adafruit,yx240qv29", "ilitek,ili9341"; - reg = <0>; - spi-max-frequency = <32000000>; - dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - rotation = <270>; - backlight = <&backlight>; - }; diff --git a/dts/Bindings/display/ilitek,ili9486.yaml b/dts/Bindings/display/ilitek,ili9486.yaml index aecff34f50..9cc1fd0751 100644 --- a/dts/Bindings/display/ilitek,ili9486.yaml +++ b/dts/Bindings/display/ilitek,ili9486.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/ilitek,ili9486.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ilitek ILI9486 display panels device tree bindings +title: Ilitek ILI9486 display panels maintainers: - Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com> @@ -50,10 +50,6 @@ examples: - | #include <dt-bindings/gpio/gpio.h> - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; - }; spi { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/display/imx/fsl,imx-fb.txt b/dts/Bindings/display/imx/fsl,imx-fb.txt deleted file mode 100644 index f4df9e83bc..0000000000 --- a/dts/Bindings/display/imx/fsl,imx-fb.txt +++ /dev/null @@ -1,57 +0,0 @@ -Freescale imx21 Framebuffer - -This framebuffer driver supports devices imx1, imx21, imx25, and imx27. - -Required properties: -- compatible : "fsl,<chip>-fb", chip should be imx1 or imx21 -- reg : Should contain 1 register ranges(address and length) -- interrupts : One interrupt of the fb dev - -Required nodes: -- display: Phandle to a display node as described in - Documentation/devicetree/bindings/display/panel/display-timing.txt - Additional, the display node has to define properties: - - bits-per-pixel: Bits per pixel - - fsl,pcr: LCDC PCR value - A display node may optionally define - - fsl,aus-mode: boolean to enable AUS mode (only for imx21) - -Optional properties: -- lcd-supply: Regulator for LCD supply voltage. -- fsl,dmacr: DMA Control Register value. This is optional. By default, the - register is not modified as recommended by the datasheet. -- fsl,lpccr: Contrast Control Register value. This property provides the - default value for the contrast control register. - If that property is omitted, the register is zeroed. -- fsl,lscr1: LCDC Sharp Configuration Register value. - -Example: - - imxfb: fb@10021000 { - compatible = "fsl,imx21-fb"; - interrupts = <61>; - reg = <0x10021000 0x1000>; - display = <&display0>; - }; - - ... - - display0: display0 { - model = "Primeview-PD050VL1"; - bits-per-pixel = <16>; - fsl,pcr = <0xf0c88080>; /* non-standard but required */ - display-timings { - native-mode = <&timing_disp0>; - timing_disp0: 640x480 { - hactive = <640>; - vactive = <480>; - hback-porch = <112>; - hfront-porch = <36>; - hsync-len = <32>; - vback-porch = <33>; - vfront-porch = <33>; - vsync-len = <2>; - clock-frequency = <25000000>; - }; - }; - }; diff --git a/dts/Bindings/display/imx/fsl,imx-lcdc.yaml b/dts/Bindings/display/imx/fsl,imx-lcdc.yaml new file mode 100644 index 0000000000..c2b29622bc --- /dev/null +++ b/dts/Bindings/display/imx/fsl,imx-lcdc.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX LCD Controller, found on i.MX1, i.MX21, i.MX25 and i.MX27 + +maintainers: + - Sascha Hauer <s.hauer@pengutronix.de> + - Pengutronix Kernel Team <kernel@pengutronix.de> + +properties: + compatible: + oneOf: + - enum: + - fsl,imx1-fb + - fsl,imx21-fb + - items: + - enum: + - fsl,imx25-fb + - fsl,imx27-fb + - const: fsl,imx21-fb + - items: + - const: fsl,imx25-lcdc + - const: fsl,imx21-lcdc + + clocks: + maxItems: 3 + + clock-names: + items: + - const: ipg + - const: ahb + - const: per + + port: + $ref: /schemas/graph.yaml#/properties/port + + display: + $ref: /schemas/types.yaml#/definitions/phandle + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + lcd-supply: + description: + Regulator for LCD supply voltage. + + fsl,dmacr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Override value for DMA Control Register + + fsl,lpccr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Contrast Control Register value. + + fsl,lscr1: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + LCDC Sharp Configuration Register value. + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx1-lcdc + - fsl,imx21-lcdc + then: + properties: + display: false + fsl,dmacr: false + fsl,lpccr: false + fsl,lscr1: false + + required: + - port + + else: + properties: + port: false + + required: + - display + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +additionalProperties: false + +examples: + - | + lcdc@53fbc000 { + compatible = "fsl,imx25-lcdc", "fsl,imx21-lcdc"; + reg = <0x53fbc000 0x4000>; + interrupts = <39>; + clocks = <&clks 103>, <&clks 66>, <&clks 49>; + clock-names = "ipg", "ahb", "per"; + + port { + parallel_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + - | + imxfb: fb@10021000 { + compatible = "fsl,imx21-fb"; + interrupts = <61>; + reg = <0x10021000 0x1000>; + display = <&display0>; + clocks = <&clks 103>, <&clks 49>, <&clks 66>; + clock-names = "ipg", "ahb", "per"; + }; + + display0: display0 { + model = "Primeview-PD050VL1"; + bits-per-pixel = <16>; + fsl,pcr = <0xf0c88080>; /* non-standard but required */ + + display-timings { + native-mode = <&timing_disp0>; + timing_disp0: timing0 { + hactive = <640>; + vactive = <480>; + hback-porch = <112>; + hfront-porch = <36>; + hsync-len = <32>; + vback-porch = <33>; + vfront-porch = <33>; + vsync-len = <2>; + clock-frequency = <25000000>; + }; + }; + }; diff --git a/dts/Bindings/display/imx/fsl,imx6-hdmi.yaml b/dts/Bindings/display/imx/fsl,imx6-hdmi.yaml index af7fe9c4d1..7979cf07f1 100644 --- a/dts/Bindings/display/imx/fsl,imx6-hdmi.yaml +++ b/dts/Bindings/display/imx/fsl,imx6-hdmi.yaml @@ -87,7 +87,7 @@ required: - interrupts - ports -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/display/imx/nxp,imx8mq-dcss.yaml b/dts/Bindings/display/imx/nxp,imx8mq-dcss.yaml index 989ab312c1..4ae6328cde 100644 --- a/dts/Bindings/display/imx/nxp,imx8mq-dcss.yaml +++ b/dts/Bindings/display/imx/nxp,imx8mq-dcss.yaml @@ -2,8 +2,8 @@ # Copyright 2019 NXP %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: iMX8MQ Display Controller Subsystem (DCSS) diff --git a/dts/Bindings/display/ingenic,ipu.yaml b/dts/Bindings/display/ingenic,ipu.yaml index 3f93def2c5..319bd7c88f 100644 --- a/dts/Bindings/display/ingenic,ipu.yaml +++ b/dts/Bindings/display/ingenic,ipu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/ingenic,ipu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ingenic SoCs Image Processing Unit (IPU) devicetree bindings +title: Ingenic SoCs Image Processing Unit (IPU) maintainers: - Paul Cercueil <paul@crapouillou.net> diff --git a/dts/Bindings/display/ingenic,lcd.yaml b/dts/Bindings/display/ingenic,lcd.yaml index 0049010b37..6d4c00f3fc 100644 --- a/dts/Bindings/display/ingenic,lcd.yaml +++ b/dts/Bindings/display/ingenic,lcd.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/ingenic,lcd.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ingenic SoCs LCD controller devicetree bindings +title: Ingenic SoCs LCD controller maintainers: - Paul Cercueil <paul@crapouillou.net> @@ -17,6 +17,8 @@ properties: enum: - ingenic,jz4740-lcd - ingenic,jz4725b-lcd + - ingenic,jz4760-lcd + - ingenic,jz4760b-lcd - ingenic,jz4770-lcd - ingenic,jz4780-lcd diff --git a/dts/Bindings/display/intel,keembay-display.yaml b/dts/Bindings/display/intel,keembay-display.yaml index bc6622b010..2cf54ecc70 100644 --- a/dts/Bindings/display/intel,keembay-display.yaml +++ b/dts/Bindings/display/intel,keembay-display.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/intel,keembay-display.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Devicetree bindings for Intel Keem Bay display controller +title: Intel Keem Bay display controller maintainers: - Anitha Chrisanthus <anitha.chrisanthus@intel.com> diff --git a/dts/Bindings/display/intel,keembay-msscam.yaml b/dts/Bindings/display/intel,keembay-msscam.yaml index a222b52d8b..cc7e1f318f 100644 --- a/dts/Bindings/display/intel,keembay-msscam.yaml +++ b/dts/Bindings/display/intel,keembay-msscam.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/intel,keembay-msscam.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Devicetree bindings for Intel Keem Bay MSSCAM +title: Intel Keem Bay MSSCAM maintainers: - Anitha Chrisanthus <anitha.chrisanthus@intel.com> diff --git a/dts/Bindings/display/lvds-data-mapping.yaml b/dts/Bindings/display/lvds-data-mapping.yaml new file mode 100644 index 0000000000..d68982fe2e --- /dev/null +++ b/dts/Bindings/display/lvds-data-mapping.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/lvds-data-mapping.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LVDS Data Mapping + +maintainers: + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> + - Thierry Reding <thierry.reding@gmail.com> + +description: | + LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple + incompatible data link layers have been used over time to transmit image data + to LVDS devices. This bindings supports devices compatible with the following + specifications. + + [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February + 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) + [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National + Semiconductor + [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video + Electronics Standards Association (VESA) + + Device compatible with those specifications have been marketed under the + FPD-Link and FlatLink brands. + +properties: + data-mapping: + enum: + - jeida-18 + - jeida-24 + - vesa-24 + description: | + The color signals mapping order. + + LVDS data mappings are defined as follows. + + - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and + [VESA] specifications. Data are transferred as follows on 3 LVDS lanes. + + Slot 0 1 2 3 4 5 6 + ________________ _________________ + Clock \_______________________/ + ______ ______ ______ ______ ______ ______ ______ + DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< + DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< + DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< + + - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI] + specifications. Data are transferred as follows on 4 LVDS lanes. + + Slot 0 1 2 3 4 5 6 + ________________ _________________ + Clock \_______________________/ + ______ ______ ______ ______ ______ ______ ______ + DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< + DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< + DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< + DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< + + - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification. + Data are transferred as follows on 4 LVDS lanes. + + Slot 0 1 2 3 4 5 6 + ________________ _________________ + Clock \_______________________/ + ______ ______ ______ ______ ______ ______ ______ + DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< + DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< + DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< + DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< + + Control signals are mapped as follows. + + CTL0: HSync + CTL1: VSync + CTL2: Data Enable + CTL3: 0 + +additionalProperties: true + +... diff --git a/dts/Bindings/display/lvds.yaml b/dts/Bindings/display/lvds.yaml index 7cd2ce7e9c..224db49320 100644 --- a/dts/Bindings/display/lvds.yaml +++ b/dts/Bindings/display/lvds.yaml @@ -6,83 +6,24 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: LVDS Display Common Properties +allOf: + - $ref: lvds-data-mapping.yaml# + maintainers: - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> - Thierry Reding <thierry.reding@gmail.com> -description: |+ - LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple - incompatible data link layers have been used over time to transmit image data - to LVDS devices. This bindings supports devices compatible with the following - specifications. - - [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February - 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) - [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National - Semiconductor - [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video - Electronics Standards Association (VESA) - - Device compatible with those specifications have been marketed under the - FPD-Link and FlatLink brands. +description: + This binding extends the data mapping defined in lvds-data-mapping.yaml. + It supports reversing the bit order on the formats defined there in order + to accomodate for even more specialized data formats, since a variety of + data formats and layouts is used to drive LVDS displays. properties: - data-mapping: - enum: - - jeida-18 - - jeida-24 - - vesa-24 - description: | - The color signals mapping order. - - LVDS data mappings are defined as follows. - - - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and - [VESA] specifications. Data are transferred as follows on 3 LVDS lanes. - - Slot 0 1 2 3 4 5 6 - ________________ _________________ - Clock \_______________________/ - ______ ______ ______ ______ ______ ______ ______ - DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< - DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< - DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< - - - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI] - specifications. Data are transferred as follows on 4 LVDS lanes. - - Slot 0 1 2 3 4 5 6 - ________________ _________________ - Clock \_______________________/ - ______ ______ ______ ______ ______ ______ ______ - DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< - DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< - DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< - DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< - - - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification. - Data are transferred as follows on 4 LVDS lanes. - - Slot 0 1 2 3 4 5 6 - ________________ _________________ - Clock \_______________________/ - ______ ______ ______ ______ ______ ______ ______ - DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< - DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< - DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< - DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< - - Control signals are mapped as follows. - - CTL0: HSync - CTL1: VSync - CTL2: Data Enable - CTL3: 0 - data-mirror: type: boolean description: - If set, reverse the bit order described in the data mappings below on all + If set, reverse the bit order described in the data mappings on all data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6. additionalProperties: true diff --git a/dts/Bindings/display/mediatek/mediatek,aal.yaml b/dts/Bindings/display/mediatek/mediatek,aal.yaml index d4d585485e..b4c28e96dd 100644 --- a/dts/Bindings/display/mediatek/mediatek,aal.yaml +++ b/dts/Bindings/display/mediatek/mediatek,aal.yaml @@ -24,13 +24,16 @@ properties: - enum: - mediatek,mt8173-disp-aal - mediatek,mt8183-disp-aal + - mediatek,mt8195-mdp3-aal - items: - enum: - mediatek,mt2712-disp-aal + - mediatek,mt6795-disp-aal - const: mediatek,mt8173-disp-aal - items: - enum: - mediatek,mt8186-disp-aal + - mediatek,mt8188-disp-aal - mediatek,mt8192-disp-aal - mediatek,mt8195-disp-aal - const: mediatek,mt8183-disp-aal diff --git a/dts/Bindings/display/mediatek/mediatek,ccorr.yaml b/dts/Bindings/display/mediatek/mediatek,ccorr.yaml index 63fb02014a..8c2a737237 100644 --- a/dts/Bindings/display/mediatek/mediatek,ccorr.yaml +++ b/dts/Bindings/display/mediatek/mediatek,ccorr.yaml @@ -21,18 +21,15 @@ description: | properties: compatible: oneOf: - - items: - - const: mediatek,mt8183-disp-ccorr - - items: - - const: mediatek,mt8192-disp-ccorr + - enum: + - mediatek,mt8183-disp-ccorr + - mediatek,mt8192-disp-ccorr - items: - enum: + - mediatek,mt8186-disp-ccorr + - mediatek,mt8188-disp-ccorr - mediatek,mt8195-disp-ccorr - const: mediatek,mt8192-disp-ccorr - - items: - - enum: - - mediatek,mt8186-disp-ccorr - - const: mediatek,mt8183-disp-ccorr reg: maxItems: 1 diff --git a/dts/Bindings/display/mediatek/mediatek,cec.yaml b/dts/Bindings/display/mediatek/mediatek,cec.yaml index 66288b9f0a..080cf32120 100644 --- a/dts/Bindings/display/mediatek/mediatek,cec.yaml +++ b/dts/Bindings/display/mediatek/mediatek,cec.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/mediatek/mediatek,cec.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek HDMI CEC Controller Device Tree Bindings +title: Mediatek HDMI CEC Controller maintainers: - CK Hu <ck.hu@mediatek.com> diff --git a/dts/Bindings/display/mediatek/mediatek,color.yaml b/dts/Bindings/display/mediatek/mediatek,color.yaml index d2f89ee799..b886ca0d89 100644 --- a/dts/Bindings/display/mediatek/mediatek,color.yaml +++ b/dts/Bindings/display/mediatek/mediatek,color.yaml @@ -22,12 +22,11 @@ description: | properties: compatible: oneOf: - - items: - - const: mediatek,mt2701-disp-color - - items: - - const: mediatek,mt8167-disp-color - - items: - - const: mediatek,mt8173-disp-color + - enum: + - mediatek,mt2701-disp-color + - mediatek,mt8167-disp-color + - mediatek,mt8173-disp-color + - mediatek,mt8195-mdp3-color - items: - enum: - mediatek,mt7623-disp-color @@ -35,8 +34,10 @@ properties: - const: mediatek,mt2701-disp-color - items: - enum: + - mediatek,mt6795-disp-color - mediatek,mt8183-disp-color - mediatek,mt8186-disp-color + - mediatek,mt8188-disp-color - mediatek,mt8192-disp-color - mediatek,mt8195-disp-color - const: mediatek,mt8173-disp-color diff --git a/dts/Bindings/display/mediatek/mediatek,dither.yaml b/dts/Bindings/display/mediatek/mediatek,dither.yaml index 8ad8187c02..1588b3f7ce 100644 --- a/dts/Bindings/display/mediatek/mediatek,dither.yaml +++ b/dts/Bindings/display/mediatek/mediatek,dither.yaml @@ -22,11 +22,12 @@ description: | properties: compatible: oneOf: - - items: - - const: mediatek,mt8183-disp-dither + - enum: + - mediatek,mt8183-disp-dither - items: - enum: - mediatek,mt8186-disp-dither + - mediatek,mt8188-disp-dither - mediatek,mt8192-disp-dither - mediatek,mt8195-disp-dither - const: mediatek,mt8183-disp-dither diff --git a/dts/Bindings/display/mediatek/mediatek,dp.yaml b/dts/Bindings/display/mediatek/mediatek,dp.yaml new file mode 100644 index 0000000000..2aef1eb32e --- /dev/null +++ b/dts/Bindings/display/mediatek/mediatek,dp.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Display Port Controller + +maintainers: + - Chun-Kuang Hu <chunkuang.hu@kernel.org> + - Jitao shi <jitao.shi@mediatek.com> + +description: | + MediaTek DP and eDP are different hardwares and there are some features + which are not supported for eDP. For example, audio is not supported for + eDP. Therefore, we need to use two different compatibles to describe them. + In addition, We just need to enable the power domain of DP, so the clock + of DP is generated by itself and we are not using other PLL to generate + clocks. + +properties: + compatible: + enum: + - mediatek,mt8188-dp-tx + - mediatek,mt8188-edp-tx + - mediatek,mt8195-dp-tx + - mediatek,mt8195-edp-tx + + reg: + maxItems: 1 + + nvmem-cells: + maxItems: 1 + description: efuse data for display port calibration + + nvmem-cell-names: + const: dp_calibration_data + + power-domains: + maxItems: 1 + + interrupts: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input endpoint of the controller, usually dp_intf + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Output endpoint of the controller + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + properties: + data-lanes: + description: | + number of lanes supported by the hardware. + The possible values: + 0 - For 1 lane enabled in IP. + 0 1 - For 2 lanes enabled in IP. + 0 1 2 3 - For 4 lanes enabled in IP. + minItems: 1 + maxItems: 4 + required: + - data-lanes + + required: + - port@0 + - port@1 + + max-linkrate-mhz: + enum: [ 1620, 2700, 5400, 8100 ] + description: maximum link rate supported by the hardware. + +required: + - compatible + - reg + - interrupts + - ports + - max-linkrate-mhz + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/mt8195-power.h> + dptx@1c600000 { + compatible = "mediatek,mt8195-dp-tx"; + reg = <0x1c600000 0x8000>; + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; + max-linkrate-mhz = <8100>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dptx_in: endpoint { + remote-endpoint = <&dp_intf0_out>; + }; + }; + port@1 { + reg = <1>; + dptx_out: endpoint { + data-lanes = <0 1 2 3>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/mediatek/mediatek,dpi.yaml b/dts/Bindings/display/mediatek/mediatek,dpi.yaml index 77ee1b9239..803c00f262 100644 --- a/dts/Bindings/display/mediatek/mediatek,dpi.yaml +++ b/dts/Bindings/display/mediatek/mediatek,dpi.yaml @@ -4,26 +4,33 @@ $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: mediatek DPI Controller Device Tree Bindings +title: MediaTek DPI and DP_INTF Controller maintainers: - CK Hu <ck.hu@mediatek.com> - Jitao shi <jitao.shi@mediatek.com> description: | - The Mediatek DPI function block is a sink of the display subsystem and - provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel - output bus. + The MediaTek DPI and DP_INTF function blocks are a sink of the display + subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a + parallel output bus. properties: compatible: - enum: - - mediatek,mt2701-dpi - - mediatek,mt7623-dpi - - mediatek,mt8173-dpi - - mediatek,mt8183-dpi - - mediatek,mt8186-dpi - - mediatek,mt8192-dpi + oneOf: + - enum: + - mediatek,mt2701-dpi + - mediatek,mt7623-dpi + - mediatek,mt8173-dpi + - mediatek,mt8183-dpi + - mediatek,mt8186-dpi + - mediatek,mt8188-dp-intf + - mediatek,mt8192-dpi + - mediatek,mt8195-dp-intf + - items: + - enum: + - mediatek,mt6795-dpi + - const: mediatek,mt8183-dpi reg: maxItems: 1 @@ -55,7 +62,7 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: Output port node. This port should be connected to the input port of an - attached HDMI or LVDS encoder chip. + attached HDMI, LVDS or DisplayPort encoder chip. required: - compatible diff --git a/dts/Bindings/display/mediatek/mediatek,dsc.yaml b/dts/Bindings/display/mediatek/mediatek,dsc.yaml index 4924886451..2cbdd9ee44 100644 --- a/dts/Bindings/display/mediatek/mediatek,dsc.yaml +++ b/dts/Bindings/display/mediatek/mediatek,dsc.yaml @@ -20,8 +20,8 @@ description: | properties: compatible: oneOf: - - items: - - const: mediatek,mt8195-disp-dsc + - enum: + - mediatek,mt8195-disp-dsc reg: maxItems: 1 diff --git a/dts/Bindings/display/mediatek/mediatek,dsi.txt b/dts/Bindings/display/mediatek/mediatek,dsi.txt deleted file mode 100644 index 36b01458f4..0000000000 --- a/dts/Bindings/display/mediatek/mediatek,dsi.txt +++ /dev/null @@ -1,62 +0,0 @@ -Mediatek DSI Device -=================== - -The Mediatek DSI function block is a sink of the display subsystem and can -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- -channel output. - -Required properties: -- compatible: "mediatek,<chip>-dsi" -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: must contain "engine", "digital", and "hs" -- phys: phandle link to the MIPI D-PHY controller. -- phy-names: must contain "dphy" -- port: Output port node with endpoint definitions as described in - Documentation/devicetree/bindings/graph.txt. This port should be connected - to the input port of an attached DSI panel or DSI-to-eDP encoder chip. - -Optional properties: -- resets: list of phandle + reset specifier pair, as described in [1]. - -[1] Documentation/devicetree/bindings/reset/reset.txt - -MIPI TX Configuration Module -============================ - -See phy/mediatek,dsi-phy.yaml - -Example: - -mipi_tx0: mipi-dphy@10215000 { - compatible = "mediatek,mt8173-mipi-tx"; - reg = <0 0x10215000 0 0x1000>; - clocks = <&clk26m>; - clock-output-names = "mipi_tx0_pll"; - #clock-cells = <0>; - #phy-cells = <0>; - drive-strength-microamp = <4600>; - nvmem-cells= <&mipi_tx_calibration>; - nvmem-cell-names = "calibration-data"; -}; - -dsi0: dsi@1401b000 { - compatible = "mediatek,mt8173-dsi"; - reg = <0 0x1401b000 0 0x1000>; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, - <&mipi_tx0>; - clock-names = "engine", "digital", "hs"; - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; - phys = <&mipi_tx0>; - phy-names = "dphy"; - - port { - dsi0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; diff --git a/dts/Bindings/display/mediatek/mediatek,dsi.yaml b/dts/Bindings/display/mediatek/mediatek,dsi.yaml new file mode 100644 index 0000000000..8611319bed --- /dev/null +++ b/dts/Bindings/display/mediatek/mediatek,dsi.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek DSI Controller + +maintainers: + - Chun-Kuang Hu <chunkuang.hu@kernel.org> + - Philipp Zabel <p.zabel@pengutronix.de> + - Jitao Shi <jitao.shi@mediatek.com> + +description: | + The MediaTek DSI function block is a sink of the display subsystem and can + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- + channel output. + +allOf: + - $ref: /schemas/display/dsi-controller.yaml# + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2701-dsi + - mediatek,mt7623-dsi + - mediatek,mt8167-dsi + - mediatek,mt8173-dsi + - mediatek,mt8183-dsi + - mediatek,mt8186-dsi + - mediatek,mt8188-dsi + - items: + - enum: + - mediatek,mt6795-dsi + - const: mediatek,mt8173-dsi + - items: + - enum: + - mediatek,mt8195-dsi + - const: mediatek,mt8183-dsi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Engine Clock + - description: Digital Clock + - description: HS Clock + + clock-names: + items: + - const: engine + - const: digital + - const: hs + + resets: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + items: + - const: dphy + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port node. This port should be connected to the input + port of an attached DSI panel or DSI-to-eDP encoder chip. + +required: + - compatible + - reg + - interrupts + - power-domains + - clocks + - clock-names + - phys + - phy-names + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8183-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/mt8183-power.h> + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/reset/mt8183-resets.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + dsi0: dsi@14014000 { + compatible = "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DSI0_MM>, + <&mmsys CLK_MM_DSI0_IF>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; + phys = <&mipi_tx0>; + phy-names = "dphy"; + port { + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/mediatek/mediatek,ethdr.yaml b/dts/Bindings/display/mediatek/mediatek,ethdr.yaml new file mode 100644 index 0000000000..677882348e --- /dev/null +++ b/dts/Bindings/display/mediatek/mediatek,ethdr.yaml @@ -0,0 +1,186 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Ethdr Device + +maintainers: + - Chun-Kuang Hu <chunkuang.hu@kernel.org> + - Philipp Zabel <p.zabel@pengutronix.de> + +description: + ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine and is + designed for HDR video and graphics conversion in the external display path. + It handles multiple HDR input types and performs tone mapping, color + space/color format conversion, and then combine different layers, + output the required HDR or SDR signal to the subsequent display path. + This engine is composed of two video frontends, two graphic frontends, + one video backend and a mixer. ETHDR has two DMA function blocks, DS and ADL. + These two function blocks read the pre-programmed registers from DRAM and + set them to HW in the v-blanking period. + +properties: + compatible: + oneOf: + - const: mediatek,mt8195-disp-ethdr + - items: + - const: mediatek,mt8188-disp-ethdr + - const: mediatek,mt8195-disp-ethdr + + reg: + maxItems: 7 + + reg-names: + items: + - const: mixer + - const: vdo_fe0 + - const: vdo_fe1 + - const: gfx_fe0 + - const: gfx_fe1 + - const: vdo_be + - const: adl_ds + + interrupts: + maxItems: 1 + + iommus: + minItems: 1 + maxItems: 2 + + clocks: + items: + - description: mixer clock + - description: video frontend 0 clock + - description: video frontend 1 clock + - description: graphic frontend 0 clock + - description: graphic frontend 1 clock + - description: video backend clock + - description: autodownload and menuload clock + - description: video frontend 0 async clock + - description: video frontend 1 async clock + - description: graphic frontend 0 async clock + - description: graphic frontend 1 async clock + - description: video backend async clock + - description: ethdr top clock + + clock-names: + items: + - const: mixer + - const: vdo_fe0 + - const: vdo_fe1 + - const: gfx_fe0 + - const: gfx_fe1 + - const: vdo_be + - const: adl_ds + - const: vdo_fe0_async + - const: vdo_fe1_async + - const: gfx_fe0_async + - const: gfx_fe1_async + - const: vdo_be_async + - const: ethdr_top + + power-domains: + maxItems: 1 + + resets: + items: + - description: video frontend 0 async reset + - description: video frontend 1 async reset + - description: graphic frontend 0 async reset + - description: graphic frontend 1 async reset + - description: video backend async reset + + reset-names: + items: + - const: vdo_fe0_async + - const: vdo_fe1_async + - const: gfx_fe0_async + - const: gfx_fe1_async + - const: vdo_be_async + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 7 + description: The register of display function block to be set by gce. + There are 4 arguments in this property, gce node, subsys id, offset and + register size. The subsys id is defined in the gce header of each chips + include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display + function block. + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - power-domains + - resets + - mediatek,gce-client-reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/gce/mt8195-gce.h> + #include <dt-bindings/memory/mt8195-memory-port.h> + #include <dt-bindings/power/mt8195-power.h> + #include <dt-bindings/reset/mt8195-resets.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + hdr-engine@1c114000 { + compatible = "mediatek,mt8195-disp-ethdr"; + reg = <0 0x1c114000 0 0x1000>, + <0 0x1c115000 0 0x1000>, + <0 0x1c117000 0 0x1000>, + <0 0x1c119000 0 0x1000>, + <0 0x1c11a000 0 0x1000>, + <0 0x1c11b000 0 0x1000>, + <0 0x1c11c000 0 0x1000>; + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds"; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, + <&vdosys1 CLK_VDO1_26M_SLOW>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, + <&topckgen CLK_TOP_ETHDR>; + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", + "ethdr_top"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, + <&iommu_vpp M4U_PORT_L3_HDR_ADL>; + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; + reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", + "gfx_fe1_async", "vdo_be_async"; + }; + }; +... diff --git a/dts/Bindings/display/mediatek/mediatek,gamma.yaml b/dts/Bindings/display/mediatek/mediatek,gamma.yaml index a89ea0ea75..c6641acd75 100644 --- a/dts/Bindings/display/mediatek/mediatek,gamma.yaml +++ b/dts/Bindings/display/mediatek/mediatek,gamma.yaml @@ -21,13 +21,17 @@ description: | properties: compatible: oneOf: + - enum: + - mediatek,mt8173-disp-gamma + - mediatek,mt8183-disp-gamma - items: + - enum: + - mediatek,mt6795-disp-gamma - const: mediatek,mt8173-disp-gamma - items: - - const: mediatek,mt8183-disp-gamma - - items: - enum: - mediatek,mt8186-disp-gamma + - mediatek,mt8188-disp-gamma - mediatek,mt8192-disp-gamma - mediatek,mt8195-disp-gamma - const: mediatek,mt8183-disp-gamma diff --git a/dts/Bindings/display/mediatek/mediatek,hdmi-ddc.yaml b/dts/Bindings/display/mediatek/mediatek,hdmi-ddc.yaml index b6fcdfb99a..bd8f7b8ae0 100644 --- a/dts/Bindings/display/mediatek/mediatek,hdmi-ddc.yaml +++ b/dts/Bindings/display/mediatek/mediatek,hdmi-ddc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek HDMI DDC Device Tree Bindings +title: Mediatek HDMI DDC maintainers: - CK Hu <ck.hu@mediatek.com> diff --git a/dts/Bindings/display/mediatek/mediatek,hdmi.yaml b/dts/Bindings/display/mediatek/mediatek,hdmi.yaml index bdaf0b51e6..b90b6d18a8 100644 --- a/dts/Bindings/display/mediatek/mediatek,hdmi.yaml +++ b/dts/Bindings/display/mediatek/mediatek,hdmi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek HDMI Encoder Device Tree Bindings +title: Mediatek HDMI Encoder maintainers: - CK Hu <ck.hu@mediatek.com> @@ -50,7 +50,7 @@ properties: - const: hdmi mediatek,syscon-hdmi: - $ref: '/schemas/types.yaml#/definitions/phandle-array' + $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: - description: phandle to system configuration registers diff --git a/dts/Bindings/display/mediatek/mediatek,merge.yaml b/dts/Bindings/display/mediatek/mediatek,merge.yaml index 69ba75777d..dae8392799 100644 --- a/dts/Bindings/display/mediatek/mediatek,merge.yaml +++ b/dts/Bindings/display/mediatek/mediatek,merge.yaml @@ -21,9 +21,15 @@ description: | properties: compatible: oneOf: + - enum: + - mediatek,mt8173-disp-merge + - mediatek,mt8195-disp-merge + - mediatek,mt8195-mdp3-merge - items: + - const: mediatek,mt6795-disp-merge - const: mediatek,mt8173-disp-merge - items: + - const: mediatek,mt8188-disp-merge - const: mediatek,mt8195-disp-merge reg: diff --git a/dts/Bindings/display/mediatek/mediatek,mutex.yaml b/dts/Bindings/display/mediatek/mediatek,mutex.yaml deleted file mode 100644 index 3fdad71210..0000000000 --- a/dts/Bindings/display/mediatek/mediatek,mutex.yaml +++ /dev/null @@ -1,87 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Mediatek mutex - -maintainers: - - Chun-Kuang Hu <chunkuang.hu@kernel.org> - - Philipp Zabel <p.zabel@pengutronix.de> - -description: | - Mediatek mutex, namely MUTEX, is used to send the triggers signals called - Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display - data path or MDP data path. - In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects - the shadow register. - MUTEX device node must be siblings to the central MMSYS_CONFIG node. - For a description of the MMSYS_CONFIG binding, see - Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml - for details. - -properties: - compatible: - enum: - - mediatek,mt2701-disp-mutex - - mediatek,mt2712-disp-mutex - - mediatek,mt8167-disp-mutex - - mediatek,mt8173-disp-mutex - - mediatek,mt8183-disp-mutex - - mediatek,mt8186-disp-mutex - - mediatek,mt8192-disp-mutex - - mediatek,mt8195-disp-mutex - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - - power-domains: - description: A phandle and PM domain specifier as defined by bindings of - the power controller specified by phandle. See - Documentation/devicetree/bindings/power/power-domain.yaml for details. - - clocks: - items: - - description: MUTEX Clock - - mediatek,gce-events: - description: - The event id which is mapping to the specific hardware event signal - to gce. The event id is defined in the gce header - include/dt-bindings/gce/<chip>-gce.h of each chips. - $ref: /schemas/types.yaml#/definitions/uint32-array - -required: - - compatible - - reg - - interrupts - - power-domains - - clocks - -additionalProperties: false - -examples: - - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/clock/mt8173-clk.h> - #include <dt-bindings/power/mt8173-power.h> - #include <dt-bindings/gce/mt8173-gce.h> - - soc { - #address-cells = <2>; - #size-cells = <2>; - - mutex: mutex@14020000 { - compatible = "mediatek,mt8173-disp-mutex"; - reg = <0 0x14020000 0 0x1000>; - interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; - power-domains = <&spm MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_MUTEX_32K>; - mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, - <CMDQ_EVENT_MUTEX1_STREAM_EOF>; - }; - }; diff --git a/dts/Bindings/display/mediatek/mediatek,od.yaml b/dts/Bindings/display/mediatek/mediatek,od.yaml index 853fcb9db2..831c653caf 100644 --- a/dts/Bindings/display/mediatek/mediatek,od.yaml +++ b/dts/Bindings/display/mediatek/mediatek,od.yaml @@ -21,9 +21,11 @@ description: | properties: compatible: oneOf: + - enum: + - mediatek,mt2712-disp-od + - mediatek,mt8173-disp-od - items: - - const: mediatek,mt2712-disp-od - - items: + - const: mediatek,mt6795-disp-od - const: mediatek,mt8173-disp-od reg: diff --git a/dts/Bindings/display/mediatek/mediatek,ovl-2l.yaml b/dts/Bindings/display/mediatek/mediatek,ovl-2l.yaml index 4e94f4e947..c7dd0ef02d 100644 --- a/dts/Bindings/display/mediatek/mediatek,ovl-2l.yaml +++ b/dts/Bindings/display/mediatek/mediatek,ovl-2l.yaml @@ -21,10 +21,9 @@ description: | properties: compatible: oneOf: - - items: - - const: mediatek,mt8183-disp-ovl-2l - - items: - - const: mediatek,mt8192-disp-ovl-2l + - enum: + - mediatek,mt8183-disp-ovl-2l + - mediatek,mt8192-disp-ovl-2l - items: - enum: - mediatek,mt8186-disp-ovl-2l diff --git a/dts/Bindings/display/mediatek/mediatek,ovl.yaml b/dts/Bindings/display/mediatek/mediatek,ovl.yaml index a2a27d0ca0..c471a181d1 100644 --- a/dts/Bindings/display/mediatek/mediatek,ovl.yaml +++ b/dts/Bindings/display/mediatek/mediatek,ovl.yaml @@ -21,14 +21,12 @@ description: | properties: compatible: oneOf: - - items: - - const: mediatek,mt2701-disp-ovl - - items: - - const: mediatek,mt8173-disp-ovl - - items: - - const: mediatek,mt8183-disp-ovl - - items: - - const: mediatek,mt8192-disp-ovl + - enum: + - mediatek,mt2701-disp-ovl + - mediatek,mt8173-disp-ovl + - mediatek,mt8183-disp-ovl + - mediatek,mt8192-disp-ovl + - mediatek,mt8195-mdp3-ovl - items: - enum: - mediatek,mt7623-disp-ovl @@ -36,6 +34,11 @@ properties: - const: mediatek,mt2701-disp-ovl - items: - enum: + - mediatek,mt6795-disp-ovl + - const: mediatek,mt8173-disp-ovl + - items: + - enum: + - mediatek,mt8188-disp-ovl - mediatek,mt8195-disp-ovl - const: mediatek,mt8183-disp-ovl - items: diff --git a/dts/Bindings/display/mediatek/mediatek,padding.yaml b/dts/Bindings/display/mediatek/mediatek,padding.yaml new file mode 100644 index 0000000000..be07bbdc54 --- /dev/null +++ b/dts/Bindings/display/mediatek/mediatek,padding.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Display Padding + +maintainers: + - Chun-Kuang Hu <chunkuang.hu@kernel.org> + - Philipp Zabel <p.zabel@pengutronix.de> + +description: + Padding provides ability to add pixels to width and height of a layer with + specified colors. Due to hardware design, Mixer in VDOSYS1 requires + width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled, + we need Padding to deal with odd width. + Please notice that even if the Padding is in bypass mode, settings in + register must be cleared to 0, or undefined behaviors could happen. + +properties: + compatible: + enum: + - mediatek,mt8188-disp-padding + - mediatek,mt8195-mdp3-padding + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Padding's clocks + + mediatek,gce-client-reg: + description: + GCE (Global Command Engine) is a multi-core micro processor that helps + its clients to execute commands without interrupting CPU. This property + describes GCE client's information that is composed by 4 fields. + 1. Phandle of the GCE (there may be several GCE processors) + 2. Sub-system ID defined in the dt-binding like a user ID + (Please refer to include/dt-bindings/gce/<chip>-gce.h) + 3. Offset from base address of the subsys you are at + 4. Size of the register the client needs + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: Phandle of the GCE + - description: Subsys ID defined in the dt-binding + - description: Offset from base address of the subsys + - description: Size of register + maxItems: 1 + +required: + - compatible + - reg + - power-domains + - clocks + - mediatek,gce-client-reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mediatek,mt8188-clk.h> + #include <dt-bindings/power/mediatek,mt8188-power.h> + #include <dt-bindings/gce/mt8195-gce.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + padding0: padding@1c11d000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c11d000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; + }; + }; diff --git a/dts/Bindings/display/mediatek/mediatek,postmask.yaml b/dts/Bindings/display/mediatek/mediatek,postmask.yaml index 654080bfbd..11fe32e50a 100644 --- a/dts/Bindings/display/mediatek/mediatek,postmask.yaml +++ b/dts/Bindings/display/mediatek/mediatek,postmask.yaml @@ -21,11 +21,12 @@ description: | properties: compatible: oneOf: - - items: - - const: mediatek,mt8192-disp-postmask + - enum: + - mediatek,mt8192-disp-postmask - items: - enum: - mediatek,mt8186-disp-postmask + - mediatek,mt8188-disp-postmask - const: mediatek,mt8192-disp-postmask reg: diff --git a/dts/Bindings/display/mediatek/mediatek,rdma.yaml b/dts/Bindings/display/mediatek/mediatek,rdma.yaml index 0882ae86e6..39dbb5c8bc 100644 --- a/dts/Bindings/display/mediatek/mediatek,rdma.yaml +++ b/dts/Bindings/display/mediatek/mediatek,rdma.yaml @@ -23,13 +23,14 @@ description: | properties: compatible: oneOf: + - enum: + - mediatek,mt2701-disp-rdma + - mediatek,mt8173-disp-rdma + - mediatek,mt8183-disp-rdma + - mediatek,mt8195-disp-rdma - items: - - const: mediatek,mt2701-disp-rdma - - items: - - const: mediatek,mt8173-disp-rdma - - items: - - const: mediatek,mt8183-disp-rdma - - items: + - enum: + - mediatek,mt8188-disp-rdma - const: mediatek,mt8195-disp-rdma - items: - enum: @@ -38,6 +39,10 @@ properties: - const: mediatek,mt2701-disp-rdma - items: - enum: + - mediatek,mt6795-disp-rdma + - const: mediatek,mt8173-disp-rdma + - items: + - enum: - mediatek,mt8186-disp-rdma - mediatek,mt8192-disp-rdma - const: mediatek,mt8183-disp-rdma diff --git a/dts/Bindings/display/mediatek/mediatek,split.yaml b/dts/Bindings/display/mediatek/mediatek,split.yaml index 35ace1f322..e4affc854f 100644 --- a/dts/Bindings/display/mediatek/mediatek,split.yaml +++ b/dts/Bindings/display/mediatek/mediatek,split.yaml @@ -21,7 +21,11 @@ description: | properties: compatible: oneOf: + - enum: + - mediatek,mt8173-disp-split + - mediatek,mt8195-mdp3-split - items: + - const: mediatek,mt6795-disp-split - const: mediatek,mt8173-disp-split reg: @@ -35,6 +39,21 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for details. + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + clocks: items: - description: SPLIT Clock @@ -45,6 +64,17 @@ required: - power-domains - clocks +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-mdp3-split + + then: + required: + - mediatek,gce-client-reg + additionalProperties: false examples: diff --git a/dts/Bindings/display/mediatek/mediatek,ufoe.yaml b/dts/Bindings/display/mediatek/mediatek,ufoe.yaml index b8bb135fe9..39e3e2d4a0 100644 --- a/dts/Bindings/display/mediatek/mediatek,ufoe.yaml +++ b/dts/Bindings/display/mediatek/mediatek,ufoe.yaml @@ -22,7 +22,10 @@ description: | properties: compatible: oneOf: + - enum: + - mediatek,mt8173-disp-ufoe - items: + - const: mediatek,mt6795-disp-ufoe - const: mediatek,mt8173-disp-ufoe reg: diff --git a/dts/Bindings/display/mediatek/mediatek,wdma.yaml b/dts/Bindings/display/mediatek/mediatek,wdma.yaml index 7d7cc1ab52..a3a2b71a45 100644 --- a/dts/Bindings/display/mediatek/mediatek,wdma.yaml +++ b/dts/Bindings/display/mediatek/mediatek,wdma.yaml @@ -21,7 +21,10 @@ description: | properties: compatible: oneOf: + - enum: + - mediatek,mt8173-disp-wdma - items: + - const: mediatek,mt6795-disp-wdma - const: mediatek,mt8173-disp-wdma reg: diff --git a/dts/Bindings/display/msm/dp-controller.yaml b/dts/Bindings/display/msm/dp-controller.yaml index cd05cfd765..ae53cbfb21 100644 --- a/dts/Bindings/display/msm/dp-controller.yaml +++ b/dts/Bindings/display/msm/dp-controller.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: MSM Display Port Controller maintainers: - - Kuogee Hsieh <khsieh@codeaurora.org> + - Kuogee Hsieh <quic_khsieh@quicinc.com> description: | Device tree bindings for DisplayPort host controller for MSM targets @@ -15,15 +15,28 @@ description: | properties: compatible: - enum: - - qcom,sc7180-dp - - qcom,sc7280-dp - - qcom,sc7280-edp - - qcom,sc8180x-dp - - qcom,sc8180x-edp - - qcom,sm8350-dp + oneOf: + - enum: + - qcom,sc7180-dp + - qcom,sc7280-dp + - qcom,sc7280-edp + - qcom,sc8180x-dp + - qcom,sc8180x-edp + - qcom,sc8280xp-dp + - qcom,sc8280xp-edp + - qcom,sdm845-dp + - qcom,sm8350-dp + - qcom,sm8650-dp + - items: + - enum: + - qcom,sm8150-dp + - qcom,sm8250-dp + - qcom,sm8450-dp + - qcom,sm8550-dp + - const: qcom,sm8350-dp reg: + minItems: 4 items: - description: ahb register block - description: aux register block @@ -67,15 +80,33 @@ properties: items: - const: dp - operating-points-v2: - maxItems: 1 + operating-points-v2: true + + opp-table: + type: object power-domains: maxItems: 1 + aux-bus: + $ref: /schemas/display/dp-aux-bus.yaml# + + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + deprecated: true + minItems: 1 + maxItems: 4 + items: + maximum: 3 + "#sound-dai-cells": const: 0 + vdda-0p9-supply: + deprecated: true + vdda-1p2-supply: + deprecated: true + ports: $ref: /schemas/graph.yaml#/properties/ports properties: @@ -84,8 +115,29 @@ properties: description: Input endpoint of the controller port@1: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: Output endpoint of the controller + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + properties: + data-lanes: + minItems: 1 + maxItems: 4 + items: + enum: [ 0, 1, 2, 3 ] + + link-frequencies: + minItems: 1 + maxItems: 4 + items: + enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ] + + required: + - port@0 + - port@1 required: - compatible @@ -95,10 +147,32 @@ required: - clock-names - phys - phy-names - - "#sound-dai-cells" - power-domains - ports +allOf: + # AUX BUS does not exist on DP controllers + # Audio output also is present only on DP output + # p1 regions is present on DP, but not on eDP + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-edp + - qcom,sc8180x-edp + - qcom,sc8280xp-edp + then: + properties: + "#sound-dai-cells": false + else: + properties: + aux-bus: false + reg: + minItems: 5 + required: + - "#sound-dai-cells" + additionalProperties: false examples: @@ -152,6 +226,8 @@ examples: reg = <1>; endpoint { remote-endpoint = <&typec>; + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; }; }; diff --git a/dts/Bindings/display/msm/dpu-common.yaml b/dts/Bindings/display/msm/dpu-common.yaml new file mode 100644 index 0000000000..3f953aa5e6 --- /dev/null +++ b/dts/Bindings/display/msm/dpu-common.yaml @@ -0,0 +1,56 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU common properties + +maintainers: + - Krishna Manikandan <quic_mkrishn@quicinc.com> + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + - Rob Clark <robdclark@gmail.com> + +description: | + Common properties for QCom DPU display controller. + +# Do not select this by default, otherwise it is also selected for all +# display-controller@ nodes +select: + false + +properties: + $nodename: + pattern: '^display-controller@[0-9a-f]+$' + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + operating-points-v2: true + opp-table: + type: object + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. + + patternProperties: + "^port@[0-9a-f]+$": + $ref: /schemas/graph.yaml#/properties/port + + # at least one port is required + required: + - port@0 + +required: + - interrupts + - power-domains + - operating-points-v2 + - ports + +additionalProperties: true diff --git a/dts/Bindings/display/msm/dpu-msm8998.yaml b/dts/Bindings/display/msm/dpu-msm8998.yaml deleted file mode 100644 index 2df64afb76..0000000000 --- a/dts/Bindings/display/msm/dpu-msm8998.yaml +++ /dev/null @@ -1,219 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Display DPU dt properties for MSM8998 target - -maintainers: - - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> - -description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for MSM8998 target. - -properties: - compatible: - items: - - const: qcom,msm8998-mdss - - reg: - maxItems: 1 - - reg-names: - const: mdss - - power-domains: - maxItems: 1 - - clocks: - items: - - description: Display AHB clock - - description: Display AXI clock - - description: Display core clock - - clock-names: - items: - - const: iface - - const: bus - - const: core - - interrupts: - maxItems: 1 - - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true - -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. - - properties: - compatible: - items: - - const: qcom,msm8998-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for regdma register set - - description: Address offset and size for vbif register set - - description: Address offset and size for non-realtime vbif register set - - reg-names: - items: - - const: mdp - - const: regdma - - const: vbif - - const: vbif_nrt - - clocks: - items: - - description: Display ahb clock - - description: Display axi clock - - description: Display mem-noc clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: iface - - const: bus - - const: mnoc - - const: core - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF2 (DSI2) - - required: - - port@0 - - port@1 - - required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -required: - - compatible - - reg - - reg-names - - power-domains - - clocks - - interrupts - - interrupt-controller - - iommus - - ranges - -additionalProperties: false - -examples: - - | - #include <dt-bindings/clock/qcom,mmcc-msm8998.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/power/qcom-rpmpd.h> - - mdss: display-subsystem@c900000 { - compatible = "qcom,msm8998-mdss"; - reg = <0x0c900000 0x1000>; - reg-names = "mdss"; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_MDP_CLK>; - clock-names = "iface", "bus", "core"; - - #address-cells = <1>; - #interrupt-cells = <1>; - #size-cells = <1>; - - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - iommus = <&mmss_smmu 0>; - - power-domains = <&mmcc MDSS_GDSC>; - ranges; - - display-controller@c901000 { - compatible = "qcom,msm8998-dpu"; - reg = <0x0c901000 0x8f000>, - <0x0c9a8e00 0xf0>, - <0x0c9b0000 0x2008>, - <0x0c9b8000 0x1040>; - reg-names = "mdp", "regdma", "vbif", "vbif_nrt"; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MNOC_AHB_CLK>, - <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "mnoc", "core", "vsync"; - - interrupt-parent = <&mdss>; - interrupts = <0>; - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmpd MSM8998_VDDMX>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - }; - }; -... diff --git a/dts/Bindings/display/msm/dpu-qcm2290.yaml b/dts/Bindings/display/msm/dpu-qcm2290.yaml deleted file mode 100644 index 734d14de96..0000000000 --- a/dts/Bindings/display/msm/dpu-qcm2290.yaml +++ /dev/null @@ -1,219 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Display DPU dt properties for QCM2290 target - -maintainers: - - Loic Poulain <loic.poulain@linaro.org> - -description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS - and DPU are mentioned for QCM2290 target. - -properties: - compatible: - items: - - const: qcom,qcm2290-mdss - - reg: - maxItems: 1 - - reg-names: - const: mdss - - power-domains: - maxItems: 1 - - clocks: - items: - - description: Display AHB clock from gcc - - description: Display AXI clock - - description: Display core clock - - clock-names: - items: - - const: iface - - const: bus - - const: core - - interrupts: - maxItems: 1 - - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 - - ranges: true - - interconnects: - items: - - description: Interconnect path specifying the port ids for data bus - - interconnect-names: - const: mdp0-mem - - resets: - items: - - description: MDSS_CORE reset - -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. - - properties: - compatible: - items: - - const: qcom,qcm2290-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display AXI clock from gcc - - description: Display AHB clock from dispcc - - description: Display core clock from dispcc - - description: Display lut clock from dispcc - - description: Display vsync clock from dispcc - - clock-names: - items: - - const: bus - - const: iface - - const: core - - const: lut - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - required: - - port@0 - - required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -required: - - compatible - - reg - - reg-names - - power-domains - - clocks - - interrupts - - interrupt-controller - - iommus - - ranges - -additionalProperties: false - -examples: - - | - #include <dt-bindings/clock/qcom,dispcc-qcm2290.h> - #include <dt-bindings/clock/qcom,gcc-qcm2290.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/interconnect/qcom,qcm2290.h> - #include <dt-bindings/power/qcom-rpmpd.h> - - mdss: mdss@5e00000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,qcm2290-mdss"; - reg = <0x05e00000 0x1000>; - reg-names = "mdss"; - power-domains = <&dispcc MDSS_GDSC>; - clocks = <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "core"; - - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - - interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>; - interconnect-names = "mdp0-mem"; - - iommus = <&apps_smmu 0x420 0x2>, - <&apps_smmu 0x421 0x0>; - ranges; - - mdss_mdp: display-controller@5e01000 { - compatible = "qcom,qcm2290-dpu"; - reg = <0x05e01000 0x8f000>, - <0x05eb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", "iface", "core", "lut", "vsync"; - - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmpd QCM2290_VDDCX>; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; - }; - }; -... diff --git a/dts/Bindings/display/msm/dpu-sc7180.yaml b/dts/Bindings/display/msm/dpu-sc7180.yaml deleted file mode 100644 index d3c3e4b078..0000000000 --- a/dts/Bindings/display/msm/dpu-sc7180.yaml +++ /dev/null @@ -1,232 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Display DPU dt properties for SC7180 target - -maintainers: - - Krishna Manikandan <quic_mkrishn@quicinc.com> - -description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for SC7180 target. - -properties: - compatible: - items: - - const: qcom,sc7180-mdss - - reg: - maxItems: 1 - - reg-names: - const: mdss - - power-domains: - maxItems: 1 - - clocks: - items: - - description: Display AHB clock from gcc - - description: Display AHB clock from dispcc - - description: Display core clock - - clock-names: - items: - - const: iface - - const: ahb - - const: core - - interrupts: - maxItems: 1 - - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true - - interconnects: - items: - - description: Interconnect path specifying the port ids for data bus - - interconnect-names: - const: mdp0-mem - - resets: - items: - - description: MDSS_CORE reset - -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. - - properties: - compatible: - items: - - const: qcom,sc7180-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display ahb clock - - description: Display rotator clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: iface - - const: rot - - const: lut - - const: core - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - port@2: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF0 (DP) - - required: - - port@0 - - required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -required: - - compatible - - reg - - reg-names - - power-domains - - clocks - - interrupts - - interrupt-controller - - iommus - - ranges - -additionalProperties: false - -examples: - - | - #include <dt-bindings/clock/qcom,dispcc-sc7180.h> - #include <dt-bindings/clock/qcom,gcc-sc7180.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/interconnect/qcom,sdm845.h> - #include <dt-bindings/power/qcom-rpmpd.h> - - display-subsystem@ae00000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,sc7180-mdss"; - reg = <0xae00000 0x1000>; - reg-names = "mdss"; - power-domains = <&dispcc MDSS_GDSC>; - clocks = <&gcc GCC_DISP_AHB_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "ahb", "core"; - - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; - interconnect-names = "mdp0-mem"; - - iommus = <&apps_smmu 0x800 0x2>; - ranges; - - display-controller@ae01000 { - compatible = "qcom,sc7180-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_ROT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", "iface", "rot", "lut", "core", - "vsync"; - - interrupt-parent = <&mdss>; - interrupts = <0>; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&mdp_opp_table>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@2 { - reg = <2>; - dpu_intf0_out: endpoint { - remote-endpoint = <&dp_in>; - }; - }; - }; - }; - }; -... diff --git a/dts/Bindings/display/msm/dpu-sc7280.yaml b/dts/Bindings/display/msm/dpu-sc7280.yaml deleted file mode 100644 index f427eec3d3..0000000000 --- a/dts/Bindings/display/msm/dpu-sc7280.yaml +++ /dev/null @@ -1,236 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Display DPU dt properties for SC7280 - -maintainers: - - Krishna Manikandan <quic_mkrishn@quicinc.com> - -description: | - Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for SC7280. - -properties: - compatible: - const: qcom,sc7280-mdss - - reg: - maxItems: 1 - - reg-names: - const: mdss - - power-domains: - maxItems: 1 - - clocks: - items: - - description: Display AHB clock from gcc - - description: Display AHB clock from dispcc - - description: Display core clock - - clock-names: - items: - - const: iface - - const: ahb - - const: core - - interrupts: - maxItems: 1 - - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true - - interconnects: - items: - - description: Interconnect path specifying the port ids for data bus - - interconnect-names: - const: mdp0-mem - - resets: - items: - - description: MDSS_CORE reset - -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. - - properties: - compatible: - const: qcom,sc7280-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display sf axi clock - - description: Display ahb clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI) - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF5 (EDP) - - required: - - port@0 - - required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -required: - - compatible - - reg - - reg-names - - power-domains - - clocks - - interrupts - - interrupt-controller - - iommus - - ranges - -additionalProperties: false - -examples: - - | - #include <dt-bindings/clock/qcom,dispcc-sc7280.h> - #include <dt-bindings/clock/qcom,gcc-sc7280.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/interconnect/qcom,sc7280.h> - #include <dt-bindings/power/qcom-rpmpd.h> - - display-subsystem@ae00000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,sc7280-mdss"; - reg = <0xae00000 0x1000>; - reg-names = "mdss"; - power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; - clocks = <&gcc GCC_DISP_AHB_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", - "ahb", - "core"; - - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; - interconnect-names = "mdp0-mem"; - - iommus = <&apps_smmu 0x900 0x402>; - ranges; - - display-controller@ae01000 { - compatible = "qcom,sc7280-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - interrupt-parent = <&mdss>; - interrupts = <0>; - power-domains = <&rpmhpd SC7280_CX>; - operating-points-v2 = <&mdp_opp_table>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf5_out: endpoint { - remote-endpoint = <&edp_in>; - }; - }; - }; - }; - }; -... diff --git a/dts/Bindings/display/msm/dpu-sdm845.yaml b/dts/Bindings/display/msm/dpu-sdm845.yaml deleted file mode 100644 index 2bb8896bef..0000000000 --- a/dts/Bindings/display/msm/dpu-sdm845.yaml +++ /dev/null @@ -1,213 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Display DPU dt properties for SDM845 target - -maintainers: - - Krishna Manikandan <quic_mkrishn@quicinc.com> - -description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for SDM845 target. - -properties: - compatible: - items: - - const: qcom,sdm845-mdss - - reg: - maxItems: 1 - - reg-names: - const: mdss - - power-domains: - maxItems: 1 - - clocks: - items: - - description: Display AHB clock from gcc - - description: Display core clock - - clock-names: - items: - - const: iface - - const: core - - interrupts: - maxItems: 1 - - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 - - ranges: true - - resets: - items: - - description: MDSS_CORE reset - -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. - - properties: - compatible: - items: - - const: qcom,sdm845-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display ahb clock - - description: Display axi clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: iface - - const: bus - - const: core - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF2 (DSI2) - - required: - - port@0 - - port@1 - - required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -required: - - compatible - - reg - - reg-names - - power-domains - - clocks - - interrupts - - interrupt-controller - - iommus - - ranges - -additionalProperties: false - -examples: - - | - #include <dt-bindings/clock/qcom,dispcc-sdm845.h> - #include <dt-bindings/clock/qcom,gcc-sdm845.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/power/qcom-rpmpd.h> - - display-subsystem@ae00000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,sdm845-mdss"; - reg = <0x0ae00000 0x1000>; - reg-names = "mdss"; - power-domains = <&dispcc MDSS_GDSC>; - - clocks = <&gcc GCC_DISP_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "core"; - - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - - iommus = <&apps_smmu 0x880 0x8>, - <&apps_smmu 0xc80 0x8>; - ranges; - - display-controller@ae01000 { - compatible = "qcom,sdm845-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_AXI_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; - - interrupt-parent = <&mdss>; - interrupts = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&mdp_opp_table>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - }; - }; -... diff --git a/dts/Bindings/display/msm/dsi-controller-main.yaml b/dts/Bindings/display/msm/dsi-controller-main.yaml index 880bfe9308..4219936eda 100644 --- a/dts/Bindings/display/msm/dsi-controller-main.yaml +++ b/dts/Bindings/display/msm/dsi-controller-main.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# @@ -9,14 +9,39 @@ title: Qualcomm Display DSI controller maintainers: - Krishna Manikandan <quic_mkrishn@quicinc.com> -allOf: - - $ref: "../dsi-controller.yaml#" - properties: compatible: - enum: - - qcom,mdss-dsi-ctrl - - qcom,dsi-ctrl-6g-qcm2290 + oneOf: + - items: + - enum: + - qcom,apq8064-dsi-ctrl + - qcom,msm8226-dsi-ctrl + - qcom,msm8916-dsi-ctrl + - qcom,msm8953-dsi-ctrl + - qcom,msm8974-dsi-ctrl + - qcom,msm8996-dsi-ctrl + - qcom,msm8998-dsi-ctrl + - qcom,qcm2290-dsi-ctrl + - qcom,sc7180-dsi-ctrl + - qcom,sc7280-dsi-ctrl + - qcom,sdm660-dsi-ctrl + - qcom,sdm670-dsi-ctrl + - qcom,sdm845-dsi-ctrl + - qcom,sm6115-dsi-ctrl + - qcom,sm6125-dsi-ctrl + - qcom,sm6350-dsi-ctrl + - qcom,sm6375-dsi-ctrl + - qcom,sm8150-dsi-ctrl + - qcom,sm8250-dsi-ctrl + - qcom,sm8350-dsi-ctrl + - qcom,sm8450-dsi-ctrl + - qcom,sm8550-dsi-ctrl + - qcom,sm8650-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + - enum: + - qcom,dsi-ctrl-6g-qcm2290 + - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible + deprecated: true reg: maxItems: 1 @@ -28,36 +53,34 @@ properties: maxItems: 1 clocks: - items: - - description: Display byte clock - - description: Display byte interface clock - - description: Display pixel clock - - description: Display escape clock - - description: Display AHB clock - - description: Display AXI clock + description: | + Several clocks are used, depending on the variant. Typical ones are:: + - bus:: Display AHB clock. + - byte:: Display byte clock. + - byte_intf:: Display byte interface clock. + - core:: Display core clock. + - core_mss:: Core MultiMedia SubSystem clock. + - iface:: Display AXI clock. + - mdp_core:: MDP Core clock. + - mnoc:: MNOC clock + - pixel:: Display pixel clock. + minItems: 3 + maxItems: 9 clock-names: - items: - - const: byte - - const: byte_intf - - const: pixel - - const: core - - const: iface - - const: bus + minItems: 3 + maxItems: 9 phys: maxItems: 1 phy-names: + deprecated: true const: dsi - "#address-cells": true - - "#size-cells": true - syscon-sfpb: description: A phandle to mmss_sfpb syscon node (only for DSIv2). - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle qcom,dual-dsi-mode: type: boolean @@ -65,15 +88,29 @@ properties: Indicates if the DSI controller is driving a panel which needs 2 DSI links. + qcom,master-dsi: + type: boolean + description: | + Indicates if the DSI controller is the master DSI controller when + qcom,dual-dsi-mode enabled. + + qcom,sync-dual-dsi: + type: boolean + description: | + Indicates if the DSI controller needs to sync the other DSI controller + with MIPI DCS commands when qcom,dual-dsi-mode enabled. + assigned-clocks: minItems: 2 - maxItems: 2 + maxItems: 4 description: | Parents of "byte" and "pixel" for the given platform. + For DSIv2 platforms this should contain "byte", "esc", "src" and + "pixel_src" clocks. assigned-clock-parents: minItems: 2 - maxItems: 2 + maxItems: 4 description: | The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. @@ -82,15 +119,18 @@ properties: operating-points-v2: true + opp-table: + type: object + ports: - $ref: "/schemas/graph.yaml#/properties/ports" + $ref: /schemas/graph.yaml#/properties/ports description: | Contains DSI controller input and output ports as children, each containing one endpoint subnode. properties: port@0: - $ref: "/schemas/graph.yaml#/$defs/port-base" + $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: | Input endpoints of the controller. @@ -101,12 +141,12 @@ properties: properties: data-lanes: maxItems: 4 - minItems: 4 + minItems: 1 items: enum: [ 0, 1, 2, 3 ] port@1: - $ref: "/schemas/graph.yaml#/$defs/port-base" + $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: | Output endpoints of the controller. @@ -117,7 +157,7 @@ properties: properties: data-lanes: maxItems: 4 - minItems: 4 + minItems: 1 items: enum: [ 0, 1, 2, 3 ] @@ -125,6 +165,30 @@ properties: - port@0 - port@1 + avdd-supply: + description: + Phandle to vdd regulator device node + + refgen-supply: + description: + Phandle to REFGEN regulator device node + + vcca-supply: + description: + Phandle to vdd regulator device node + + vdd-supply: + description: + VDD regulator + + vddio-supply: + description: + VDD-IO regulator + + vdda-supply: + description: + VDDA regulator + required: - compatible - reg @@ -133,14 +197,202 @@ required: - clocks - clock-names - phys - - phy-names - assigned-clocks - assigned-clock-parents - - power-domains - - operating-points-v2 - ports -additionalProperties: false +allOf: + - $ref: ../dsi-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,apq8064-dsi-ctrl + then: + properties: + clocks: + maxItems: 7 + clock-names: + items: + - const: iface + - const: bus + - const: core_mmss + - const: src + - const: byte + - const: pixel + - const: core + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8916-dsi-ctrl + then: + properties: + clocks: + maxItems: 6 + clock-names: + items: + - const: mdp_core + - const: iface + - const: bus + - const: byte + - const: pixel + - const: core + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8953-dsi-ctrl + then: + properties: + clocks: + maxItems: 6 + clock-names: + items: + - const: mdp_core + - const: iface + - const: bus + - const: byte + - const: pixel + - const: core + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8226-dsi-ctrl + - qcom,msm8974-dsi-ctrl + then: + properties: + clocks: + maxItems: 7 + clock-names: + items: + - const: mdp_core + - const: iface + - const: bus + - const: byte + - const: pixel + - const: core + - const: core_mmss + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-dsi-ctrl + then: + properties: + clocks: + maxItems: 7 + clock-names: + items: + - const: mdp_core + - const: byte + - const: iface + - const: bus + - const: core_mmss + - const: pixel + - const: core + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-dsi-ctrl + - qcom,sm6125-dsi-ctrl + - qcom,sm6350-dsi-ctrl + then: + properties: + clocks: + maxItems: 6 + clock-names: + items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: bus + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-dsi-ctrl + - qcom,sc7280-dsi-ctrl + - qcom,sm8150-dsi-ctrl + - qcom,sm8250-dsi-ctrl + - qcom,sm8350-dsi-ctrl + - qcom,sm8450-dsi-ctrl + - qcom,sm8550-dsi-ctrl + - qcom,sm8650-dsi-ctrl + then: + properties: + clocks: + maxItems: 6 + clock-names: + items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: bus + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm660-dsi-ctrl + then: + properties: + clocks: + maxItems: 9 + clock-names: + items: + - const: mdp_core + - const: byte + - const: byte_intf + - const: mnoc + - const: iface + - const: bus + - const: core_mmss + - const: pixel + - const: core + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-dsi-ctrl + - qcom,sm6115-dsi-ctrl + - qcom,sm6375-dsi-ctrl + then: + properties: + clocks: + maxItems: 6 + clock-names: + items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: bus + +unevaluatedProperties: false examples: - | @@ -150,7 +402,7 @@ examples: #include <dt-bindings/power/qcom-rpmpd.h> dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0ae94000 0x400>; reg-names = "dsi_ctrl"; diff --git a/dts/Bindings/display/msm/dsi-phy-10nm.yaml b/dts/Bindings/display/msm/dsi-phy-10nm.yaml index 716f921e35..69d13867b7 100644 --- a/dts/Bindings/display/msm/dsi-phy-10nm.yaml +++ b/dts/Bindings/display/msm/dsi-phy-10nm.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml# @@ -37,7 +37,6 @@ properties: qcom,phy-rescode-offset-top: $ref: /schemas/types.yaml#/definitions/int8-array - minItems: 5 maxItems: 5 description: Integer array of offset for pull-up legs rescode for all five lanes. @@ -49,7 +48,6 @@ properties: qcom,phy-rescode-offset-bot: $ref: /schemas/types.yaml#/definitions/int8-array - minItems: 5 maxItems: 5 description: Integer array of offset for pull-down legs rescode for all five lanes. @@ -60,7 +58,7 @@ properties: maximum: 31 qcom,phy-drive-ldo-level: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: The PHY LDO has an amplitude tuning feature to adjust the LDO output for the HSTX drive. Use supported levels (mV) to offset the drive level @@ -71,7 +69,6 @@ required: - compatible - reg - reg-names - - vdds-supply unevaluatedProperties: false diff --git a/dts/Bindings/display/msm/dsi-phy-14nm.yaml b/dts/Bindings/display/msm/dsi-phy-14nm.yaml index 1342d74ecf..52bbe132e6 100644 --- a/dts/Bindings/display/msm/dsi-phy-14nm.yaml +++ b/dts/Bindings/display/msm/dsi-phy-14nm.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml# @@ -16,8 +16,10 @@ properties: compatible: enum: - qcom,dsi-phy-14nm + - qcom,dsi-phy-14nm-2290 - qcom,dsi-phy-14nm-660 - qcom,dsi-phy-14nm-8953 + - qcom,sm6125-dsi-phy-14nm reg: items: @@ -34,11 +36,20 @@ properties: vcca-supply: description: Phandle to vcca regulator device node. + power-domains: + description: + A phandle and PM domain specifier for an optional power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing the power domain's performance point. + maxItems: 1 + required: - compatible - reg - reg-names - - vcca-supply unevaluatedProperties: false diff --git a/dts/Bindings/display/msm/dsi-phy-20nm.yaml b/dts/Bindings/display/msm/dsi-phy-20nm.yaml index 9c1f9140c7..7e6687cb00 100644 --- a/dts/Bindings/display/msm/dsi-phy-20nm.yaml +++ b/dts/Bindings/display/msm/dsi-phy-20nm.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml# diff --git a/dts/Bindings/display/msm/dsi-phy-28nm.yaml b/dts/Bindings/display/msm/dsi-phy-28nm.yaml index 3d8540a06f..288d8babb7 100644 --- a/dts/Bindings/display/msm/dsi-phy-28nm.yaml +++ b/dts/Bindings/display/msm/dsi-phy-28nm.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml# @@ -15,9 +15,11 @@ allOf: properties: compatible: enum: + - qcom,dsi-phy-28nm-8226 + - qcom,dsi-phy-28nm-8960 - qcom,dsi-phy-28nm-hpm + - qcom,dsi-phy-28nm-hpm-fam-b - qcom,dsi-phy-28nm-lp - - qcom,dsi-phy-28nm-8960 reg: items: @@ -34,6 +36,10 @@ properties: vddio-supply: description: Phandle to vdd-io regulator device node. + qcom,dsi-phy-regulator-ldo-mode: + type: boolean + description: Indicates if the LDO mode PHY regulator is wanted. + required: - compatible - reg diff --git a/dts/Bindings/display/msm/dsi-phy-7nm.yaml b/dts/Bindings/display/msm/dsi-phy-7nm.yaml index c851770bbd..7e764eac3e 100644 --- a/dts/Bindings/display/msm/dsi-phy-7nm.yaml +++ b/dts/Bindings/display/msm/dsi-phy-7nm.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml# @@ -18,6 +18,11 @@ properties: - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 - qcom,sc7280-dsi-phy-7nm + - qcom,sm6375-dsi-phy-7nm + - qcom,sm8350-dsi-phy-5nm + - qcom,sm8450-dsi-phy-5nm + - qcom,sm8550-dsi-phy-4nm + - qcom,sm8650-dsi-phy-4nm reg: items: @@ -44,7 +49,6 @@ required: - compatible - reg - reg-names - - vdds-supply unevaluatedProperties: false diff --git a/dts/Bindings/display/msm/dsi-phy-common.yaml b/dts/Bindings/display/msm/dsi-phy-common.yaml index 76d40f7933..6b57ce41c9 100644 --- a/dts/Bindings/display/msm/dsi-phy-common.yaml +++ b/dts/Bindings/display/msm/dsi-phy-common.yaml @@ -1,17 +1,16 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Description of Qualcomm Display DSI PHY common dt properties +title: Qualcomm Display DSI PHY Common Properties maintainers: - Krishna Manikandan <quic_mkrishn@quicinc.com> -description: | - This defines the DSI PHY dt properties which are common for all - dsi phy versions. +description: + Common properties for Qualcomm Display DSI PHY. properties: "#clock-cells": diff --git a/dts/Bindings/display/msm/gmu.yaml b/dts/Bindings/display/msm/gmu.yaml index fe55611d26..4e1c25b429 100644 --- a/dts/Bindings/display/msm/gmu.yaml +++ b/dts/Bindings/display/msm/gmu.yaml @@ -3,10 +3,10 @@ %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/msm/gmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# -title: Devicetree bindings for the GMU attached to certain Adreno GPUs +title: GMU attached to certain Adreno GPUs maintainers: - Rob Clark <robdclark@gmail.com> @@ -19,43 +19,33 @@ description: | properties: compatible: - items: - - enum: - - qcom,adreno-gmu-630.2 - - const: qcom,adreno-gmu + oneOf: + - items: + - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$' + - const: qcom,adreno-gmu + - const: qcom,adreno-gmu-wrapper reg: - items: - - description: Core GMU registers - - description: GMU PDC registers - - description: GMU PDC sequence registers + minItems: 1 + maxItems: 4 reg-names: - items: - - const: gmu - - const: gmu_pdc - - const: gmu_pdc_seq + minItems: 1 + maxItems: 4 clocks: - items: - - description: GMU clock - - description: GPU CX clock - - description: GPU AXI clock - - description: GPU MEMNOC clock + minItems: 4 + maxItems: 7 clock-names: - items: - - const: gmu - - const: cxo - - const: axi - - const: memnoc + minItems: 4 + maxItems: 7 interrupts: items: - description: GMU HFI interrupt - description: GMU interrupt - interrupt-names: items: - const: hfi @@ -74,23 +64,222 @@ properties: iommus: maxItems: 1 + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM + operating-points-v2: true + opp-table: + type: object + required: - compatible - reg - reg-names - - clocks - - clock-names - - interrupts - - interrupt-names - power-domains - power-domain-names - - iommus - - operating-points-v2 additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-618.0 + - qcom,adreno-gmu-630.2 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: GMU PDC registers + - description: GMU PDC sequence registers + reg-names: + items: + - const: gmu + - const: gmu_pdc + - const: gmu_pdc_seq + clocks: + items: + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + clock-names: + items: + - const: gmu + - const: cxo + - const: axi + - const: memnoc + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-635.0 + - qcom,adreno-gmu-660.1 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: Resource controller registers + - description: GMU PDC registers + reg-names: + items: + - const: gmu + - const: rscc + - const: gmu_pdc + clocks: + items: + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GPU AHB clock + - description: GPU HUB CX clock + - description: GPU SMMU vote clock + clock-names: + items: + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: ahb + - const: hub + - const: smmu_vote + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-640.1 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: GMU PDC registers + - description: GMU PDC sequence registers + reg-names: + items: + - const: gmu + - const: gmu_pdc + - const: gmu_pdc_seq + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-650.2 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: Resource controller registers + - description: GMU PDC registers + - description: GMU PDC sequence registers + reg-names: + items: + - const: gmu + - const: rscc + - const: gmu_pdc + - const: gmu_pdc_seq + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-640.1 + - qcom,adreno-gmu-650.2 + then: + properties: + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: axi + - const: memnoc + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-730.1 + - qcom,adreno-gmu-740.1 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: Resource controller registers + - description: GMU PDC registers + reg-names: + items: + - const: gmu + - const: rscc + - const: gmu_pdc + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GMU HUB clock + - description: GPUSS DEMET clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: hub + - const: demet + + required: + - qcom,qmp + + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-wrapper + then: + properties: + reg: + items: + - description: GMU wrapper register space + reg-names: + items: + - const: gmu + else: + required: + - clocks + - clock-names + - interrupts + - interrupt-names + - iommus + - operating-points-v2 + examples: - | #include <dt-bindings/clock/qcom,gpucc-sdm845.h> @@ -99,7 +288,7 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> gmu: gmu@506a000 { - compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; + compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; reg = <0x506a000 0x30000>, <0xb280000 0x10000>, @@ -123,3 +312,12 @@ examples: iommus = <&adreno_smmu 5>; operating-points-v2 = <&gmu_opp_table>; }; + + gmu_wrapper: gmu@596a000 { + compatible = "qcom,adreno-gmu-wrapper"; + reg = <0x0596a000 0x30000>; + reg-names = "gmu"; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + }; diff --git a/dts/Bindings/display/msm/gpu.yaml b/dts/Bindings/display/msm/gpu.yaml index 3397bc31d0..b019db9547 100644 --- a/dts/Bindings/display/msm/gpu.yaml +++ b/dts/Bindings/display/msm/gpu.yaml @@ -2,10 +2,10 @@ %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/msm/gpu.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/msm/gpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# -title: Devicetree bindings for the Adreno or Snapdragon GPUs +title: Adreno or Snapdragon GPUs maintainers: - Rob Clark <robdclark@gmail.com> @@ -15,9 +15,15 @@ properties: oneOf: - description: | The driver is parsing the compat string for Adreno to + figure out the chip-id. + items: + - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$' + - const: qcom,adreno + - description: | + The driver is parsing the compat string for Adreno to figure out the gpu-id and patch level. items: - - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$' + - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]$' - const: qcom,adreno - description: | The driver is parsing the compat string for Imageon to @@ -36,10 +42,7 @@ properties: reg-names: minItems: 1 - items: - - const: kgsl_3d0_reg_memory - - const: cx_mem - - const: cx_dbgc + maxItems: 3 interrupts: maxItems: 1 @@ -58,7 +61,8 @@ properties: - const: ocmem iommus: - maxItems: 1 + minItems: 1 + maxItems: 64 sram: $ref: /schemas/types.yaml#/definitions/phandle-array @@ -81,13 +85,14 @@ properties: zap-shader: type: object + additionalProperties: false description: | For a5xx and a6xx devices this node contains a memory-region that points to reserved memory to store the zap shader that can be used to help bring the GPU out of secure mode. properties: memory-region: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 firmware-name: description: | @@ -147,22 +152,70 @@ allOf: description: GPU 3D engine clock - const: rbbmtimer description: GPU RBBM Timer for Adreno 5xx series + - const: rbcpr + description: GPU RB Core Power Reduction clock minItems: 2 maxItems: 7 required: - clocks - clock-names + - if: properties: compatible: contains: - pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' - - then: # Since Adreno 6xx series clocks should be defined in GMU + enum: + - qcom,adreno-610.0 + - qcom,adreno-619.1 + then: properties: - clocks: false - clock-names: false + clocks: + minItems: 6 + maxItems: 6 + + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gmu + description: CX GMU clock + - const: xo + description: GPUCC clocksource clock + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_dbgc + + required: + - clocks + - clock-names + else: + if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]$' + + then: # Starting with A6xx, the clocks are usually defined in the GMU node + properties: + clocks: false + clock-names: false + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc examples: - | diff --git a/dts/Bindings/display/msm/hdmi.txt b/dts/Bindings/display/msm/hdmi.txt deleted file mode 100644 index 5f90a40da5..0000000000 --- a/dts/Bindings/display/msm/hdmi.txt +++ /dev/null @@ -1,99 +0,0 @@ -Qualcomm adreno/snapdragon hdmi output - -Required properties: -- compatible: one of the following - * "qcom,hdmi-tx-8996" - * "qcom,hdmi-tx-8994" - * "qcom,hdmi-tx-8084" - * "qcom,hdmi-tx-8974" - * "qcom,hdmi-tx-8660" - * "qcom,hdmi-tx-8960" -- reg: Physical base address and length of the controller's registers -- reg-names: "core_physical" -- interrupts: The interrupt signal from the hdmi block. -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See ../clocks/clock-bindings.txt for details. -- core-vdda-supply: phandle to supply regulator -- hdmi-mux-supply: phandle to mux regulator -- phys: the phandle for the HDMI PHY device -- phy-names: the name of the corresponding PHY device - -Optional properties: -- hpd-gpios: hpd pin -- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin -- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin -- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin -- power-domains: reference to the power domain(s), if available. -- pinctrl-names: the pin control state names; should contain "default" -- pinctrl-0: the default pinctrl state (active) -- pinctrl-1: the "sleep" pinctrl state - -HDMI PHY: -Required properties: -- compatible: Could be the following - * "qcom,hdmi-phy-8660" - * "qcom,hdmi-phy-8960" - * "qcom,hdmi-phy-8974" - * "qcom,hdmi-phy-8084" - * "qcom,hdmi-phy-8996" -- #phy-cells: Number of cells in a PHY specifier; Should be 0. -- reg: Physical base address and length of the registers of the PHY sub blocks. -- reg-names: The names of register regions. The following regions are required: - * "hdmi_phy" - * "hdmi_pll" - For HDMI PHY on msm8996, these additional register regions are required: - * "hdmi_tx_l0" - * "hdmi_tx_l1" - * "hdmi_tx_l3" - * "hdmi_tx_l4" -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- core-vdda-supply: phandle to vdda regulator device node - -Example: - -/ { - ... - - hdmi: hdmi@4a00000 { - compatible = "qcom,hdmi-tx-8960"; - reg-names = "core_physical"; - reg = <0x04a00000 0x2f0>; - interrupts = <GIC_SPI 79 0>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = - "core", - "master_iface", - "slave_iface"; - clocks = - <&mmcc HDMI_APP_CLK>, - <&mmcc HDMI_M_AHB_CLK>, - <&mmcc HDMI_S_AHB_CLK>; - qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>; - qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>; - qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>; - core-vdda-supply = <&pm8921_hdmi_mvs>; - hdmi-mux-supply = <&ext_3p3v>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hpd_active &ddc_active &cec_active>; - pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; - - phys = <&hdmi_phy>; - phy-names = "hdmi_phy"; - }; - - hdmi_phy: phy@4a00400 { - compatible = "qcom,hdmi-phy-8960"; - reg-names = "hdmi_phy", - "hdmi_pll"; - reg = <0x4a00400 0x60>, - <0x4a00500 0x100>; - #phy-cells = <0>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = "slave_iface"; - clocks = <&mmcc HDMI_S_AHB_CLK>; - core-vdda-supply = <&pm8921_hdmi_mvs>; - }; -}; diff --git a/dts/Bindings/display/msm/hdmi.yaml b/dts/Bindings/display/msm/hdmi.yaml new file mode 100644 index 0000000000..47e9766982 --- /dev/null +++ b/dts/Bindings/display/msm/hdmi.yaml @@ -0,0 +1,232 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/display/msm/hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Adreno/Snapdragon HDMI output + +maintainers: + - Rob Clark <robdclark@gmail.com> + +properties: + compatible: + enum: + - qcom,hdmi-tx-8084 + - qcom,hdmi-tx-8660 + - qcom,hdmi-tx-8960 + - qcom,hdmi-tx-8974 + - qcom,hdmi-tx-8994 + - qcom,hdmi-tx-8996 + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + reg: + minItems: 1 + maxItems: 3 + + reg-names: + minItems: 1 + items: + - const: core_physical + - const: qfprom_physical + - const: hdcp_physical + + interrupts: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + enum: + - hdmi_phy + - hdmi-phy + deprecated: true + + core-vdda-supply: + description: phandle to VDDA supply regulator + + hdmi-mux-supply: + description: phandle to mux regulator + deprecated: true + + core-vcc-supply: + description: phandle to VCC supply regulator + + hpd-gpios: + maxItems: 1 + description: hpd pin + + qcom,hdmi-tx-mux-en-gpios: + maxItems: 1 + deprecated: true + description: HDMI mux enable pin + + qcom,hdmi-tx-mux-sel-gpios: + maxItems: 1 + deprecated: true + description: HDMI mux select pin + + qcom,hdmi-tx-mux-lpm-gpios: + maxItems: 1 + deprecated: true + description: HDMI mux lpm pin + + '#sound-dai-cells': + const: 1 + + ports: + type: object + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + description: | + Input endpoints of the controller. + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + description: | + Output endpoints of the controller. + + required: + - port@0 + +required: + - compatible + - clocks + - clock-names + - reg + - reg-names + - interrupts + - phys + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,hdmi-tx-8960 + - qcom,hdmi-tx-8660 + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: core + - const: master_iface + - const: slave_iface + core-vcc-supplies: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,hdmi-tx-8974 + - qcom,hdmi-tx-8084 + - qcom,hdmi-tx-8994 + - qcom,hdmi-tx-8996 + then: + properties: + clocks: + minItems: 5 + clock-names: + items: + - const: mdp_core + - const: iface + - const: core + - const: alt_iface + - const: extp + hdmi-mux-supplies: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + hdmi: hdmi@4a00000 { + compatible = "qcom,hdmi-tx-8960"; + reg-names = "core_physical"; + reg = <0x04a00000 0x2f0>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "core", + "master_iface", + "slave_iface"; + clocks = <&clk 61>, + <&clk 72>, + <&clk 98>; + hpd-gpios = <&msmgpio 72 GPIO_ACTIVE_HIGH>; + core-vdda-supply = <&pm8921_hdmi_mvs>; + hdmi-mux-supply = <&ext_3p3v>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hpd_active &ddc_active &cec_active>; + pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; + + phys = <&hdmi_phy>; + }; + - | + #include <dt-bindings/clock/qcom,gcc-msm8996.h> + #include <dt-bindings/clock/qcom,mmcc-msm8996.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + hdmi@9a0000 { + compatible = "qcom,hdmi-tx-8996"; + reg = <0x009a0000 0x50c>, + <0x00070000 0x6158>, + <0x009e0000 0xfff>; + reg-names = "core_physical", + "qfprom_physical", + "hdcp_physical"; + + interrupt-parent = <&mdss>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_HDMI_CLK>, + <&mmcc MDSS_HDMI_AHB_CLK>, + <&mmcc MDSS_EXTPCLK_CLK>; + clock-names = "mdp_core", + "iface", + "core", + "alt_iface", + "extp"; + + phys = <&hdmi_phy>; + #sound-dai-cells = <1>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; + pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; + + core-vdda-supply = <&vreg_l12a_1p8>; + core-vcc-supply = <&vreg_s4a_1p8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&mdp5_intf3_out>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/mdp4.yaml b/dts/Bindings/display/msm/mdp4.yaml index f63f60fea2..35204a2875 100644 --- a/dts/Bindings/display/msm/mdp4.yaml +++ b/dts/Bindings/display/msm/mdp4.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/msm/mdp4.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/msm/mdp4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Adreno/Snapdragon MDP4 display controller @@ -36,7 +36,7 @@ properties: maxItems: 1 iommus: - maxItems: 1 + maxItems: 4 ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/dts/Bindings/display/msm/mdp5.txt b/dts/Bindings/display/msm/mdp5.txt deleted file mode 100644 index 43d11279c9..0000000000 --- a/dts/Bindings/display/msm/mdp5.txt +++ /dev/null @@ -1,160 +0,0 @@ -Qualcomm adreno/snapdragon MDP5 display controller - -Description: - -This is the bindings documentation for the Mobile Display Subsytem(MDSS) that -encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display -controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996. - -MDSS: -Required properties: -- compatible: - * "qcom,mdss" - MDSS -- reg: Physical base address and length of the controller's registers. -- reg-names: The names of register regions. The following regions are required: - * "mdss_phys" - * "vbif_phys" -- interrupts: The interrupt signal from MDSS. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt -- clocks: device clocks. See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required. - * "iface" - * "bus" - * "vsync" -- #address-cells: number of address cells for the MDSS children. Should be 1. -- #size-cells: Should be 1. -- ranges: parent bus address space is the same as the child bus address space. - -Optional properties: -- clock-names: the following clocks are optional: - * "lut" - -MDP5: -Required properties: -- compatible: - * "qcom,mdp5" - MDP5 -- reg: Physical base address and length of the controller's registers. -- reg-names: The names of register regions. The following regions are required: - * "mdp_phys" -- interrupts: Interrupt line from MDP5 to MDSS interrupt controller. -- clocks: device clocks. See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required. -- * "bus" -- * "iface" -- * "core" -- * "vsync" -- ports: contains the list of output ports from MDP. These connect to interfaces - that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a - special case since it is a part of the MDP block itself). - - Each output port contains an endpoint that describes how it is connected to an - external interface. These are described by the standard properties documented - here: - Documentation/devicetree/bindings/graph.txt - Documentation/devicetree/bindings/media/video-interfaces.txt - - The availability of output ports can vary across SoC revisions: - - For MSM8974 and APQ8084: - Port 0 -> MDP_INTF0 (eDP) - Port 1 -> MDP_INTF1 (DSI1) - Port 2 -> MDP_INTF2 (DSI2) - Port 3 -> MDP_INTF3 (HDMI) - - For MSM8916: - Port 0 -> MDP_INTF1 (DSI1) - - For MSM8994 and MSM8996: - Port 0 -> MDP_INTF1 (DSI1) - Port 1 -> MDP_INTF2 (DSI2) - Port 2 -> MDP_INTF3 (HDMI) - -Optional properties: -- clock-names: the following clocks are optional: - * "lut" - * "tbu" - * "tbu_rt" - -Example: - -/ { - ... - - mdss: mdss@1a00000 { - compatible = "qcom,mdss"; - reg = <0x1a00000 0x1000>, - <0x1ac8000 0x3000>; - reg-names = "mdss_phys", "vbif_phys"; - - power-domains = <&gcc MDSS_GDSC>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "vsync" - - interrupts = <0 72 0>; - - interrupt-controller; - #interrupt-cells = <1>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mdp: mdp@1a01000 { - compatible = "qcom,mdp5"; - reg = <0x1a01000 0x90000>; - reg-names = "mdp_phys"; - - interrupt-parent = <&mdss>; - interrupts = <0 0>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_MDP_CLK>, - <&gcc GCC_MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "core", - "vsync"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; - }; - - dsi0: dsi@1a98000 { - ... - ports { - ... - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp5_intf1_out>; - }; - }; - ... - }; - ... - }; - - dsi_phy0: dsi-phy@1a98300 { - ... - }; - }; -}; diff --git a/dts/Bindings/display/msm/mdss-common.yaml b/dts/Bindings/display/msm/mdss-common.yaml new file mode 100644 index 0000000000..c6305a6e03 --- /dev/null +++ b/dts/Bindings/display/msm/mdss-common.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/mdss-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display MDSS common properties + +maintainers: + - Krishna Manikandan <quic_mkrishn@quicinc.com> + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + - Rob Clark <robdclark@gmail.com> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. + +# Do not select this by default, otherwise it is also selected for qcom,mdss +# devices. +select: + false + +properties: + $nodename: + pattern: "^display-subsystem@[0-9a-f]+$" + + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 4 + + clock-names: + minItems: 2 + maxItems: 4 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#address-cells": true + + "#size-cells": true + + "#interrupt-cells": + const: 1 + + iommus: + minItems: 1 + items: + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 + + ranges: true + + # This is not a perfect description, but it's impossible to discern and match + # the entries like we do with interconnect-names + interconnects: + minItems: 1 + items: + - description: Interconnect path from mdp0 (or a single mdp) port to the data bus + - description: Interconnect path from mdp1 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + oneOf: + - minItems: 1 + items: + - const: mdp0-mem + - const: cpu-cfg + + - minItems: 2 + items: + - const: mdp0-mem + - const: mdp1-mem + - const: cpu-cfg + + resets: + items: + - description: MDSS_CORE reset + + memory-region: + maxItems: 1 + description: + Phandle to a node describing a reserved framebuffer memory region. + For example, the splash memory region set up by the bootloader. + +required: + - reg + - reg-names + - power-domains + - clocks + - interrupts + - interrupt-controller + - iommus + - ranges + +additionalProperties: true diff --git a/dts/Bindings/display/msm/qcom,mdp5.yaml b/dts/Bindings/display/msm/qcom,mdp5.yaml new file mode 100644 index 0000000000..91c774f106 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,mdp5.yaml @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,mdp5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Adreno/Snapdragon Mobile Display controller (MDP5) + +description: + MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 + and MSM8996. + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + - Rob Clark <robdclark@gmail.com> + +properties: + compatible: + oneOf: + - const: qcom,mdp5 + deprecated: true + - items: + - enum: + - qcom,apq8084-mdp5 + - qcom,msm8226-mdp5 + - qcom,msm8916-mdp5 + - qcom,msm8917-mdp5 + - qcom,msm8953-mdp5 + - qcom,msm8974-mdp5 + - qcom,msm8976-mdp5 + - qcom,msm8994-mdp5 + - qcom,msm8996-mdp5 + - qcom,sdm630-mdp5 + - qcom,sdm660-mdp5 + - const: qcom,mdp5 + + $nodename: + pattern: '^display-controller@[0-9a-f]+$' + + reg: + maxItems: 1 + + reg-names: + items: + - const: mdp_phys + + interrupts: + maxItems: 1 + + clocks: + minItems: 4 + maxItems: 7 + + clock-names: + oneOf: + - minItems: 4 + items: + - const: iface + - const: bus + - const: core + - const: vsync + - const: lut + - const: tbu + - const: tbu_rt + # MSM8996 has additional iommu clock + - items: + - const: iface + - const: bus + - const: core + - const: iommu + - const: vsync + + interconnects: + minItems: 1 + items: + - description: Interconnect path from mdp0 (or a single mdp) port to the data bus + - description: Interconnect path from mdp1 port to the data bus + - description: Interconnect path from rotator port to the data bus + + interconnect-names: + minItems: 1 + items: + - const: mdp0-mem + - const: mdp1-mem + - const: rotator-mem + + iommus: + items: + - description: apps SMMU with the Stream-ID mask for Hard-Fail port0 + + power-domains: + maxItems: 1 + + operating-points-v2: true + opp-table: + type: object + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: > + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. MDP5 devices support up to 4 ports: + one or two DSI ports, HDMI and eDP. + + patternProperties: + "^port@[0-3]+$": + $ref: /schemas/graph.yaml#/properties/port + + # at least one port is required + required: + - port@0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8916.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + display-controller@1a01000 { + compatible = "qcom,mdp5"; + reg = <0x1a01000 0x90000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,mdss.yaml b/dts/Bindings/display/msm/qcom,mdss.yaml new file mode 100644 index 0000000000..0999ea07f4 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,mdss.yaml @@ -0,0 +1,212 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Mobile Display SubSystem (MDSS) + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + - Rob Clark <robdclark@gmail.com> + +description: + This is the bindings documentation for the Mobile Display Subsystem(MDSS) that + encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc. + +properties: + $nodename: + pattern: "^display-subsystem@[0-9a-f]+$" + + compatible: + enum: + - qcom,mdss + + reg: + minItems: 2 + maxItems: 3 + + reg-names: + minItems: 2 + items: + - const: mdss_phys + - const: vbif_phys + - const: vbif_nrt_phys + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + power-domains: + maxItems: 1 + description: | + The MDSS power domain provided by GCC + + clocks: + oneOf: + - minItems: 3 + items: + - description: Display abh clock + - description: Display axi clock + - description: Display vsync clock + - description: Display core clock + - minItems: 1 + items: + - description: Display abh clock + - description: Display core clock + + clock-names: + oneOf: + - minItems: 3 + items: + - const: iface + - const: bus + - const: vsync + - const: core + - minItems: 1 + items: + - const: iface + - const: core + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + + resets: + items: + - description: MDSS_CORE reset + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-controller + - "#interrupt-cells" + - power-domains + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + - ranges + +patternProperties: + "^display-controller@[1-9a-f][0-9a-f]*$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,mdp5 + + "^dsi@[1-9a-f][0-9a-f]*$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,mdss-dsi-ctrl + + "^phy@[1-9a-f][0-9a-f]*$": + type: object + additionalProperties: true + properties: + compatible: + enum: + - qcom,dsi-phy-14nm + - qcom,dsi-phy-14nm-660 + - qcom,dsi-phy-14nm-8953 + - qcom,dsi-phy-20nm + - qcom,dsi-phy-28nm-8226 + - qcom,dsi-phy-28nm-hpm + - qcom,dsi-phy-28nm-lp + - qcom,hdmi-phy-8084 + - qcom,hdmi-phy-8660 + - qcom,hdmi-phy-8960 + - qcom,hdmi-phy-8974 + - qcom,hdmi-phy-8996 + + "^hdmi-tx@[1-9a-f][0-9a-f]*$": + type: object + additionalProperties: true + properties: + compatible: + enum: + - qcom,hdmi-tx-8084 + - qcom,hdmi-tx-8660 + - qcom,hdmi-tx-8960 + - qcom,hdmi-tx-8974 + - qcom,hdmi-tx-8994 + - qcom,hdmi-tx-8996 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8916.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + display-subsystem@1a00000 { + compatible = "qcom,mdss"; + reg = <0x1a00000 0x1000>, + <0x1ac8000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@1a01000 { + compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; + reg = <0x01a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + iommus = <&apps_iommu 4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,msm8998-dpu.yaml b/dts/Bindings/display/msm/qcom,msm8998-dpu.yaml new file mode 100644 index 0000000000..d5a64c8a92 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,msm8998-dpu.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,msm8998-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU on MSM8998 + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,msm8998-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for regdma register set + - description: Address offset and size for vbif register set + - description: Address offset and size for non-realtime vbif register set + + reg-names: + items: + - const: mdp + - const: regdma + - const: vbif + - const: vbif_nrt + + clocks: + items: + - description: Display ahb clock + - description: Display axi clock + - description: Display mem-noc clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: iface + - const: bus + - const: mnoc + - const: core + - const: vsync + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,mmcc-msm8998.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@c901000 { + compatible = "qcom,msm8998-dpu"; + reg = <0x0c901000 0x8f000>, + <0x0c9a8e00 0xf0>, + <0x0c9b0000 0x2008>, + <0x0c9b8000 0x1040>; + reg-names = "mdp", "regdma", "vbif", "vbif_nrt"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MNOC_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "mnoc", "core", "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd MSM8998_VDDMX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,msm8998-mdss.yaml b/dts/Bindings/display/msm/qcom,msm8998-mdss.yaml new file mode 100644 index 0000000000..2d9edab5a3 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,msm8998-mdss.yaml @@ -0,0 +1,278 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8998 Display MDSS + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS are mentioned for MSM8998 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,msm8998-mdss + + clocks: + items: + - description: Display AHB clock + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 1 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,msm8998-dpu + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,msm8998-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,dsi-phy-10nm-8998 + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,mmcc-msm8998.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@c900000 { + compatible = "qcom,msm8998-mdss"; + reg = <0x0c900000 0x1000>; + reg-names = "mdss"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + #address-cells = <1>; + #interrupt-cells = <1>; + #size-cells = <1>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + iommus = <&mmss_smmu 0>; + + power-domains = <&mmcc MDSS_GDSC>; + ranges; + + display-controller@c901000 { + compatible = "qcom,msm8998-dpu"; + reg = <0x0c901000 0x8f000>, + <0x0c9a8e00 0xf0>, + <0x0c9b0000 0x2008>, + <0x0c9b8000 0x1040>; + reg-names = "mdp", "regdma", "vbif", "vbif_nrt"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MNOC_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "mnoc", "core", "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd MSM8998_VDDMX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi@c994000 { + compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0c994000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_BYTE0_INTF_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd MSM8998_VDDCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@c994400 { + compatible = "qcom,dsi-phy-10nm-8998"; + reg = <0x0c994400 0x200>, + <0x0c994600 0x280>, + <0x0c994a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + vdds-supply = <&pm8998_l1>; + }; + + dsi@c996000 { + compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0c996000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_BYTE1_INTF_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd MSM8998_VDDCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@c996400 { + compatible = "qcom,dsi-phy-10nm-8998"; + reg = <0x0c996400 0x200>, + <0x0c996600 0x280>, + <0x0c996a00 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + vdds-supply = <&pm8998_l1>; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,qcm2290-dpu.yaml b/dts/Bindings/display/msm/qcom,qcm2290-dpu.yaml new file mode 100644 index 0000000000..be6cd8adb3 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,qcm2290-dpu.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU on QCM2290 + +maintainers: + - Loic Poulain <loic.poulain@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,qcm2290-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display AXI clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock from dispcc + - description: Display lut clock from dispcc + - description: Display vsync clock from dispcc + + clock-names: + items: + - const: bus + - const: iface + - const: core + - const: lut + - const: vsync + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-qcm2290.h> + #include <dt-bindings/clock/qcom,gcc-qcm2290.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@5e01000 { + compatible = "qcom,qcm2290-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "core", "lut", "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd QCM2290_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,qcm2290-mdss.yaml b/dts/Bindings/display/msm/qcom,qcm2290-mdss.yaml new file mode 100644 index 0000000000..f0cdb54226 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,qcm2290-mdss.yaml @@ -0,0 +1,215 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCM220 Display MDSS + +maintainers: + - Loic Poulain <loic.poulain@linaro.org> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS + are mentioned for QCM2290 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,qcm2290-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 2 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,qcm2290-dpu + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,qcm2290-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,dsi-phy-14nm-2290 + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-qcm2290.h> + #include <dt-bindings/clock/qcom,gcc-qcm2290.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,qcm2290.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@5e00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qcm2290-mdss"; + reg = <0x05e00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>, + <&bimc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + iommus = <&apps_smmu 0x420 0x2>, + <&apps_smmu 0x421 0x0>; + ranges; + + display-controller@5e01000 { + compatible = "qcom,qcm2290-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "core", "lut", "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd QCM2290_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi@5e94000 { + compatible = "qcom,qcm2290-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x05e94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd QCM2290_VDDCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@5e94400 { + compatible = "qcom,dsi-phy-14nm-2290"; + reg = <0x05e94400 0x100>, + <0x05e94500 0x300>, + <0x05e94800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + vcca-supply = <&vreg_dsi_phy>; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sc7180-dpu.yaml b/dts/Bindings/display/msm/qcom,sc7180-dpu.yaml new file mode 100644 index 0000000000..8137618237 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sc7180-dpu.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU on SC7180 + +maintainers: + - Krishna Manikandan <quic_mkrishn@quicinc.com> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + enum: + - qcom,sc7180-dpu + - qcom,sm6125-dpu + - qcom,sm6350-dpu + - qcom,sm6375-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + minItems: 6 + items: + - description: Display hf axi clock + - description: Display ahb clock + - description: Display rotator clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + - description: Display core throttle clock + + clock-names: + minItems: 6 + items: + - const: bus + - const: iface + - const: rot + - const: lut + - const: core + - const: vsync + - const: throttle + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +allOf: + - if: + properties: + compatible: + enum: + - qcom,sm6375-dpu + - qcom,sm6125-dpu + + then: + properties: + clocks: + minItems: 7 + + clock-names: + minItems: 7 + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc7180.h> + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@ae01000 { + compatible = "qcom,sc7180-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "rot", "lut", "core", + "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + endpoint { + remote-endpoint = <&dp_in>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sc7180-mdss.yaml b/dts/Bindings/display/msm/qcom,sc7180-mdss.yaml new file mode 100644 index 0000000000..7a0555b15d --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sc7180-mdss.yaml @@ -0,0 +1,322 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7180 Display MDSS + +maintainers: + - Krishna Manikandan <quic_mkrishn@quicinc.com> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS are mentioned for SC7180 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sc7180-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sc7180-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sc7180-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sc7180-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,dsi-phy-10nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc7180.h> + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sdm845.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sc7180-mdss"; + reg = <0xae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "ahb", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + iommus = <&apps_smmu 0x800 0x2>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sc7180-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "rot", "lut", "core", + "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC7180_CX>; + + phys = <&dsi_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + displayport-controller@ae90000 { + compatible = "qcom,sc7180-dp"; + + reg = <0xae90000 0x200>, + <0xae90200 0x200>, + <0xae90400 0xc00>, + <0xae91000 0x400>, + <0xae91400 0x400>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", "core_aux", "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; + phys = <&dp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SC7180_CX>; + + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sc7280-dpu.yaml b/dts/Bindings/display/msm/qcom,sc7280-dpu.yaml new file mode 100644 index 0000000000..b0fbe86219 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sc7280-dpu.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU on SC7280 + +maintainers: + - Krishna Manikandan <quic_mkrishn@quicinc.com> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sc7280-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc7280.h> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@ae01000 { + compatible = "qcom,sc7280-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&edp_in>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sc7280-mdss.yaml b/dts/Bindings/display/msm/qcom,sc7280-mdss.yaml new file mode 100644 index 0000000000..2947f27e05 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sc7280-mdss.yaml @@ -0,0 +1,443 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7280 Display MDSS + +maintainers: + - Krishna Manikandan <quic_mkrishn@quicinc.com> + +description: + Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS are mentioned for SC7280. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sc7280-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sc7280-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sc7280-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sc7280-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^edp@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sc7280-edp + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + enum: + - qcom,sc7280-dsi-phy-7nm + - qcom,sc7280-edp-phy + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc7280.h> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sc7280.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sc7280-mdss"; + reg = <0xae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_DISPLAY_CFG>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + iommus = <&apps_smmu 0x900 0x402>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sc7280-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf5_out: endpoint { + remote-endpoint = <&edp_in>; + }; + }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sc7280-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + phys = <&mdss_dsi_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi_phy: phy@ae94400 { + compatible = "qcom,sc7280-dsi-phy-7nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x280>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + vdds-supply = <&vreg_dsi_supply>; + }; + + edp@aea0000 { + compatible = "qcom,sc7280-edp"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hot_plug_det>; + + reg = <0xaea0000 0x200>, + <0xaea0200 0x200>, + <0xaea0400 0xc00>, + <0xaea1000 0x400>; + + interrupt-parent = <&mdss>; + interrupts = <14>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; + + phys = <&mdss_edp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&edp_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + edp_in: endpoint { + remote-endpoint = <&dpu_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_edp_out: endpoint { }; + }; + }; + + edp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_edp_phy: phy@aec2a00 { + compatible = "qcom,sc7280-edp-phy"; + + reg = <0xaec2a00 0x19c>, + <0xaec2200 0xa0>, + <0xaec2600 0xa0>, + <0xaec2000 0x1c0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb"; + + #clock-cells = <1>; + #phy-cells = <0>; + }; + + displayport-controller@ae90000 { + compatible = "qcom,sc7280-dp"; + + reg = <0xae90000 0x200>, + <0xae90200 0x200>, + <0xae90400 0xc00>, + <0xae91000 0x400>, + <0xae91400 0x400>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; + phys = <&dp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sc8280xp-dpu.yaml b/dts/Bindings/display/msm/qcom,sc8280xp-dpu.yaml new file mode 100644 index 0000000000..d19e3bec46 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sc8280xp-dpu.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP Display Processing Unit + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + Device tree bindings for SC8280XP Display Processing Unit. + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sc8280xp-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sc8280xp.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@ae01000 { + compatible = "qcom,sc8280xp-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <460000000>, + <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + interrupt-parent = <&mdss0>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&mdss0_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + endpoint { + remote-endpoint = <&mdss0_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + endpoint { + remote-endpoint = <&mdss0_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + endpoint { + remote-endpoint = <&mdss0_dp2_in>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sc8280xp-mdss.yaml b/dts/Bindings/display/msm/qcom,sc8280xp-mdss.yaml new file mode 100644 index 0000000000..af79406e16 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sc8280xp-mdss.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP Mobile Display Subsystem + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sc8280xp-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sc8280xp-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + enum: + - qcom,sc8280xp-dp + - qcom,sc8280xp-edp + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sc8280xp.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sc8280xp-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc0 MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + + resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x1000 0x402>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sc8280xp-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdss0_mdp_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + interrupt-parent = <&mdss0>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&mdss0_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + endpoint { + remote-endpoint = <&mdss0_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + endpoint { + remote-endpoint = <&mdss0_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + endpoint { + remote-endpoint = <&mdss0_dp2_in>; + }; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sdm670-mdss.yaml b/dts/Bindings/display/msm/qcom,sdm670-mdss.yaml new file mode 100644 index 0000000000..7dc269322b --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sdm670-mdss.yaml @@ -0,0 +1,292 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sdm670-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM670 Display MDSS + +maintainers: + - Richard Acayan <mailingradian@gmail.com> + +description: + SDM670 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sdm670-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: core + + iommus: + maxItems: 2 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sdm670-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sdm670-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + contains: + const: qcom,sdm670-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,dsi-phy-10nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sdm670-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sdm670-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SDM670_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96a00 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sdm845-dpu.yaml b/dts/Bindings/display/msm/qcom,sdm845-dpu.yaml new file mode 100644 index 0000000000..dc11fd421a --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sdm845-dpu.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU on SDM845 + +maintainers: + - Krishna Manikandan <quic_mkrishn@quicinc.com> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + enum: + - qcom,sdm670-dpu + - qcom,sdm845-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display GCC bus clock + - description: Display ahb clock + - description: Display axi clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: gcc-bus + - const: iface + - const: bus + - const: core + - const: vsync + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sdm845-mdss.yaml b/dts/Bindings/display/msm/qcom,sdm845-mdss.yaml new file mode 100644 index 0000000000..6e8b69e5ec --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sdm845-mdss.yaml @@ -0,0 +1,288 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM845 Display MDSS + +maintainers: + - Krishna Manikandan <quic_mkrishn@quicinc.com> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS are mentioned for SDM845 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sdm845-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: core + + iommus: + maxItems: 2 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sdm845-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sdm845-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sdm845-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,dsi-phy-10nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sdm845-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM845_CX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM845_CX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96a00 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm6115-dpu.yaml b/dts/Bindings/display/msm/qcom,sm6115-dpu.yaml new file mode 100644 index 0000000000..510eb6c193 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm6115-dpu.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU on SM6115 + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm6115-dpu + + reg: + items: + - description: MDP register set + - description: VBIF register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display AXI + - description: Display AHB + - description: Display core + - description: Display lut + - description: Display rotator + - description: Display vsync + + clock-names: + items: + - const: bus + - const: iface + - const: core + - const: lut + - const: rot + - const: vsync + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm6115.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@5e01000 { + compatible = "qcom,sm6115-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm6115-mdss.yaml b/dts/Bindings/display/msm/qcom,sm6115-mdss.yaml new file mode 100644 index 0000000000..309de1953c --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm6115-mdss.yaml @@ -0,0 +1,203 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6115 Display MDSS + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS + are mentioned for SM6115 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm6115-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock + - description: Display core clock + + iommus: + maxItems: 2 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm6115-dpu + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + oneOf: + - items: + - const: qcom,sm6115-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + - description: Old binding, please don't use + deprecated: true + const: qcom,dsi-ctrl-6g-qcm2290 + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,dsi-phy-14nm-2290 + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm6115.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@5e00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sm6115-mdss"; + reg = <0x05e00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x420 0x2>, + <&apps_smmu 0x421 0x0>; + ranges; + + display-controller@5e01000 { + compatible = "qcom,sm6115-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi@5e94000 { + compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x05e94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + phys = <&dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@5e94400 { + compatible = "qcom,dsi-phy-14nm-2290"; + reg = <0x05e94400 0x100>, + <0x05e94500 0x300>, + <0x05e94800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm6125-mdss.yaml b/dts/Bindings/display/msm/qcom,sm6125-mdss.yaml new file mode 100644 index 0000000000..3deb9dc81c --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm6125-mdss.yaml @@ -0,0 +1,223 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6125 Display MDSS + +maintainers: + - Marijn Suijten <marijn.suijten@somainline.org> + +description: + SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm6125-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm6125-dpu + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sm6125-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm6125-dsi-phy-14nm + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm6125.h> + #include <dt-bindings/clock/qcom,gcc-sm6125.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@5e00000 { + compatible = "qcom,sm6125-mdss"; + reg = <0x05e00000 0x1000>; + reg-names = "mdss"; + + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + + power-domains = <&dispcc MDSS_GDSC>; + + iommus = <&apps_smmu 0x400 0x0>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@5e01000 { + compatible = "qcom,sm6125-dpu"; + reg = <0x05e01000 0x83208>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>; + clock-names = "bus", + "iface", + "rot", + "lut", + "core", + "vsync", + "throttle"; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6125_VDDCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + }; + + dsi@5e94000 { + compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x05e94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SM6125_VDDCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + phy@5e94400 { + compatible = "qcom,sm6125-dsi-phy-14nm"; + reg = <0x05e94400 0x100>, + <0x05e94500 0x300>, + <0x05e94800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + + required-opps = <&rpmpd_opp_nom>; + power-domains = <&rpmpd SM6125_VDDMX>; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm6350-mdss.yaml b/dts/Bindings/display/msm/qcom,sm6350-mdss.yaml new file mode 100644 index 0000000000..c9ba1fae80 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm6350-mdss.yaml @@ -0,0 +1,216 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 Display MDSS + +maintainers: + - Krishna Manikandan <quic_mkrishn@quicinc.com> + +description: + SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm6350-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm6350-dpu + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sm6350-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,dsi-phy-10nm + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm6350.h> + #include <dt-bindings/clock/qcom,gcc-sm6350.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sm6350-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x800 0x2>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm6350-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "rot", "lut", "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + assigned-clock-rates = <300000000>, + <19200000>, + <19200000>, + <19200000>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM6350_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM6350_MX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm6375-mdss.yaml b/dts/Bindings/display/msm/qcom,sm6375-mdss.yaml new file mode 100644 index 0000000000..8e8a288d31 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm6375-mdss.yaml @@ -0,0 +1,218 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6375 Display MDSS + +maintainers: + - Konrad Dybcio <konrad.dybcio@linaro.org> + +description: + SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm6375-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm6375-dpu + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sm6375-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm6375-dsi-phy-7nm + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/clock/qcom,sm6375-gcc.h> + #include <dt-bindings/clock/qcom,sm6375-dispcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@5e00000 { + compatible = "qcom,sm6375-mdss"; + reg = <0x05e00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "ahb", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x820 0x2>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@5e01000 { + compatible = "qcom,sm6375-dpu"; + reg = <0x05e01000 0x8e030>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>; + clock-names = "bus", + "iface", + "rot", + "lut", + "core", + "vsync", + "throttle"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6375_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi@5e94000 { + compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x05e94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SM6375_VDDMX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@5e94400 { + compatible = "qcom,sm6375-dsi-phy-7nm"; + reg = <0x05e94400 0x200>, + <0x05e94600 0x280>, + <0x05e94900 0x264>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm8150-dpu.yaml b/dts/Bindings/display/msm/qcom,sm8150-dpu.yaml new file mode 100644 index 0000000000..13146b3f05 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm8150-dpu.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8150-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8150 Display DPU + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8150-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display ahb clock + - description: Display hf axi clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm8150.h> + #include <dt-bindings/clock/qcom,gcc-sm8150.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8150.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@ae01000 { + compatible = "qcom,sm8150-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8150_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm8150-mdss.yaml b/dts/Bindings/display/msm/qcom,sm8150-mdss.yaml new file mode 100644 index 0000000000..c0d6a4fdff --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm8150-mdss.yaml @@ -0,0 +1,338 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8150 Display MDSS + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS are mentioned for SM8150 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm8150-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm8150-dpu + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sm8150-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,dsi-phy-7nm-8150 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm8150.h> + #include <dt-bindings/clock/qcom,gcc-sm8150.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8150.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sm8150-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x800 0x420>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8150-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8150_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-171428571 { + opp-hz = /bits/ 64 <171428571>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8150_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-7nm-8150"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8150_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-7nm-8150"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm8250-dpu.yaml b/dts/Bindings/display/msm/qcom,sm8250-dpu.yaml new file mode 100644 index 0000000000..ffa5047e90 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm8250-dpu.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8250 Display DPU + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8250-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display ahb clock + - description: Display hf axi clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + - const: vsync + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm8250.h> + #include <dt-bindings/clock/qcom,gcc-sm8250.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8250.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + display-controller@ae01000 { + compatible = "qcom,sm8250-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm8250-mdss.yaml b/dts/Bindings/display/msm/qcom,sm8250-mdss.yaml new file mode 100644 index 0000000000..51368cda7b --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm8250-mdss.yaml @@ -0,0 +1,350 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8250 Display MDSS + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS are mentioned for SM8250 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm8250-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm8250-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sm8250-dp + - const: qcom,sm8350-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sm8250-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,dsi-phy-7nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm8250.h> + #include <dt-bindings/clock/qcom,gcc-sm8250.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8250.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sm8250-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x820 0x402>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8250-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm8350-dpu.yaml b/dts/Bindings/display/msm/qcom,sm8350-dpu.yaml new file mode 100644 index 0000000000..96ef2d9c35 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm8350-dpu.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Display DPU + +maintainers: + - Robert Foss <robert.foss@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8350-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm8350.h> + #include <dt-bindings/clock/qcom,gcc-sm8350.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8350.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + display-controller@ae01000 { + compatible = "qcom,sm8350-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm8350-mdss.yaml b/dts/Bindings/display/msm/qcom,sm8350-mdss.yaml new file mode 100644 index 0000000000..163fc83c1e --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm8350-mdss.yaml @@ -0,0 +1,237 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Display MDSS + +maintainers: + - Robert Foss <robert.foss@linaro.org> + +description: + MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm8350-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: mdp0-mem + - const: mdp1-mem + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm8350-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm8350-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sm8350-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm8350-dsi-phy-5nm + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm8350.h> + #include <dt-bindings/clock/qcom,gcc-sm8350.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8350.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sm8350-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + iommus = <&apps_smmu 0x820 0x402>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8350-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi0_phy>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm8450-dpu.yaml b/dts/Bindings/display/msm/qcom,sm8450-dpu.yaml new file mode 100644 index 0000000000..2a5d3daed0 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm8450-dpu.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 Display DPU + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8450-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi + - description: Display sf axi + - description: Display ahb + - description: Display lut + - description: Display core + - description: Display vsync + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8450.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + display-controller@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-172000000{ + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm8450-mdss.yaml b/dts/Bindings/display/msm/qcom,sm8450-mdss.yaml new file mode 100644 index 0000000000..747a2e9665 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm8450-mdss.yaml @@ -0,0 +1,364 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 Display MDSS + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: + SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm8450-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display sf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 3 + + interconnect-names: + maxItems: 3 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm8450-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sm8450-dp + - const: qcom,sm8350-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sm8450-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm8450-dsi-phy-5nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8450.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sm8450-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>, + <&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x2800 0x402>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-172000000{ + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160310000{ + opp-hz = /bits/ 64 <160310000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,sm8450-dsi-phy-5nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible = "qcom,sm8450-dsi-phy-5nm"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm8550-dpu.yaml b/dts/Bindings/display/msm/qcom,sm8550-dpu.yaml new file mode 100644 index 0000000000..16a541fca6 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm8550-dpu.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Display DPU + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8550-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display AHB + - description: Display hf axi + - description: Display MDSS ahb + - description: Display lut + - description: Display core + - description: Display vsync + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8550-dispcc.h> + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + display-controller@ae01000 { + compatible = "qcom,sm8550-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm8550-mdss.yaml b/dts/Bindings/display/msm/qcom,sm8550-mdss.yaml new file mode 100644 index 0000000000..1ea50a2c7c --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm8550-mdss.yaml @@ -0,0 +1,349 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Display MDSS + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +description: + SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm8550-mdss + + clocks: + items: + - description: Display MDSS AHB + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm8550-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sm8550-dp + - const: qcom,sm8350-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sm8550-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sm8550-dsi-phy-4nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8550-dispcc.h> + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sm8550-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8550-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,sm8550-dsi-phy-4nm"; + reg = <0x0ae95000 0x200>, + <0x0ae95200 0x280>, + <0x0ae95500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + }; + + dsi@ae96000 { + compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible = "qcom,sm8550-dsi-phy-4nm"; + reg = <0x0ae97000 0x200>, + <0x0ae97200 0x280>, + <0x0ae97500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm8650-dpu.yaml b/dts/Bindings/display/msm/qcom,sm8650-dpu.yaml new file mode 100644 index 0000000000..a01d15a033 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm8650-dpu.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8650 Display DPU + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8650-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi + - description: Display MDSS ahb + - description: Display lut + - description: Display core + - description: Display vsync + + clock-names: + items: + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + display-controller@ae01000 { + compatible = "qcom,sm8650-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc_axi_clk>, + <&dispcc_ahb_clk>, + <&dispcc_mdp_lut_clk>, + <&dispcc_mdp_clk>, + <&dispcc_vsync_clk>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc_vsync_clk>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/qcom,sm8650-mdss.yaml b/dts/Bindings/display/msm/qcom,sm8650-mdss.yaml new file mode 100644 index 0000000000..bd11119dc9 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,sm8650-mdss.yaml @@ -0,0 +1,328 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8650 Display MDSS + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +description: + SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm8650-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8650-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8650-dp + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm8650-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8650-dsi-phy-4nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sm8650-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + resets = <&dispcc_core_bcr>; + + power-domains = <&dispcc_gdsc>; + + clocks = <&gcc_ahb_clk>, + <&gcc_axi_clk>, + <&dispcc_mdp_clk>; + clock-names = "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8650-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc_axi_clk>, + <&dispcc_ahb_clk>, + <&dispcc_mdp_lut_clk>, + <&dispcc_mdp_clk>, + <&dispcc_mdp_vsync_clk>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc_mdp_vsync_clk>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispc_byte_clk>, + <&dispcc_intf_clk>, + <&dispcc_pclk>, + <&dispcc_esc_clk>, + <&dispcc_ahb_clk>, + <&gcc_bus_clk>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc_byte_clk>, + <&dispcc_pclk>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,sm8650-dsi-phy-4nm"; + reg = <0x0ae95000 0x200>, + <0x0ae95200 0x280>, + <0x0ae95500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc_iface_clk>, + <&rpmhcc_ref_clk>; + clock-names = "iface", "ref"; + }; + + dsi@ae96000 { + compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispc_byte_clk>, + <&dispcc_intf_clk>, + <&dispcc_pclk>, + <&dispcc_esc_clk>, + <&dispcc_ahb_clk>, + <&gcc_bus_clk>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc_byte_clk>, + <&dispcc_pclk>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible = "qcom,sm8650-dsi-phy-4nm"; + reg = <0x0ae97000 0x200>, + <0x0ae97200 0x280>, + <0x0ae97500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc_iface_clk>, + <&rpmhcc_ref_clk>; + clock-names = "iface", "ref"; + }; + }; +... diff --git a/dts/Bindings/display/panel/advantech,idk-1110wr.yaml b/dts/Bindings/display/panel/advantech,idk-1110wr.yaml index 3a8c2c11f9..f6fea9085a 100644 --- a/dts/Bindings/display/panel/advantech,idk-1110wr.yaml +++ b/dts/Bindings/display/panel/advantech,idk-1110wr.yaml @@ -12,7 +12,7 @@ maintainers: allOf: - $ref: panel-common.yaml# - - $ref: /schemas/display/lvds.yaml/# + - $ref: /schemas/display/lvds.yaml# select: properties: diff --git a/dts/Bindings/display/panel/advantech,idk-2121wr.yaml b/dts/Bindings/display/panel/advantech,idk-2121wr.yaml index 67682fe77f..2e8dbdb5a3 100644 --- a/dts/Bindings/display/panel/advantech,idk-2121wr.yaml +++ b/dts/Bindings/display/panel/advantech,idk-2121wr.yaml @@ -19,6 +19,9 @@ description: | second port, therefore the ports must be marked accordingly (with either dual-lvds-odd-pixels or dual-lvds-even-pixels). +allOf: + - $ref: panel-common.yaml# + properties: compatible: items: diff --git a/dts/Bindings/display/panel/arm,rtsm-display.yaml b/dts/Bindings/display/panel/arm,rtsm-display.yaml new file mode 100644 index 0000000000..4ad484f09b --- /dev/null +++ b/dts/Bindings/display/panel/arm,rtsm-display.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/arm,rtsm-display.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm RTSM Virtual Platforms Display + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: arm,rtsm-display + + port: true + +required: + - compatible + - port + +additionalProperties: false + +... diff --git a/dts/Bindings/display/panel/arm,versatile-tft-panel.yaml b/dts/Bindings/display/panel/arm,versatile-tft-panel.yaml index be69e0cc50..c9958f824d 100644 --- a/dts/Bindings/display/panel/arm,versatile-tft-panel.yaml +++ b/dts/Bindings/display/panel/arm,versatile-tft-panel.yaml @@ -37,9 +37,6 @@ examples: compatible = "arm,versatile-sysreg", "syscon", "simple-mfd"; reg = <0x00000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - panel { compatible = "arm,versatile-tft-panel"; diff --git a/dts/Bindings/display/panel/auo,a030jtn01.yaml b/dts/Bindings/display/panel/auo,a030jtn01.yaml new file mode 100644 index 0000000000..86c834eb4d --- /dev/null +++ b/dts/Bindings/display/panel/auo,a030jtn01.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/auo,a030jtn01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AUO A030JTN01 3.0" (320x480 pixels) 24-bit TFT LCD panel + +description: | + Delta RGB 8-bit panel found in some Retrogame handhelds + +maintainers: + - Paul Cercueil <paul@crapouillou.net> + - Christophe Branchereau <cbranchereau@gmail.com> + +allOf: + - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: auo,a030jtn01 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - power-supply + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "auo,a030jtn01"; + reg = <0>; + + spi-max-frequency = <10000000>; + + reset-gpios = <&gpe 4 GPIO_ACTIVE_LOW>; + power-supply = <&lcd_power>; + + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&panel_output>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/panel/boe,tv101wum-nl6.yaml b/dts/Bindings/display/panel/boe,tv101wum-nl6.yaml index a2384bd74c..906ef62709 100644 --- a/dts/Bindings/display/panel/boe,tv101wum-nl6.yaml +++ b/dts/Bindings/display/panel/boe,tv101wum-nl6.yaml @@ -30,6 +30,12 @@ properties: - boe,tv110c9m-ll3 # INX HJ110IZ-01A 10.95" WUXGA TFT LCD panel - innolux,hj110iz-01a + # STARRY 2081101QFH032011-53G 10.1" WUXGA TFT LCD panel + - starry,2081101qfh032011-53g + # STARRY himax83102-j02 10.51" WUXGA TFT LCD panel + - starry,himax83102-j02 + # STARRY ili9882t 10.51" WUXGA TFT LCD panel + - starry,ili9882t reg: description: the virtual channel number of a DSI peripheral @@ -53,6 +59,7 @@ properties: description: phandle of the backlight device attached to the panel port: true + rotation: true required: - compatible diff --git a/dts/Bindings/display/panel/display-timings.yaml b/dts/Bindings/display/panel/display-timings.yaml index 6d30575819..dc5f7e36e3 100644 --- a/dts/Bindings/display/panel/display-timings.yaml +++ b/dts/Bindings/display/panel/display-timings.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/panel/display-timings.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: display timings bindings +title: display timings maintainers: - Thierry Reding <thierry.reding@gmail.com> diff --git a/dts/Bindings/display/panel/ebbg,ft8719.yaml b/dts/Bindings/display/panel/ebbg,ft8719.yaml new file mode 100644 index 0000000000..80deedc01c --- /dev/null +++ b/dts/Bindings/display/panel/ebbg,ft8719.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/ebbg,ft8719.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EBBG FT8719 MIPI-DSI LCD panel + +maintainers: + - Joel Selvaraj <jo@jsfamily.in> + +description: | + The FT8719 panel from EBBG is a FHD+ LCD display panel with a resolution + of 1080x2246. It is a video mode DSI panel. The backlight is managed + through the QCOM WLED driver. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: ebbg,ft8719 + + reg: + maxItems: 1 + description: DSI virtual channel of the peripheral + + vddio-supply: + description: power IC supply regulator + + vddpos-supply: + description: positive boost supply regulator + + vddneg-supply: + description: negative boost supply regulator + +required: + - compatible + - reg + - vddio-supply + - vddpos-supply + - vddneg-supply + - reset-gpios + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "ebbg,ft8719"; + reg = <0>; + + vddio-supply = <&vreg_l14a_1p88>; + vddpos-supply = <&lab>; + vddneg-supply = <&ibb>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + backlight = <&pmi8998_wled>; + + port { + ebbg_ft8719_in_0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/panel/elida,kd35t133.yaml b/dts/Bindings/display/panel/elida,kd35t133.yaml index 7adb83e2e8..265ab6d305 100644 --- a/dts/Bindings/display/panel/elida,kd35t133.yaml +++ b/dts/Bindings/display/panel/elida,kd35t133.yaml @@ -17,7 +17,9 @@ properties: const: elida,kd35t133 reg: true backlight: true + port: true reset-gpios: true + rotation: true iovcc-supply: description: regulator that supplies the iovcc voltage vdd-supply: @@ -27,6 +29,7 @@ required: - compatible - reg - backlight + - port - iovcc-supply - vdd-supply @@ -43,6 +46,12 @@ examples: backlight = <&backlight>; iovcc-supply = <&vcc_1v8>; vdd-supply = <&vcc3v3_lcd>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; }; }; diff --git a/dts/Bindings/display/panel/fascontek,fs035vg158.yaml b/dts/Bindings/display/panel/fascontek,fs035vg158.yaml new file mode 100644 index 0000000000..d13c4bd26d --- /dev/null +++ b/dts/Bindings/display/panel/fascontek,fs035vg158.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/fascontek,fs035vg158.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Fascontek FS035VG158 3.5" (640x480 pixels) 24-bit IPS LCD panel + +maintainers: + - John Watts <contact@jookia.org> + +allOf: + - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: fascontek,fs035vg158 + + spi-3wire: true + +required: + - compatible + - reg + - port + - power-supply + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "fascontek,fs035vg158"; + reg = <0>; + + spi-3wire; + spi-max-frequency = <3125000>; + + reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>; + + backlight = <&backlight>; + power-supply = <&vcc>; + + port { + panel_input: endpoint { + remote-endpoint = <&panel_output>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/panel/feiyang,fy07024di26a30d.yaml b/dts/Bindings/display/panel/feiyang,fy07024di26a30d.yaml index 95acf9e96f..92df69e80a 100644 --- a/dts/Bindings/display/panel/feiyang,fy07024di26a30d.yaml +++ b/dts/Bindings/display/panel/feiyang,fy07024di26a30d.yaml @@ -26,6 +26,7 @@ properties: dvdd-supply: description: 3v3 digital regulator + port: true reset-gpios: true backlight: true @@ -35,7 +36,7 @@ required: - reg - avdd-supply - dvdd-supply - - reset-gpios + - port additionalProperties: false @@ -54,5 +55,11 @@ examples: dvdd-supply = <®_dldo2>; reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */ backlight = <&backlight>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; }; }; diff --git a/dts/Bindings/display/panel/focaltech,gpt3.yaml b/dts/Bindings/display/panel/focaltech,gpt3.yaml new file mode 100644 index 0000000000..d54e96b2a9 --- /dev/null +++ b/dts/Bindings/display/panel/focaltech,gpt3.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/focaltech,gpt3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Focaltech GPT3 3.0" (640x480 pixels) IPS LCD panel + +maintainers: + - Christophe Branchereau <cbranchereau@gmail.com> + +allOf: + - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: focaltech,gpt3 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - power-supply + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "focaltech,gpt3"; + reg = <0>; + + spi-max-frequency = <3125000>; + + reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>; + + backlight = <&backlight>; + power-supply = <&vcc>; + + port { + panel_input: endpoint { + remote-endpoint = <&panel_output>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/panel/himax,hx8394.yaml b/dts/Bindings/display/panel/himax,hx8394.yaml new file mode 100644 index 0000000000..916bb7f942 --- /dev/null +++ b/dts/Bindings/display/panel/himax,hx8394.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/himax,hx8394.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Himax HX8394 MIPI-DSI LCD panel controller + +maintainers: + - Ondrej Jirman <megi@xff.cz> + - Javier Martinez Canillas <javierm@redhat.com> + +description: + Device tree bindings for panels based on the Himax HX8394 controller, + such as the HannStar HSD060BHW4 720x1440 TFT LCD panel connected with + a MIPI-DSI video interface. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - hannstar,hsd060bhw4 + - powkiddy,x55-panel + - const: himax,hx8394 + + reg: true + + reset-gpios: true + + backlight: true + + rotation: true + + port: true + + vcc-supply: + description: Panel power supply + + iovcc-supply: + description: I/O voltage supply + +required: + - compatible + - reg + - reset-gpios + - backlight + - port + - vcc-supply + - iovcc-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "hannstar,hsd060bhw4", "himax,hx8394"; + reg = <0>; + vcc-supply = <®_2v8_p>; + iovcc-supply = <®_1v8_p>; + reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; + backlight = <&backlight>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/panel/ilitek,ili9163.yaml b/dts/Bindings/display/panel/ilitek,ili9163.yaml index 7e7a8362b9..3cabbba865 100644 --- a/dts/Bindings/display/panel/ilitek,ili9163.yaml +++ b/dts/Bindings/display/panel/ilitek,ili9163.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/panel/ilitek,ili9163.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ilitek ILI9163 display panels device tree bindings +title: Ilitek ILI9163 display panels maintainers: - Daniel Mack <daniel@zonque.org> @@ -15,6 +15,7 @@ description: allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: @@ -41,16 +42,12 @@ required: - dc-gpios - reset-gpios -additionalProperties: false +unevaluatedProperties: false examples: - | #include <dt-bindings/gpio/gpio.h> - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; - }; spi { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/display/panel/ilitek,ili9341.yaml b/dts/Bindings/display/panel/ilitek,ili9341.yaml index 6058948a97..94f169ea06 100644 --- a/dts/Bindings/display/panel/ilitek,ili9341.yaml +++ b/dts/Bindings/display/panel/ilitek,ili9341.yaml @@ -16,13 +16,16 @@ description: | allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: items: - enum: + - adafruit,yx240qv29 # ili9341 240*320 Color on stm32f429-disco board - st,sf-tc240t-9370-t + - canaan,kd233-tft - const: ilitek,ili9341 reg: true @@ -47,31 +50,50 @@ properties: vddi-led-supply: description: Voltage supply for the LED driver (1.65 .. 3.3 V) -additionalProperties: false +unevaluatedProperties: false required: - compatible - reg - dc-gpios - - port + +if: + properties: + compatible: + contains: + enum: + - st,sf-tc240t-9370-t +then: + required: + - port examples: - |+ + #include <dt-bindings/gpio/gpio.h> spi { #address-cells = <1>; #size-cells = <0>; panel: display@0 { - compatible = "st,sf-tc240t-9370-t", - "ilitek,ili9341"; - reg = <0>; - spi-3wire; - spi-max-frequency = <10000000>; - dc-gpios = <&gpiod 13 0>; - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; + compatible = "st,sf-tc240t-9370-t", + "ilitek,ili9341"; + reg = <0>; + spi-3wire; + spi-max-frequency = <10000000>; + dc-gpios = <&gpiod 13 0>; + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + display@1{ + compatible = "adafruit,yx240qv29", "ilitek,ili9341"; + reg = <1>; + spi-max-frequency = <10000000>; + dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + rotation = <270>; + backlight = <&backlight>; }; + }; ... diff --git a/dts/Bindings/display/panel/ilitek,ili9805.yaml b/dts/Bindings/display/panel/ilitek,ili9805.yaml new file mode 100644 index 0000000000..f4f91f93f4 --- /dev/null +++ b/dts/Bindings/display/panel/ilitek,ili9805.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/ilitek,ili9805.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ilitek ILI9805 based MIPI-DSI panels + +maintainers: + - Michael Trimarchi <michael@amarulasolutions.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - giantplus,gpm1790a0 + - tianma,tm041xdhg01 + - const: ilitek,ili9805 + + avdd-supply: true + dvdd-supply: true + reg: true + +required: + - compatible + - avdd-supply + - dvdd-supply + - reg + - reset-gpios + - port + - backlight + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "giantplus,gpm1790a0", "ilitek,ili9805"; + reg = <0>; + avdd-supply = <&avdd_display>; + dvdd-supply = <&dvdd_display>; + reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */ + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/panel/ilitek,ili9881c.yaml b/dts/Bindings/display/panel/ilitek,ili9881c.yaml index c5d1df6808..b1e624be3e 100644 --- a/dts/Bindings/display/panel/ilitek,ili9881c.yaml +++ b/dts/Bindings/display/panel/ilitek,ili9881c.yaml @@ -16,8 +16,10 @@ properties: compatible: items: - enum: + - ampire,am8001280g - bananapi,lhr050h41 - feixin,k101-im2byl02 + - tdo,tl050hdv35 - wanchanglong,w552946aba - const: ilitek,ili9881c diff --git a/dts/Bindings/display/panel/innolux,ee101ia-01d.yaml b/dts/Bindings/display/panel/innolux,ee101ia-01d.yaml index 566e11f6bf..ab6b7be883 100644 --- a/dts/Bindings/display/panel/innolux,ee101ia-01d.yaml +++ b/dts/Bindings/display/panel/innolux,ee101ia-01d.yaml @@ -12,7 +12,7 @@ maintainers: allOf: - $ref: panel-common.yaml# - - $ref: /schemas/display/lvds.yaml/# + - $ref: /schemas/display/lvds.yaml# select: properties: diff --git a/dts/Bindings/display/panel/innolux,p120zdg-bf1.yaml b/dts/Bindings/display/panel/innolux,p120zdg-bf1.yaml deleted file mode 100644 index 243dac2416..0000000000 --- a/dts/Bindings/display/panel/innolux,p120zdg-bf1.yaml +++ /dev/null @@ -1,43 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/panel/innolux,p120zdg-bf1.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel - -maintainers: - - Sandeep Panda <spanda@codeaurora.org> - - Douglas Anderson <dianders@chromium.org> - -allOf: - - $ref: panel-common.yaml# - -properties: - compatible: - const: innolux,p120zdg-bf1 - - enable-gpios: true - power-supply: true - backlight: true - no-hpd: true - -required: - - compatible - - power-supply - -additionalProperties: false - -examples: - - | - #include <dt-bindings/gpio/gpio.h> - - panel_edp: panel-edp { - compatible = "innolux,p120zdg-bf1"; - enable-gpios = <&msmgpio 31 GPIO_ACTIVE_LOW>; - power-supply = <&pm8916_l2>; - backlight = <&backlight>; - no-hpd; - }; - -... diff --git a/dts/Bindings/display/panel/jadard,jd9365da-h3.yaml b/dts/Bindings/display/panel/jadard,jd9365da-h3.yaml new file mode 100644 index 0000000000..41eb7fbf77 --- /dev/null +++ b/dts/Bindings/display/panel/jadard,jd9365da-h3.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/jadard,jd9365da-h3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Jadard JD9365DA-HE WXGA DSI panel + +maintainers: + - Jagan Teki <jagan@edgeble.ai> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - chongzhou,cz101b4001 + - radxa,display-10hd-ad001 + - radxa,display-8hd-ad002 + - const: jadard,jd9365da-h3 + + reg: true + + vdd-supply: + description: supply regulator for VDD, usually 3.3V + + vccio-supply: + description: supply regulator for VCCIO, usually 1.8V + + reset-gpios: true + + backlight: true + + port: true + +required: + - compatible + - reg + - vdd-supply + - vccio-supply + - reset-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/pinctrl/rockchip.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "chongzhou,cz101b4001", "jadard,jd9365da-h3"; + reg = <0>; + vdd-supply = <&lcd_3v3>; + vccio-supply = <&vcca_1v8>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/panel/jdi,lpm102a188a.yaml b/dts/Bindings/display/panel/jdi,lpm102a188a.yaml new file mode 100644 index 0000000000..2f4d27a309 --- /dev/null +++ b/dts/Bindings/display/panel/jdi,lpm102a188a.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/jdi,lpm102a188a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: JDI LPM102A188A 2560x1800 10.2" DSI Panel + +maintainers: + - Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> + +description: | + This panel requires a dual-channel DSI host to operate. It supports two modes: + - left-right: each channel drives the left or right half of the screen + - even-odd: each channel drives the even or odd lines of the screen + + Each of the DSI channels controls a separate DSI peripheral. The peripheral + driven by the first link (DSI-LINK1) is considered the primary peripheral + and controls the device. The 'link2' property contains a phandle to the + peripheral driven by the second link (DSI-LINK2). + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: jdi,lpm102a188a + + reg: true + enable-gpios: true + reset-gpios: true + power-supply: true + backlight: true + + ddi-supply: + description: The regulator that provides IOVCC (1.8V). + + link2: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + phandle to the DSI peripheral on the secondary link. Note that the + presence of this property marks the containing node as DSI-LINK1. + +required: + - compatible + - reg + +if: + required: + - link2 +then: + required: + - power-supply + - ddi-supply + - enable-gpios + - reset-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/gpio/tegra-gpio.h> + + dsia: dsi@54300000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x54300000 0x0 0x00040000>; + + link2: panel@0 { + compatible = "jdi,lpm102a188a"; + reg = <0>; + }; + }; + + dsib: dsi@54400000{ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x54400000 0x0 0x00040000>; + nvidia,ganged-mode = <&dsia>; + + link1: panel@0 { + compatible = "jdi,lpm102a188a"; + reg = <0>; + power-supply = <&pplcd_vdd>; + ddi-supply = <&pp1800_lcdio>; + enable-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + link2 = <&link2>; + backlight = <&backlight>; + }; + }; + +... diff --git a/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml b/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml index 2a2756d196..b4be9bd8dd 100644 --- a/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml +++ b/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml @@ -23,6 +23,8 @@ properties: reg: true reset-gpios: true + spi-3wire: true + required: - compatible - power-supply diff --git a/dts/Bindings/display/panel/leadtek,ltk035c5444t.yaml b/dts/Bindings/display/panel/leadtek,ltk035c5444t.yaml index 817a9bed7d..7a55961e1a 100644 --- a/dts/Bindings/display/panel/leadtek,ltk035c5444t.yaml +++ b/dts/Bindings/display/panel/leadtek,ltk035c5444t.yaml @@ -18,14 +18,12 @@ properties: compatible: const: leadtek,ltk035c5444t - backlight: true - port: true - power-supply: true - reg: true - reset-gpios: true + spi-3wire: true required: - compatible + - reg + - port - power-supply - reset-gpios diff --git a/dts/Bindings/display/panel/leadtek,ltk050h3146w.yaml b/dts/Bindings/display/panel/leadtek,ltk050h3146w.yaml index 3f6efbb942..a40ab887ad 100644 --- a/dts/Bindings/display/panel/leadtek,ltk050h3146w.yaml +++ b/dts/Bindings/display/panel/leadtek,ltk050h3146w.yaml @@ -17,6 +17,7 @@ properties: enum: - leadtek,ltk050h3146w - leadtek,ltk050h3146w-a2 + - leadtek,ltk050h3148w reg: true backlight: true reset-gpios: true diff --git a/dts/Bindings/display/panel/lg,lg4573.yaml b/dts/Bindings/display/panel/lg,lg4573.yaml index b4314ce7b4..ee357e139a 100644 --- a/dts/Bindings/display/panel/lg,lg4573.yaml +++ b/dts/Bindings/display/panel/lg,lg4573.yaml @@ -15,13 +15,13 @@ maintainers: allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: const: lg,lg4573 reg: true - spi-max-frequency: true required: - compatible diff --git a/dts/Bindings/display/panel/lgphilips,lb035q02.yaml b/dts/Bindings/display/panel/lgphilips,lb035q02.yaml index 5e4e0e552c..628c4b8981 100644 --- a/dts/Bindings/display/panel/lgphilips,lb035q02.yaml +++ b/dts/Bindings/display/panel/lgphilips,lb035q02.yaml @@ -21,6 +21,9 @@ properties: enable-gpios: true port: true + spi-cpha: true + spi-cpol: true + required: - compatible - enable-gpios diff --git a/dts/Bindings/display/panel/mantix,mlaf057we51-x.yaml b/dts/Bindings/display/panel/mantix,mlaf057we51-x.yaml index a4b8569ab8..74ff772973 100644 --- a/dts/Bindings/display/panel/mantix,mlaf057we51-x.yaml +++ b/dts/Bindings/display/panel/mantix,mlaf057we51-x.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/panel/mantix,mlaf057we51-x.yaml# diff --git a/dts/Bindings/display/panel/mitsubishi,aa104xd12.yaml b/dts/Bindings/display/panel/mitsubishi,aa104xd12.yaml index 5cf3c588f4..3623ffa651 100644 --- a/dts/Bindings/display/panel/mitsubishi,aa104xd12.yaml +++ b/dts/Bindings/display/panel/mitsubishi,aa104xd12.yaml @@ -12,7 +12,7 @@ maintainers: allOf: - $ref: panel-common.yaml# - - $ref: /schemas/display/lvds.yaml/# + - $ref: /schemas/display/lvds.yaml# select: properties: diff --git a/dts/Bindings/display/panel/mitsubishi,aa121td01.yaml b/dts/Bindings/display/panel/mitsubishi,aa121td01.yaml index 54750cc544..37f01d847a 100644 --- a/dts/Bindings/display/panel/mitsubishi,aa121td01.yaml +++ b/dts/Bindings/display/panel/mitsubishi,aa121td01.yaml @@ -12,7 +12,7 @@ maintainers: allOf: - $ref: panel-common.yaml# - - $ref: /schemas/display/lvds.yaml/# + - $ref: /schemas/display/lvds.yaml# select: properties: diff --git a/dts/Bindings/display/panel/nec,nl8048hl11.yaml b/dts/Bindings/display/panel/nec,nl8048hl11.yaml index aa788eaa2f..accf933d6e 100644 --- a/dts/Bindings/display/panel/nec,nl8048hl11.yaml +++ b/dts/Bindings/display/panel/nec,nl8048hl11.yaml @@ -15,6 +15,7 @@ maintainers: allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: @@ -34,13 +35,13 @@ required: - reset-gpios - port -additionalProperties: false +unevaluatedProperties: false examples: - | #include <dt-bindings/gpio/gpio.h> - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/display/panel/newvision,nv3051d.yaml b/dts/Bindings/display/panel/newvision,nv3051d.yaml new file mode 100644 index 0000000000..7a634fbc46 --- /dev/null +++ b/dts/Bindings/display/panel/newvision,nv3051d.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/newvision,nv3051d.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NewVision NV3051D based LCD panel + +description: | + The NewVision NV3051D is a driver chip used to drive DSI panels. + +maintainers: + - Chris Morgan <macromorgan@hotmail.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - anbernic,rg351v-panel + - anbernic,rg353p-panel + - powkiddy,rk2023-panel + - const: newvision,nv3051d + + reg: true + backlight: true + port: true + reset-gpios: + description: Active low reset GPIO + vdd-supply: true + +required: + - compatible + - reg + - backlight + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "anbernic,rg353p-panel", "newvision,nv3051d"; + reg = <0>; + backlight = <&backlight>; + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + vdd-supply = <&vcc3v3_lcd>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/panel/novatek,nt36523.yaml b/dts/Bindings/display/panel/novatek,nt36523.yaml new file mode 100644 index 0000000000..5f7e4c4860 --- /dev/null +++ b/dts/Bindings/display/panel/novatek,nt36523.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/novatek,nt36523.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek NT36523 based DSI display Panels + +maintainers: + - Jianhua Lu <lujianhua000@gmail.com> + +description: | + The Novatek NT36523 is a generic DSI Panel IC used to drive dsi + panels. Support video mode panels from China Star Optoelectronics + Technology (CSOT) and BOE Technology. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - xiaomi,elish-boe-nt36523 + - xiaomi,elish-csot-nt36523 + - const: novatek,nt36523 + - items: + - enum: + - lenovo,j606f-boe-nt36523w + - const: novatek,nt36523w + + reset-gpios: + maxItems: 1 + description: phandle of gpio for reset line - This should be 8mA + + vddio-supply: + description: regulator that supplies the I/O voltage + + reg: true + ports: true + rotation: true + backlight: true + +required: + - compatible + - reg + - vddio-supply + - reset-gpios + - ports + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "xiaomi,elish-csot-nt36523", "novatek,nt36523"; + reg = <0>; + + vddio-supply = <&vreg_l14a_1p88>; + reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; + backlight = <&backlight>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1{ + reg = <1>; + panel_in_1: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/panel/novatek,nt36672a.yaml b/dts/Bindings/display/panel/novatek,nt36672a.yaml index 563766d283..ae821f465e 100644 --- a/dts/Bindings/display/panel/novatek,nt36672a.yaml +++ b/dts/Bindings/display/panel/novatek,nt36672a.yaml @@ -34,7 +34,7 @@ properties: description: phandle of gpio for reset line - This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names (active high) - vddi0-supply: + vddio-supply: description: phandle of the regulator that provides the supply voltage Power IC supply @@ -46,11 +46,12 @@ properties: reg: true port: true + backlight: true required: - compatible - reg - - vddi0-supply + - vddio-supply - vddpos-supply - vddneg-supply - reset-gpios @@ -69,10 +70,11 @@ examples: panel@0 { compatible = "tianma,fhd-video", "novatek,nt36672a"; reg = <0>; - vddi0-supply = <&vreg_l14a_1p88>; + vddio-supply = <&vreg_l14a_1p88>; vddpos-supply = <&lab>; vddneg-supply = <&ibb>; + backlight = <&pmi8998_wled>; reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; port { diff --git a/dts/Bindings/display/panel/olimex,lcd-olinuxino.yaml b/dts/Bindings/display/panel/olimex,lcd-olinuxino.yaml index 2329d9610f..72463795e4 100644 --- a/dts/Bindings/display/panel/olimex,lcd-olinuxino.yaml +++ b/dts/Bindings/display/panel/olimex,lcd-olinuxino.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/panel/olimex,lcd-olinuxino.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Binding for Olimex Ltd. LCD-OLinuXino bridge panel. +title: Olimex Ltd. LCD-OLinuXino bridge panel. maintainers: - Stefan Mavrodiev <stefan@olimex.com> @@ -20,7 +20,7 @@ description: | The panel itself contains: - AT24C16C EEPROM holding panel identification and timing requirements - AR1021 resistive touch screen controller (optional) - - FT5x6 capacitive touch screnn controller (optional) + - FT5x6 capacitive touch screen controller (optional) - GT911/GT928 capacitive touch screen controller (optional) The above chips share same I2C bus. The EEPROM is factory preprogrammed with diff --git a/dts/Bindings/display/panel/orisetech,otm8009a.yaml b/dts/Bindings/display/panel/orisetech,otm8009a.yaml index ad7d357519..1e4f140f48 100644 --- a/dts/Bindings/display/panel/orisetech,otm8009a.yaml +++ b/dts/Bindings/display/panel/orisetech,otm8009a.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/panel/orisetech,otm8009a.yaml# diff --git a/dts/Bindings/display/panel/panel-common.yaml b/dts/Bindings/display/panel/panel-common.yaml index 5b38dc89cb..0a57a31f4f 100644 --- a/dts/Bindings/display/panel/panel-common.yaml +++ b/dts/Bindings/display/panel/panel-common.yaml @@ -12,7 +12,7 @@ maintainers: description: | This document defines device tree properties common to several classes of - display panels. It doesn't constitue a device tree binding specification by + display panels. It doesn't constitute a device tree binding specification by itself but is meant to be referenced by device tree bindings. When referenced from panel device tree bindings the properties defined in this diff --git a/dts/Bindings/display/panel/panel-dsi-cm.yaml b/dts/Bindings/display/panel/panel-dsi-cm.yaml index 4a36aa64c7..f8dc9929e8 100644 --- a/dts/Bindings/display/panel/panel-dsi-cm.yaml +++ b/dts/Bindings/display/panel/panel-dsi-cm.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/panel/panel-dsi-cm.yaml# diff --git a/dts/Bindings/display/panel/panel-lvds.yaml b/dts/Bindings/display/panel/panel-lvds.yaml index fcc50db6a8..9f1016551e 100644 --- a/dts/Bindings/display/panel/panel-lvds.yaml +++ b/dts/Bindings/display/panel/panel-lvds.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/panel/panel-lvds.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Generic LVDS Display Panel Device Tree Bindings +title: Generic LVDS Display Panel maintainers: - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> @@ -12,7 +12,7 @@ maintainers: allOf: - $ref: panel-common.yaml# - - $ref: /schemas/display/lvds.yaml/# + - $ref: /schemas/display/lvds.yaml# select: properties: @@ -40,6 +40,12 @@ properties: items: - enum: - auo,b101ew05 + # Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel + - chunghwa,claa070wp03xg + # HannStar Display Corp. HSD101PWW2 10.1" WXGA (1280x800) LVDS panel + - hannstar,hsd101pww2 + # Hydis Technologies 7" WXGA (800x1280) TFT LCD LVDS panel + - hydis,hv070wx2-1e0 - tbs,a711-panel - const: panel-lvds diff --git a/dts/Bindings/display/panel/panel-mipi-dbi-spi.yaml b/dts/Bindings/display/panel/panel-mipi-dbi-spi.yaml index c2df8d28aa..e808215cb3 100644 --- a/dts/Bindings/display/panel/panel-mipi-dbi-spi.yaml +++ b/dts/Bindings/display/panel/panel-mipi-dbi-spi.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml# @@ -22,8 +22,9 @@ description: | The standard defines the following interface signals for type C: - Power: - Vdd: Power supply for display module + Called power-supply in this binding. - Vddi: Logic level supply for interface signals - Combined into one in this binding called: power-supply + Called io-supply in this binding. - Interface: - CSx: Chip select - SCL: Serial clock @@ -65,7 +66,9 @@ properties: compatible: items: - enum: + - saef,sftc154b - sainsmart18 + - shineworld,lh133k - const: panel-mipi-dbi-spi write-only: @@ -80,6 +83,13 @@ properties: Controller data/command selection (D/CX) in 4-line SPI mode. If not set, the controller is in 3-line SPI mode. + io-supply: + description: | + Logic level supply for interface signals (Vddi). + No need to set if this is the same as power-supply. + + spi-3wire: true + required: - compatible - reg diff --git a/dts/Bindings/display/panel/panel-simple-dsi.yaml b/dts/Bindings/display/panel/panel-simple-dsi.yaml index 2c00813f5d..f9160d7bac 100644 --- a/dts/Bindings/display/panel/panel-simple-dsi.yaml +++ b/dts/Bindings/display/panel/panel-simple-dsi.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/panel/panel-simple-dsi.yaml# @@ -19,9 +19,6 @@ description: | If the panel is more advanced a dedicated binding file is required. -allOf: - - $ref: panel-common.yaml# - properties: compatible: @@ -45,6 +42,8 @@ properties: - lg,acx467akm-7 # LG Corporation 7" WXGA TFT LCD panel - lg,ld070wx3-sl01 + # LG Corporation 5" HD TFT LCD panel + - lg,lh500wx1-sd03 # One Stop Displays OSD101T2587-53TS 10.1" 1920x1200 panel - osddisplays,osd101t2587-53ts # Panasonic 10" WUXGA TFT LCD panel @@ -67,12 +66,31 @@ properties: reset-gpios: true port: true power-supply: true + vddio-supply: true + +allOf: + - $ref: panel-common.yaml# + - if: + properties: + compatible: + enum: + - samsung,s6e3fc2x01 + - samsung,sofef00 + then: + properties: + power-supply: false + required: + - vddio-supply + else: + properties: + vddio-supply: false + required: + - power-supply additionalProperties: false required: - compatible - - power-supply - reg examples: diff --git a/dts/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml b/dts/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml new file mode 100644 index 0000000000..716ece5f39 --- /dev/null +++ b/dts/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/panel-simple-lvds-dual-ports.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple LVDS panels with one power supply and dual LVDS ports + +maintainers: + - Liu Ying <victor.liu@nxp.com> + - Thierry Reding <thierry.reding@gmail.com> + - Sam Ravnborg <sam@ravnborg.org> + +description: | + This binding file is a collection of the LVDS panels that + has dual LVDS ports and requires only a single power-supply. + The first port receives odd pixels, and the second port receives even pixels. + There are optionally a backlight and an enable GPIO. + The panel may use an OF graph binding for the association to the display, + or it may be a direct child node of the display. + + If the panel is more advanced a dedicated binding file is required. + +allOf: + - $ref: panel-common.yaml# + +properties: + + compatible: + enum: + # compatible must be listed in alphabetical order, ordered by compatible. + # The description in the comment is mandatory for each compatible. + + # AU Optronics Corporation 13.3" FHD (1920x1080) TFT LCD panel + - auo,g133han01 + # AU Optronics Corporation 15.6" FHD (1920x1080) TFT LCD panel + - auo,g156han04 + # AU Optronics Corporation 18.5" FHD (1920x1080) TFT LCD panel + - auo,g185han01 + # AU Optronics Corporation 19.0" (1280x1024) TFT LCD panel + - auo,g190ean01 + # Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel + - koe,tx26d202vm0bwa + # NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel + - nlt,nl192108ac18-02d + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: The first sink port. + + properties: + dual-lvds-odd-pixels: + type: boolean + description: The first sink port for odd pixels. + + required: + - dual-lvds-odd-pixels + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: The second sink port. + + properties: + dual-lvds-even-pixels: + type: boolean + description: The second sink port for even pixels. + + required: + - dual-lvds-even-pixels + + required: + - port@0 + - port@1 + + backlight: true + enable-gpios: true + power-supply: true + +additionalProperties: false + +required: + - compatible + - ports + - power-supply + +examples: + - | + panel: panel-lvds { + compatible = "koe,tx26d202vm0bwa"; + power-supply = <&vdd_lcd_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + dual-lvds-odd-pixels; + reg = <0>; + + panel_lvds0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@1 { + dual-lvds-even-pixels; + reg = <1>; + + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/panel/panel-simple.yaml b/dts/Bindings/display/panel/panel-simple.yaml index 21ba90c9fe..634a10c6f2 100644 --- a/dts/Bindings/display/panel/panel-simple.yaml +++ b/dts/Bindings/display/panel/panel-simple.yaml @@ -21,9 +21,9 @@ description: | allOf: - $ref: panel-common.yaml# + - $ref: ../lvds-data-mapping.yaml# properties: - compatible: enum: # compatible must be listed in alphabetical order, ordered by compatible. @@ -33,8 +33,12 @@ properties: - ampire,am-1280800n3tzqw-t00h # Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel - ampire,am-480272h3tmqw-t01h + # Ampire AM-800480L1TMQW-T00H 5" WVGA TFT LCD panel + - ampire,am-800480l1tmqw-t00h # Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel - ampire,am800480r3tmqwa1h + # Ampire AM-800600P5TMQW-TB8H 8.0" SVGA TFT LCD panel + - ampire,am800600p5tmqw-tb8h # AU Optronics Corporation 10.1" WSVGA TFT LCD panel - auo,b101aw03 # AU Optronics Corporation 10.1" WSVGA TFT LCD panel @@ -61,20 +65,18 @@ properties: - auo,g104sn02 # AU Optronics Corporation 12.1" (1280x800) TFT LCD panel - auo,g121ean01 - # AU Optronics Corporation 13.3" FHD (1920x1080) TFT LCD panel - - auo,g133han01 # AU Optronics Corporation 15.6" (1366x768) TFT LCD panel - auo,g156xtn01 - # AU Optronics Corporation 18.5" FHD (1920x1080) TFT LCD panel - - auo,g185han01 - # AU Optronics Corporation 19.0" (1280x1024) TFT LCD panel - - auo,g190ean01 # AU Optronics Corporation 31.5" FHD (1920x1080) TFT LCD panel - auo,p320hvn03 # AU Optronics Corporation 21.5" FHD (1920x1080) color TFT LCD panel - auo,t215hvn01 # Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel - avic,tm070ddh03 + # BOE BP101WX1-100 10.1" WXGA (1280x800) LVDS panel + - boe,bp101wx1-100 + # BOE EV121WXM-N10-1850 12.1" WXGA (1280x800) TFT LCD panel + - boe,ev121wxm-n10-1850 # BOE HV070WSA-100 7.01" WSVGA TFT LCD panel - boe,hv070wsa-100 # BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel @@ -97,8 +99,6 @@ properties: - cdtech,s070wv95-ct16 # Chefree CH101OLHLWH-002 10.1" (1280x800) color TFT LCD panel - chefree,ch101olhlwh-002 - # Chunghwa Picture Tubes Ltd. 7" WXGA TFT LCD panel - - chunghwa,claa070wp03xg # Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel - chunghwa,claa101wa01a # Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel @@ -107,6 +107,8 @@ properties: - chunghwa,claa101wb03 # DataImage, Inc. 4.3" WQVGA (480x272) TFT LCD panel with 24-bit parallel interface. - dataimage,fg040346dsswbg04 + # DataImage, Inc. 10.1" WXGA (1280×800) TFT LCD panel + - dataimage,fg1001l0dsswmg01 # DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface. - dataimage,scf0700c48ggu18 # DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel @@ -137,11 +139,15 @@ properties: # Emerging Display Technology Corp. WVGA TFT Display with capacitive touch - edt,etm0700g0dh6 - edt,etm0700g0edh6 + # Emerging Display Technology Corp. LVDS WSVGA TFT Display with capacitive touch + - edt,etml0700y5dha # Emerging Display Technology Corp. 5.7" VGA TFT LCD panel with # capacitive touch - edt,etmv570g2dhu # E Ink VB3300-KCA - eink,vb3300-kca + # Evervision Electronics Co. Ltd. VGG644804 5.7" VGA TFT LCD Panel + - evervision,vgg644804 # Evervision Electronics Co. Ltd. VGG804821 5.0" WVGA TFT LCD Panel - evervision,vgg804821 # Foxlink Group 5" WVGA TFT LCD panel @@ -166,6 +172,8 @@ properties: - innolux,at043tn24 # Innolux AT070TN92 7.0" WQVGA TFT LCD panel - innolux,at070tn92 + # Innolux G070ACE-L01 7" WVGA (800x480) TFT LCD panel + - innolux,g070ace-l01 # Innolux G070Y2-L01 7" WVGA (800x480) TFT LCD panel - innolux,g070y2-l01 # Innolux G070Y2-T02 7" WVGA (800x480) TFT LCD TTL panel @@ -182,16 +190,18 @@ properties: - innolux,n116bge # InnoLux 13.3" FHD (1920x1080) eDP TFT LCD panel - innolux,n125hce-gn1 + # InnoLux 15.6" FHD (1920x1080) TFT LCD panel + - innolux,g156hce-l01 # InnoLux 15.6" WXGA TFT LCD panel - innolux,n156bge-l21 + # Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel + - innolux,p120zdg-bf1 # Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel - innolux,zj070na-01p # King & Display KD116N21-30NV-A010 eDP TFT LCD panel - kingdisplay,kd116n21-30nv-a010 # Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel - koe,tx14d24vm1bpa - # Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel - - koe,tx26d202vm0bwa # Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel - koe,tx31d200vm0baa # Kyocera Corporation 7" WVGA (800x480) transmissive color TFT @@ -202,8 +212,6 @@ properties: - lemaker,bl035-rgb-002 # LG 7" (800x480 pixels) TFT LCD panel - lg,lb070wv8 - # LG Corporation 5" HD TFT LCD panel - - lg,lh500wx1-sd03 # LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel - lg,lp079qx1-sp0v # LG 9.7" (2048x1536 pixels) TFT LCD panel @@ -224,8 +232,12 @@ properties: - logictechno,lttd800480070-l6wh-rt # Mitsubishi "AA070MC01 7.0" WVGA TFT LCD panel - mitsubishi,aa070mc01-ca1 + # Mitsubishi AA084XE01 8.4" XGA TFT LCD panel + - mitsubishi,aa084xe01 # Multi-Inno Technology Co.,Ltd MI0700S4T-6 7" 800x480 TFT Resistive Touch Module - multi-inno,mi0700s4t-6 + # Multi-Inno Technology Co.,Ltd MI0800FT-9 8" 800x600 TFT Resistive Touch Module + - multi-inno,mi0800ft-9 # Multi-Inno Technology Co.,Ltd MI1010AIT-1CP 10.1" 1280x800 LVDS IPS Cap Touch Mod. - multi-inno,mi1010ait-1cp # NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel @@ -238,8 +250,6 @@ properties: - neweast,wjfh116008a # Newhaven Display International 480 x 272 TFT LCD panel - newhaven,nhd-4.3-480272ef-atxl - # NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel - - nlt,nl192108ac18-02d # New Vision Display 7.0" 800 RGB x 480 TFT LCD panel - nvd,9128 # OKAYA Electric America, Inc. RS800480T-7X0GP 7" WVGA LCD panel @@ -268,10 +278,14 @@ properties: - rocktech,rk101ii01d-ct # Rocktech Display Ltd. RK070ER9427 800(RGB)x480 TFT LCD panel - rocktech,rk070er9427 + # Rocktech Display Ltd. RK043FN48H 4.3" 480x272 LCD-TFT panel + - rocktech,rk043fn48h # Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel - samsung,atna33xc20 # Samsung 12.2" (2560x1600 pixels) TFT LCD panel - samsung,lsn122dl01-c01 + # Samsung Electronics 10.1" WXGA (1280x800) TFT LCD panel + - samsung,ltl101al01 # Samsung Electronics 10.1" WSVGA TFT LCD panel - samsung,ltn101nt05 # Samsung Electronics 14" WXGA (1366x768) TFT LCD panel @@ -337,6 +351,17 @@ properties: power-supply: true no-hpd: true hpd-gpios: true + data-mapping: true + +if: + not: + properties: + compatible: + contains: + const: innolux,g101ice-l01 +then: + properties: + data-mapping: false additionalProperties: false @@ -356,3 +381,16 @@ examples: }; }; }; + - | + panel_lvds: panel-lvds { + compatible = "innolux,g101ice-l01"; + power-supply = <&vcc_lcd_reg>; + + data-mapping = "jeida-24"; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <<dc_out_lvds>; + }; + }; + }; diff --git a/dts/Bindings/display/panel/panel-timing.yaml b/dts/Bindings/display/panel/panel-timing.yaml index 229e3b36ee..aea69b84ca 100644 --- a/dts/Bindings/display/panel/panel-timing.yaml +++ b/dts/Bindings/display/panel/panel-timing.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: panel timing bindings +title: panel timing maintainers: - Thierry Reding <thierry.reding@gmail.com> @@ -17,29 +17,29 @@ description: | The parameters are defined as seen in the following illustration. - +----------+-------------------------------------+----------+-------+ - | | ^ | | | - | | |vback_porch | | | - | | v | | | - +----------#######################################----------+-------+ - | # ^ # | | - | # | # | | - | hback # | # hfront | hsync | - | porch # | hactive # porch | len | - |<-------->#<-------+--------------------------->#<-------->|<----->| - | # | # | | - | # |vactive # | | - | # | # | | - | # v # | | - +----------#######################################----------+-------+ - | | ^ | | | - | | |vfront_porch | | | - | | v | | | - +----------+-------------------------------------+----------+-------+ - | | ^ | | | - | | |vsync_len | | | - | | v | | | - +----------+-------------------------------------+----------+-------+ + +-------+----------+-------------------------------------+----------+ + | | | ^ | | + | | | |vsync_len | | + | | | v | | + +-------+----------+-------------------------------------+----------+ + | | | ^ | | + | | | |vback_porch | | + | | | v | | + +-------+----------#######################################----------+ + | | # ^ # | + | | # | # | + | hsync | hback # | # hfront | + | len | porch # | hactive # porch | + |<----->|<-------->#<-------+--------------------------->#<-------->| + | | # | # | + | | # |vactive # | + | | # | # | + | | # v # | + +-------+----------#######################################----------+ + | | | ^ | | + | | | |vfront_porch | | + | | | v | | + +-------+----------+-------------------------------------+----------+ The following is the panel timings shown with time on the x-axis. diff --git a/dts/Bindings/display/panel/raydium,rm67191.yaml b/dts/Bindings/display/panel/raydium,rm67191.yaml index 617aa8c8c0..d62fd692bf 100644 --- a/dts/Bindings/display/panel/raydium,rm67191.yaml +++ b/dts/Bindings/display/panel/raydium,rm67191.yaml @@ -38,6 +38,7 @@ properties: 0 - burst-mode 1 - non-burst with sync event 2 - non-burst with sync pulse + $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2] required: diff --git a/dts/Bindings/display/panel/raydium,rm68200.yaml b/dts/Bindings/display/panel/raydium,rm68200.yaml index e8ce231563..46fe1014eb 100644 --- a/dts/Bindings/display/panel/raydium,rm68200.yaml +++ b/dts/Bindings/display/panel/raydium,rm68200.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/panel/raydium,rm68200.yaml# diff --git a/dts/Bindings/display/panel/raydium,rm692e5.yaml b/dts/Bindings/display/panel/raydium,rm692e5.yaml new file mode 100644 index 0000000000..f436ba6738 --- /dev/null +++ b/dts/Bindings/display/panel/raydium,rm692e5.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/raydium,rm692e5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Raydium RM692E5 based DSI display panels + +maintainers: + - Konrad Dybcio <konradybcio@kernel.org> + +description: + The Raydium RM692E5 is a generic DSI Panel IC used to control + AMOLED panels. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - const: fairphone,fp5-rm692e5-boe + - const: raydium,rm692e5 + + dvdd-supply: + description: Digital voltage rail + + vci-supply: + description: Analog voltage rail + + vddio-supply: + description: I/O voltage rail + + reg: true + port: true + +required: + - compatible + - reg + - reset-gpios + - dvdd-supply + - vci-supply + - vddio-supply + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "fairphone,fp5-rm692e5-boe", "raydium,rm692e5"; + reg = <0>; + + reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; + dvdd-supply = <&vreg_oled_vci>; + vci-supply = <&vreg_l12c>; + vddio-supply = <&vreg_oled_dvdd>; + + port { + panel_in_0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/panel/rocktech,jh057n00900.yaml b/dts/Bindings/display/panel/rocktech,jh057n00900.yaml index 09b5eb7542..97cccd8a84 100644 --- a/dts/Bindings/display/panel/rocktech,jh057n00900.yaml +++ b/dts/Bindings/display/panel/rocktech,jh057n00900.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/panel/rocktech,jh057n00900.yaml# @@ -20,6 +20,10 @@ allOf: properties: compatible: enum: + # Anberic RG353V-V2 5.0" 640x480 TFT LCD panel + - anbernic,rg353v-panel-v2 + # Powkiddy RGB30 3.0" 720x720 TFT LCD panel + - powkiddy,rgb30-panel # Rocktech JH057N00900 5.5" 720x1440 TFT LCD panel - rocktech,jh057n00900 # Xingbangda XBD599 5.99" 720x1440 TFT LCD panel diff --git a/dts/Bindings/display/panel/ronbo,rb070d30.yaml b/dts/Bindings/display/panel/ronbo,rb070d30.yaml index d67617f6f7..95ce22c678 100644 --- a/dts/Bindings/display/panel/ronbo,rb070d30.yaml +++ b/dts/Bindings/display/panel/ronbo,rb070d30.yaml @@ -37,7 +37,7 @@ properties: backlight: description: Backlight used by the panel - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle required: - compatible diff --git a/dts/Bindings/display/panel/samsung,ams495qa01.yaml b/dts/Bindings/display/panel/samsung,ams495qa01.yaml new file mode 100644 index 0000000000..58fa073ce2 --- /dev/null +++ b/dts/Bindings/display/panel/samsung,ams495qa01.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,ams495qa01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung AMS495QA01 panel with Magnachip D53E6EA8966 controller + +maintainers: + - Chris Morgan <macromorgan@hotmail.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: samsung,ams495qa01 + + reg: true + reset-gpios: + description: reset gpio, must be GPIO_ACTIVE_LOW + elvdd-supply: + description: regulator that supplies voltage to the panel display + enable-gpios: true + port: true + vdd-supply: + description: regulator that supplies voltage to panel logic + +required: + - compatible + - reg + - reset-gpios + - vdd-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "samsung,ams495qa01"; + reg = <0>; + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + vdd-supply = <&vcc_3v3>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/panel/samsung,ld9040.yaml b/dts/Bindings/display/panel/samsung,ld9040.yaml index d525165d6d..c0fabeb386 100644 --- a/dts/Bindings/display/panel/samsung,ld9040.yaml +++ b/dts/Bindings/display/panel/samsung,ld9040.yaml @@ -42,6 +42,9 @@ properties: panel-height-mm: description: physical panel height [mm] + spi-cpha: true + spi-cpol: true + required: - compatible - reg diff --git a/dts/Bindings/display/panel/samsung,lms380kf01.yaml b/dts/Bindings/display/panel/samsung,lms380kf01.yaml index 251f0c7115..70ffc88d2a 100644 --- a/dts/Bindings/display/panel/samsung,lms380kf01.yaml +++ b/dts/Bindings/display/panel/samsung,lms380kf01.yaml @@ -9,14 +9,13 @@ title: Samsung LMS380KF01 display panel description: The LMS380KF01 is a 480x800 DPI display panel from Samsung Mobile Displays (SMD) utilizing the WideChips WS2401 display controller. It can be used with internal or external backlight control. - The panel must obey the rules for a SPI slave device as specified in - spi/spi-controller.yaml maintainers: - Linus Walleij <linus.walleij@linaro.org> allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: @@ -59,7 +58,7 @@ required: - spi-cpol - port -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/display/panel/samsung,lms397kf04.yaml b/dts/Bindings/display/panel/samsung,lms397kf04.yaml index cd62968426..5e77cee93f 100644 --- a/dts/Bindings/display/panel/samsung,lms397kf04.yaml +++ b/dts/Bindings/display/panel/samsung,lms397kf04.yaml @@ -14,6 +14,7 @@ maintainers: allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: @@ -51,7 +52,7 @@ required: - spi-cpol - port -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/display/panel/samsung,s6d27a1.yaml b/dts/Bindings/display/panel/samsung,s6d27a1.yaml index 26e3c820a2..d273faf444 100644 --- a/dts/Bindings/display/panel/samsung,s6d27a1.yaml +++ b/dts/Bindings/display/panel/samsung,s6d27a1.yaml @@ -7,14 +7,14 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung S6D27A1 display panel description: The S6D27A1 is a 480x800 DPI display panel from Samsung Mobile - Displays (SMD). The panel must obey the rules for a SPI slave device - as specified in spi/spi-controller.yaml + Displays (SMD). maintainers: - Markuss Broks <markuss.broks@gmail.com> allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: diff --git a/dts/Bindings/display/panel/samsung,s6d7aa0.yaml b/dts/Bindings/display/panel/samsung,s6d7aa0.yaml new file mode 100644 index 0000000000..45a236d2cc --- /dev/null +++ b/dts/Bindings/display/panel/samsung,s6d7aa0.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,s6d7aa0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S6D7AA0 MIPI-DSI LCD panel controller + +maintainers: + - Artur Weber <aweber.kernel@gmail.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + # 1280x800 LSL080AL02 panel + - samsung,lsl080al02 + # 1024x768 LSL080AL03 panel + - samsung,lsl080al03 + # 1024x768 LTL101AT01 panel + - samsung,ltl101at01 + - const: samsung,s6d7aa0 + + reg: true + + backlight: + description: + Backlight to use for the panel. If this property is set on panels + that have DSI-based backlight control (LSL080AL03 and LTL101AT01), + it overrides the DSI-based backlight. + + reset-gpios: + description: Reset GPIO pin, usually GPIO_ACTIVE_LOW. + + power-supply: + description: + Main power supply for the panel; the exact voltage differs between + panels, and is usually somewhere around 3.3-5v. + + vmipi-supply: + description: VMIPI supply, usually 1.8v. + +required: + - compatible + - reg + - reset-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,lsl080al02", "samsung,s6d7aa0"; + reg = <0>; + power-supply = <&display_3v3_supply>; + reset-gpios = <&gpf0 4 GPIO_ACTIVE_LOW>; + backlight = <&backlight>; + }; + }; + +... diff --git a/dts/Bindings/display/panel/samsung,s6e63m0.yaml b/dts/Bindings/display/panel/samsung,s6e63m0.yaml index 940f7f8852..6f1fc7469f 100644 --- a/dts/Bindings/display/panel/samsung,s6e63m0.yaml +++ b/dts/Bindings/display/panel/samsung,s6e63m0.yaml @@ -24,6 +24,10 @@ properties: default-brightness: true max-brightness: true + spi-3wire: true + spi-cpha: true + spi-cpol: true + vdd3-supply: description: VDD regulator diff --git a/dts/Bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml b/dts/Bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml index 44ce98f687..b749e9e906 100644 --- a/dts/Bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml +++ b/dts/Bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml @@ -16,6 +16,7 @@ properties: compatible: const: samsung,s6e88a0-ams452ef01 reg: true + port: true reset-gpios: true vdd3-supply: description: core voltage supply @@ -25,6 +26,7 @@ properties: required: - compatible - reg + - port - vdd3-supply - vci-supply - reset-gpios @@ -46,5 +48,11 @@ examples: vdd3-supply = <&pm8916_l17>; vci-supply = <®_vlcd_vci>; reset-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; }; }; diff --git a/dts/Bindings/display/panel/samsung,s6e8aa0.yaml b/dts/Bindings/display/panel/samsung,s6e8aa0.yaml index 1cdc91b343..200fbf1c74 100644 --- a/dts/Bindings/display/panel/samsung,s6e8aa0.yaml +++ b/dts/Bindings/display/panel/samsung,s6e8aa0.yaml @@ -74,7 +74,7 @@ examples: vdd3-supply = <&vcclcd_reg>; vci-supply = <&vlcd_reg>; reset-gpios = <&gpy4 5 0>; - power-on-delay= <50>; + power-on-delay = <50>; reset-delay = <100>; init-delay = <100>; panel-width-mm = <58>; diff --git a/dts/Bindings/display/panel/seiko,43wvf1g.yaml b/dts/Bindings/display/panel/seiko,43wvf1g.yaml index cfaa50cf5f..1df3cbb51f 100644 --- a/dts/Bindings/display/panel/seiko,43wvf1g.yaml +++ b/dts/Bindings/display/panel/seiko,43wvf1g.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480) TFT with Touch-Panel maintainers: - - Marco Franchi <marco.franchi@nxp.com> + - Fabio Estevam <festevam@gmail.com> allOf: - $ref: panel-common.yaml# @@ -25,6 +25,8 @@ properties: avdd-supply: description: 5v analog regulator + enable-gpios: true + required: - compatible - dvdd-supply diff --git a/dts/Bindings/display/panel/sgd,gktw70sdae4se.yaml b/dts/Bindings/display/panel/sgd,gktw70sdae4se.yaml index 44e02decdf..e32d9188a3 100644 --- a/dts/Bindings/display/panel/sgd,gktw70sdae4se.yaml +++ b/dts/Bindings/display/panel/sgd,gktw70sdae4se.yaml @@ -7,12 +7,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Solomon Goldentek Display GKTW70SDAE4SE 7" WVGA LVDS Display Panel maintainers: - - Neil Armstrong <narmstrong@baylibre.com> + - Neil Armstrong <neil.armstrong@linaro.org> - Thierry Reding <thierry.reding@gmail.com> allOf: - $ref: panel-common.yaml# - - $ref: /schemas/display/lvds.yaml/# + - $ref: /schemas/display/lvds.yaml# select: properties: diff --git a/dts/Bindings/display/panel/sharp,lq101r1sx01.yaml b/dts/Bindings/display/panel/sharp,lq101r1sx01.yaml index a679d3647d..57b44a0e76 100644 --- a/dts/Bindings/display/panel/sharp,lq101r1sx01.yaml +++ b/dts/Bindings/display/panel/sharp,lq101r1sx01.yaml @@ -30,7 +30,12 @@ allOf: properties: compatible: - const: sharp,lq101r1sx01 + oneOf: + - items: + - const: sharp,lq101r1sx03 + - const: sharp,lq101r1sx01 + - enum: + - sharp,lq101r1sx01 reg: true power-supply: true diff --git a/dts/Bindings/display/panel/sitronix,st7701.yaml b/dts/Bindings/display/panel/sitronix,st7701.yaml index 6dff59fe4b..b348f5bf0a 100644 --- a/dts/Bindings/display/panel/sitronix,st7701.yaml +++ b/dts/Bindings/display/panel/sitronix,st7701.yaml @@ -17,6 +17,9 @@ description: | Techstar TS8550B is 480x854, 2-lane MIPI DSI LCD panel which has inbuilt ST7701 chip. + Densitron DMT028VGHMCMI-1A is 480x640, 2-lane MIPI DSI LCD panel + which has built-in ST7701 chip. + allOf: - $ref: panel-common.yaml# @@ -24,6 +27,9 @@ properties: compatible: items: - enum: + - anbernic,rg-arc-panel + - densitron,dmt028vghmcmi-1a + - elida,kd50t048a - techstar,ts8550b - const: sitronix,st7701 @@ -37,7 +43,9 @@ properties: IOVCC-supply: description: I/O system regulator + port: true reset-gpios: true + rotation: true backlight: true @@ -46,6 +54,7 @@ required: - reg - VCC-supply - IOVCC-supply + - port - reset-gpios additionalProperties: false @@ -65,5 +74,11 @@ examples: IOVCC-supply = <®_dldo2>; reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */ backlight = <&backlight>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; }; }; diff --git a/dts/Bindings/display/panel/sitronix,st7789v.yaml b/dts/Bindings/display/panel/sitronix,st7789v.yaml index 9e1d707c2a..ef162b51d0 100644 --- a/dts/Bindings/display/panel/sitronix,st7789v.yaml +++ b/dts/Bindings/display/panel/sitronix,st7789v.yaml @@ -15,18 +15,33 @@ allOf: properties: compatible: - const: sitronix,st7789v + enum: + - edt,et028013dma + - inanbo,t28cp45tn89-v17 + - jasonic,jt240mhqs-hwt-ek-e3 + - sitronix,st7789v reg: true reset-gpios: true power-supply: true backlight: true port: true + rotation: true + + spi-cpha: true + spi-cpol: true + + spi-rx-bus-width: + minimum: 0 + maximum: 1 + + dc-gpios: + maxItems: 1 + description: DCX pin, Display data/command selection pin in parallel interface required: - compatible - reg - - reset-gpios - power-supply unevaluatedProperties: false @@ -45,6 +60,7 @@ examples: reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; backlight = <&pwm_bl>; power-supply = <&power>; + rotation = <180>; spi-max-frequency = <100000>; spi-cpol; spi-cpha; diff --git a/dts/Bindings/display/panel/sony,td4353-jdi.yaml b/dts/Bindings/display/panel/sony,td4353-jdi.yaml new file mode 100644 index 0000000000..b6b885b4c2 --- /dev/null +++ b/dts/Bindings/display/panel/sony,td4353-jdi.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sony,td4353-jdi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony TD4353 JDI 5 / 5.7" 2160x1080 MIPI-DSI Panel + +maintainers: + - Konrad Dybcio <konrad.dybcio@somainline.org> + +description: | + The Sony TD4353 JDI is a 5 (XZ2c) / 5.7 (XZ2) inch 2160x1080 + MIPI-DSI panel, used in Xperia XZ2 and XZ2 Compact smartphones. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: sony,td4353-jdi-tama + + reg: true + + backlight: true + + vddio-supply: + description: VDDIO 1.8V supply + + vsp-supply: + description: Positive 5.5V supply + + vsn-supply: + description: Negative 5.5V supply + + panel-reset-gpios: + description: Display panel reset pin + + touch-reset-gpios: + description: Touch panel reset pin + + port: true + +required: + - compatible + - reg + - vddio-supply + - vsp-supply + - vsn-supply + - panel-reset-gpios + - touch-reset-gpios + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel: panel@0 { + compatible = "sony,td4353-jdi-tama"; + reg = <0>; + + backlight = <&pmi8998_wled>; + vddio-supply = <&vreg_l14a_1p8>; + vsp-supply = <&lab>; + vsn-supply = <&ibb>; + panel-reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + touch-reset-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/panel/startek,kd070fhfid015.yaml b/dts/Bindings/display/panel/startek,kd070fhfid015.yaml new file mode 100644 index 0000000000..d817f998cd --- /dev/null +++ b/dts/Bindings/display/panel/startek,kd070fhfid015.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/startek,kd070fhfid015.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Startek Electronic Technology Co. kd070fhfid015 7 inch TFT LCD panel + +maintainers: + - Alexandre Mergnat <amergnat@baylibre.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: startek,kd070fhfid015 + + enable-gpios: true + + iovcc-supply: + description: Reference to the regulator powering the panel IO pins. + + reg: + maxItems: 1 + description: DSI virtual channel + + reset-gpios: true + + port: true + + power-supply: true + +additionalProperties: false + +required: + - compatible + - enable-gpios + - iovcc-supply + - reg + - reset-gpios + - port + - power-supply + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "startek,kd070fhfid015"; + reg = <0>; + enable-gpios = <&pio 67 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + iovcc-supply = <&mt6357_vsim1_reg>; + power-supply = <&vsys_lcm_reg>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/panel/synaptics,r63353.yaml b/dts/Bindings/display/panel/synaptics,r63353.yaml new file mode 100644 index 0000000000..e5617d1255 --- /dev/null +++ b/dts/Bindings/display/panel/synaptics,r63353.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/synaptics,r63353.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synaptics R63353 based MIPI-DSI panels + +maintainers: + - Michael Trimarchi <michael@amarulasolutions.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - sharp,ls068b3sx02 + - const: syna,r63353 + + avdd-supply: true + dvdd-supply: true + reg: true + +required: + - compatible + - avdd-supply + - dvdd-supply + - reg + - reset-gpios + - port + - backlight + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "sharp,ls068b3sx02", "syna,r63353"; + reg = <0>; + avdd-supply = <&avdd_display>; + dvdd-supply = <&dvdd_display>; + reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */ + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/panel/tpo,td.yaml b/dts/Bindings/display/panel/tpo,td.yaml index f902a9d741..e8c8ee8d7c 100644 --- a/dts/Bindings/display/panel/tpo,td.yaml +++ b/dts/Bindings/display/panel/tpo,td.yaml @@ -28,6 +28,9 @@ properties: backlight: true port: true + spi-cpha: true + spi-cpol: true + required: - compatible - port diff --git a/dts/Bindings/display/panel/tpo,tpg110.yaml b/dts/Bindings/display/panel/tpo,tpg110.yaml index 6f1f02044b..f0243d1961 100644 --- a/dts/Bindings/display/panel/tpo,tpg110.yaml +++ b/dts/Bindings/display/panel/tpo,tpg110.yaml @@ -41,6 +41,7 @@ description: |+ allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: diff --git a/dts/Bindings/display/panel/visionox,r66451.yaml b/dts/Bindings/display/panel/visionox,r66451.yaml new file mode 100644 index 0000000000..6ba3236839 --- /dev/null +++ b/dts/Bindings/display/panel/visionox,r66451.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/visionox,r66451.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Visionox R66451 AMOLED DSI Panel + +maintainers: + - Jessica Zhang <quic_jesszhan@quicinc.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: visionox,r66451 + + reg: + maxItems: 1 + description: DSI virtual channel + + vddio-supply: true + vdd-supply: true + port: true + reset-gpios: true + +additionalProperties: false + +required: + - compatible + - reg + - vddio-supply + - vdd-supply + - reset-gpios + - port + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "visionox,r66451"; + reg = <0>; + vddio-supply = <&vreg_l12c_1p8>; + vdd-supply = <&vreg_l13c_3p0>; + + reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/panel/visionox,rm69299.yaml b/dts/Bindings/display/panel/visionox,rm69299.yaml index 076b057b4a..fa745a6f44 100644 --- a/dts/Bindings/display/panel/visionox,rm69299.yaml +++ b/dts/Bindings/display/panel/visionox,rm69299.yaml @@ -1,10 +1,10 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/panel/visionox,rm69299.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Visionox model RM69299 Panels Device Tree Bindings. +title: Visionox model RM69299 Panels maintainers: - Harigovindan P <harigovi@codeaurora.org> @@ -19,6 +19,8 @@ properties: compatible: const: visionox,rm69299-1080p-display + reg: true + vdda-supply: description: | Phandle of the regulator that provides the vdda supply voltage. @@ -34,6 +36,7 @@ additionalProperties: false required: - compatible + - reg - vdda-supply - vdd3p3-supply - reset-gpios @@ -41,16 +44,22 @@ required: examples: - | - panel { - compatible = "visionox,rm69299-1080p-display"; + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "visionox,rm69299-1080p-display"; + reg = <0>; - vdda-supply = <&src_pp1800_l8c>; - vdd3p3-supply = <&src_pp2800_l18a>; + vdda-supply = <&src_pp1800_l8c>; + vdd3p3-supply = <&src_pp2800_l18a>; - reset-gpios = <&pm6150l_gpio 3 0>; - port { - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; + reset-gpios = <&pm6150l_gpio 3 0>; + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; }; }; }; diff --git a/dts/Bindings/display/panel/visionox,vtdr6130.yaml b/dts/Bindings/display/panel/visionox,vtdr6130.yaml new file mode 100644 index 0000000000..d5a8295106 --- /dev/null +++ b/dts/Bindings/display/panel/visionox,vtdr6130.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/visionox,vtdr6130.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Visionox VTDR6130 AMOLED DSI Panel + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: visionox,vtdr6130 + + reg: + maxItems: 1 + description: DSI virtual channel + + vddio-supply: true + vci-supply: true + vdd-supply: true + port: true + reset-gpios: true + +additionalProperties: false + +required: + - compatible + - reg + - vddio-supply + - vci-supply + - vdd-supply + - reset-gpios + - port + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/panel/xinpeng,xpp055c272.yaml b/dts/Bindings/display/panel/xinpeng,xpp055c272.yaml index d5c46a3cc2..c407deb6af 100644 --- a/dts/Bindings/display/panel/xinpeng,xpp055c272.yaml +++ b/dts/Bindings/display/panel/xinpeng,xpp055c272.yaml @@ -17,6 +17,7 @@ properties: const: xinpeng,xpp055c272 reg: true backlight: true + port: true reset-gpios: true iovcc-supply: description: regulator that supplies the iovcc voltage @@ -27,6 +28,7 @@ required: - compatible - reg - backlight + - port - iovcc-supply - vci-supply @@ -44,6 +46,12 @@ examples: backlight = <&backlight>; iovcc-supply = <&vcc_1v8>; vci-supply = <&vcc3v3_lcd>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; }; }; diff --git a/dts/Bindings/display/renesas,du.yaml b/dts/Bindings/display/renesas,du.yaml index b3e5880220..c5b9e6812b 100644 --- a/dts/Bindings/display/renesas,du.yaml +++ b/dts/Bindings/display/renesas,du.yaml @@ -40,6 +40,7 @@ properties: - renesas,du-r8a77990 # for R-Car E3 compatible DU - renesas,du-r8a77995 # for R-Car D3 compatible DU - renesas,du-r8a779a0 # for R-Car V3U compatible DU + - renesas,du-r8a779g0 # for R-Car V4H compatible DU reg: maxItems: 1 @@ -75,7 +76,7 @@ properties: unevaluatedProperties: false renesas,cmms: - $ref: "/schemas/types.yaml#/definitions/phandle-array" + $ref: /schemas/types.yaml#/definitions/phandle-array items: maxItems: 1 description: @@ -83,7 +84,7 @@ properties: available DU channel. renesas,vsps: - $ref: "/schemas/types.yaml#/definitions/phandle-array" + $ref: /schemas/types.yaml#/definitions/phandle-array items: items: - description: phandle to VSP instance that serves the DU channel @@ -762,6 +763,7 @@ allOf: contains: enum: - renesas,du-r8a779a0 + - renesas,du-r8a779g0 then: properties: clocks: diff --git a/dts/Bindings/display/renesas,shmobile-lcdc.yaml b/dts/Bindings/display/renesas,shmobile-lcdc.yaml new file mode 100644 index 0000000000..9816c4cacc --- /dev/null +++ b/dts/Bindings/display/renesas,shmobile-lcdc.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/renesas,shmobile-lcdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH-Mobile LCD Controller (LCDC) + +maintainers: + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> + - Geert Uytterhoeven <geert+renesas@glider.be> + +properties: + compatible: + enum: + - renesas,r8a7740-lcdc # R-Mobile A1 + - renesas,sh73a0-lcdc # SH-Mobile AG5 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 5 + description: + Only the functional clock is mandatory. + Some of the optional clocks are model-dependent (e.g. "video" (a.k.a. + "vou" or "dv_clk") is available on R-Mobile A1 only). + + clock-names: + minItems: 1 + items: + - const: fck + - enum: [ media, lclk, hdmi, video ] + - enum: [ media, lclk, hdmi, video ] + - enum: [ media, lclk, hdmi, video ] + - enum: [ media, lclk, hdmi, video ] + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: LCD port (R-Mobile A1 and SH-Mobile AG5) + unevaluatedProperties: false + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI port (R-Mobile A1 LCDC1 and SH-Mobile AG5) + unevaluatedProperties: false + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: MIPI-DSI port (SH-Mobile AG5) + unevaluatedProperties: false + + required: + - port@0 + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - ports + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r8a7740-lcdc + then: + properties: + ports: + properties: + port@2: false + + - if: + properties: + compatible: + contains: + const: renesas,sh73a0-lcdc + then: + properties: + ports: + required: + - port@1 + - port@2 + +examples: + - | + #include <dt-bindings/clock/r8a7740-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + lcd-controller@fe940000 { + compatible = "renesas,r8a7740-lcdc"; + reg = <0xfe940000 0x4000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7740_CLK_LCDC0>, + <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk0_clk>, + <&vou_clk>; + clock-names = "fck", "media", "lclk", "video"; + power-domains = <&pd_a4lc>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lcdc0_rgb: endpoint { + }; + }; + }; + }; diff --git a/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt b/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt deleted file mode 100644 index 43561584c1..0000000000 --- a/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt +++ /dev/null @@ -1,98 +0,0 @@ -Rockchip RK3288 specific extensions to the Analogix Display Port -================================ - -Required properties: -- compatible: "rockchip,rk3288-dp", - "rockchip,rk3399-edp"; - -- reg: physical base address of the controller and length - -- clocks: from common clock binding: handle to dp clock. - of memory mapped region. - -- clock-names: from common clock binding: - Required elements: "dp" "pclk" - -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - -- pinctrl-names: Names corresponding to the chip hotplug pinctrl states. -- pinctrl-0: pin-control mode. should be <&edp_hpd> - -- reset-names: Must include the name "dp" - -- rockchip,grf: this soc should set GRF regs, so need get grf here. - -- ports: there are 2 port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - Port 0: contained 2 endpoints, connecting to the output of vop. - Port 1: contained 1 endpoint, connecting to the input of panel. - -Optional property for different chips: -- clocks: from common clock binding: handle to grf_vio clock. - -- clock-names: from common clock binding: - Required elements: "grf" - -For the below properties, please refer to Analogix DP binding document: - * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt -- phys (required) -- phy-names (required) -- hpd-gpios (optional) -- force-hpd (optional) -------------------------------------------------------------------------------- - -Example: - dp-controller: dp@ff970000 { - compatible = "rockchip,rk3288-dp"; - reg = <0xff970000 0x4000>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; - clock-names = "dp", "pclk"; - phys = <&dp_phy>; - phy-names = "dp"; - - rockchip,grf = <&grf>; - resets = <&cru 111>; - reset-names = "dp"; - - pinctrl-names = "default"; - pinctrl-0 = <&edp_hpd>; - - - ports { - #address-cells = <1>; - #size-cells = <0>; - edp_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - edp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_edp>; - }; - edp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_edp>; - }; - }; - - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - edp_out_panel: endpoint { - reg = <0>; - remote-endpoint = <&panel_in_edp> - }; - }; - }; - }; - - pinctrl { - edp { - edp_hpd: edp-hpd { - rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - }; diff --git a/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt deleted file mode 100644 index 39792f051d..0000000000 --- a/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ /dev/null @@ -1,93 +0,0 @@ -Rockchip specific extensions to the Synopsys Designware MIPI DSI -================================ - -Required properties: -- #address-cells: Should be <1>. -- #size-cells: Should be <0>. -- compatible: one of - "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi" - "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi" - "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi" -- reg: Represent the physical address range of the controller. -- interrupts: Represent the controller's interrupt to the CPU(s). -- clocks, clock-names: Phandles to the controller's pll reference - clock(ref) when using an internal dphy and APB clock(pclk). - For RK3399, a phy config clock (phy_cfg) and a grf clock(grf) - are required. As described in [1]. -- rockchip,grf: this soc should set GRF regs to mux vopl/vopb. -- ports: contain a port node with endpoint definitions as defined in [2]. - For vopb,set the reg = <0> and set the reg = <1> for vopl. -- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl -- video port 1 for either a panel or subsequent encoder - -Optional properties: -- phys: from general PHY binding: the phandle for the PHY device. -- phy-names: Should be "dphy" if phys references an external phy. -- #phy-cells: Defined when used as ISP phy, should be 0. -- power-domains: a phandle to mipi dsi power domain node. -- resets: list of phandle + reset specifier pairs, as described in [3]. -- reset-names: string reset name, must be "apb". - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/media/video-interfaces.txt -[3] Documentation/devicetree/bindings/reset/reset.txt - -Example: - mipi_dsi: mipi@ff960000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0xff960000 0x4000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>; - clock-names = "ref", "pclk"; - resets = <&cru SRST_MIPIDSI0>; - reset-names = "apb"; - rockchip,grf = <&grf>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mipi_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_mipi>; - }; - mipi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_mipi>; - }; - }; - - mipi_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_out_panel: endpoint { - remote-endpoint = <&panel_in_mipi>; - }; - }; - }; - - panel { - compatible ="boe,tv080wum-nl0"; - reg = <0>; - - enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_en>; - backlight = <&backlight>; - - port { - panel_in_mipi: endpoint { - remote-endpoint = <&mipi_out_panel>; - }; - }; - }; - }; diff --git a/dts/Bindings/display/rockchip/inno_hdmi-rockchip.txt b/dts/Bindings/display/rockchip/inno_hdmi-rockchip.txt deleted file mode 100644 index cec21714f0..0000000000 --- a/dts/Bindings/display/rockchip/inno_hdmi-rockchip.txt +++ /dev/null @@ -1,49 +0,0 @@ -Rockchip specific extensions to the Innosilicon HDMI -================================ - -Required properties: -- compatible: - "rockchip,rk3036-inno-hdmi"; -- reg: - Physical base address and length of the controller's registers. -- clocks, clock-names: - Phandle to hdmi controller clock, name should be "pclk" -- interrupts: - HDMI interrupt number -- ports: - Contain one port node with endpoint definitions as defined in - Documentation/devicetree/bindings/graph.txt. -- pinctrl-0, pinctrl-name: - Switch the iomux of HPD/CEC pins to HDMI function. - -Example: -hdmi: hdmi@20034000 { - compatible = "rockchip,rk3036-inno-hdmi"; - reg = <0x20034000 0x4000>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_HDMI>; - clock-names = "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_ctl>; - - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_lcdc: endpoint@0 { - reg = <0>; - remote-endpoint = <&lcdc_out_hdmi>; - }; - }; -}; - -&pinctrl { - hdmi { - hdmi_ctl: hdmi-ctl { - rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>, - <1 9 RK_FUNC_1 &pcfg_pull_none>, - <1 10 RK_FUNC_1 &pcfg_pull_none>, - <1 11 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - -}; diff --git a/dts/Bindings/display/rockchip/rockchip,analogix-dp.yaml b/dts/Bindings/display/rockchip/rockchip,analogix-dp.yaml new file mode 100644 index 0000000000..60dedf9b2b --- /dev/null +++ b/dts/Bindings/display/rockchip/rockchip,analogix-dp.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,analogix-dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip specific extensions to the Analogix Display Port + +maintainers: + - Sandy Huang <hjc@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3288-dp + - rockchip,rk3399-edp + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + items: + - const: dp + - const: pclk + - const: grf + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: dp + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + This SoC makes use of GRF regs. + +required: + - compatible + - clocks + - clock-names + - resets + - reset-names + - rockchip,grf + +allOf: + - $ref: /schemas/display/bridge/analogix,dp.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3288-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + dp@ff970000 { + compatible = "rockchip,rk3288-dp"; + reg = <0xff970000 0x4000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; + clock-names = "dp", "pclk"; + phys = <&dp_phy>; + phy-names = "dp"; + resets = <&cru 111>; + reset-names = "dp"; + rockchip,grf = <&grf>; + pinctrl-0 = <&edp_hpd>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + edp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_edp>; + }; + edp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + + edp_out: port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/dts/Bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml new file mode 100644 index 0000000000..ccf79e738f --- /dev/null +++ b/dts/Bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml @@ -0,0 +1,168 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip specific extensions to the Synopsys Designware MIPI DSI + +maintainers: + - Sandy Huang <hjc@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + items: + - enum: + - rockchip,px30-mipi-dsi + - rockchip,rk3288-mipi-dsi + - rockchip,rk3399-mipi-dsi + - rockchip,rk3568-mipi-dsi + - rockchip,rv1126-mipi-dsi + - const: snps,dw-mipi-dsi + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + oneOf: + - minItems: 2 + items: + - const: ref + - const: pclk + - const: phy_cfg + - const: grf + - const: pclk + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + This SoC uses GRF regs to switch between vopl/vopb. + + phys: + maxItems: 1 + + phy-names: + const: dphy + + "#phy-cells": + const: 0 + description: + Defined when in use as ISP phy. + + power-domains: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +required: + - compatible + - clocks + - clock-names + - rockchip,grf + +allOf: + - $ref: /schemas/display/bridge/snps,dw-mipi-dsi.yaml# + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-mipi-dsi + - rockchip,rk3568-mipi-dsi + - rockchip,rv1126-mipi-dsi + + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + required: + - phys + - phy-names + + - if: + properties: + compatible: + contains: + const: rockchip,rk3288-mipi-dsi + + then: + properties: + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + + - if: + properties: + compatible: + contains: + const: rockchip,rk3399-mipi-dsi + + then: + properties: + clocks: + minItems: 4 + + clock-names: + minItems: 4 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3288-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + mipi_dsi: dsi@ff960000 { + compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0xff960000 0x4000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; + clock-names = "ref", "pclk"; + resets = <&cru SRST_MIPIDSI0>; + reset-names = "apb"; + rockchip,grf = <&grf>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi>; + }; + mipi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi>; + }; + }; + + mipi_out: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&panel_in_mipi>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/rockchip/rockchip,inno-hdmi.yaml b/dts/Bindings/display/rockchip/rockchip,inno-hdmi.yaml new file mode 100644 index 0000000000..be78dcfa1c --- /dev/null +++ b/dts/Bindings/display/rockchip/rockchip,inno-hdmi.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,inno-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Innosilicon HDMI controller + +maintainers: + - Sandy Huang <hjc@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3036-inno-hdmi + - rockchip,rk3128-inno-hdmi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: The HDMI controller main clock + - description: The HDMI PHY reference clock + + clock-names: + minItems: 1 + items: + - const: pclk + - const: ref + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Port node with one endpoint connected to a vop node. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Port node with one endpoint connected to a hdmi-connector node. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - pinctrl-0 + - pinctrl-names + - ports + +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,rk3036-inno-hdmi + + then: + properties: + power-domains: false + + - if: + properties: + compatible: + contains: + const: rockchip,rk3128-inno-hdmi + + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + required: + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3036-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/rockchip.h> + hdmi: hdmi@20034000 { + compatible = "rockchip,rk3036-inno-hdmi"; + reg = <0x20034000 0x4000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_HDMI>; + clock-names = "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ctl>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + hdmi_in_vop: endpoint { + remote-endpoint = <&vop_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + }; + }; + + pinctrl { + hdmi { + hdmi_ctl: hdmi-ctl { + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>, + <1 RK_PB1 1 &pcfg_pull_none>, + <1 RK_PB2 1 &pcfg_pull_none>, + <1 RK_PB3 1 &pcfg_pull_none>; + }; + }; + }; diff --git a/dts/Bindings/display/rockchip/rockchip,lvds.yaml b/dts/Bindings/display/rockchip/rockchip,lvds.yaml new file mode 100644 index 0000000000..03b002a05c --- /dev/null +++ b/dts/Bindings/display/rockchip/rockchip,lvds.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,lvds.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip low-voltage differential signal (LVDS) transmitter + +maintainers: + - Sandy Huang <hjc@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,px30-lvds + - rockchip,rk3288-lvds + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: pclk_lvds + + avdd1v0-supply: + description: 1.0V analog power. + + avdd1v8-supply: + description: 1.8V analog power. + + avdd3v3-supply: + description: 3.3V analog power. + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the general register files syscon. + + rockchip,output: + $ref: /schemas/types.yaml#/definitions/string + enum: [rgb, lvds, duallvds] + description: This describes the output interface. + + phys: + maxItems: 1 + + phy-names: + const: dphy + + pinctrl-names: + const: lcdc + + pinctrl-0: true + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port 0 for the VOP input. + The remote endpoint maybe vopb or vopl. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port 1 for either a panel or subsequent encoder. + + required: + - port@0 + - port@1 + +required: + - compatible + - rockchip,grf + - rockchip,output + - ports + +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,px30-lvds + + then: + properties: + reg: false + clocks: false + clock-names: false + avdd1v0-supply: false + avdd1v8-supply: false + avdd3v3-supply: false + + required: + - phys + - phy-names + + - if: + properties: + compatible: + contains: + const: rockchip,rk3288-lvds + + then: + properties: + phys: false + phy-names: false + + required: + - reg + - clocks + - clock-names + - avdd1v0-supply + - avdd1v8-supply + - avdd3v3-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3288-cru.h> + + lvds: lvds@ff96c000 { + compatible = "rockchip,rk3288-lvds"; + reg = <0xff96c000 0x4000>; + clocks = <&cru PCLK_LVDS_PHY>; + clock-names = "pclk_lvds"; + avdd1v0-supply = <&vdd10_lcd>; + avdd1v8-supply = <&vcc18_lcd>; + avdd3v3-supply = <&vcca_33>; + pinctrl-names = "lcdc"; + pinctrl-0 = <&lcdc_ctl>; + rockchip,grf = <&grf>; + rockchip,output = "rgb"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + lvds_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + lvds_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_lvds>; + }; + lvds_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_lvds>; + }; + }; + + lvds_out: port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/rockchip/rockchip-lvds.txt b/dts/Bindings/display/rockchip/rockchip-lvds.txt deleted file mode 100644 index aaf8c44cf9..0000000000 --- a/dts/Bindings/display/rockchip/rockchip-lvds.txt +++ /dev/null @@ -1,92 +0,0 @@ -Rockchip RK3288 LVDS interface -================================ - -Required properties: -- compatible: matching the soc type, one of - - "rockchip,rk3288-lvds"; - - "rockchip,px30-lvds"; - -- reg: physical base address of the controller and length - of memory mapped region. -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. -- clock-names: must contain "pclk_lvds" - -- avdd1v0-supply: regulator phandle for 1.0V analog power -- avdd1v8-supply: regulator phandle for 1.8V analog power -- avdd3v3-supply: regulator phandle for 3.3V analog power - -- rockchip,grf: phandle to the general register files syscon -- rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface - -- phys: LVDS/DSI DPHY (px30 only) -- phy-names: name of the PHY, must be "dphy" (px30 only) - -Optional properties: -- pinctrl-names: must contain a "lcdc" entry. -- pinctrl-0: pin control group to be used for this controller. - -Required nodes: - -The lvds has two video ports as described by - Documentation/devicetree/bindings/media/video-interfaces.txt -Their connections are modeled using the OF graph bindings specified in - Documentation/devicetree/bindings/graph.txt. - -- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl -- video port 1 for either a panel or subsequent encoder - -Example: - -lvds_panel: lvds-panel { - compatible = "auo,b101ean01"; - enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>; - data-mapping = "jeida-24"; - - ports { - panel_in_lvds: endpoint { - remote-endpoint = <&lvds_out_panel>; - }; - }; -}; - -For Rockchip RK3288: - - lvds: lvds@ff96c000 { - compatible = "rockchip,rk3288-lvds"; - rockchip,grf = <&grf>; - reg = <0xff96c000 0x4000>; - clocks = <&cru PCLK_LVDS_PHY>; - clock-names = "pclk_lvds"; - pinctrl-names = "lcdc"; - pinctrl-0 = <&lcdc_ctl>; - avdd1v0-supply = <&vdd10_lcd>; - avdd1v8-supply = <&vcc18_lcd>; - avdd3v3-supply = <&vcca_33>; - rockchip,output = "rgb"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - lvds_in: port@0 { - reg = <0>; - - lvds_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_lvds>; - }; - lvds_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_lvds>; - }; - }; - - lvds_out: port@1 { - reg = <1>; - - lvds_out_panel: endpoint { - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; - }; diff --git a/dts/Bindings/display/rockchip/rockchip-vop.yaml b/dts/Bindings/display/rockchip/rockchip-vop.yaml index 6f43d885c9..b339b7e708 100644 --- a/dts/Bindings/display/rockchip/rockchip-vop.yaml +++ b/dts/Bindings/display/rockchip/rockchip-vop.yaml @@ -31,6 +31,7 @@ properties: - rockchip,rk3368-vop - rockchip,rk3399-vop-big - rockchip,rk3399-vop-lit + - rockchip,rv1126-vop reg: minItems: 1 @@ -121,11 +122,11 @@ examples: #size-cells = <0>; vopb_out_edp: endpoint@0 { reg = <0>; - remote-endpoint=<&edp_in_vopb>; + remote-endpoint = <&edp_in_vopb>; }; vopb_out_hdmi: endpoint@1 { reg = <1>; - remote-endpoint=<&hdmi_in_vopb>; + remote-endpoint = <&hdmi_in_vopb>; }; }; }; diff --git a/dts/Bindings/display/rockchip/rockchip-vop2.yaml b/dts/Bindings/display/rockchip/rockchip-vop2.yaml index fba45091d9..2531726af3 100644 --- a/dts/Bindings/display/rockchip/rockchip-vop2.yaml +++ b/dts/Bindings/display/rockchip/rockchip-vop2.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml# @@ -8,8 +8,8 @@ title: Rockchip SoC display controller (VOP2) description: VOP2 (Video Output Processor v2) is the display controller for the Rockchip - series of SoCs which transfers the image data from a video memory - buffer to an external LCD interface. + series of SoCs which transfers the image data from a video memory buffer to + an external LCD interface. maintainers: - Sandy Huang <hjc@rock-chips.com> @@ -20,6 +20,7 @@ properties: enum: - rockchip,rk3566-vop - rockchip,rk3568-vop + - rockchip,rk3588-vop reg: items: @@ -27,8 +28,8 @@ properties: Must contain one entry corresponding to the base address and length of the register space. - description: - Can optionally contain a second entry corresponding to - the CRTC gamma LUT address. + Can optionally contain a second entry corresponding to the CRTC gamma + LUT address. reg-names: items: @@ -41,45 +42,63 @@ properties: The VOP interrupt is shared by several interrupt sources, such as frame start (VSYNC), line flag and other status interrupts. + # See compatible-specific constraints below. clocks: + minItems: 5 items: - - description: Clock for ddr buffer transfer. - - description: Clock for the ahb bus to R/W the phy regs. + - description: Clock for ddr buffer transfer via axi. + - description: Clock for the ahb bus to R/W the regs. - description: Pixel clock for video port 0. - description: Pixel clock for video port 1. - description: Pixel clock for video port 2. + - description: Pixel clock for video port 3. + - description: Peripheral(vop grf/dsi) clock. clock-names: + minItems: 5 items: - const: aclk - const: hclk - const: dclk_vp0 - const: dclk_vp1 - const: dclk_vp2 + - const: dclk_vp3 + - const: pclk_vop rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: - Phandle to GRF regs used for misc control + Phandle to GRF regs used for control the polarity of dclk/hsync/vsync of DPI, + also used for query vop memory bisr enable status, etc. + + rockchip,vo1-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to VO GRF regs used for control the polarity of dclk/hsync/vsync of hdmi + on rk3588. + + rockchip,vop-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to VOP GRF regs used for control data path between vopr and hdmi/edp. + + rockchip,pmu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to PMU GRF used for query vop memory bisr status on rk3588. ports: $ref: /schemas/graph.yaml#/properties/ports - properties: - port@0: + patternProperties: + "^port@[0-3]$": $ref: /schemas/graph.yaml#/properties/port - description: - Output endpoint of VP0 + description: Output endpoint of VP0/1/2/3. - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: - Output endpoint of VP1 + required: + - port@0 - port@2: - $ref: /schemas/graph.yaml#/properties/port - description: - Output endpoint of VP2 + unevaluatedProperties: false iommus: maxItems: 1 @@ -96,6 +115,49 @@ required: - clock-names - ports +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,rk3588-vop + then: + properties: + clocks: + minItems: 7 + clock-names: + minItems: 7 + + ports: + required: + - port@0 + - port@1 + - port@2 + - port@3 + + required: + - rockchip,grf + - rockchip,vo1-grf + - rockchip,vop-grf + - rockchip,pmu + + else: + properties: + rockchip,vo1-grf: false + rockchip,vop-grf: false + rockchip,pmu: false + + clocks: + maxItems: 5 + clock-names: + maxItems: 5 + + ports: + required: + - port@0 + - port@1 + - port@2 + additionalProperties: false examples: diff --git a/dts/Bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml b/dts/Bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml index 919734c05c..458d399cb0 100644 --- a/dts/Bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml +++ b/dts/Bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml @@ -8,7 +8,6 @@ title: Samsung Exynos SoC HDMI DDC maintainers: - Inki Dae <inki.dae@samsung.com> - - Joonyoung Shim <jy0922.shim@samsung.com> - Seung-Woo Kim <sw0312.kim@samsung.com> - Kyungmin Park <kyungmin.park@samsung.com> - Krzysztof Kozlowski <krzk@kernel.org> diff --git a/dts/Bindings/display/samsung/samsung,exynos-hdmi.yaml b/dts/Bindings/display/samsung/samsung,exynos-hdmi.yaml index 63379fae36..e4a68c5a1a 100644 --- a/dts/Bindings/display/samsung/samsung,exynos-hdmi.yaml +++ b/dts/Bindings/display/samsung/samsung,exynos-hdmi.yaml @@ -8,7 +8,6 @@ title: Samsung Exynos SoC HDMI maintainers: - Inki Dae <inki.dae@samsung.com> - - Joonyoung Shim <jy0922.shim@samsung.com> - Seung-Woo Kim <sw0312.kim@samsung.com> - Kyungmin Park <kyungmin.park@samsung.com> - Krzysztof Kozlowski <krzk@kernel.org> diff --git a/dts/Bindings/display/samsung/samsung,exynos-mixer.yaml b/dts/Bindings/display/samsung/samsung,exynos-mixer.yaml index 00e325a19c..597c9cc6a3 100644 --- a/dts/Bindings/display/samsung/samsung,exynos-mixer.yaml +++ b/dts/Bindings/display/samsung/samsung,exynos-mixer.yaml @@ -8,7 +8,6 @@ title: Samsung Exynos SoC Mixer maintainers: - Inki Dae <inki.dae@samsung.com> - - Joonyoung Shim <jy0922.shim@samsung.com> - Seung-Woo Kim <sw0312.kim@samsung.com> - Kyungmin Park <kyungmin.park@samsung.com> - Krzysztof Kozlowski <krzk@kernel.org> @@ -86,7 +85,7 @@ allOf: clocks: minItems: 6 maxItems: 6 - regs: + reg: minItems: 2 maxItems: 2 @@ -100,7 +99,7 @@ allOf: clocks: minItems: 4 maxItems: 4 - regs: + reg: minItems: 2 maxItems: 2 @@ -117,7 +116,7 @@ allOf: clocks: minItems: 3 maxItems: 3 - regs: + reg: minItems: 1 maxItems: 1 diff --git a/dts/Bindings/display/samsung/samsung,exynos5433-decon.yaml b/dts/Bindings/display/samsung/samsung,exynos5433-decon.yaml index 7c37470bd3..6380eeebb0 100644 --- a/dts/Bindings/display/samsung/samsung,exynos5433-decon.yaml +++ b/dts/Bindings/display/samsung/samsung,exynos5433-decon.yaml @@ -8,7 +8,6 @@ title: Samsung Exynos5433 SoC Display and Enhancement Controller (DECON) maintainers: - Inki Dae <inki.dae@samsung.com> - - Joonyoung Shim <jy0922.shim@samsung.com> - Seung-Woo Kim <sw0312.kim@samsung.com> - Kyungmin Park <kyungmin.park@samsung.com> - Krzysztof Kozlowski <krzk@kernel.org> @@ -25,7 +24,6 @@ properties: - samsung,exynos5433-decon-tv clocks: - minItems: 11 maxItems: 11 clock-names: @@ -60,7 +58,6 @@ properties: - const: te iommus: - minItems: 2 maxItems: 2 iommu-names: diff --git a/dts/Bindings/display/samsung/samsung,exynos5433-mic.yaml b/dts/Bindings/display/samsung/samsung,exynos5433-mic.yaml index c5c6239c28..26e5017737 100644 --- a/dts/Bindings/display/samsung/samsung,exynos5433-mic.yaml +++ b/dts/Bindings/display/samsung/samsung,exynos5433-mic.yaml @@ -8,7 +8,6 @@ title: Samsung Exynos5433 SoC Mobile Image Compressor (MIC) maintainers: - Inki Dae <inki.dae@samsung.com> - - Joonyoung Shim <jy0922.shim@samsung.com> - Seung-Woo Kim <sw0312.kim@samsung.com> - Kyungmin Park <kyungmin.park@samsung.com> - Krzysztof Kozlowski <krzk@kernel.org> @@ -25,7 +24,6 @@ properties: const: samsung,exynos5433-mic clocks: - minItems: 2 maxItems: 2 clock-names: diff --git a/dts/Bindings/display/samsung/samsung,exynos7-decon.yaml b/dts/Bindings/display/samsung/samsung,exynos7-decon.yaml index 320eedc61a..992c23ca7a 100644 --- a/dts/Bindings/display/samsung/samsung,exynos7-decon.yaml +++ b/dts/Bindings/display/samsung/samsung,exynos7-decon.yaml @@ -8,7 +8,6 @@ title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON) maintainers: - Inki Dae <inki.dae@samsung.com> - - Joonyoung Shim <jy0922.shim@samsung.com> - Seung-Woo Kim <sw0312.kim@samsung.com> - Kyungmin Park <kyungmin.park@samsung.com> - Krzysztof Kozlowski <krzk@kernel.org> @@ -23,7 +22,6 @@ properties: const: samsung,exynos7-decon clocks: - minItems: 4 maxItems: 4 clock-names: @@ -38,6 +36,7 @@ properties: i80-if-timings: type: object + additionalProperties: false description: timing configuration for lcd i80 interface support properties: cs-setup: diff --git a/dts/Bindings/display/samsung/samsung,fimd.yaml b/dts/Bindings/display/samsung/samsung,fimd.yaml index c62ea9d228..075231716b 100644 --- a/dts/Bindings/display/samsung/samsung,fimd.yaml +++ b/dts/Bindings/display/samsung/samsung,fimd.yaml @@ -8,7 +8,6 @@ title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD) maintainers: - Inki Dae <inki.dae@samsung.com> - - Joonyoung Shim <jy0922.shim@samsung.com> - Seung-Woo Kim <sw0312.kim@samsung.com> - Kyungmin Park <kyungmin.park@samsung.com> - Krzysztof Kozlowski <krzk@kernel.org> @@ -28,7 +27,6 @@ properties: const: 1 clocks: - minItems: 2 maxItems: 2 clock-names: @@ -41,6 +39,7 @@ properties: i80-if-timings: type: object + additionalProperties: false description: | Timing configuration for lcd i80 interface support. The parameters are defined as:: diff --git a/dts/Bindings/display/simple-framebuffer.yaml b/dts/Bindings/display/simple-framebuffer.yaml index 27ba4323d2..296500f9da 100644 --- a/dts/Bindings/display/simple-framebuffer.yaml +++ b/dts/Bindings/display/simple-framebuffer.yaml @@ -4,10 +4,9 @@ $id: http://devicetree.org/schemas/display/simple-framebuffer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Simple Framebuffer Device Tree Bindings +title: Simple Framebuffer maintainers: - - Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> - Hans de Goede <hdegoede@redhat.com> description: |+ @@ -27,6 +26,11 @@ description: |+ over control to a driver for the real hardware. The bindings for the hw nodes must specify which node is considered the primary node. + If a panel node is given, then the driver uses this to configure the + physical width and height of the display. If no panel node is given, + then the driver uses the width and height properties of the simplefb + node to estimate it. + It is advised to add display# aliases to help the OS determine how to number things. If display# aliases are used, then if the simplefb node contains a display property then the /aliases/display# path @@ -64,6 +68,11 @@ properties: reg: description: Location and size of the framebuffer memory + memory-region: + maxItems: 1 + description: Phandle to a node describing the memory to be used for the + framebuffer. If present, overrides the "reg" property (if one exists). + clocks: description: List of clocks used by the framebuffer. @@ -95,6 +104,7 @@ properties: * `x1r5g5b5` - 16-bit pixels, d[14:10]=r, d[9:5]=g, d[4:0]=b * `x2r10g10b10` - 32-bit pixels, d[29:20]=r, d[19:10]=g, d[9:0]=b * `x8r8g8b8` - 32-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b + * `x8b8g8r8` - 32-bit pixels, d[23:16]=b, d[15:8]=g, d[7:0]=r enum: - a1r5g5b5 - a2r10g10b10 @@ -106,11 +116,16 @@ properties: - x1r5g5b5 - x2r10g10b10 - x8r8g8b8 + - x8b8g8r8 display: $ref: /schemas/types.yaml#/definitions/phandle description: Primary display hardware node + panel: + $ref: /schemas/types.yaml#/definitions/phandle + description: Display panel node + allwinner,pipeline: description: Pipeline used by the framebuffer on Allwinner SoCs enum: diff --git a/dts/Bindings/display/sitronix,st7735r.yaml b/dts/Bindings/display/sitronix,st7735r.yaml index 157b1a7b18..3b0ebc0db8 100644 --- a/dts/Bindings/display/sitronix,st7735r.yaml +++ b/dts/Bindings/display/sitronix,st7735r.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/sitronix,st7735r.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Sitronix ST7735R Display Panels Device Tree Bindings +title: Sitronix ST7735R Display Panels maintainers: - David Lechner <david@lechnology.com> @@ -15,6 +15,7 @@ description: allOf: - $ref: panel/panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: @@ -53,11 +54,6 @@ examples: - | #include <dt-bindings/gpio/gpio.h> - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; - }; - spi { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/display/solomon,ssd-common.yaml b/dts/Bindings/display/solomon,ssd-common.yaml new file mode 100644 index 0000000000..3e6998481a --- /dev/null +++ b/dts/Bindings/display/solomon,ssd-common.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/solomon,ssd-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common properties for Solomon OLED Display Controllers + +maintainers: + - Javier Martinez Canillas <javierm@redhat.com> + +properties: + reg: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + # Only required for SPI + dc-gpios: + description: + GPIO connected to the controller's D/C# (Data/Command) pin, + that is needed for 4-wire SPI to tell the controller if the + data sent is for a command register or the display data RAM + maxItems: 1 + + solomon,height: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Height in pixel of the screen driven by the controller. + The default value is controller-dependent. + + solomon,width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Width in pixel of the screen driven by the controller. + The default value is controller-dependent. + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +additionalProperties: true diff --git a/dts/Bindings/display/solomon,ssd1307fb.yaml b/dts/Bindings/display/solomon,ssd1307fb.yaml index 3fbd87c2c1..3afbb52d1b 100644 --- a/dts/Bindings/display/solomon,ssd1307fb.yaml +++ b/dts/Bindings/display/solomon,ssd1307fb.yaml @@ -14,56 +14,25 @@ properties: compatible: oneOf: # Deprecated compatible strings - - items: - - enum: - - solomon,ssd1305fb-i2c - - solomon,ssd1306fb-i2c - - solomon,ssd1307fb-i2c - - solomon,ssd1309fb-i2c + - enum: + - solomon,ssd1305fb-i2c + - solomon,ssd1306fb-i2c + - solomon,ssd1307fb-i2c + - solomon,ssd1309fb-i2c deprecated: true - - items: - - enum: - - sinowealth,sh1106 - - solomon,ssd1305 - - solomon,ssd1306 - - solomon,ssd1307 - - solomon,ssd1309 - - reg: - maxItems: 1 + - enum: + - sinowealth,sh1106 + - solomon,ssd1305 + - solomon,ssd1306 + - solomon,ssd1307 + - solomon,ssd1309 pwms: maxItems: 1 - reset-gpios: - maxItems: 1 - - # Only required for SPI - dc-gpios: - description: - GPIO connected to the controller's D/C# (Data/Command) pin, - that is needed for 4-wire SPI to tell the controller if the - data sent is for a command register or the display data RAM - maxItems: 1 - vbat-supply: description: The supply for VBAT - # Only required for SPI - spi-max-frequency: true - - solomon,height: - $ref: /schemas/types.yaml#/definitions/uint32 - default: 16 - description: - Height in pixel of the screen driven by the controller - - solomon,width: - $ref: /schemas/types.yaml#/definitions/uint32 - default: 96 - description: - Width in pixel of the screen driven by the controller - solomon,page-offset: $ref: /schemas/types.yaml#/definitions/uint32 default: 1 @@ -153,6 +122,8 @@ required: - reg allOf: + - $ref: solomon,ssd-common.yaml# + - if: properties: compatible: @@ -160,6 +131,10 @@ allOf: const: sinowealth,sh1106 then: properties: + width: + default: 132 + height: + default: 64 solomon,dclk-div: default: 1 solomon,dclk-frq: @@ -174,6 +149,10 @@ allOf: - solomon,ssd1305 then: properties: + width: + default: 132 + height: + default: 64 solomon,dclk-div: default: 1 solomon,dclk-frq: @@ -188,6 +167,10 @@ allOf: - solomon,ssd1306 then: properties: + width: + default: 128 + height: + default: 64 solomon,dclk-div: default: 1 solomon,dclk-frq: @@ -202,6 +185,10 @@ allOf: - solomon,ssd1307 then: properties: + width: + default: 128 + height: + default: 39 solomon,dclk-div: default: 2 solomon,dclk-frq: @@ -218,16 +205,20 @@ allOf: - solomon,ssd1309 then: properties: + width: + default: 128 + height: + default: 64 solomon,dclk-div: default: 1 solomon,dclk-frq: default: 10 -additionalProperties: false +unevaluatedProperties: false examples: - | - i2c1 { + i2c { #address-cells = <1>; #size-cells = <0>; @@ -240,7 +231,7 @@ examples: ssd1306_i2c: oled@3d { compatible = "solomon,ssd1306"; - reg = <0x3c>; + reg = <0x3d>; pwms = <&pwm 4 3000>; reset-gpios = <&gpio2 7>; solomon,com-lrremap; diff --git a/dts/Bindings/display/solomon,ssd132x.yaml b/dts/Bindings/display/solomon,ssd132x.yaml new file mode 100644 index 0000000000..37975ee61c --- /dev/null +++ b/dts/Bindings/display/solomon,ssd132x.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/solomon,ssd132x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Solomon SSD132x OLED Display Controllers + +maintainers: + - Javier Martinez Canillas <javierm@redhat.com> + +properties: + compatible: + enum: + - solomon,ssd1322 + - solomon,ssd1325 + - solomon,ssd1327 + +required: + - compatible + - reg + +allOf: + - $ref: solomon,ssd-common.yaml# + + - if: + properties: + compatible: + contains: + const: solomon,ssd1322 + then: + properties: + width: + default: 480 + height: + default: 128 + + - if: + properties: + compatible: + contains: + const: solomon,ssd1325 + then: + properties: + width: + default: 128 + height: + default: 80 + + - if: + properties: + compatible: + contains: + const: solomon,ssd1327 + then: + properties: + width: + default: 128 + height: + default: 128 + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + oled@3c { + compatible = "solomon,ssd1327"; + reg = <0x3c>; + reset-gpios = <&gpio2 7>; + }; + + }; + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + oled@0 { + compatible = "solomon,ssd1327"; + reg = <0x0>; + reset-gpios = <&gpio2 7>; + dc-gpios = <&gpio2 8>; + spi-max-frequency = <10000000>; + }; + }; diff --git a/dts/Bindings/display/st,stm32-dsi.yaml b/dts/Bindings/display/st,stm32-dsi.yaml index 54f67cb510..53560052aa 100644 --- a/dts/Bindings/display/st,stm32-dsi.yaml +++ b/dts/Bindings/display/st,stm32-dsi.yaml @@ -58,13 +58,22 @@ properties: DSI input port node, connected to the ltdc rgb output port. port@1: - $ref: /schemas/graph.yaml#/properties/port - description: - DSI output port node, connected to a panel or a bridge input port" + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: | + DSI output port node, connected to a panel or a bridge input port. + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + properties: + data-lanes: + minItems: 1 + items: + - const: 1 + - const: 2 required: - - "#address-cells" - - "#size-cells" - compatible - reg - clocks diff --git a/dts/Bindings/display/tegra/nvidia,tegra114-mipi.txt b/dts/Bindings/display/tegra/nvidia,tegra114-mipi.txt deleted file mode 100644 index e4a25cedc5..0000000000 --- a/dts/Bindings/display/tegra/nvidia,tegra114-mipi.txt +++ /dev/null @@ -1,41 +0,0 @@ -NVIDIA Tegra MIPI pad calibration controller - -Required properties: -- compatible: "nvidia,tegra<chip>-mipi" -- reg: Physical base address and length of the controller's registers. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - mipi-cal -- #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads - that need to be calibrated for a given device. - -User nodes need to contain an nvidia,mipi-calibrate property that has a -phandle to refer to the calibration controller node and a bitmask of the pads -that need to be calibrated. - -Example: - - mipi: mipi@700e3000 { - compatible = "nvidia,tegra114-mipi"; - reg = <0x700e3000 0x100>; - clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; - clock-names = "mipi-cal"; - #nvidia,mipi-calibrate-cells = <1>; - }; - - ... - - host1x@50000000 { - ... - - dsi@54300000 { - ... - - nvidia,mipi-calibrate = <&mipi 0x060>; - - ... - }; - - ... - }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra114-mipi.yaml b/dts/Bindings/display/tegra/nvidia,tegra114-mipi.yaml new file mode 100644 index 0000000000..f448624dd7 --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra114-mipi.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra MIPI pad calibration controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + pattern: "^mipi@[0-9a-f]+$" + + compatible: + enum: + - nvidia,tegra114-mipi + - nvidia,tegra210-mipi + - nvidia,tegra186-mipi + + reg: + maxItems: 1 + + clocks: + items: + - description: module clock + + clock-names: + items: + - const: mipi-cal + + power-domains: + maxItems: 1 + + "#nvidia,mipi-calibrate-cells": + description: The number of cells in a MIPI calibration specifier. + Should be 1. The single cell specifies a bitmask of the pads that + need to be calibrated for a given device. + $ref: /schemas/types.yaml#/definitions/uint32 + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - "#nvidia,mipi-calibrate-cells" + +examples: + - | + #include <dt-bindings/clock/tegra114-car.h> + + mipi@700e3000 { + compatible = "nvidia,tegra114-mipi"; + reg = <0x700e3000 0x100>; + clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; + clock-names = "mipi-cal"; + #nvidia,mipi-calibrate-cells = <1>; + }; + + dsia: dsi@54300000 { + compatible = "nvidia,tegra114-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_DSIA>, + <&tegra_car TEGRA114_CLK_DSIALP>, + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra124-dpaux.yaml b/dts/Bindings/display/tegra/nvidia,tegra124-dpaux.yaml new file mode 100644 index 0000000000..5cdbc527a5 --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra124-dpaux.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra DisplayPort AUX Interface + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: | + The Tegra Display Port Auxiliary (DPAUX) pad controller manages two + pins which can be assigned to either the DPAUX channel or to an I2C + controller. + + When configured for DisplayPort AUX operation, the DPAUX controller + can also be used to communicate with a DisplayPort device using the + AUX channel. + +properties: + $nodename: + pattern: "^dpaux@[0-9a-f]+$" + + compatible: + oneOf: + - enum: + - nvidia,tegra124-dpaux + - nvidia,tegra210-dpaux + - nvidia,tegra186-dpaux + - nvidia,tegra194-dpaux + + - items: + - const: nvidia,tegra132-dpaux + - const: nvidia,tegra124-dpaux + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: clock input for the DPAUX hardware + - description: reference clock + + clock-names: + items: + - const: dpaux + - const: parent + + resets: + items: + - description: module reset + + reset-names: + items: + - const: dpaux + + power-domains: + maxItems: 1 + + i2c-bus: + description: Subnode where I2C slave devices are listed. This + subnode must be always present. If there are no I2C slave + devices, an empty node should be added. See ../../i2c/i2c.yaml + for more information. + type: object + + aux-bus: + $ref: /schemas/display/dp-aux-bus.yaml# + + vdd-supply: + description: phandle of a supply that powers the DisplayPort + link + +patternProperties: + "^pinmux-[a-z0-9]+$": + description: + Since only three configurations are possible, only three child + nodes are needed to describe the pin mux'ing options for the + DPAUX pads. Furthermore, given that the pad functions are only + applicable to a single set of pads, the child nodes only need + to describe the pad group the functions are being applied to + rather than the individual pads. + type: object + properties: + groups: + const: dpaux-io + + function: + enum: + - aux + - i2c + - off + + additionalProperties: false + + required: + - groups + - function + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + +examples: + - | + #include <dt-bindings/clock/tegra210-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + dpaux: dpaux@545c0000 { + compatible = "nvidia,tegra210-dpaux"; + reg = <0x545c0000 0x00040000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA210_CLK_DPAUX>, + <&tegra_car TEGRA210_CLK_PLL_DP>; + clock-names = "dpaux", "parent"; + resets = <&tegra_car 181>; + reset-names = "dpaux"; + power-domains = <&pd_sor>; + + state_dpaux_aux: pinmux-aux { + groups = "dpaux-io"; + function = "aux"; + }; + + state_dpaux_i2c: pinmux-i2c { + groups = "dpaux-io"; + function = "i2c"; + }; + + state_dpaux_off: pinmux-off { + groups = "dpaux-io"; + function = "off"; + }; + + i2c-bus { + #address-cells = <1>; + #size-cells = <0>; + }; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra124-sor.yaml b/dts/Bindings/display/tegra/nvidia,tegra124-sor.yaml new file mode 100644 index 0000000000..6f2e224719 --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra124-sor.yaml @@ -0,0 +1,197 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra SOR Output Encoder + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: | + The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP + and DP outputs. + +properties: + $nodename: + pattern: "^sor@[0-9a-f]+$" + + compatible: + oneOf: + - enum: + - nvidia,tegra124-sor + - nvidia,tegra210-sor + - nvidia,tegra210-sor1 + - nvidia,tegra186-sor + - nvidia,tegra186-sor1 + - nvidia,tegra194-sor + + - items: + - const: nvidia,tegra132-sor + - const: nvidia,tegra124-sor + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 5 + maxItems: 6 + + clock-names: + minItems: 5 + maxItems: 6 + + resets: + items: + - description: module reset + + reset-names: + items: + - const: sor + + power-domains: + maxItems: 1 + + avdd-io-hdmi-dp-supply: + description: I/O supply for HDMI/DP + + vdd-hdmi-dp-pll-supply: + description: PLL supply for HDMI/DP + + hdmi-supply: + description: +5.0V HDMI connector supply, required for HDMI + + # Tegra186 and later + nvidia,interface: + description: index of the SOR interface + $ref: /schemas/types.yaml#/definitions/uint32 + + nvidia,ddc-i2c-bus: + description: phandle of an I2C controller used for DDC EDID + probing + $ref: /schemas/types.yaml#/definitions/phandle + + nvidia,hpd-gpio: + description: specifies a GPIO used for hotplug detection + maxItems: 1 + + nvidia,edid: + description: supplies a binary EDID blob + $ref: /schemas/types.yaml#/definitions/uint8-array + + nvidia,panel: + description: phandle of a display panel, required for eDP + $ref: /schemas/types.yaml#/definitions/phandle + + nvidia,xbar-cfg: + description: 5 cells containing the crossbar configuration. + Each lane of the SOR, identified by the cell's index, is + mapped via the crossbar to the pad specified by the cell's + value. + $ref: /schemas/types.yaml#/definitions/uint32-array + + # optional when driving an eDP output + nvidia,dpaux: + description: phandle to a DisplayPort AUX interface + $ref: /schemas/types.yaml#/definitions/phandle + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-sor + - nvidia,tegra194-sor + then: + properties: + clocks: + items: + - description: clock input for the SOR hardware + - description: SOR output clock + - description: input for the pixel clock + - description: reference clock for the SOR clock + - description: safe reference clock for the SOR clock + during power up + - description: SOR pad output clock + + clock-names: + items: + - const: sor + - enum: + - source # deprecated + - out + - const: parent + - const: dp + - const: safe + - const: pad + else: + properties: + clocks: + items: + - description: clock input for the SOR hardware + - description: SOR output clock + - description: input for the pixel clock + - description: reference clock for the SOR clock + - description: safe reference clock for the SOR clock + during power up + + clock-names: + items: + - const: sor + - enum: + - source # deprecated + - out + - const: parent + - const: dp + - const: safe + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - avdd-io-hdmi-dp-supply + - vdd-hdmi-dp-pll-supply + +examples: + - | + #include <dt-bindings/clock/tegra210-car.h> + #include <dt-bindings/gpio/tegra-gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + sor0: sor@54540000 { + compatible = "nvidia,tegra210-sor"; + reg = <0x54540000 0x00040000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA210_CLK_SOR0>, + <&tegra_car TEGRA210_CLK_SOR0_OUT>, + <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, + <&tegra_car TEGRA210_CLK_PLL_DP>, + <&tegra_car TEGRA210_CLK_SOR_SAFE>; + clock-names = "sor", "out", "parent", "dp", "safe"; + resets = <&tegra_car 182>; + reset-names = "sor"; + pinctrl-0 = <&state_dpaux_aux>; + pinctrl-1 = <&state_dpaux_i2c>; + pinctrl-2 = <&state_dpaux_off>; + pinctrl-names = "aux", "i2c", "off"; + power-domains = <&pd_sor>; + + avdd-io-hdmi-dp-supply = <&avdd_1v05>; + vdd-hdmi-dp-pll-supply = <&vdd_1v8>; + hdmi-supply = <&vdd_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) GPIO_ACTIVE_LOW>; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra124-vic.yaml b/dts/Bindings/display/tegra/nvidia,tegra124-vic.yaml new file mode 100644 index 0000000000..7200095ef1 --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra124-vic.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-vic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Video Image Composer + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + pattern: "^vic@[0-9a-f]+$" + + compatible: + oneOf: + - enum: + - nvidia,tegra124-vic + - nvidia,tegra210-vic + - nvidia,tegra186-vic + - nvidia,tegra194-vic + - nvidia,tegra234-vic + + - items: + - const: nvidia,tegra132-vic + - const: nvidia,tegra124-vic + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: clock input for the VIC hardware + + clock-names: + items: + - const: vic + + resets: + items: + - description: module reset + + reset-names: + items: + - const: vic + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + interconnects: + description: Description of the interconnect paths for the VIC; + see ../interconnect/interconnect.txt for details. + items: + - description: memory read client for VIC + - description: memory write client for VIC + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + dma-coherent: true + +additionalProperties: false diff --git a/dts/Bindings/display/tegra/nvidia,tegra186-dc.yaml b/dts/Bindings/display/tegra/nvidia,tegra186-dc.yaml new file mode 100644 index 0000000000..ce4589466a --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra186-dc.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 (and later) Display Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + pattern: "^display@[0-9a-f]+$" + + compatible: + enum: + - nvidia,tegra186-dc + - nvidia,tegra194-dc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: display controller pixel clock + + clock-names: + items: + - const: dc + + resets: + items: + - description: display controller reset + + reset-names: + items: + - const: dc + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + interconnects: + description: Description of the interconnect paths for the + display controller; see ../interconnect/interconnect.txt + for details. + + interconnect-names: + items: + - const: dma-mem # read-0 + - const: read-1 + + nvidia,outputs: + description: A list of phandles of outputs that this display + controller can drive. + $ref: /schemas/types.yaml#/definitions/phandle-array + + nvidia,head: + description: The number of the display controller head. This + is used to setup the various types of output to receive + video data from the given head. + $ref: /schemas/types.yaml#/definitions/uint32 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - power-domains + - nvidia,outputs + - nvidia,head + +# see nvidia,tegra186-display.yaml for examples diff --git a/dts/Bindings/display/tegra/nvidia,tegra186-display.yaml b/dts/Bindings/display/tegra/nvidia,tegra186-display.yaml new file mode 100644 index 0000000000..117c371ce2 --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra186-display.yaml @@ -0,0 +1,308 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 (and later) Display Hub + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + pattern: "^display-hub@[0-9a-f]+$" + + compatible: + enum: + - nvidia,tegra186-display + - nvidia,tegra194-display + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + + resets: + items: + - description: display hub reset + - description: window group 0 reset + - description: window group 1 reset + - description: window group 2 reset + - description: window group 3 reset + - description: window group 4 reset + - description: window group 5 reset + + reset-names: + items: + - const: misc + - const: wgrp0 + - const: wgrp1 + - const: wgrp2 + - const: wgrp3 + - const: wgrp4 + - const: wgrp5 + + power-domains: + maxItems: 1 + + ranges: + maxItems: 1 + +patternProperties: + "^display@[0-9a-f]+$": + type: object + +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra186-display + then: + properties: + clocks: + items: + - description: display core clock + - description: display stream compression clock + - description: display hub clock + + clock-names: + items: + - const: disp + - const: dsc + - const: hub + else: + properties: + clocks: + items: + - description: display core clock + - description: display hub clock + + clock-names: + items: + - const: disp + - const: hub + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + - "#address-cells" + - "#size-cells" + - ranges + +examples: + - | + #include <dt-bindings/clock/tegra186-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/tegra186-mc.h> + #include <dt-bindings/power/tegra186-powergate.h> + #include <dt-bindings/reset/tegra186-reset.h> + + display-hub@15200000 { + compatible = "nvidia,tegra186-display"; + reg = <0x15200000 0x00040000>; + resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, + <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, + <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, + <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, + <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, + <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, + <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; + reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", + "wgrp3", "wgrp4", "wgrp5"; + clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, + <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, + <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; + clock-names = "disp", "dsc", "hub"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x15200000 0x15200000 0x40000>; + + display@15200000 { + compatible = "nvidia,tegra186-dc"; + reg = <0x15200000 0x10000>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; + clock-names = "dc"; + resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; + reset-names = "dc"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; + interconnect-names = "dma-mem", "read-1"; + iommus = <&smmu TEGRA186_SID_NVDISPLAY>; + + nvidia,outputs = <&dsia &dsib &sor0 &sor1>; + nvidia,head = <0>; + }; + + display@15210000 { + compatible = "nvidia,tegra186-dc"; + reg = <0x15210000 0x10000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; + clock-names = "dc"; + resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; + reset-names = "dc"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; + interconnect-names = "dma-mem", "read-1"; + iommus = <&smmu TEGRA186_SID_NVDISPLAY>; + + nvidia,outputs = <&dsia &dsib &sor0 &sor1>; + nvidia,head = <1>; + }; + + display@15220000 { + compatible = "nvidia,tegra186-dc"; + reg = <0x15220000 0x10000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; + clock-names = "dc"; + resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; + reset-names = "dc"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; + interconnect-names = "dma-mem", "read-1"; + iommus = <&smmu TEGRA186_SID_NVDISPLAY>; + + nvidia,outputs = <&sor0 &sor1>; + nvidia,head = <2>; + }; + }; + + - | + #include <dt-bindings/clock/tegra194-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/tegra194-mc.h> + #include <dt-bindings/power/tegra194-powergate.h> + #include <dt-bindings/reset/tegra194-reset.h> + + display-hub@15200000 { + compatible = "nvidia,tegra194-display"; + reg = <0x15200000 0x00040000>; + resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, + <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, + <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, + <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, + <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, + <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, + <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; + reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", + "wgrp3", "wgrp4", "wgrp5"; + clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, + <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; + clock-names = "disp", "hub"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x15200000 0x15200000 0x40000>; + + display@15200000 { + compatible = "nvidia,tegra194-dc"; + reg = <0x15200000 0x10000>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; + clock-names = "dc"; + resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; + reset-names = "dc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; + interconnect-names = "dma-mem", "read-1"; + + nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; + nvidia,head = <0>; + }; + + display@15210000 { + compatible = "nvidia,tegra194-dc"; + reg = <0x15210000 0x10000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; + clock-names = "dc"; + resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; + reset-names = "dc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; + interconnect-names = "dma-mem", "read-1"; + + nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; + nvidia,head = <1>; + }; + + display@15220000 { + compatible = "nvidia,tegra194-dc"; + reg = <0x15220000 0x10000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; + clock-names = "dc"; + resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; + reset-names = "dc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; + interconnect-names = "dma-mem", "read-1"; + + nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; + nvidia,head = <2>; + }; + + display@15230000 { + compatible = "nvidia,tegra194-dc"; + reg = <0x15230000 0x10000>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; + clock-names = "dc"; + resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; + reset-names = "dc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; + interconnect-names = "dma-mem", "read-1"; + + nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; + nvidia,head = <3>; + }; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml b/dts/Bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml new file mode 100644 index 0000000000..da75b71e8e --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dsi-padctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra MIPI DSI pad controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + pattern: "^padctl@[0-9a-f]+$" + + compatible: + const: nvidia,tegra186-dsi-padctl + + reg: + maxItems: 1 + + resets: + items: + - description: module reset + + reset-names: + items: + - const: dsi + +allOf: + - $ref: /schemas/reset/reset.yaml + +additionalProperties: false + +examples: + - | + #include <dt-bindings/reset/tegra186-reset.h> + + padctl@15880000 { + compatible = "nvidia,tegra186-dsi-padctl"; + reg = <0x15880000 0x10000>; + resets = <&bpmp TEGRA186_RESET_DSI>; + reset-names = "dsi"; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-dc.yaml b/dts/Bindings/display/tegra/nvidia,tegra20-dc.yaml new file mode 100644 index 0000000000..69be95afd5 --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra20-dc.yaml @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Display Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + pattern: "^dc@[0-9a-f]+$" + + compatible: + oneOf: + - enum: + - nvidia,tegra20-dc + - nvidia,tegra30-dc + - nvidia,tegra114-dc + - nvidia,tegra124-dc + - nvidia,tegra210-dc + + - items: + - const: nvidia,tegra124-dc + - const: nvidia,tegra132-dc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: display controller pixel clock + - description: parent clock # optional + + clock-names: + minItems: 1 + items: + - const: dc + - const: parent # optional + + resets: + items: + - description: module reset + + reset-names: + items: + - const: dc + + interconnect-names: true + interconnects: true + + iommus: + maxItems: 1 + + operating-points-v2: true + + power-domains: + items: + - description: phandle to the core power domain + + memory-region: true + + nvidia,head: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of the display controller head. This is used to setup the various + types of output to receive video data from the given head. + + nvidia,outputs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: A list of phandles of outputs that this display controller can drive. + + rgb: + type: object + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-dc + - nvidia,tegra30-dc + - nvidia,tegra114-dc + then: + properties: + interconnects: + items: + - description: window A memory client + - description: window B memory client + - description: window B memory client (vertical filter) + - description: window C memory client + - description: cursor memory client + + interconnect-names: + items: + - const: wina + - const: winb + - const: winb-vfilter + - const: winc + - const: cursor + + rgb: + description: Each display controller node has a child node, named "rgb", that represents + the RGB output associated with the controller. + type: object + properties: + nvidia,ddc-i2c-bus: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle of an I2C controller used for DDC EDID probing + + nvidia,hpd-gpio: + description: specifies a GPIO used for hotplug detection + maxItems: 1 + + nvidia,edid: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: supplies a binary EDID blob + + nvidia,panel: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle of a display panel + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra124-dc + then: + properties: + interconnects: + minItems: 4 + items: + - description: window A memory client + - description: window B memory client + - description: window C memory client + - description: cursor memory client + - description: window D memory client + - description: window T memory client + + interconnect-names: + minItems: 4 + items: + - const: wina + - const: winb + - const: winc + - const: cursor + - const: wind + - const: wint + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + dc@54200000 { + compatible = "nvidia,tegra20-dc"; + reg = <0x54200000 0x00040000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_DISP1>; + clock-names = "dc"; + resets = <&tegra_car 27>; + reset-names = "dc"; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-dsi.yaml b/dts/Bindings/display/tegra/nvidia,tegra20-dsi.yaml new file mode 100644 index 0000000000..59e1dc0813 --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra20-dsi.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Display Serial Interface + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-dsi + - nvidia,tegra30-dsi + - nvidia,tegra114-dsi + - nvidia,tegra124-dsi + - nvidia,tegra210-dsi + - nvidia,tegra186-dsi + + - items: + - const: nvidia,tegra132-dsi + - const: nvidia,tegra124-dsi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + + resets: + items: + - description: module reset + + reset-names: + items: + - const: dsi + + operating-points-v2: true + + power-domains: + maxItems: 1 + + avdd-dsi-csi-supply: + description: phandle of a supply that powers the DSI controller + + nvidia,mipi-calibrate: + description: Should contain a phandle and a specifier specifying + which pads are used by this DSI output and need to be + calibrated. See nvidia,tegra114-mipi.yaml for details. + $ref: /schemas/types.yaml#/definitions/phandle-array + + nvidia,ddc-i2c-bus: + description: phandle of an I2C controller used for DDC EDID + probing + $ref: /schemas/types.yaml#/definitions/phandle + + nvidia,hpd-gpio: + description: specifies a GPIO used for hotplug detection + maxItems: 1 + + nvidia,edid: + description: supplies a binary EDID blob + $ref: /schemas/types.yaml#/definitions/uint8-array + + nvidia,panel: + description: phandle of a display panel + $ref: /schemas/types.yaml#/definitions/phandle + + nvidia,ganged-mode: + description: contains a phandle to a second DSI controller to + gang up with in order to support up to 8 data lanes + $ref: /schemas/types.yaml#/definitions/phandle + +allOf: + - $ref: ../dsi-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-dsi + - nvidia,tegra30-dsi + then: + properties: + clocks: + items: + - description: DSI module clock + - description: input for the pixel clock + + clock-names: + items: + - const: dsi + - const: parent + else: + properties: + clocks: + items: + - description: DSI module clock + - description: low-power module clock + - description: input for the pixel clock + + clock-names: + items: + - const: dsi + - const: lp + - const: parent + + - if: + properties: + compatible: + contains: + const: nvidia,tegra186-dsi + then: + required: + - interrupts + +unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + +examples: + - | + #include <dt-bindings/clock/tegra186-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/tegra186-powergate.h> + #include <dt-bindings/reset/tegra186-reset.h> + + dsi@15300000 { + compatible = "nvidia,tegra186-dsi"; + reg = <0x15300000 0x10000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA186_CLK_DSI>, + <&bpmp TEGRA186_CLK_DSIA_LP>, + <&bpmp TEGRA186_CLK_PLLD>; + clock-names = "dsi", "lp", "parent"; + resets = <&bpmp TEGRA186_RESET_DSI>; + reset-names = "dsi"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-epp.yaml b/dts/Bindings/display/tegra/nvidia,tegra20-epp.yaml new file mode 100644 index 0000000000..3c095a5491 --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra20-epp.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Encoder Pre-Processor + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + pattern: "^epp@[0-9a-f]+$" + + compatible: + enum: + - nvidia,tegra20-epp + - nvidia,tegra30-epp + - nvidia,tegra114-epp + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + items: + - description: module reset + + reset-names: + items: + - const: epp + + iommus: + maxItems: 1 + + interconnects: + maxItems: 4 + + interconnect-names: + maxItems: 4 + + operating-points-v2: true + + power-domains: + items: + - description: phandle to the core power domain + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + epp@540c0000 { + compatible = "nvidia,tegra20-epp"; + reg = <0x540c0000 0x00040000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_EPP>; + resets = <&tegra_car 19>; + reset-names = "epp"; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-gr2d.yaml b/dts/Bindings/display/tegra/nvidia,tegra20-gr2d.yaml new file mode 100644 index 0000000000..1026b0bc3d --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra20-gr2d.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr2d.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA 2D graphics engine + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + pattern: "^gr2d@[0-9a-f]+$" + + compatible: + enum: + - nvidia,tegra20-gr2d + - nvidia,tegra30-gr2d + - nvidia,tegra114-gr2d + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: module clock + + resets: + items: + - description: module reset + - description: memory client hotflush reset + + reset-names: + items: + - const: 2d + - const: mc + + iommus: + maxItems: 1 + + interconnects: + maxItems: 4 + + interconnect-names: + maxItems: 4 + + operating-points-v2: true + + power-domains: + items: + - description: phandle to the HEG or core power domain + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/tegra20-mc.h> + + gr2d@54140000 { + compatible = "nvidia,tegra20-gr2d"; + reg = <0x54140000 0x00040000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_GR2D>; + resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; + reset-names = "2d", "mc"; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-gr3d.yaml b/dts/Bindings/display/tegra/nvidia,tegra20-gr3d.yaml new file mode 100644 index 0000000000..59a52e732c --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra20-gr3d.yaml @@ -0,0 +1,213 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr3d.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA 3D graphics engine + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + pattern: "^gr3d@[0-9a-f]+$" + + compatible: + enum: + - nvidia,tegra20-gr3d + - nvidia,tegra30-gr3d + - nvidia,tegra114-gr3d + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + + resets: + minItems: 2 + maxItems: 4 + + reset-names: + minItems: 2 + maxItems: 4 + + iommus: + minItems: 1 + maxItems: 2 + + interconnects: + minItems: 4 + maxItems: 10 + + interconnect-names: + minItems: 4 + maxItems: 10 + + operating-points-v2: true + + power-domains: + minItems: 1 + maxItems: 2 + + power-domain-names: + maxItems: 2 + +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra20-gr2d + then: + properties: + clocks: + items: + - description: module clock + + clock-names: + items: + - const: 3d + + resets: + items: + - description: module reset + - description: memory client hotflush reset + + reset-names: + items: + - const: 3d + - const: mc + + iommus: + maxItems: 1 + + interconnects: + minItems: 4 + maxItems: 4 + + interconnect-names: + minItems: 4 + maxItems: 4 + + power-domains: + items: + - description: phandle to the TD power domain + + - if: + properties: + compatible: + contains: + const: nvidia,tegra30-gr3d + then: + properties: + clocks: + items: + - description: primary module clock + - description: secondary module clock + + clock-names: + items: + - const: 3d + - const: 3d2 + + resets: + items: + - description: primary module reset + - description: secondary module reset + - description: primary memory client hotflush reset + - description: secondary memory client hotflush reset + + reset-names: + items: + - const: 3d + - const: 3d2 + - const: mc + - const: mc2 + + iommus: + minItems: 2 + maxItems: 2 + + interconnects: + minItems: 8 + maxItems: 8 + + interconnect-names: + minItems: 8 + maxItems: 8 + + power-domains: + items: + - description: phandle to the TD power domain + - description: phandle to the TD2 power domain + + power-domain-names: + items: + - const: 3d0 + - const: 3d1 + + dependencies: + power-domains: [ power-domain-names ] + + - if: + properties: + compatible: + contains: + const: nvidia,tegra114-gr2d + then: + properties: + clocks: + items: + - description: module clock + + clock-names: + items: + - const: 3d + + resets: + items: + - description: module reset + - description: memory client hotflush reset + + reset-names: + items: + - const: 3d + - const: mc + + iommus: + maxItems: 1 + + interconnects: + minItems: 10 + maxItems: 10 + + interconnect-names: + minItems: 10 + maxItems: 10 + + power-domains: + items: + - description: phandle to the TD power domain + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/memory/tegra20-mc.h> + + gr3d@54180000 { + compatible = "nvidia,tegra20-gr3d"; + reg = <0x54180000 0x00040000>; + clocks = <&tegra_car TEGRA20_CLK_GR3D>; + resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; + reset-names = "3d", "mc"; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-hdmi.yaml b/dts/Bindings/display/tegra/nvidia,tegra20-hdmi.yaml new file mode 100644 index 0000000000..f77197e486 --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra20-hdmi.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra HDMI Output Encoder + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + pattern: "^hdmi@[0-9a-f]+$" + + compatible: + oneOf: + - enum: + - nvidia,tegra20-hdmi + - nvidia,tegra30-hdmi + - nvidia,tegra114-hdmi + - nvidia,tegra124-hdmi + + - items: + - const: nvidia,tegra132-hdmi + - const: nvidia,tegra124-hdmi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: module clock + - description: parent clock + + clock-names: + items: + - const: hdmi + - const: parent + + resets: + items: + - description: module reset + + reset-names: + items: + - const: hdmi + + operating-points-v2: true + + power-domains: + items: + - description: phandle to the core power domain + + hdmi-supply: + description: supply for the +5V HDMI connector pin + + vdd-supply: + description: regulator for supply voltage + + pll-supply: + description: regulator for PLL + + nvidia,ddc-i2c-bus: + description: phandle of an I2C controller used for DDC EDID + probing + $ref: /schemas/types.yaml#/definitions/phandle + + nvidia,hpd-gpio: + description: specifies a GPIO used for hotplug detection + maxItems: 1 + + nvidia,edid: + description: supplies a binary EDID blob + $ref: /schemas/types.yaml#/definitions/uint8-array + + nvidia,panel: + description: phandle of a display panel + $ref: /schemas/types.yaml#/definitions/phandle + + "#sound-dai-cells": + const: 0 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - pll-supply + - vdd-supply + - nvidia,ddc-i2c-bus + - nvidia,hpd-gpio + +examples: + - | + #include <dt-bindings/clock/tegra124-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/tegra-gpio.h> + + hdmi@54280000 { + compatible = "nvidia,tegra124-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_HDMI>, + <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; + + hdmi-supply = <&vdd_5v0_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + vdd-supply = <&vdd_3v3_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt b/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt deleted file mode 100644 index e61999ce54..0000000000 --- a/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt +++ /dev/null @@ -1,675 +0,0 @@ -NVIDIA Tegra host1x - -Required properties: -- compatible: "nvidia,tegra<chip>-host1x" -- reg: Physical base address and length of the controller's registers. - For pre-Tegra186, one entry describing the whole register area. - For Tegra186, one entry for each entry in reg-names: - "vm" - VM region assigned to Linux - "hypervisor" - Hypervisor region (only if Linux acts as hypervisor) -- interrupts: The interrupt outputs from the controller. -- #address-cells: The number of cells used to represent physical base addresses - in the host1x address space. Should be 1. -- #size-cells: The number of cells used to represent the size of an address - range in the host1x address space. Should be 1. -- ranges: The mapping of the host1x address space to the CPU address space. -- clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - host1x - - mc - -Optional properties: -- operating-points-v2: See ../bindings/opp/opp.txt for details. - - power-domains: Phandle to HEG or core power domain. - -For each opp entry in 'operating-points-v2' table of host1x and its modules: -- opp-supported-hw: One bitfield indicating: - On Tegra20: SoC process ID mask - On Tegra30+: SoC speedo ID mask - - A bitwise AND is performed against the value and if any bit - matches, the OPP gets enabled. - -Each host1x client module having to perform DMA through the Memory Controller -should have the interconnect endpoints set to the Memory Client and External -Memory respectively. - -The host1x top-level node defines a number of children, each representing one -of the following host1x client modules: - -- mpe: video encoder - - Required properties: - - compatible: "nvidia,tegra<chip>-mpe" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - mpe - - Optional properties: - - interconnects: Must contain entry for the MPE memory clients. - - interconnect-names: Must include name of the interconnect path for each - interconnect entry. Consult TRM documentation for information about - available memory clients, see MEMORY CONTROLLER section. - - operating-points-v2: See ../bindings/opp/opp.txt for details. - - power-domains: Phandle to MPE power domain. - -- vi: video input - - Required properties: - - compatible: "nvidia,tegra<chip>-vi" - - reg: Physical base address and length of the controller registers. - - interrupts: The interrupt outputs from the controller. - - clocks: clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - - Tegra20/Tegra30/Tegra114/Tegra124: - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - vi - - Tegra210: - - power-domains: Must include venc powergate node as vi is in VE partition. - - ports (optional node) - vi can have optional ports node and max 6 ports are supported. Each port - should have single 'endpoint' child node. All port nodes are grouped under - ports node. Please refer to the bindings defined in - Documentation/devicetree/bindings/media/video-interfaces.txt - - csi (required node) - Tegra210 has CSI part of VI sharing same host interface and register space. - So, VI device node should have CSI child node. - - - csi: mipi csi interface to vi - - Required properties: - - compatible: "nvidia,tegra210-csi" - - reg: Physical base address offset to parent and length of the controller - registers. - - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks. - See ../clocks/clock-bindings.txt for details. - - power-domains: Must include sor powergate node as csicil is in - SOR partition. - - channel (optional nodes) - Maximum 6 channels are supported with each csi brick as either x4 or x2 - based on hw connectivity to sensor. - - Required properties: - - reg: csi port number. Valid port numbers are 0 through 5. - - nvidia,mipi-calibrate: Should contain a phandle and a specifier - specifying which pads are used by this CSI port and need to be - calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt. - - Each channel node must contain 2 port nodes which can be grouped - under 'ports' node and each port should have a single child 'endpoint' - node. - - ports node - Please refer to the bindings defined in - Documentation/devicetree/bindings/media/video-interfaces.txt - - ports node must contain below 2 port nodes. - port@0 with single child 'endpoint' node always a sink. - port@1 with single child 'endpoint' node always a source. - - port@0 (required node) - Required properties: - - reg: 0 - - endpoint (required node) - Required properties: - - data-lanes: an array of data lane from 1 to 8. Valid array - lengths are 1/2/4/8. - - remote-endpoint: phandle to sensor 'endpoint' node. - - port@1 (required node) - Required properties: - - reg: 1 - - endpoint (required node) - Required properties: - - remote-endpoint: phandle to vi port 'endpoint' node. - - Optional properties: - - interconnects: Must contain entry for the VI memory clients. - - interconnect-names: Must include name of the interconnect path for each - interconnect entry. Consult TRM documentation for information about - available memory clients, see MEMORY CONTROLLER section. - - operating-points-v2: See ../bindings/opp/opp.txt for details. - - power-domains: Phandle to VENC power domain. - -- epp: encoder pre-processor - - Required properties: - - compatible: "nvidia,tegra<chip>-epp" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - epp - - Optional properties: - - interconnects: Must contain entry for the EPP memory clients. - - interconnect-names: Must include name of the interconnect path for each - interconnect entry. Consult TRM documentation for information about - available memory clients, see MEMORY CONTROLLER section. - - operating-points-v2: See ../bindings/opp/opp.txt for details. - - power-domains: Phandle to HEG or core power domain. - -- isp: image signal processor - - Required properties: - - compatible: "nvidia,tegra<chip>-isp" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - isp - - Optional properties: - - interconnects: Must contain entry for the ISP memory clients. - - interconnect-names: Must include name of the interconnect path for each - interconnect entry. Consult TRM documentation for information about - available memory clients, see MEMORY CONTROLLER section. - - power-domains: Phandle to VENC or core power domain. - -- gr2d: 2D graphics engine - - Required properties: - - compatible: "nvidia,tegra<chip>-gr2d" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - 2d - - mc - - Optional properties: - - interconnects: Must contain entry for the GR2D memory clients. - - interconnect-names: Must include name of the interconnect path for each - interconnect entry. Consult TRM documentation for information about - available memory clients, see MEMORY CONTROLLER section. - - operating-points-v2: See ../bindings/opp/opp.txt for details. - - power-domains: Phandle to HEG or core power domain. - -- gr3d: 3D graphics engine - - Required properties: - - compatible: "nvidia,tegra<chip>-gr3d" - - reg: Physical base address and length of the controller's registers. - - clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must include the following entries: - (This property may be omitted if the only clock in the list is "3d") - - 3d - This MUST be the first entry. - - 3d2 (Only required on SoCs with two 3D clocks) - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - 3d - - 3d2 (Only required on SoCs with two 3D clocks) - - mc - - mc2 (Only required on SoCs with two 3D clocks) - - Optional properties: - - interconnects: Must contain entry for the GR3D memory clients. - - interconnect-names: Must include name of the interconnect path for each - interconnect entry. Consult TRM documentation for information about - available memory clients, see MEMORY CONTROLLER section. - - operating-points-v2: See ../bindings/opp/opp.txt for details. - - power-domains: Phandles to 3D or core power domain. - -- dc: display controller - - Required properties: - - compatible: "nvidia,tegra<chip>-dc" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must include the following entries: - - dc - This MUST be the first entry. - - parent - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - dc - - nvidia,head: The number of the display controller head. This is used to - setup the various types of output to receive video data from the given - head. - - Each display controller node has a child node, named "rgb", that represents - the RGB output associated with the controller. It can take the following - optional properties: - - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing - - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - - nvidia,edid: supplies a binary EDID blob - - nvidia,panel: phandle of a display panel - - interconnects: Must contain entry for the DC memory clients. - - interconnect-names: Must include name of the interconnect path for each - interconnect entry. Consult TRM documentation for information about - available memory clients, see MEMORY CONTROLLER section. - - operating-points-v2: See ../bindings/opp/opp.txt for details. - - power-domains: Phandle to core power domain. - -- hdmi: High Definition Multimedia Interface - - Required properties: - - compatible: "nvidia,tegra<chip>-hdmi" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - hdmi-supply: supply for the +5V HDMI connector pin - - vdd-supply: regulator for supply voltage - - pll-supply: regulator for PLL - - clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must include the following entries: - - hdmi - This MUST be the first entry. - - parent - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - hdmi - - Optional properties: - - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing - - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - - nvidia,edid: supplies a binary EDID blob - - nvidia,panel: phandle of a display panel - - operating-points-v2: See ../bindings/opp/opp.txt for details. - -- tvo: TV encoder output - - Required properties: - - compatible: "nvidia,tegra<chip>-tvo" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - - Optional properties: - - operating-points-v2: See ../bindings/opp/opp.txt for details. - - power-domains: Phandle to core power domain. - -- dsi: display serial interface - - Required properties: - - compatible: "nvidia,tegra<chip>-dsi" - - reg: Physical base address and length of the controller's registers. - - clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must include the following entries: - - dsi - This MUST be the first entry. - - lp - - parent - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - dsi - - avdd-dsi-supply: phandle of a supply that powers the DSI controller - - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying - which pads are used by this DSI output and need to be calibrated. See also - ../display/tegra/nvidia,tegra114-mipi.txt. - - Optional properties: - - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing - - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - - nvidia,edid: supplies a binary EDID blob - - nvidia,panel: phandle of a display panel - - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang - up with in order to support up to 8 data lanes - - operating-points-v2: See ../bindings/opp/opp.txt for details. - -- sor: serial output resource - - Required properties: - - compatible: Should be: - - "nvidia,tegra124-sor": for Tegra124 and Tegra132 - - "nvidia,tegra132-sor": for Tegra132 - - "nvidia,tegra210-sor": for Tegra210 - - "nvidia,tegra210-sor1": for Tegra210 - - "nvidia,tegra186-sor": for Tegra186 - - "nvidia,tegra186-sor1": for Tegra186 - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must include the following entries: - - sor: clock input for the SOR hardware - - out: SOR output clock - - parent: input for the pixel clock - - dp: reference clock for the SOR clock - - safe: safe reference for the SOR clock during power up - - For Tegra186 and later: - - pad: SOR pad output clock (on Tegra186 and later) - - Obsolete: - - source: source clock for the SOR clock (obsolete, use "out" instead) - - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - sor - - Required properties on Tegra186 and later: - - nvidia,interface: index of the SOR interface - - Optional properties: - - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing - - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - - nvidia,edid: supplies a binary EDID blob - - nvidia,panel: phandle of a display panel - - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane - of the SOR, identified by the cell's index, is mapped via the crossbar to - the pad specified by the cell's value. - - Optional properties when driving an eDP output: - - nvidia,dpaux: phandle to a DispayPort AUX interface - -- dpaux: DisplayPort AUX interface - - compatible : Should contain one of the following: - - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132 - - "nvidia,tegra210-dpaux": for Tegra210 - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must include the following entries: - - dpaux: clock input for the DPAUX hardware - - parent: reference clock - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - dpaux - - vdd-supply: phandle of a supply that powers the DisplayPort link - - i2c-bus: Subnode where I2C slave devices are listed. This subnode - must be always present. If there are no I2C slave devices, an empty - node should be added. See ../../i2c/i2c.txt for more information. - - See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information - regarding the DPAUX pad controller bindings. - -- vic: Video Image Compositor - - compatible : "nvidia,tegra<chip>-vic" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must include the following entries: - - vic: clock input for the VIC hardware - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - vic - - Optional properties: - - interconnects: Must contain entry for the VIC memory clients. - - interconnect-names: Must include name of the interconnect path for each - interconnect entry. Consult TRM documentation for information about - available memory clients, see MEMORY CONTROLLER section. - -Example: - -/ { - ... - - host1x { - compatible = "nvidia,tegra20-host1x", "simple-bus"; - reg = <0x50000000 0x00024000>; - interrupts = <0 65 0x04 /* mpcore syncpt */ - 0 67 0x04>; /* mpcore general */ - clocks = <&tegra_car TEGRA20_CLK_HOST1X>; - resets = <&tegra_car 28>; - reset-names = "host1x"; - operating-points-v2 = <&dvfs_opp_table>; - power-domains = <&domain>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x54000000 0x54000000 0x04000000>; - - mpe { - compatible = "nvidia,tegra20-mpe"; - reg = <0x54040000 0x00040000>; - interrupts = <0 68 0x04>; - clocks = <&tegra_car TEGRA20_CLK_MPE>; - resets = <&tegra_car 60>; - reset-names = "mpe"; - operating-points-v2 = <&dvfs_opp_table>; - power-domains = <&domain>; - }; - - vi@54080000 { - compatible = "nvidia,tegra210-vi"; - reg = <0x0 0x54080000 0x0 0x700>; - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; - operating-points-v2 = <&dvfs_opp_table>; - - clocks = <&tegra_car TEGRA210_CLK_VI>; - power-domains = <&pd_venc>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x0 0x0 0x54080000 0x2000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - imx219_vi_in0: endpoint { - remote-endpoint = <&imx219_csi_out0>; - }; - }; - }; - - csi@838 { - compatible = "nvidia,tegra210-csi"; - reg = <0x838 0x1300>; - assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, - <&tegra_car TEGRA210_CLK_CILCD>, - <&tegra_car TEGRA210_CLK_CILE>, - <&tegra_car TEGRA210_CLK_CSI_TPG>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, - <&tegra_car TEGRA210_CLK_PLL_P>, - <&tegra_car TEGRA210_CLK_PLL_P>; - assigned-clock-rates = <102000000>, - <102000000>, - <102000000>, - <972000000>; - - clocks = <&tegra_car TEGRA210_CLK_CSI>, - <&tegra_car TEGRA210_CLK_CILAB>, - <&tegra_car TEGRA210_CLK_CILCD>, - <&tegra_car TEGRA210_CLK_CILE>, - <&tegra_car TEGRA210_CLK_CSI_TPG>; - clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; - power-domains = <&pd_sor>; - - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0>; - nvidia,mipi-calibrate = <&mipi 0x001>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - imx219_csi_in0: endpoint { - data-lanes = <1 2>; - remote-endpoint = <&imx219_out0>; - }; - }; - - port@1 { - reg = <1>; - imx219_csi_out0: endpoint { - remote-endpoint = <&imx219_vi_in0>; - }; - }; - }; - }; - }; - }; - - epp { - compatible = "nvidia,tegra20-epp"; - reg = <0x540c0000 0x00040000>; - interrupts = <0 70 0x04>; - clocks = <&tegra_car TEGRA20_CLK_EPP>; - resets = <&tegra_car 19>; - reset-names = "epp"; - operating-points-v2 = <&dvfs_opp_table>; - power-domains = <&domain>; - }; - - isp { - compatible = "nvidia,tegra20-isp"; - reg = <0x54100000 0x00040000>; - interrupts = <0 71 0x04>; - clocks = <&tegra_car TEGRA20_CLK_ISP>; - resets = <&tegra_car 23>; - reset-names = "isp"; - }; - - gr2d { - compatible = "nvidia,tegra20-gr2d"; - reg = <0x54140000 0x00040000>; - interrupts = <0 72 0x04>; - clocks = <&tegra_car TEGRA20_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; - operating-points-v2 = <&dvfs_opp_table>; - power-domains = <&domain>; - }; - - gr3d { - compatible = "nvidia,tegra20-gr3d"; - reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA20_CLK_GR3D>; - resets = <&tegra_car 24>; - reset-names = "3d"; - operating-points-v2 = <&dvfs_opp_table>; - power-domains = <&domain>; - }; - - dc@54200000 { - compatible = "nvidia,tegra20-dc"; - reg = <0x54200000 0x00040000>; - interrupts = <0 73 0x04>; - clocks = <&tegra_car TEGRA20_CLK_DISP1>, - <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - operating-points-v2 = <&dvfs_opp_table>; - power-domains = <&domain>; - - interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, - <&mc TEGRA20_MC_DISPLAY0B &emc>, - <&mc TEGRA20_MC_DISPLAY0C &emc>, - <&mc TEGRA20_MC_DISPLAYHC &emc>; - interconnect-names = "wina", - "winb", - "winc", - "cursor"; - - rgb { - status = "disabled"; - }; - }; - - dc@54240000 { - compatible = "nvidia,tegra20-dc"; - reg = <0x54240000 0x00040000>; - interrupts = <0 74 0x04>; - clocks = <&tegra_car TEGRA20_CLK_DISP2>, - <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - operating-points-v2 = <&dvfs_opp_table>; - power-domains = <&domain>; - - interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, - <&mc TEGRA20_MC_DISPLAY0BB &emc>, - <&mc TEGRA20_MC_DISPLAY0CB &emc>, - <&mc TEGRA20_MC_DISPLAYHCB &emc>; - interconnect-names = "wina", - "winb", - "winc", - "cursor"; - - rgb { - status = "disabled"; - }; - }; - - hdmi { - compatible = "nvidia,tegra20-hdmi"; - reg = <0x54280000 0x00040000>; - interrupts = <0 75 0x04>; - clocks = <&tegra_car TEGRA20_CLK_HDMI>, - <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - status = "disabled"; - operating-points-v2 = <&dvfs_opp_table>; - }; - - tvo { - compatible = "nvidia,tegra20-tvo"; - reg = <0x542c0000 0x00040000>; - interrupts = <0 76 0x04>; - clocks = <&tegra_car TEGRA20_CLK_TVO>; - status = "disabled"; - operating-points-v2 = <&dvfs_opp_table>; - }; - - dsi { - compatible = "nvidia,tegra20-dsi"; - reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA20_CLK_DSI>, - <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; - clock-names = "dsi", "parent"; - resets = <&tegra_car 48>; - reset-names = "dsi"; - status = "disabled"; - operating-points-v2 = <&dvfs_opp_table>; - }; - }; - - ... -}; diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-host1x.yaml b/dts/Bindings/display/tegra/nvidia,tegra20-host1x.yaml new file mode 100644 index 0000000000..94c5242c03 --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra20-host1x.yaml @@ -0,0 +1,430 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra host1x controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: The host1x top-level node defines a number of children, each + representing one of the host1x client modules defined in this binding. + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-host1x + - nvidia,tegra30-host1x + - nvidia,tegra114-host1x + - nvidia,tegra124-host1x + - nvidia,tegra210-host1x + - nvidia,tegra186-host1x + - nvidia,tegra194-host1x + - nvidia,tegra234-host1x + + - items: + - const: nvidia,tegra132-host1x + - const: nvidia,tegra124-host1x + + reg: + minItems: 1 + maxItems: 3 + + reg-names: + minItems: 1 + maxItems: 3 + + interrupts: + minItems: 1 + maxItems: 9 + + interrupt-names: + minItems: 1 + maxItems: 9 + + '#address-cells': + description: The number of cells used to represent physical base addresses + in the host1x address space. + enum: [1, 2] + + '#size-cells': + description: The number of cells used to represent the size of an address + range in the host1x address space. + enum: [1, 2] + + ranges: + maxItems: 1 + + clocks: + description: Must contain one entry, for the module clock. See + ../clocks/clock-bindings.txt for details. + + clock-names: + items: + - const: host1x + + resets: + minItems: 1 # MC reset is optional on Tegra186 and later + items: + - description: module reset + - description: memory client hotflush reset + + reset-names: + minItems: 1 # MC reset is optional on Tegra186 and later + items: + - const: host1x + - const: mc + + iommus: + maxItems: 1 + + interconnects: + items: + - description: memory read client for host1x + + interconnect-names: + items: + - const: dma-mem # read + + operating-points-v2: true + + power-domains: + items: + - description: phandle to the HEG or core power domain + +required: + - compatible + - interrupts + - interrupt-names + - '#address-cells' + - '#size-cells' + - ranges + - reg + - clocks + - clock-names + +unevaluatedProperties: + type: object + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-host1x + - nvidia,tegra30-host1x + - nvidia,tegra114-host1x + - nvidia,tegra124-host1x + - nvidia,tegra210-host1x + then: + properties: + interrupts: + items: + - description: host1x syncpoint interrupt + - description: host1x general interrupt + + interrupt-names: + items: + - const: syncpt + - const: host1x + required: + - resets + - reset-names + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-host1x + - nvidia,tegra194-host1x + then: + properties: + reg-names: + items: + - const: hypervisor + - const: vm + + reg: + items: + - description: region used by the hypervisor + - description: region assigned to the virtual machine + + resets: + maxItems: 1 + + reset-names: + maxItems: 1 + + interrupts: + items: + - description: host1x syncpoint interrupt + - description: host1x general interrupt + + interrupt-names: + items: + - const: syncpt + - const: host1x + + iommu-map: + description: Specification of stream IDs available for memory context device + use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to + usable stream IDs. + + required: + - reg-names + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra234-host1x + then: + properties: + reg-names: + items: + - const: common + - const: hypervisor + - const: vm + + reg: + items: + - description: region used by host1x server + - description: region used by the hypervisor + - description: region assigned to the virtual machine + + interrupts: + items: + - description: host1x syncpoint interrupt 0 + - description: host1x syncpoint interrupt 1 + - description: host1x syncpoint interrupt 2 + - description: host1x syncpoint interrupt 3 + - description: host1x syncpoint interrupt 4 + - description: host1x syncpoint interrupt 5 + - description: host1x syncpoint interrupt 6 + - description: host1x syncpoint interrupt 7 + - description: host1x general interrupt + + interrupt-names: + items: + - const: syncpt0 + - const: syncpt1 + - const: syncpt2 + - const: syncpt3 + - const: syncpt4 + - const: syncpt5 + - const: syncpt6 + - const: syncpt7 + - const: host1x + + iommu-map: + description: Specification of stream IDs available for memory context device + use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to + usable stream IDs. + + required: + - reg-names + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/gpio/tegra-gpio.h> + #include <dt-bindings/memory/tegra20-mc.h> + + host1x@50000000 { + compatible = "nvidia,tegra20-host1x"; + reg = <0x50000000 0x00024000>; + interrupts = <0 65 0x04>, /* mpcore syncpt */ + <0 67 0x04>; /* mpcore general */ + interrupt-names = "syncpt", "host1x"; + clocks = <&tegra_car TEGRA20_CLK_HOST1X>; + clock-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; + reset-names = "host1x", "mc"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x04000000>; + + mpe@54040000 { + compatible = "nvidia,tegra20-mpe"; + reg = <0x54040000 0x00040000>; + interrupts = <0 68 0x04>; + clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&tegra_car 60>; + reset-names = "mpe"; + }; + + vi@54080000 { + compatible = "nvidia,tegra20-vi"; + reg = <0x54080000 0x00040000>; + interrupts = <0 69 0x04>; + clocks = <&tegra_car TEGRA20_CLK_VI>; + resets = <&tegra_car 100>; + reset-names = "vi"; + }; + + epp@540c0000 { + compatible = "nvidia,tegra20-epp"; + reg = <0x540c0000 0x00040000>; + interrupts = <0 70 0x04>; + clocks = <&tegra_car TEGRA20_CLK_EPP>; + resets = <&tegra_car 19>; + reset-names = "epp"; + }; + + isp@54100000 { + compatible = "nvidia,tegra20-isp"; + reg = <0x54100000 0x00040000>; + interrupts = <0 71 0x04>; + clocks = <&tegra_car TEGRA20_CLK_ISP>; + resets = <&tegra_car 23>; + reset-names = "isp"; + }; + + gr2d@54140000 { + compatible = "nvidia,tegra20-gr2d"; + reg = <0x54140000 0x00040000>; + interrupts = <0 72 0x04>; + clocks = <&tegra_car TEGRA20_CLK_GR2D>; + resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; + reset-names = "2d", "mc"; + }; + + gr3d@54180000 { + compatible = "nvidia,tegra20-gr3d"; + reg = <0x54180000 0x00040000>; + clocks = <&tegra_car TEGRA20_CLK_GR3D>; + resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; + reset-names = "3d", "mc"; + }; + + dc@54200000 { + compatible = "nvidia,tegra20-dc"; + reg = <0x54200000 0x00040000>; + interrupts = <0 73 0x04>; + clocks = <&tegra_car TEGRA20_CLK_DISP1>; + clock-names = "dc"; + resets = <&tegra_car 27>; + reset-names = "dc"; + + rgb { + }; + }; + + dc@54240000 { + compatible = "nvidia,tegra20-dc"; + reg = <0x54240000 0x00040000>; + interrupts = <0 74 0x04>; + clocks = <&tegra_car TEGRA20_CLK_DISP2>; + clock-names = "dc"; + resets = <&tegra_car 26>; + reset-names = "dc"; + + rgb { + }; + }; + + hdmi@54280000 { + compatible = "nvidia,tegra20-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = <0 75 0x04>; + clocks = <&tegra_car TEGRA20_CLK_HDMI>, + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; + + hdmi-supply = <&vdd_5v0_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + vdd-supply = <&vdd_3v3_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + + tvo@542c0000 { + compatible = "nvidia,tegra20-tvo"; + reg = <0x542c0000 0x00040000>; + interrupts = <0 76 0x04>; + clocks = <&tegra_car TEGRA20_CLK_TVO>; + }; + + dsi@54300000 { + compatible = "nvidia,tegra20-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA20_CLK_DSI>, + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + }; + }; + + - | + #include <dt-bindings/clock/tegra210-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/tegra210-mc.h> + + host1x@50000000 { + compatible = "nvidia,tegra210-host1x"; + reg = <0x50000000 0x00024000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */ + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */ + interrupt-names = "syncpt", "host1x"; + clocks = <&tegra_car TEGRA210_CLK_HOST1X>; + clock-names = "host1x"; + resets = <&tegra_car 28>; + reset-names = "host1x"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x01000000>; + iommus = <&mc TEGRA_SWGROUP_HC>; + + vi@54080000 { + compatible = "nvidia,tegra210-vi"; + reg = <0x54080000 0x00000700>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>, + <972000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; + power-domains = <&pd_sor>; + }; + }; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-isp.yaml b/dts/Bindings/display/tegra/nvidia,tegra20-isp.yaml new file mode 100644 index 0000000000..3bc3b22e98 --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra20-isp.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra ISP processor + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + enum: + - nvidia,tegra20-isp + - nvidia,tegra30-isp + - nvidia,tegra210-isp + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: module clock + + resets: + items: + - description: module reset + + reset-names: + items: + - const: isp + + iommus: + maxItems: 1 + + interconnects: + items: + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # write + + power-domains: + items: + - description: phandle to the VENC or core power domain + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + isp@54100000 { + compatible = "nvidia,tegra20-isp"; + reg = <0x54100000 0x00040000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_ISP>; + resets = <&tegra_car 23>; + reset-names = "isp"; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-mpe.yaml b/dts/Bindings/display/tegra/nvidia,tegra20-mpe.yaml new file mode 100644 index 0000000000..2cd3e60cd0 --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra20-mpe.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Video Encoder + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + pattern: "^mpe@[0-9a-f]+$" + + compatible: + enum: + - nvidia,tegra20-mpe + - nvidia,tegra30-mpe + - nvidia,tegra114-mpe + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: module clock + + resets: + items: + - description: module reset + + reset-names: + items: + - const: mpe + + iommus: + maxItems: 1 + + interconnects: + maxItems: 6 + + interconnect-names: + maxItems: 6 + + operating-points-v2: true + + power-domains: + items: + - description: phandle to the MPE power domain + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + mpe@54040000 { + compatible = "nvidia,tegra20-mpe"; + reg = <0x54040000 0x00040000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&tegra_car 60>; + reset-names = "mpe"; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-tvo.yaml b/dts/Bindings/display/tegra/nvidia,tegra20-tvo.yaml new file mode 100644 index 0000000000..6c84d8b7eb --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra20-tvo.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-tvo.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra TV Encoder Output + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + pattern: "^tvo@[0-9a-f]+$" + + compatible: + enum: + - nvidia,tegra20-tvo + - nvidia,tegra30-tvo + - nvidia,tegra114-tvo + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: module clock + + operating-points-v2: true + + power-domains: + items: + - description: phandle to the core power domain + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tvo@542c0000 { + compatible = "nvidia,tegra20-tvo"; + reg = <0x542c0000 0x00040000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_TVO>; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-vi.yaml b/dts/Bindings/display/tegra/nvidia,tegra20-vi.yaml new file mode 100644 index 0000000000..2181855a09 --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra20-vi.yaml @@ -0,0 +1,221 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Video Input controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + pattern: "^vi@[0-9a-f]+$" + + compatible: + oneOf: + - const: nvidia,tegra20-vi + - const: nvidia,tegra30-vi + - const: nvidia,tegra114-vi + - const: nvidia,tegra124-vi + - items: + - const: nvidia,tegra132-vi + - const: nvidia,tegra124-vi + - const: nvidia,tegra210-vi + - const: nvidia,tegra186-vi + - const: nvidia,tegra194-vi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + items: + - description: module reset + + reset-names: + items: + - const: vi + + iommus: + maxItems: 1 + + interconnects: + minItems: 4 + maxItems: 5 + + interconnect-names: + minItems: 4 + maxItems: 5 + + operating-points-v2: true + + power-domains: + items: + - description: phandle to the VENC power domain + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: + maxItems: 1 + + avdd-dsi-csi-supply: + description: DSI/CSI power supply. Must supply 1.2 V. + + vip: + $ref: /schemas/display/tegra/nvidia,tegra20-vip.yaml + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Input from the VIP (parallel input capture) module + +patternProperties: + "^csi@[0-9a-f]+$": + type: object + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-vi + - nvidia,tegra30-vi + - nvidia,tegra114-vi + - nvidia,tegra124-vi + then: + required: + - resets + - reset-names + else: + required: + - power-domains + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + camera@48 { + compatible = "aptina,mt9v111"; + reg = <0x48>; + clocks = <&camera_clk>; + + port { + mt9v111_out: endpoint { + remote-endpoint = <&vi_vip_in>; + }; + }; + }; + }; + + vi@54080000 { + compatible = "nvidia,tegra20-vi"; + reg = <0x54080000 0x00040000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_VI>; + resets = <&tegra_car 100>; + reset-names = "vi"; + + vip { + compatible = "nvidia,tegra20-vip"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + vi_vip_in: endpoint { + remote-endpoint = <&mt9v111_out>; + }; + }; + port@1 { + reg = <1>; + vi_vip_out: endpoint { + remote-endpoint = <&vi_in>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + vi_in: endpoint { + remote-endpoint = <&vi_vip_out>; + }; + }; + }; + }; + + - | + #include <dt-bindings/clock/tegra210-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + vi@54080000 { + compatible = "nvidia,tegra210-vi"; + reg = <0x54080000 0x00000700>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>, + <972000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; + power-domains = <&pd_sor>; + }; + }; diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-vip.yaml b/dts/Bindings/display/tegra/nvidia,tegra20-vip.yaml new file mode 100644 index 0000000000..14294edb8d --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra20-vip.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra VIP (parallel video capture) controller + +maintainers: + - Luca Ceresoli <luca.ceresoli@bootlin.com> + +properties: + compatible: + enum: + - nvidia,tegra20-vip + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Port receiving the video stream from the sensor + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Port sending the video stream to the VI + + required: + - port@0 + - port@1 + +unevaluatedProperties: false + +required: + - compatible + - ports + +# see nvidia,tegra20-vi.yaml for an example diff --git a/dts/Bindings/display/tegra/nvidia,tegra210-csi.yaml b/dts/Bindings/display/tegra/nvidia,tegra210-csi.yaml new file mode 100644 index 0000000000..fa07a40d10 --- /dev/null +++ b/dts/Bindings/display/tegra/nvidia,tegra210-csi.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra CSI controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + $nodename: + pattern: "^csi@[0-9a-f]+$" + + compatible: + enum: + - nvidia,tegra210-csi + + reg: + maxItems: 1 + + clocks: + items: + - description: module clock + - description: A/B lanes clock + - description: C/D lanes clock + - description: E lane clock + - description: test pattern generator clock + + clock-names: + items: + - const: csi + - const: cilab + - const: cilcd + - const: cile + - const: csi_tpg + + power-domains: + maxItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + +# see nvidia,tegra20-vi.yaml for an example diff --git a/dts/Bindings/display/ti/ti,am65x-dss.yaml b/dts/Bindings/display/ti/ti,am65x-dss.yaml index 5c7d2cbc4a..b6767ef0d2 100644 --- a/dts/Bindings/display/ti/ti,am65x-dss.yaml +++ b/dts/Bindings/display/ti/ti,am65x-dss.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Texas Instruments Incorporated %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Texas Instruments AM65x Display Subsystem @@ -12,14 +12,19 @@ maintainers: - Tomi Valkeinen <tomi.valkeinen@ti.com> description: | - The AM65x TI Keystone Display SubSystem with two output ports and - two video planes. The first video port supports OLDI and the second - supports DPI format. The fist plane is full video plane with all - features and the second is a "lite plane" without scaling support. + The AM625 and AM65x TI Keystone Display SubSystem with two output + ports and two video planes. In AM65x DSS, the first video port + supports 1 OLDI TX and in AM625 DSS, the first video port output is + internally routed to 2 OLDI TXes. The second video port supports DPI + format. The first plane is full video plane with all features and the + second is a "lite plane" without scaling support. properties: compatible: - const: ti,am65x-dss + enum: + - ti,am625-dss + - ti,am62a7,dss + - ti,am65x-dss reg: description: @@ -80,7 +85,10 @@ properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: - The DSS OLDI output port node form video port 1 + For AM65x DSS, the OLDI output port node from video port 1. + For AM625 DSS, the internal DPI output port node from video + port 1. + For AM62A7 DSS, the port is tied off inside the SoC. port@1: $ref: /schemas/graph.yaml#/properties/port @@ -88,7 +96,7 @@ properties: The DSS DPI output port node from video port 2 ti,am65x-oldi-io-ctrl: - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle description: phandle to syscon device node mapping OLDI IO_CTRL registers. The mapped range should point to OLDI_DAT0_IO_CTRL, map it and @@ -102,6 +110,18 @@ properties: Input memory (from main memory to dispc) bandwidth limit in bytes per second +allOf: + - if: + properties: + compatible: + contains: + const: ti,am62a7-dss + then: + properties: + ports: + properties: + port@0: false + required: - compatible - reg diff --git a/dts/Bindings/display/ti/ti,j721e-dss.yaml b/dts/Bindings/display/ti/ti,j721e-dss.yaml index 2986f9acc9..fad7cba58d 100644 --- a/dts/Bindings/display/ti/ti,j721e-dss.yaml +++ b/dts/Bindings/display/ti/ti,j721e-dss.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Texas Instruments Incorporated %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Texas Instruments J721E Display Subsystem diff --git a/dts/Bindings/display/ti/ti,k2g-dss.yaml b/dts/Bindings/display/ti/ti,k2g-dss.yaml index 7ce7bbad57..96b1439f88 100644 --- a/dts/Bindings/display/ti/ti,k2g-dss.yaml +++ b/dts/Bindings/display/ti/ti,k2g-dss.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Texas Instruments Incorporated %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Texas Instruments K2G Display Subsystem diff --git a/dts/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml b/dts/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml index 10ec78ca1c..554f9d5809 100644 --- a/dts/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml +++ b/dts/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml @@ -117,6 +117,45 @@ properties: - const: dp-phy0 - const: dp-phy1 + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Connections to the programmable logic and the DisplayPort PHYs. Each port + shall have a single endpoint. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: The live video input from the programmable logic + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: The live graphics input from the programmable logic + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: The live audio input from the programmable logic + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: The blended video output to the programmable logic + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: The mixed audio output to the programmable logic + + port@5: + $ref: /schemas/graph.yaml#/properties/port + description: The DisplayPort output + + required: + - port@0 + - port@1 + - port@2 + - port@3 + - port@4 + - port@5 + required: - compatible - reg @@ -130,6 +169,7 @@ required: - dma-names - phys - phy-names + - ports additionalProperties: false @@ -164,6 +204,33 @@ examples: <&psgtr 0 PHY_TYPE_DP 1 3>; phy-names = "dp-phy0", "dp-phy1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + port@3 { + reg = <3>; + }; + port@4 { + reg = <4>; + }; + port@5 { + reg = <5>; + dpsub_dp_out: endpoint { + remote-endpoint = <&dp_connector>; + }; + }; + }; }; ... diff --git a/dts/Bindings/display/xylon,logicvc-display.yaml b/dts/Bindings/display/xylon,logicvc-display.yaml index fc02c5d50c..76b804b7c8 100644 --- a/dts/Bindings/display/xylon,logicvc-display.yaml +++ b/dts/Bindings/display/xylon,logicvc-display.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Bootlin %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Xylon LogiCVC display controller @@ -89,25 +89,25 @@ properties: description: Display output colorspace (C_DISPLAY_COLOR_SPACE). xylon,display-depth: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: Display output depth (C_PIXEL_DATA_WIDTH). xylon,row-stride: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: Fixed number of pixels in a framebuffer row (C_ROW_STRIDE). xylon,dithering: - $ref: "/schemas/types.yaml#/definitions/flag" + $ref: /schemas/types.yaml#/definitions/flag description: Dithering module is enabled (C_XCOLOR) xylon,background-layer: - $ref: "/schemas/types.yaml#/definitions/flag" + $ref: /schemas/types.yaml#/definitions/flag description: | The last layer is used to display a black background (C_USE_BACKGROUND). The layer must still be registered. xylon,layers-configurable: - $ref: "/schemas/types.yaml#/definitions/flag" + $ref: /schemas/types.yaml#/definitions/flag description: | Configuration of layers' size, position and offset is enabled (C_USE_SIZE_POSITION). @@ -131,7 +131,7 @@ properties: maxItems: 1 xylon,layer-depth: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: Layer depth (C_LAYER_X_DATA_WIDTH). xylon,layer-colorspace: @@ -151,19 +151,19 @@ properties: description: Alpha mode for the layer (C_LAYER_X_ALPHA_MODE). xylon,layer-base-offset: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: | Offset in number of lines (C_LAYER_X_OFFSET) starting from the video RAM base (C_VMEM_BASEADDR), only for version 3. xylon,layer-buffer-offset: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: | Offset in number of lines (C_BUFFER_*_OFFSET) starting from the layer base offset for the second buffer used in double-buffering. xylon,layer-primary: - $ref: "/schemas/types.yaml#/definitions/flag" + $ref: /schemas/types.yaml#/definitions/flag description: | Layer should be registered as a primary plane (exactly one is required). |