diff options
Diffstat (limited to 'dts/Bindings/display')
38 files changed, 521 insertions, 58 deletions
diff --git a/dts/Bindings/display/brcm,bcm-vc4.txt b/dts/Bindings/display/brcm,bcm-vc4.txt index 284e2b14cf..26649b4c4d 100644 --- a/dts/Bindings/display/brcm,bcm-vc4.txt +++ b/dts/Bindings/display/brcm,bcm-vc4.txt @@ -74,6 +74,12 @@ Required properties for DSI: The 3 clocks output from the DSI analog PHY: dsi[01]_byte, dsi[01]_ddr2, and dsi[01]_ddr +Required properties for the TXP (writeback) block: +- compatible: Should be "brcm,bcm2835-txp" +- reg: Physical base address and length of the TXP block's registers +- interrupts: The interrupt number + See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt + [1] Documentation/devicetree/bindings/media/video-interfaces.txt Example: diff --git a/dts/Bindings/display/bridge/analogix_dp.txt b/dts/Bindings/display/bridge/analogix_dp.txt index 0c7473dd0e..027d76c27a 100644 --- a/dts/Bindings/display/bridge/analogix_dp.txt +++ b/dts/Bindings/display/bridge/analogix_dp.txt @@ -15,8 +15,6 @@ Required properties for dp-controller: from common clock binding: handle to dp clock. -clock-names: from common clock binding: Shall be "dp". - -interrupt-parent: - phandle to Interrupt combiner node. -phys: from general PHY binding: the phandle for the PHY device. -phy-names: diff --git a/dts/Bindings/display/bridge/anx7814.txt b/dts/Bindings/display/bridge/anx7814.txt index b2a22c28c9..dbd7c84ee5 100644 --- a/dts/Bindings/display/bridge/anx7814.txt +++ b/dts/Bindings/display/bridge/anx7814.txt @@ -8,8 +8,6 @@ Required properties: - compatible : "analogix,anx7814" - reg : I2C address of the device - - interrupt-parent : Should be the phandle of the interrupt controller - that services interrupts for this device - interrupts : Should contain the INTP interrupt - hpd-gpios : Which GPIO to use for hpd - pd-gpios : Which GPIO to use for power down diff --git a/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt b/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt index aacc8b9296..09e0a21f70 100644 --- a/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt +++ b/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt @@ -19,8 +19,6 @@ hardware are EDID, HPD, and interrupts. stdp4028-ge-b850v3-fw required properties: - compatible : "megachips,stdp4028-ge-b850v3-fw" - reg : I2C bus address - - interrupt-parent : phandle of the interrupt controller that services - interrupts to the device - interrupts : one interrupt should be described here, as in <0 IRQ_TYPE_LEVEL_HIGH> - ports : One input port(reg = <0>) and one output port(reg = <1>) diff --git a/dts/Bindings/display/bridge/sii902x.txt b/dts/Bindings/display/bridge/sii902x.txt index 56a3e68ccb..72d2dc6c3e 100644 --- a/dts/Bindings/display/bridge/sii902x.txt +++ b/dts/Bindings/display/bridge/sii902x.txt @@ -5,8 +5,8 @@ Required properties: - reg: i2c address of the bridge Optional properties: - - interrupts-extended or interrupt-parent + interrupts: describe - the interrupt line used to inform the host about hotplug events. + - interrupts: describe the interrupt line used to inform the host + about hotplug events. - reset-gpios: OF device-tree gpio specification for RST_N pin. Optional subnodes: diff --git a/dts/Bindings/display/bridge/sii9234.txt b/dts/Bindings/display/bridge/sii9234.txt index 88041ba23d..a55bf77bd9 100644 --- a/dts/Bindings/display/bridge/sii9234.txt +++ b/dts/Bindings/display/bridge/sii9234.txt @@ -7,7 +7,7 @@ Required properties: - iovcc18-supply : I/O Supply Voltage (1.8V) - avcc12-supply : TMDS Analog Supply Voltage (1.2V) - cvcc12-supply : Digital Core Supply Voltage (1.2V) - - interrupts, interrupt-parent: interrupt specifier of INT pin + - interrupts: interrupt specifier of INT pin - reset-gpios: gpio specifier of RESET pin (active low) - video interfaces: Device node can contain two video interface port nodes for HDMI encoder and connector according to [1]. diff --git a/dts/Bindings/display/bridge/sil-sii8620.txt b/dts/Bindings/display/bridge/sil-sii8620.txt index 9409d9c6a2..b05052f7d6 100644 --- a/dts/Bindings/display/bridge/sil-sii8620.txt +++ b/dts/Bindings/display/bridge/sil-sii8620.txt @@ -5,7 +5,7 @@ Required properties: - reg: i2c address of the bridge - cvcc10-supply: Digital Core Supply Voltage (1.0V) - iovcc18-supply: I/O Supply Voltage (1.8V) - - interrupts, interrupt-parent: interrupt specifier of INT pin + - interrupts: interrupt specifier of INT pin - reset-gpios: gpio specifier of RESET pin - clocks, clock-names: specification and name of "xtal" clock - video interfaces: Device node can contain video interface port diff --git a/dts/Bindings/display/exynos/exynos7-decon.txt b/dts/Bindings/display/exynos/exynos7-decon.txt index 9e2e7f6f76..53912c99ec 100644 --- a/dts/Bindings/display/exynos/exynos7-decon.txt +++ b/dts/Bindings/display/exynos/exynos7-decon.txt @@ -9,9 +9,6 @@ Required properties: - reg: physical base address and length of the DECON registers set. -- interrupt-parent: should be the phandle of the decon controller's - parent interrupt controller. - - interrupts: should contain a list of all DECON IP block interrupts in the order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier format depends on the interrupt controller used. diff --git a/dts/Bindings/display/exynos/exynos_dp.txt b/dts/Bindings/display/exynos/exynos_dp.txt index ade5d8eebf..9b6cba3f82 100644 --- a/dts/Bindings/display/exynos/exynos_dp.txt +++ b/dts/Bindings/display/exynos/exynos_dp.txt @@ -25,8 +25,6 @@ Required properties for dp-controller: from common clock binding: handle to dp clock. -clock-names: from common clock binding: Shall be "dp". - -interrupt-parent: - phandle to Interrupt combiner node. -phys: from general PHY binding: the phandle for the PHY device. -phy-names: diff --git a/dts/Bindings/display/exynos/samsung-fimd.txt b/dts/Bindings/display/exynos/samsung-fimd.txt index 5837402c3a..b3096421d4 100644 --- a/dts/Bindings/display/exynos/samsung-fimd.txt +++ b/dts/Bindings/display/exynos/samsung-fimd.txt @@ -16,9 +16,6 @@ Required properties: - reg: physical base address and length of the FIMD registers set. -- interrupt-parent: should be the phandle of the fimd controller's - parent interrupt controller. - - interrupts: should contain a list of all FIMD IP block interrupts in the order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier format depends on the interrupt controller used. diff --git a/dts/Bindings/display/ht16k33.txt b/dts/Bindings/display/ht16k33.txt index 8e5b30b877..d5a8b070b4 100644 --- a/dts/Bindings/display/ht16k33.txt +++ b/dts/Bindings/display/ht16k33.txt @@ -4,8 +4,6 @@ Holtek ht16k33 RAM mapping 16*8 LED controller driver with keyscan Required properties: - compatible: "holtek,ht16k33" - reg: I2C slave address of the chip. -- interrupt-parent: A phandle pointing to the interrupt controller - serving the interrupt for this chip. - interrupts: Interrupt specification for the key pressed interrupt. - refresh-rate-hz: Display update interval in HZ. - debounce-delay-ms: Debouncing interval time in milliseconds. diff --git a/dts/Bindings/display/ilitek,ili9341.txt b/dts/Bindings/display/ilitek,ili9341.txt new file mode 100644 index 0000000000..169b32e4ee --- /dev/null +++ b/dts/Bindings/display/ilitek,ili9341.txt @@ -0,0 +1,27 @@ +Ilitek ILI9341 display panels + +This binding is for display panels using an Ilitek ILI9341 controller in SPI +mode. + +Required properties: +- compatible: "adafruit,yx240qv29", "ilitek,ili9341" +- dc-gpios: D/C pin +- reset-gpios: Reset pin + +The node for this driver must be a child node of a SPI controller, hence +all mandatory properties described in ../spi/spi-bus.txt must be specified. + +Optional properties: +- rotation: panel rotation in degrees counter clockwise (0,90,180,270) +- backlight: phandle of the backlight device attached to the panel + +Example: + display@0{ + compatible = "adafruit,yx240qv29", "ilitek,ili9341"; + reg = <0>; + spi-max-frequency = <32000000>; + dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + rotation = <270>; + backlight = <&backlight>; + }; diff --git a/dts/Bindings/display/marvell,pxa2xx-lcdc.txt b/dts/Bindings/display/marvell,pxa2xx-lcdc.txt index f79641bd5f..45ffd6c417 100644 --- a/dts/Bindings/display/marvell,pxa2xx-lcdc.txt +++ b/dts/Bindings/display/marvell,pxa2xx-lcdc.txt @@ -10,6 +10,9 @@ Required properties: - interrupts : framebuffer controller interrupt. - clocks: phandle to input clocks +Optional properties: + - lcd-supply: A phandle to a power regulator that controls the LCD voltage. + Required nodes: - port: connection to the LCD panel (see video-interfaces.txt) This node must have its properties bus-width and remote-endpoint set. diff --git a/dts/Bindings/display/marvell,pxa300-gcu.txt b/dts/Bindings/display/marvell,pxa300-gcu.txt new file mode 100644 index 0000000000..9cfae5c4e8 --- /dev/null +++ b/dts/Bindings/display/marvell,pxa300-gcu.txt @@ -0,0 +1,17 @@ +PXA3xx GCU Controller +--------------------- + +Required properties: + - compatible : "marvell,pxa300-gcu" + - reg : should contain the register range (address and length). + - interrupts : Controller interrupt. + - clocks: phandle to the PXA specific input clock. + +Example for PXA300: + + display-controller@54000000 { + compatible = "marvell,pxa300-gcu"; + reg = <0x54000000 0x1000>; + interrupts = <39>; + clocks = <&clks CLK_PXA300_GCU>; + }; diff --git a/dts/Bindings/display/mediatek/mediatek,disp.txt b/dts/Bindings/display/mediatek/mediatek,disp.txt index 383183a891..8469de5100 100644 --- a/dts/Bindings/display/mediatek/mediatek,disp.txt +++ b/dts/Bindings/display/mediatek/mediatek,disp.txt @@ -40,7 +40,7 @@ Required properties (all function blocks): "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt "mediatek,<chip>-disp-mutex" - display mutex "mediatek,<chip>-disp-od" - overdrive - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt2712 and mt8173. - reg: Physical base address and length of the function block register space - interrupts: The interrupt signal from the function block (required, except for merge and split function blocks). diff --git a/dts/Bindings/display/msm/dpu.txt b/dts/Bindings/display/msm/dpu.txt new file mode 100644 index 0000000000..ad2e883032 --- /dev/null +++ b/dts/Bindings/display/msm/dpu.txt @@ -0,0 +1,131 @@ +Qualcomm Technologies, Inc. DPU KMS + +Description: + +Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates +sub-blocks like DPU display controller, DSI and DP interfaces etc. +The DPU display controller is found in SDM845 SoC. + +MDSS: +Required properties: +- compatible: "qcom,sdm845-mdss" +- reg: physical base address and length of contoller's registers. +- reg-names: register region names. The following region is required: + * "mdss" +- power-domains: a power domain consumer specifier according to + Documentation/devicetree/bindings/power/power_domain.txt +- clocks: list of clock specifiers for clocks needed by the device. +- clock-names: device clock names, must be in same order as clocks property. + The following clocks are required: + * "iface" + * "bus" + * "core" +- interrupts: interrupt signal from MDSS. +- interrupt-controller: identifies the node as an interrupt controller. +- #interrupt-cells: specifies the number of cells needed to encode an interrupt + source, should be 1. +- iommus: phandle of iommu device node. +- #address-cells: number of address cells for the MDSS children. Should be 1. +- #size-cells: Should be 1. +- ranges: parent bus address space is the same as the child bus address space. + +Optional properties: +- assigned-clocks: list of clock specifiers for clocks needing rate assignment +- assigned-clock-rates: list of clock frequencies sorted in the same order as + the assigned-clocks property. + +MDP: +Required properties: +- compatible: "qcom,sdm845-dpu" +- reg: physical base address and length of controller's registers. +- reg-names : register region names. The following region is required: + * "mdp" + * "vbif" +- clocks: list of clock specifiers for clocks needed by the device. +- clock-names: device clock names, must be in same order as clocks property. + The following clocks are required. + * "bus" + * "iface" + * "core" + * "vsync" +- interrupts: interrupt line from DPU to MDSS. +- ports: contains the list of output ports from DPU device. These ports connect + to interfaces that are external to the DPU hardware, such as DSI, DP etc. + + Each output port contains an endpoint that describes how it is connected to an + external interface. These are described by the standard properties documented + here: + Documentation/devicetree/bindings/graph.txt + Documentation/devicetree/bindings/media/video-interfaces.txt + + Port 0 -> DPU_INTF1 (DSI1) + Port 1 -> DPU_INTF2 (DSI2) + +Optional properties: +- assigned-clocks: list of clock specifiers for clocks needing rate assignment +- assigned-clock-rates: list of clock frequencies sorted in the same order as + the assigned-clocks property. + +Example: + + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0xae00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&clock_dispcc 0>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_iommu 0>; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xae00000 0xb2008>; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <0 0 300000000 19200000>; + + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/display/msm/dsi.txt b/dts/Bindings/display/msm/dsi.txt index 518e9cdf0d..dfc743219b 100644 --- a/dts/Bindings/display/msm/dsi.txt +++ b/dts/Bindings/display/msm/dsi.txt @@ -43,8 +43,6 @@ Optional properties: the master link of the 2-DSI panel. - qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is driving a 2-DSI panel whose 2 links need receive command simultaneously. -- interrupt-parent: phandle to the MDP block if the interrupt signal is routed - through MDP block - pinctrl-names: the pin control state names; should contain "default" - pinctrl-0: the default pinctrl state (active) - pinctrl-n: the "sleep" pinctrl state @@ -121,6 +119,20 @@ Required properties: Optional properties: - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY regulator is wanted. +- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split is enabled, this time should not be higher + than two times the dsi link rate time. + If the property is not specified, then the default value is 14000 us. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Documentation/devicetree/bindings/graph.txt @@ -171,6 +183,8 @@ Example: qcom,master-dsi; qcom,sync-dual-dsi; + qcom,mdss-mdp-transfer-time-us = <12000>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&dsi_active>; pinctrl-1 = <&dsi_suspend>; diff --git a/dts/Bindings/display/msm/edp.txt b/dts/Bindings/display/msm/edp.txt index 95ce19ca7b..eff9daff41 100644 --- a/dts/Bindings/display/msm/edp.txt +++ b/dts/Bindings/display/msm/edp.txt @@ -25,10 +25,6 @@ Required properties: - panel-hpd-gpios: GPIO pin used for eDP hpd. -Optional properties: -- interrupt-parent: phandle to the MDP block if the interrupt signal is routed - through MDP block - Example: mdss_edp: qcom,mdss_edp@fd923400 { compatible = "qcom,mdss-edp"; diff --git a/dts/Bindings/display/msm/mdp5.txt b/dts/Bindings/display/msm/mdp5.txt index 1b31977a68..4e11338548 100644 --- a/dts/Bindings/display/msm/mdp5.txt +++ b/dts/Bindings/display/msm/mdp5.txt @@ -41,8 +41,6 @@ Required properties: - reg-names: The names of register regions. The following regions are required: * "mdp_phys" - interrupts: Interrupt line from MDP5 to MDSS interrupt controller. -- interrupt-parent: phandle to the MDSS block - through MDP block - clocks: device clocks. See ../clocks/clock-bindings.txt for details. - clock-names: the following clocks are required. - * "bus" diff --git a/dts/Bindings/display/panel/auo,g070vvn01.txt b/dts/Bindings/display/panel/auo,g070vvn01.txt new file mode 100644 index 0000000000..49e4105378 --- /dev/null +++ b/dts/Bindings/display/panel/auo,g070vvn01.txt @@ -0,0 +1,29 @@ +AU Optronics Corporation 7.0" FHD (800 x 480) TFT LCD panel + +Required properties: +- compatible: should be "auo,g070vvn01" +- backlight: phandle of the backlight device attached to the panel +- power-supply: single regulator to provide the supply voltage + +Required nodes: +- port: Parallel port mapping to connect this display + +This panel needs single power supply voltage. Its backlight is conntrolled +via PWM signal. + +Example: +-------- + +Example device-tree definition when connected to iMX6Q based board + + lcd_panel: lcd-panel { + compatible = "auo,g070vvn01"; + backlight = <&backlight_lcd>; + power-supply = <®_display>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; diff --git a/dts/Bindings/display/panel/boe,hv070wsa-100.txt b/dts/Bindings/display/panel/boe,hv070wsa-100.txt new file mode 100644 index 0000000000..55183d3600 --- /dev/null +++ b/dts/Bindings/display/panel/boe,hv070wsa-100.txt @@ -0,0 +1,28 @@ +BOE HV070WSA-100 7.01" WSVGA TFT LCD panel + +Required properties: +- compatible: should be "boe,hv070wsa-100" +- power-supply: regulator to provide the VCC supply voltage (3.3 volts) +- enable-gpios: GPIO pin to enable and disable panel (active high) + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. + +The device node can contain one 'port' child node with one child +'endpoint' node, according to the bindings defined in [1]. This +node should describe panel's video bus. + +[1]: Documentation/devicetree/bindings/media/video-interfaces.txt + +Example: + + panel: panel { + compatible = "boe,hv070wsa-100"; + power-supply = <&vcc_3v3_reg>; + enable-gpios = <&gpd1 3 GPIO_ACTIVE_HIGH>; + port { + panel_ep: endpoint { + remote-endpoint = <&bridge_out_ep>; + }; + }; + }; diff --git a/dts/Bindings/display/panel/dataimage,scf0700c48ggu18.txt b/dts/Bindings/display/panel/dataimage,scf0700c48ggu18.txt new file mode 100644 index 0000000000..897085ee3c --- /dev/null +++ b/dts/Bindings/display/panel/dataimage,scf0700c48ggu18.txt @@ -0,0 +1,8 @@ +DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface. + +Required properties: +- compatible: should be "dataimage,scf0700c48ggu18" +- power-supply: as specified in the base binding + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/dts/Bindings/display/panel/dlc,dlc0700yzg-1.txt b/dts/Bindings/display/panel/dlc,dlc0700yzg-1.txt new file mode 100644 index 0000000000..bf06bb025b --- /dev/null +++ b/dts/Bindings/display/panel/dlc,dlc0700yzg-1.txt @@ -0,0 +1,13 @@ +DLC Display Co. DLC0700YZG-1 7.0" WSVGA TFT LCD panel + +Required properties: +- compatible: should be "dlc,dlc0700yzg-1" +- power-supply: See simple-panel.txt + +Optional properties: +- reset-gpios: See panel-common.txt +- enable-gpios: See simple-panel.txt +- backlight: See simple-panel.txt + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/dts/Bindings/display/panel/edt,et-series.txt b/dts/Bindings/display/panel/edt,et-series.txt new file mode 100644 index 0000000000..f56b99ebd9 --- /dev/null +++ b/dts/Bindings/display/panel/edt,et-series.txt @@ -0,0 +1,39 @@ +Emerging Display Technology Corp. Displays +========================================== + + +Display bindings for EDT Display Technology Corp. Displays which are +compatible with the simple-panel binding, which is specified in +simple-panel.txt + + +5,7" WVGA TFT Panels +-------------------- + ++-----------------+---------------------+-------------------------------------+ +| Identifier | compatbile | description | ++=================+=====================+=====================================+ +| ET057090DHU | edt,et057090dhu | 5.7" VGA TFT LCD panel | ++-----------------+---------------------+-------------------------------------+ + + +7,0" WVGA TFT Panels +-------------------- + ++-----------------+---------------------+-------------------------------------+ +| Identifier | compatbile | description | ++=================+=====================+=====================================+ +| ETM0700G0DH6 | edt,etm070080dh6 | WVGA TFT Display with capacitive | +| | | Touchscreen | ++-----------------+---------------------+-------------------------------------+ +| ETM0700G0BDH6 | edt,etm070080bdh6 | Same as ETM0700G0DH6 but with | +| | | inverted pixel clock. | ++-----------------+---------------------+-------------------------------------+ +| ETM0700G0EDH6 | edt,etm070080edh6 | Same display as the ETM0700G0BDH6, | +| | | but with changed Hardware for the | +| | | backlight and the touch interface | ++-----------------+---------------------+-------------------------------------+ +| ET070080DH6 | edt,etm070080dh6 | Same timings as the ETM0700G0DH6, | +| | | but with resistive touch. | ++-----------------+---------------------+-------------------------------------+ + diff --git a/dts/Bindings/display/panel/edt,et070080dh6.txt b/dts/Bindings/display/panel/edt,et070080dh6.txt deleted file mode 100644 index 20cb38e836..0000000000 --- a/dts/Bindings/display/panel/edt,et070080dh6.txt +++ /dev/null @@ -1,10 +0,0 @@ -Emerging Display Technology Corp. ET070080DH6 7.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "edt,et070080dh6" - -This panel is the same as ETM0700G0DH6 except for the touchscreen. -ET070080DH6 is the model with resistive touch. - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/dts/Bindings/display/panel/edt,etm0700g0dh6.txt b/dts/Bindings/display/panel/edt,etm0700g0dh6.txt deleted file mode 100644 index ee4b18053e..0000000000 --- a/dts/Bindings/display/panel/edt,etm0700g0dh6.txt +++ /dev/null @@ -1,10 +0,0 @@ -Emerging Display Technology Corp. ETM0700G0DH6 7.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "edt,etm0700g0dh6" - -This panel is the same as ET070080DH6 except for the touchscreen. -ETM0700G0DH6 is the model with capacitive multitouch. - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/dts/Bindings/display/panel/ilitek,ili9881c.txt b/dts/Bindings/display/panel/ilitek,ili9881c.txt new file mode 100644 index 0000000000..4a041acb4e --- /dev/null +++ b/dts/Bindings/display/panel/ilitek,ili9881c.txt @@ -0,0 +1,20 @@ +Ilitek ILI9881c based MIPI-DSI panels + +Required properties: + - compatible: must be "ilitek,ili9881c" and one of: + * "bananapi,lhr050h41" + - reg: DSI virtual channel used by that screen + - power-supply: phandle to the power regulator + - reset-gpios: a GPIO phandle for the reset pin + +Optional properties: + - backlight: phandle to the backlight used + +Example: +panel@0 { + compatible = "bananapi,lhr050h41", "ilitek,ili9881c"; + reg = <0>; + power-supply = <®_display>; + reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */ + backlight = <&pwm_bl>; +}; diff --git a/dts/Bindings/display/panel/innolux,g070y2-l01.txt b/dts/Bindings/display/panel/innolux,g070y2-l01.txt new file mode 100644 index 0000000000..7c234cf68e --- /dev/null +++ b/dts/Bindings/display/panel/innolux,g070y2-l01.txt @@ -0,0 +1,12 @@ +Innolux G070Y2-L01 7" WVGA (800x480) TFT LCD panel + +Required properties: +- compatible: should be "innolux,g070y2-l01" +- power-supply: as specified in the base binding + +Optional properties: +- backlight: as specified in the base binding +- enable-gpios: as specified in the base binding + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/dts/Bindings/display/panel/innolux,p097pfg.txt b/dts/Bindings/display/panel/innolux,p097pfg.txt new file mode 100644 index 0000000000..595d9dfeff --- /dev/null +++ b/dts/Bindings/display/panel/innolux,p097pfg.txt @@ -0,0 +1,24 @@ +Innolux P097PFG 9.7" 1536x2048 TFT LCD panel + +Required properties: +- compatible: should be "innolux,p097pfg" +- reg: DSI virtual channel of the peripheral +- avdd-supply: phandle of the regulator that provides positive voltage +- avee-supply: phandle of the regulator that provides negative voltage +- enable-gpios: panel enable gpio + +Optional properties: +- backlight: phandle of the backlight device attached to the panel + +Example: + + &mipi_dsi { + panel { + compatible = "innolux,p079zca"; + reg = <0>; + avdd-supply = <...>; + avee-supply = <...>; + backlight = <&backlight>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/dts/Bindings/display/panel/innolux,tv123wam.txt b/dts/Bindings/display/panel/innolux,tv123wam.txt new file mode 100644 index 0000000000..a9b35265fa --- /dev/null +++ b/dts/Bindings/display/panel/innolux,tv123wam.txt @@ -0,0 +1,20 @@ +Innolux TV123WAM 12.3 inch eDP 2K display panel + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. + +Required properties: +- compatible: should be "innolux,tv123wam" +- power-supply: regulator to provide the supply voltage + +Optional properties: +- enable-gpios: GPIO pin to enable or disable the panel +- backlight: phandle of the backlight device attached to the panel + +Example: + panel_edp: panel-edp { + compatible = "innolux,tv123wam"; + enable-gpios = <&msmgpio 31 GPIO_ACTIVE_LOW>; + power-supply = <&pm8916_l2>; + backlight = <&backlight>; + }; diff --git a/dts/Bindings/display/panel/kingdisplay,kd097d04.txt b/dts/Bindings/display/panel/kingdisplay,kd097d04.txt new file mode 100644 index 0000000000..164a5fa236 --- /dev/null +++ b/dts/Bindings/display/panel/kingdisplay,kd097d04.txt @@ -0,0 +1,22 @@ +Kingdisplay KD097D04 9.7" 1536x2048 TFT LCD panel + +Required properties: +- compatible: should be "kingdisplay,kd097d04" +- reg: DSI virtual channel of the peripheral +- power-supply: phandle of the regulator that provides the supply voltage +- enable-gpios: panel enable gpio + +Optional properties: +- backlight: phandle of the backlight device attached to the panel + +Example: + + &mipi_dsi { + panel { + compatible = "kingdisplay,kd097d04"; + reg = <0>; + power-supply = <...>; + backlight = <&backlight>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/dts/Bindings/display/panel/edt,et057090dhu.txt b/dts/Bindings/display/panel/newhaven,nhd-4.3-480272ef-atxl.txt index 4903d7b1d9..e78292b1a1 100644 --- a/dts/Bindings/display/panel/edt,et057090dhu.txt +++ b/dts/Bindings/display/panel/newhaven,nhd-4.3-480272ef-atxl.txt @@ -1,7 +1,7 @@ -Emerging Display Technology Corp. 5.7" VGA TFT LCD panel +Newhaven Display International 480 x 272 TFT LCD panel Required properties: -- compatible: should be "edt,et057090dhu" +- compatible: should be "newhaven,nhd-4.3-480272ef-atxl" This binding is compatible with the simple-panel binding, which is specified in simple-panel.txt in this directory. diff --git a/dts/Bindings/display/panel/rocktech,rk070er9427.txt b/dts/Bindings/display/panel/rocktech,rk070er9427.txt new file mode 100644 index 0000000000..eb1fb9f8d1 --- /dev/null +++ b/dts/Bindings/display/panel/rocktech,rk070er9427.txt @@ -0,0 +1,25 @@ +Rocktech Display Ltd. RK070ER9427 800(RGB)x480 TFT LCD panel + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. + +Required properties: +- compatible: should be "rocktech,rk070er9427" + +Optional properties: +- backlight: phandle of the backlight device attached to the panel + +Optional nodes: +- Video port for LCD panel input. + +Example: + panel { + compatible = "rocktech,rk070er9427"; + backlight = <&backlight_lcd>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; diff --git a/dts/Bindings/display/panel/sharp,lq035q7db03.txt b/dts/Bindings/display/panel/sharp,lq035q7db03.txt new file mode 100644 index 0000000000..0753f69672 --- /dev/null +++ b/dts/Bindings/display/panel/sharp,lq035q7db03.txt @@ -0,0 +1,12 @@ +Sharp LQ035Q7DB03 3.5" QVGA TFT LCD panel + +Required properties: +- compatible: should be "sharp,lq035q7db03" +- power-supply: phandle of the regulator that provides the supply voltage + +Optional properties: +- enable-gpios: GPIO pin to enable or disable the panel +- backlight: phandle of the backlight device attached to the panel + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/dts/Bindings/display/renesas,du.txt b/dts/Bindings/display/renesas,du.txt index 7c6854bd0a..ec9d34be2f 100644 --- a/dts/Bindings/display/renesas,du.txt +++ b/dts/Bindings/display/renesas,du.txt @@ -19,7 +19,6 @@ Required Properties: - reg: the memory-mapped I/O registers base address and length - - interrupt-parent: phandle of the parent interrupt controller. - interrupts: Interrupt specifiers for the DU interrupts. - clocks: A list of phandles + clock-specifier pairs, one for each entry in diff --git a/dts/Bindings/display/sm501fb.txt b/dts/Bindings/display/sm501fb.txt index 9d9f009809..1c79c267a5 100644 --- a/dts/Bindings/display/sm501fb.txt +++ b/dts/Bindings/display/sm501fb.txt @@ -9,8 +9,6 @@ Required properties: - First entry: System Configuration register - Second entry: IO space (Display Controller register) - interrupts : SMI interrupt to the cpu should be described here. -- interrupt-parent : the phandle for the interrupt controller that - services interrupts for this device. Optional properties: - mode : select a video mode: diff --git a/dts/Bindings/display/sunxi/sun4i-drm.txt b/dts/Bindings/display/sunxi/sun4i-drm.txt index 3346c1e2a7..f8773ecb75 100644 --- a/dts/Bindings/display/sunxi/sun4i-drm.txt +++ b/dts/Bindings/display/sunxi/sun4i-drm.txt @@ -103,6 +103,7 @@ Required properties: - compatible: value must be one of: * allwinner,sun8i-a83t-hdmi-phy * allwinner,sun8i-h3-hdmi-phy + * allwinner,sun50i-a64-hdmi-phy - reg: base address and size of memory-mapped region - clocks: phandles to the clocks feeding the HDMI PHY * bus: the HDMI PHY interface clock @@ -111,8 +112,9 @@ Required properties: - resets: phandle to the reset controller driving the PHY - reset-names: must be "phy" -H3 HDMI PHY requires additional clock: +H3 and A64 HDMI PHY require additional clocks: - pll-0: parent of phy clock + - pll-1: second possible phy clock parent (A64 only) TV Encoder ---------- @@ -145,6 +147,7 @@ Required properties: * allwinner,sun8i-a33-tcon * allwinner,sun8i-a83t-tcon-lcd * allwinner,sun8i-a83t-tcon-tv + * allwinner,sun8i-r40-tcon-tv * allwinner,sun8i-v3s-tcon * allwinner,sun9i-a80-tcon-lcd * allwinner,sun9i-a80-tcon-tv @@ -179,7 +182,7 @@ For TCONs with channel 0, there is one more clock required: For TCONs with channel 1, there is one more clock required: - 'tcon-ch1': The clock driving the TCON channel 1 -When TCON support LVDS (all TCONs except TV TCON on A83T and those found +When TCON support LVDS (all TCONs except TV TCONs on A83T, R40 and those found in A13, H3, H5 and V3s SoCs), you need one more reset line: - 'lvds': The reset line driving the LVDS logic @@ -187,6 +190,62 @@ And on the A23, A31, A31s and A33, you need one more clock line: - 'lvds-alt': An alternative clock source, separate from the TCON channel 0 clock, that can be used to drive the LVDS clock +TCON TOP +-------- + +TCON TOPs main purpose is to configure whole display pipeline. It determines +relationships between mixers and TCONs, selects source TCON for HDMI, muxes +LCD and TV encoder GPIO output, selects TV encoder clock source and contains +additional TV TCON and DSI gates. + +It allows display pipeline to be configured in very different ways: + + / LCD0/LVDS0 + / [0] TCON-LCD0 + | \ MIPI DSI + mixer0 | + \ / [1] TCON-LCD1 - LCD1/LVDS1 + TCON-TOP + / \ [2] TCON-TV0 [0] - TVE0/RGB + mixer1 | \ + | TCON-TOP - HDMI + | / + \ [3] TCON-TV1 [1] - TVE1/RGB + +Note that both TCON TOP references same physical unit. Both mixers can be +connected to any TCON. + +Required properties: + - compatible: value must be one of: + * allwinner,sun8i-r40-tcon-top + - reg: base address and size of the memory-mapped region. + - clocks: phandle to the clocks feeding the TCON TOP + * bus: TCON TOP interface clock + * tcon-tv0: TCON TV0 clock + * tve0: TVE0 clock + * tcon-tv1: TCON TV1 clock + * tve1: TVE0 clock + * dsi: MIPI DSI clock + - clock-names: clock name mentioned above + - resets: phandle to the reset line driving the TCON TOP + - #clock-cells : must contain 1 + - clock-output-names: Names of clocks created for TCON TV0 channel clock, + TCON TV1 channel clock and DSI channel clock, in that order. + +- ports: A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. 6 ports should + be defined: + * port 0 is input for mixer0 mux + * port 1 is output for mixer0 mux + * port 2 is input for mixer1 mux + * port 3 is output for mixer1 mux + * port 4 is input for HDMI mux + * port 5 is output for HDMI mux + All output endpoints for mixer muxes and input endpoints for HDMI mux should + have reg property with the id of the target TCON, as shown in above graph + (0-3 for mixer muxes and 0-1 for HDMI mux). All ports should have only one + endpoint connected to remote endpoint. + DRC --- @@ -341,6 +400,7 @@ Required properties: * allwinner,sun8i-a33-display-engine * allwinner,sun8i-a83t-display-engine * allwinner,sun8i-h3-display-engine + * allwinner,sun8i-r40-display-engine * allwinner,sun8i-v3s-display-engine * allwinner,sun9i-a80-display-engine diff --git a/dts/Bindings/display/tilcdc/tilcdc.txt b/dts/Bindings/display/tilcdc/tilcdc.txt index 3055d5c2c0..7bf1bb4448 100644 --- a/dts/Bindings/display/tilcdc/tilcdc.txt +++ b/dts/Bindings/display/tilcdc/tilcdc.txt @@ -8,8 +8,6 @@ Required properties: - reg: base address and size of the LCDC device Recommended properties: - - interrupt-parent: the phandle for the interrupt controller that - services interrupts for this device. - ti,hwmods: Name of the hwmod associated to the LCDC Optional properties: |