diff options
Diffstat (limited to 'dts/Bindings/dma/snps,dw-axi-dmac.yaml')
| -rw-r--r-- | dts/Bindings/dma/snps,dw-axi-dmac.yaml | 69 |
1 files changed, 47 insertions, 22 deletions
diff --git a/dts/Bindings/dma/snps,dw-axi-dmac.yaml b/dts/Bindings/dma/snps,dw-axi-dmac.yaml index 4324a94b26..363cf8bd15 100644 --- a/dts/Bindings/dma/snps,dw-axi-dmac.yaml +++ b/dts/Bindings/dma/snps,dw-axi-dmac.yaml @@ -8,19 +8,19 @@ title: Synopsys DesignWare AXI DMA Controller maintainers: - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> - - Jee Heng Sia <jee.heng.sia@intel.com> description: Synopsys DesignWare AXI DMA Controller DT Binding allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: enum: - snps,axi-dma-1.01a - intel,kmb-axi-dma + - starfive,jh7110-axi-dma reg: minItems: 1 @@ -34,7 +34,12 @@ properties: - const: axidma_apb_regs interrupts: - maxItems: 1 + description: + If the IP-core synthesis parameter DMAX_INTR_IO_TYPE is set to 1, this + will be per-channel interrupts. Otherwise, this is a single combined IRQ + for all channels. + minItems: 1 + maxItems: 8 clocks: items: @@ -54,7 +59,8 @@ properties: maximum: 8 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 snps,dma-masters: description: | @@ -105,25 +111,44 @@ required: - snps,priority - snps,block-size +if: + properties: + compatible: + contains: + enum: + - starfive,jh7110-axi-dma +then: + properties: + resets: + minItems: 2 + items: + - description: AXI reset line + - description: AHB reset line + - description: module reset +else: + properties: + resets: + maxItems: 1 + additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/interrupt-controller/irq.h> - /* example with snps,dw-axi-dmac */ - dmac: dma-controller@80000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0x80000 0x400>; - clocks = <&core_clk>, <&cfgr_clk>; - clock-names = "core-clk", "cfgr-clk"; - interrupt-parent = <&intc>; - interrupts = <27>; - #dma-cells = <1>; - dma-channels = <4>; - snps,dma-masters = <2>; - snps,data-width = <3>; - snps,block-size = <4096 4096 4096 4096>; - snps,priority = <0 1 2 3>; - snps,axi-max-burst-len = <16>; - }; + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + /* example with snps,dw-axi-dmac */ + dma-controller@80000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x80000 0x400>; + clocks = <&core_clk>, <&cfgr_clk>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = <27>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <2>; + snps,data-width = <3>; + snps,block-size = <4096 4096 4096 4096>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <16>; + }; |