diff options
Diffstat (limited to 'dts/Bindings/dma/st,stm32-dma.yaml')
| -rw-r--r-- | dts/Bindings/dma/st,stm32-dma.yaml | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/dts/Bindings/dma/st,stm32-dma.yaml b/dts/Bindings/dma/st,stm32-dma.yaml index 0c0ac11ad5..329847ef09 100644 --- a/dts/Bindings/dma/st,stm32-dma.yaml +++ b/dts/Bindings/dma/st,stm32-dma.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: STMicroelectronics STM32 DMA Controller bindings +title: STMicroelectronics STM32 DMA Controller description: | The STM32 DMA is a general-purpose direct memory access controller capable of @@ -36,12 +36,24 @@ description: | 0x1: 1/2 full FIFO 0x2: 3/4 full FIFO 0x3: full FIFO + -bit 2: DMA direct mode + 0x0: FIFO mode with threshold selectable with bit 0-1 + 0x1: Direct mode: each DMA request immediately initiates a transfer + from/to the memory, FIFO is bypassed. + -bit 4: alternative DMA request/acknowledge protocol + 0x0: Use standard DMA ACK management, where ACK signal is maintained + up to the removal of request and transfer completion + 0x1: Use alternative DMA ACK management, where ACK de-assertion does + not wait for the de-assertion of the REQuest, ACK is only managed + by transfer completion. This must only be used on channels + managing transfers for STM32 USART/UART. + maintainers: - - Amelie Delaunay <amelie.delaunay@st.com> + - Amelie Delaunay <amelie.delaunay@foss.st.com> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: "#dma-cells": @@ -76,6 +88,8 @@ required: - clocks - interrupts +unevaluatedProperties: false + examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> |