diff options
Diffstat (limited to 'dts/Bindings/fpga/fpga-region.txt')
| -rw-r--r-- | dts/Bindings/fpga/fpga-region.txt | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/dts/Bindings/fpga/fpga-region.txt b/dts/Bindings/fpga/fpga-region.txt index 7d35152648..528df8a0e6 100644 --- a/dts/Bindings/fpga/fpga-region.txt +++ b/dts/Bindings/fpga/fpga-region.txt @@ -63,7 +63,7 @@ FPGA Bridge will be disabled. * During Partial Reconfiguration of a specific region, that region's bridge will be used to gate the busses. Traffic to other regions is not affected. - * In some implementations, the FPGA Manager transparantly handles gating the + * In some implementations, the FPGA Manager transparently handles gating the buses, eliminating the need to show the hardware FPGA bridges in the device tree. * An FPGA image may create a set of reprogrammable regions, each having its @@ -330,7 +330,7 @@ succeeded. The Device Tree Overlay will contain: * "target-path" or "target" - The insertion point where the the contents of the overlay will go into the + The insertion point where the contents of the overlay will go into the live tree. target-path is a full path, while target is a phandle. * "ranges" The address space mapping from processor to FPGA bus(ses). @@ -466,7 +466,7 @@ It is beyond the scope of this document to fully describe all the FPGA design constraints required to make partial reconfiguration work[1] [2] [3], but a few deserve quick mention. -A persona must have boundary connections that line up with those of the partion +A persona must have boundary connections that line up with those of the partition or region it is designed to go into. During programming, transactions through those connections must be stopped and |