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-Device tree configuration for i2c-ocores
-
-Required properties:
-- compatible : "opencores,i2c-ocores"
- "aeroflexgaisler,i2cmst"
- "sifive,fu540-c000-i2c", "sifive,i2c0"
- For Opencore based I2C IP block reimplemented in
- FU540-C000 SoC.
- "sifive,fu740-c000-i2c", "sifive,i2c0"
- For Opencore based I2C IP block reimplemented in
- FU740-C000 SoC.
- Please refer to sifive-blocks-ip-versioning.txt for
- additional details.
-- reg : bus address start and address range size of device
-- clocks : handle to the controller clock; see the note below.
- Mutually exclusive with opencores,ip-clock-frequency
-- opencores,ip-clock-frequency: frequency of the controller clock in Hz;
- see the note below. Mutually exclusive with clocks
-- #address-cells : should be <1>
-- #size-cells : should be <0>
-
-Optional properties:
-- interrupts : interrupt number.
-- clock-frequency : frequency of bus clock in Hz; see the note below.
- Defaults to 100 KHz when the property is not specified
-- reg-shift : device register offsets are shifted by this value
-- reg-io-width : io register width in bytes (1, 2 or 4)
-- regstep : deprecated, use reg-shift above
-
-Note
-clock-frequency property is meant to control the bus frequency for i2c bus
-drivers, but it was incorrectly used to specify i2c controller input clock
-frequency. So the following rules are set to fix this situation:
-- if clock-frequency is present and neither opencores,ip-clock-frequency nor
- clocks are, then clock-frequency specifies i2c controller clock frequency.
- This is to keep backwards compatibility with setups using old DTB. i2c bus
- frequency is fixed at 100 KHz.
-- if clocks is present it specifies i2c controller clock. clock-frequency
- property specifies i2c bus frequency.
-- if opencores,ip-clock-frequency is present it specifies i2c controller
- clock frequency. clock-frequency property specifies i2c bus frequency.
-
-Examples:
-
- i2c0: ocores@a0000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "opencores,i2c-ocores";
- reg = <0xa0000000 0x8>;
- interrupts = <10>;
- opencores,ip-clock-frequency = <20000000>;
-
- reg-shift = <0>; /* 8 bit registers */
- reg-io-width = <1>; /* 8 bit read/write */
-
- dummy@60 {
- compatible = "dummy";
- reg = <0x60>;
- };
- };
-or
- i2c0: ocores@a0000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "opencores,i2c-ocores";
- reg = <0xa0000000 0x8>;
- interrupts = <10>;
- clocks = <&osc>;
- clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
-
- reg-shift = <0>; /* 8 bit registers */
- reg-io-width = <1>; /* 8 bit read/write */
-
- dummy@60 {
- compatible = "dummy";
- reg = <0x60>;
- };
- };