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-rw-r--r--dts/Bindings/i2c/brcm,iproc-i2c.txt17
-rw-r--r--dts/Bindings/i2c/i2c-designware.txt9
-rw-r--r--dts/Bindings/i2c/i2c-mt65xx.txt5
-rw-r--r--dts/Bindings/i2c/i2c-riic.txt5
-rw-r--r--dts/Bindings/i2c/i2c-stm32.txt37
5 files changed, 49 insertions, 24 deletions
diff --git a/dts/Bindings/i2c/brcm,iproc-i2c.txt b/dts/Bindings/i2c/brcm,iproc-i2c.txt
index 81f982c..d12cc33 100644
--- a/dts/Bindings/i2c/brcm,iproc-i2c.txt
+++ b/dts/Bindings/i2c/brcm,iproc-i2c.txt
@@ -3,15 +3,12 @@ Broadcom iProc I2C controller
Required properties:
- compatible:
- Must be "brcm,iproc-i2c"
+ Must be "brcm,iproc-i2c" or "brcm,iproc-nic-i2c"
- reg:
Define the base and range of the I/O address space that contain the iProc
I2C controller registers
-- interrupts:
- Should contain the I2C interrupt
-
- clock-frequency:
This is the I2C bus clock. Need to be either 100000 or 400000
@@ -21,6 +18,18 @@ Required properties:
- #size-cells:
Always 0
+Optional properties:
+
+- interrupts:
+ Should contain the I2C interrupt. For certain revisions of the I2C
+ controller, I2C interrupt is unwired to the interrupt controller. In such
+ case, this property should be left unspecified, and driver will fall back
+ to polling mode
+
+- brcm,ape-hsls-addr-mask:
+ Required for "brcm,iproc-nic-i2c". Host view of address mask into the
+ 'APE' co-processor. Value must be unsigned, 32-bit
+
Example:
i2c0: i2c@18008000 {
compatible = "brcm,iproc-i2c";
diff --git a/dts/Bindings/i2c/i2c-designware.txt b/dts/Bindings/i2c/i2c-designware.txt
index 3e4bcc2..08be4d3 100644
--- a/dts/Bindings/i2c/i2c-designware.txt
+++ b/dts/Bindings/i2c/i2c-designware.txt
@@ -6,12 +6,21 @@ Required properties :
or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback
- reg : Offset and length of the register set for the device
- interrupts : <IRQ> where IRQ is the interrupt number.
+ - clocks : phandles for the clocks, see the description of clock-names below.
+ The phandle for the "ic_clk" clock is required. The phandle for the "pclk"
+ clock is optional. If a single clock is specified but no clock-name, it is
+ the "ic_clk" clock. If both clocks are listed, the "ic_clk" must be first.
Recommended properties :
- clock-frequency : desired I2C bus clock frequency in Hz.
Optional properties :
+
+ - clock-names : Contains the names of the clocks:
+ "ic_clk", for the core clock used to generate the external I2C clock.
+ "pclk", the interface clock, required for register access.
+
- reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold
time, named ICPU_CFG:TWI_DELAY in the datasheet.
diff --git a/dts/Bindings/i2c/i2c-mt65xx.txt b/dts/Bindings/i2c/i2c-mt65xx.txt
index ee4c324..68f6d73 100644
--- a/dts/Bindings/i2c/i2c-mt65xx.txt
+++ b/dts/Bindings/i2c/i2c-mt65xx.txt
@@ -12,13 +12,16 @@ Required properties:
"mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
"mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
"mediatek,mt8173-i2c": for MediaTek MT8173
+ "mediatek,mt8183-i2c": for MediaTek MT8183
+ "mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
- reg: physical base address of the controller and dma base, length of memory
mapped region.
- interrupts: interrupt number to the cpu.
- clock-div: the fixed value for frequency divider of clock source in i2c
module. Each IC may be different.
- clocks: clock name from clock manager
- - clock-names: Must include "main" and "dma", if enable have-pmic need include
+ - clock-names: Must include "main" and "dma", "arb" is for multi-master that
+ one bus has more than two i2c controllers, if enable have-pmic need include
"pmic" extra.
Optional properties:
diff --git a/dts/Bindings/i2c/i2c-riic.txt b/dts/Bindings/i2c/i2c-riic.txt
index 0bcc471..e26fe3a 100644
--- a/dts/Bindings/i2c/i2c-riic.txt
+++ b/dts/Bindings/i2c/i2c-riic.txt
@@ -1,7 +1,10 @@
Device tree configuration for Renesas RIIC driver
Required properties:
-- compatible : "renesas,riic-<soctype>". "renesas,riic-rz" as fallback
+- compatible :
+ "renesas,riic-r7s72100" if the device is a part of a R7S72100 SoC.
+ "renesas,riic-r7s9210" if the device is a part of a R7S9210 SoC.
+ "renesas,riic-rz" for a generic RZ/A compatible device.
- reg : address start and address range size of device
- interrupts : 8 interrupts (TEI, RI, TI, SPI, STI, NAKI, ALI, TMOI)
- clock-frequency : frequency of bus clock in Hz
diff --git a/dts/Bindings/i2c/i2c-stm32.txt b/dts/Bindings/i2c/i2c-stm32.txt
index 69240e1..f334738 100644
--- a/dts/Bindings/i2c/i2c-stm32.txt
+++ b/dts/Bindings/i2c/i2c-stm32.txt
@@ -1,11 +1,11 @@
* I2C controller embedded in STMicroelectronics STM32 I2C platform
-Required properties :
-- compatible : Must be one of the following
+Required properties:
+- compatible: Must be one of the following
- "st,stm32f4-i2c"
- "st,stm32f7-i2c"
-- reg : Offset and length of the register set for the device
-- interrupts : Must contain the interrupt id for I2C event and then the
+- reg: Offset and length of the register set for the device
+- interrupts: Must contain the interrupt id for I2C event and then the
interrupt id for I2C error.
- resets: Must contain the phandle to the reset controller.
- clocks: Must contain the input clock of the I2C instance.
@@ -14,25 +14,26 @@ Required properties :
- #address-cells = <1>;
- #size-cells = <0>;
-Optional properties :
-- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
+Optional properties:
+- clock-frequency: Desired I2C bus clock frequency in Hz. If not specified,
the default 100 kHz frequency will be used.
For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are
100000 and 400000.
- For STM32F7 SoC, Standard-mode, Fast-mode and Fast-mode Plus are supported,
- possible values are 100000, 400000 and 1000000.
-- i2c-scl-rising-time-ns : Only for STM32F7, I2C SCL Rising time for the board
- (default: 25)
-- i2c-scl-falling-time-ns : Only for STM32F7, I2C SCL Falling time for the board
- (default: 10)
+ For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode, Fast-mode and Fast-mode
+ Plus are supported, possible values are 100000, 400000 and 1000000.
+- i2c-scl-rising-time-ns: I2C SCL Rising time for the board (default: 25)
+ For STM32F7, STM32H7 and STM32MP1 only.
+- i2c-scl-falling-time-ns: I2C SCL Falling time for the board (default: 10)
+ For STM32F7, STM32H7 and STM32MP1 only.
I2C Timings are derived from these 2 values
-- st,syscfg-fmp: Only for STM32F7, use to set Fast Mode Plus bit within SYSCFG
- whether Fast Mode Plus speed is selected by slave.
- 1st cell : phandle to syscfg
- 2nd cell : register offset within SYSCFG
- 3rd cell : register bitmask for FMP bit
+- st,syscfg-fmp: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode
+ Plus speed is selected by slave.
+ 1st cell: phandle to syscfg
+ 2nd cell: register offset within SYSCFG
+ 3rd cell: register bitmask for FMP bit
+ For STM32F7, STM32H7 and STM32MP1 only.
-Example :
+Example:
i2c@40005400 {
compatible = "st,stm32f4-i2c";