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Diffstat (limited to 'dts/Bindings/interrupt-controller/apple,aic.yaml')
| -rw-r--r-- | dts/Bindings/interrupt-controller/apple,aic.yaml | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/dts/Bindings/interrupt-controller/apple,aic.yaml b/dts/Bindings/interrupt-controller/apple,aic.yaml index cf6c091a07..698588e9aa 100644 --- a/dts/Bindings/interrupt-controller/apple,aic.yaml +++ b/dts/Bindings/interrupt-controller/apple,aic.yaml @@ -56,6 +56,8 @@ properties: - 1: virtual HV timer - 2: physical guest timer - 3: virtual guest timer + - 4: 'efficient' CPU PMU + - 5: 'performance' CPU PMU The 3rd cell contains the interrupt flags. This is normally IRQ_TYPE_LEVEL_HIGH (4). @@ -65,6 +67,37 @@ properties: Specifies base physical address and size of the AIC registers. maxItems: 1 + power-domains: + maxItems: 1 + + affinities: + type: object + additionalProperties: false + description: + FIQ affinity can be expressed as a single "affinities" node, + containing a set of sub-nodes, one per FIQ with a non-default + affinity. + patternProperties: + "^.+-affinity$": + type: object + additionalProperties: false + properties: + apple,fiq-index: + description: + The interrupt number specified as a FIQ, and for which + the affinity is not the default. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 5 + + cpus: + description: + Should be a list of phandles to CPU nodes (as described in + Documentation/devicetree/bindings/arm/cpus.yaml). + + required: + - apple,fiq-index + - cpus + required: - compatible - '#interrupt-cells' |