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diff --git a/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
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-Microsemi Ocelot SoC ICPU Interrupt Controller
-
-Required properties:
-
-- compatible : should be "mscc,ocelot-icpu-intr"
-- reg : Specifies base physical address and size of the registers.
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source. The value shall be 1.
-- interrupts : Specifies the CPU interrupt the controller is connected to.
-
-Example:
-
- intc: interrupt-controller@70000070 {
- compatible = "mscc,ocelot-icpu-intr";
- reg = <0x70000070 0x70>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupt-parent = <&cpuintc>;
- interrupts = <2>;
- };