diff options
Diffstat (limited to 'dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml')
| -rw-r--r-- | dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 80 |
1 files changed, 72 insertions, 8 deletions
diff --git a/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 27092c6a86..709b221127 100644 --- a/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -26,9 +26,14 @@ description: with priority below this threshold will not cause the PLIC to raise its interrupt line leading to the context. - While the PLIC supports both edge-triggered and level-triggered interrupts, - interrupt handlers are oblivious to this distinction and therefore it is not - specified in the PLIC device-tree binding. + The PLIC supports both edge-triggered and level-triggered interrupts. For + edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges + seen while an interrupt handler is active; the PLIC may either queue them or + ignore them. In the first case, handlers are oblivious to the trigger type, so + it is not included in the interrupt specifier. In the second case, software + needs to know the trigger type, so it can reorder the interrupt flow to avoid + missing interrupts. This special handling is needed by at least the Renesas + RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC. While the RISC-V ISA doesn't specify a memory layout for the PLIC, the "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that @@ -40,7 +45,6 @@ description: from S-mode. So add thead,c900-plic to distinguish them. maintainers: - - Sagar Kadam <sagar.kadam@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> - Palmer Dabbelt <palmer@dabbelt.com> @@ -49,14 +53,28 @@ properties: oneOf: - items: - enum: + - renesas,r9a07g043-plic + - const: andestech,nceplic100 + - items: + - enum: + - canaan,k210-plic - sifive,fu540-c000-plic - starfive,jh7100-plic - - canaan,k210-plic + - starfive,jh7110-plic - const: sifive,plic-1.0.0 - items: - enum: - allwinner,sun20i-d1-plic + - sophgo,cv1800b-plic + - sophgo,cv1812h-plic + - sophgo,sg2042-plic + - thead,th1520-plic - const: thead,c900-plic + - items: + - const: sifive,plic-1.0.0 + - const: riscv,plic0 + deprecated: true + description: For the QEMU virt machine only reg: maxItems: 1 @@ -64,8 +82,7 @@ properties: '#address-cells': const: 0 - '#interrupt-cells': - const: 1 + '#interrupt-cells': true interrupt-controller: true @@ -78,10 +95,16 @@ properties: riscv,cpu-intc node, which has a riscv node as parent. riscv,ndev: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: Specifies how many external interrupts are supported by this controller. + clocks: true + + power-domains: true + + resets: true + required: - compatible - '#address-cells' @@ -91,6 +114,47 @@ required: - interrupts-extended - riscv,ndev +allOf: + - if: + properties: + compatible: + contains: + enum: + - andestech,nceplic100 + - thead,c900-plic + + then: + properties: + '#interrupt-cells': + const: 2 + + else: + properties: + '#interrupt-cells': + const: 1 + + - if: + properties: + compatible: + contains: + const: renesas,r9a07g043-plic + + then: + properties: + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + required: + - clocks + - power-domains + - resets + additionalProperties: false examples: |