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-rw-r--r--dts/Bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml2
-rw-r--r--dts/Bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml2
-rw-r--r--dts/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml2
-rw-r--r--dts/Bindings/interrupt-controller/apple,aic.yaml2
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic-v3.yaml1
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic.yaml4
-rw-r--r--dts/Bindings/interrupt-controller/fsl,mu-msi.yaml99
-rw-r--r--dts/Bindings/interrupt-controller/idt,32434-pic.yaml2
-rw-r--r--dts/Bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml46
-rw-r--r--dts/Bindings/interrupt-controller/qcom,pdc.txt78
-rw-r--r--dts/Bindings/interrupt-controller/qcom,pdc.yaml87
-rw-r--r--dts/Bindings/interrupt-controller/realtek,rtl-intc.yaml60
-rw-r--r--dts/Bindings/interrupt-controller/renesas,irqc.yaml1
-rw-r--r--dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml5
-rw-r--r--dts/Bindings/interrupt-controller/st,stm32-exti.yaml2
-rw-r--r--dts/Bindings/interrupt-controller/ti,sci-inta.yaml3
-rw-r--r--dts/Bindings/interrupt-controller/ti,sci-intr.yaml3
17 files changed, 297 insertions, 102 deletions
diff --git a/dts/Bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml b/dts/Bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml
index 953d875b5e..a713633be7 100644
--- a/dts/Bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml
+++ b/dts/Bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun4i-a10-ic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Allwinner A10 Interrupt Controller Device Tree Bindings
+title: Allwinner A10 Interrupt Controller
maintainers:
- Chen-Yu Tsai <wens@csie.org>
diff --git a/dts/Bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml b/dts/Bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml
index 4db24b8a9f..4fa6fd400e 100644
--- a/dts/Bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml
+++ b/dts/Bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Allwinner A31 NMI/Wakeup Interrupt Controller Device Tree Bindings
+title: Allwinner A31 NMI/Wakeup Interrupt Controller
maintainers:
- Chen-Yu Tsai <wens@csie.org>
diff --git a/dts/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/dts/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
index 7fc9ad5ef3..83603180d8 100644
--- a/dts/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
+++ b/dts/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Allwinner A20 Non-Maskable Interrupt Controller Device Tree Bindings
+title: Allwinner A20 Non-Maskable Interrupt Controller
maintainers:
- Chen-Yu Tsai <wens@csie.org>
diff --git a/dts/Bindings/interrupt-controller/apple,aic.yaml b/dts/Bindings/interrupt-controller/apple,aic.yaml
index 85c85b6942..e18107eafe 100644
--- a/dts/Bindings/interrupt-controller/apple,aic.yaml
+++ b/dts/Bindings/interrupt-controller/apple,aic.yaml
@@ -96,7 +96,7 @@ properties:
Documentation/devicetree/bindings/arm/cpus.yaml).
required:
- - fiq-index
+ - apple,fiq-index
- cpus
required:
diff --git a/dts/Bindings/interrupt-controller/arm,gic-v3.yaml b/dts/Bindings/interrupt-controller/arm,gic-v3.yaml
index 3912a89162..9f7d3e11aa 100644
--- a/dts/Bindings/interrupt-controller/arm,gic-v3.yaml
+++ b/dts/Bindings/interrupt-controller/arm,gic-v3.yaml
@@ -170,7 +170,6 @@ dependencies:
required:
- compatible
- - interrupts
- reg
patternProperties:
diff --git a/dts/Bindings/interrupt-controller/arm,gic.yaml b/dts/Bindings/interrupt-controller/arm,gic.yaml
index 62219a5c21..2202569074 100644
--- a/dts/Bindings/interrupt-controller/arm,gic.yaml
+++ b/dts/Bindings/interrupt-controller/arm,gic.yaml
@@ -64,9 +64,9 @@ properties:
interrupt-controller: true
"#address-cells":
- enum: [ 0, 1 ]
+ enum: [ 0, 1, 2 ]
"#size-cells":
- const: 1
+ enum: [ 1, 2 ]
"#interrupt-cells":
const: 3
diff --git a/dts/Bindings/interrupt-controller/fsl,mu-msi.yaml b/dts/Bindings/interrupt-controller/fsl,mu-msi.yaml
new file mode 100644
index 0000000000..799ae5c3e3
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/fsl,mu-msi.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description: |
+ The Messaging Unit module enables two processors within the SoC to
+ communicate and coordinate by passing messages (e.g. data, status
+ and control) through the MU interface. The MU also provides the ability
+ for one processor (A side) to signal the other processor (B side) using
+ interrupts.
+
+ Because the MU manages the messaging between processors, the MU uses
+ different clocks (from each side of the different peripheral buses).
+ Therefore, the MU must synchronize the accesses from one side to the
+ other. The MU accomplishes synchronization using two sets of matching
+ registers (Processor A-side, Processor B-side).
+
+ MU can work as msi interrupt controller to do doorbell
+
+allOf:
+ - $ref: /schemas/interrupt-controller/msi-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx6sx-mu-msi
+ - fsl,imx7ulp-mu-msi
+ - fsl,imx8ulp-mu-msi
+ - fsl,imx8ulp-mu-msi-s4
+
+ reg:
+ items:
+ - description: a side register base address
+ - description: b side register base address
+
+ reg-names:
+ items:
+ - const: processor-a-side
+ - const: processor-b-side
+
+ interrupts:
+ description: a side interrupt number.
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ items:
+ - description: a side power domain
+ - description: b side power domain
+
+ power-domain-names:
+ items:
+ - const: processor-a-side
+ - const: processor-b-side
+
+ interrupt-controller: true
+
+ msi-controller: true
+
+ "#msi-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - msi-controller
+ - "#msi-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+
+ msi-controller@5d270000 {
+ compatible = "fsl,imx6sx-mu-msi";
+ msi-controller;
+ #msi-cells = <0>;
+ interrupt-controller;
+ reg = <0x5d270000 0x10000>, /* A side */
+ <0x5d300000 0x10000>; /* B side */
+ reg-names = "processor-a-side", "processor-b-side";
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd IMX_SC_R_MU_12A>,
+ <&pd IMX_SC_R_MU_12B>;
+ power-domain-names = "processor-a-side", "processor-b-side";
+ };
diff --git a/dts/Bindings/interrupt-controller/idt,32434-pic.yaml b/dts/Bindings/interrupt-controller/idt,32434-pic.yaml
index 160ff4b07c..afb3dd80b6 100644
--- a/dts/Bindings/interrupt-controller/idt,32434-pic.yaml
+++ b/dts/Bindings/interrupt-controller/idt,32434-pic.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/interrupt-controller/idt,32434-pic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: IDT 79RC32434 Interrupt Controller Device Tree Bindings
+title: IDT 79RC32434 Interrupt Controller
maintainers:
- Thomas Bogendoerfer <tsbogend@alpha.franken.de>
diff --git a/dts/Bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml b/dts/Bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml
new file mode 100644
index 0000000000..46a1f5f54b
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mti,cpu-interrupt-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS CPU Interrupt Controller
+
+description: >
+ On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
+ IRQs from a devicetree file and create a irq_domain for IRQ controller.
+
+ With the irq_domain in place we can describe how the 8 IRQs are wired to the
+ platforms internal interrupt controller cascade.
+
+maintainers:
+ - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+
+properties:
+ compatible:
+ const: mti,cpu-interrupt-controller
+
+ '#interrupt-cells':
+ const: 1
+
+ '#address-cells':
+ const: 0
+
+ interrupt-controller: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - '#address-cells'
+ - interrupt-controller
+
+examples:
+ - |
+ interrupt-controller {
+ compatible = "mti,cpu-interrupt-controller";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
diff --git a/dts/Bindings/interrupt-controller/qcom,pdc.txt b/dts/Bindings/interrupt-controller/qcom,pdc.txt
deleted file mode 100644
index 159a423e55..0000000000
--- a/dts/Bindings/interrupt-controller/qcom,pdc.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-PDC interrupt controller
-
-Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
-Power Domain Controller (PDC) that is on always-on domain. In addition to
-providing power control for the power domains, the hardware also has an
-interrupt controller that can be used to help detect edge low interrupts as
-well detect interrupts when the GIC is non-operational.
-
-GIC is parent interrupt controller at the highest level. Platform interrupt
-controller PDC is next in hierarchy, followed by others. Drivers requiring
-wakeup capabilities of their device interrupts routed through the PDC, must
-specify PDC as their interrupt controller and request the PDC port associated
-with the GIC interrupt. See example below.
-
-Properties:
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc"
- - "qcom,sc7180-pdc": For SC7180
- - "qcom,sc7280-pdc": For SC7280
- - "qcom,sdm845-pdc": For SDM845
- - "qcom,sm6350-pdc": For SM6350
- - "qcom,sm8150-pdc": For SM8150
- - "qcom,sm8250-pdc": For SM8250
- - "qcom,sm8350-pdc": For SM8350
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Specifies the base physical address for PDC hardware.
-
-- interrupt-cells:
- Usage: required
- Value type: <u32>
- Definition: Specifies the number of cells needed to encode an interrupt
- source.
- Must be 2.
- The first element of the tuple is the PDC pin for the
- interrupt.
- The second element is the trigger type.
-
-- interrupt-controller:
- Usage: required
- Value type: <bool>
- Definition: Identifies the node as an interrupt controller.
-
-- qcom,pdc-ranges:
- Usage: required
- Value type: <u32 array>
- Definition: Specifies the PDC pin offset and the number of PDC ports.
- The tuples indicates the valid mapping of valid PDC ports
- and their hwirq mapping.
- The first element of the tuple is the starting PDC port.
- The second element is the GIC hwirq number for the PDC port.
- The third element is the number of interrupts in sequence.
-
-Example:
-
- pdc: interrupt-controller@b220000 {
- compatible = "qcom,sdm845-pdc";
- reg = <0xb220000 0x30000>;
- qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
- #interrupt-cells = <2>;
- interrupt-parent = <&intc>;
- interrupt-controller;
- };
-
-DT binding of a device that wants to use the GIC SPI 514 as a wakeup
-interrupt, must do -
-
- wake-device {
- interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
- };
-
-In this case interrupt 514 would be mapped to port 2 on the PDC as defined by
-the qcom,pdc-ranges property.
diff --git a/dts/Bindings/interrupt-controller/qcom,pdc.yaml b/dts/Bindings/interrupt-controller/qcom,pdc.yaml
new file mode 100644
index 0000000000..b6f56cf5fb
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/qcom,pdc.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PDC interrupt controller
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description: |
+ Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
+ Power Domain Controller (PDC) that is on always-on domain. In addition to
+ providing power control for the power domains, the hardware also has an
+ interrupt controller that can be used to help detect edge low interrupts as
+ well detect interrupts when the GIC is non-operational.
+
+ GIC is parent interrupt controller at the highest level. Platform interrupt
+ controller PDC is next in hierarchy, followed by others. Drivers requiring
+ wakeup capabilities of their device interrupts routed through the PDC, must
+ specify PDC as their interrupt controller and request the PDC port associated
+ with the GIC interrupt. See example below.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,sc7180-pdc
+ - qcom,sc7280-pdc
+ - qcom,sdm845-pdc
+ - qcom,sm6350-pdc
+ - qcom,sm8150-pdc
+ - qcom,sm8250-pdc
+ - qcom,sm8350-pdc
+ - const: qcom,pdc
+
+ reg:
+ minItems: 1
+ items:
+ - description: PDC base register region
+ - description: Edge or Level config register for SPI interrupts
+
+ '#interrupt-cells':
+ const: 2
+
+ interrupt-controller: true
+
+ qcom,pdc-ranges:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ minItems: 1
+ maxItems: 32 # no hard limit
+ items:
+ items:
+ - description: starting PDC port
+ - description: GIC hwirq number for the PDC port
+ - description: number of interrupts in sequence
+ description: |
+ Specifies the PDC pin offset and the number of PDC ports.
+ The tuples indicates the valid mapping of valid PDC ports
+ and their hwirq mapping.
+
+required:
+ - compatible
+ - reg
+ - '#interrupt-cells'
+ - interrupt-controller
+ - qcom,pdc-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sdm845-pdc", "qcom,pdc";
+ reg = <0xb220000 0x30000>;
+ qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ wake-device {
+ interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/dts/Bindings/interrupt-controller/realtek,rtl-intc.yaml b/dts/Bindings/interrupt-controller/realtek,rtl-intc.yaml
index 9e76fff203..13a893b18f 100644
--- a/dts/Bindings/interrupt-controller/realtek,rtl-intc.yaml
+++ b/dts/Bindings/interrupt-controller/realtek,rtl-intc.yaml
@@ -6,6 +6,14 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek RTL SoC interrupt controller devicetree bindings
+description:
+ Interrupt controller and router for Realtek MIPS SoCs, allowing each SoC
+ interrupt to be routed to one parent CPU (hardware) interrupt, or left
+ disconnected.
+ All connected input lines from SoC peripherals can be masked individually,
+ and an interrupt status register is present to indicate which interrupts are
+ pending.
+
maintainers:
- Birger Koblitz <mail@birger-koblitz.de>
- Bert Vermeulen <bert@biot.com>
@@ -13,23 +21,33 @@ maintainers:
properties:
compatible:
- const: realtek,rtl-intc
+ oneOf:
+ - items:
+ - enum:
+ - realtek,rtl8380-intc
+ - const: realtek,rtl-intc
+ - const: realtek,rtl-intc
+ deprecated: true
"#interrupt-cells":
+ description:
+ SoC interrupt line index.
const: 1
reg:
maxItems: 1
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 15
+ description:
+ List of parent interrupts, in the order that they are connected to this
+ interrupt router's outputs, starting at the first output.
interrupt-controller: true
- "#address-cells":
- const: 0
-
interrupt-map:
+ deprecated: true
description: Describes mapping from SoC interrupts to CPU interrupts
required:
@@ -37,21 +55,33 @@ required:
- reg
- "#interrupt-cells"
- interrupt-controller
- - "#address-cells"
- - interrupt-map
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ const: realtek,rtl-intc
+ then:
+ properties:
+ "#address-cells":
+ const: 0
+ required:
+ - "#address-cells"
+ - interrupt-map
+ else:
+ required:
+ - interrupts
additionalProperties: false
examples:
- |
- intc: interrupt-controller@3000 {
- compatible = "realtek,rtl-intc";
+ interrupt-controller@3000 {
+ compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
#interrupt-cells = <1>;
interrupt-controller;
- reg = <0x3000 0x20>;
- #address-cells = <0>;
- interrupt-map =
- <31 &cpuintc 2>,
- <30 &cpuintc 1>,
- <29 &cpuintc 5>;
+ reg = <0x3000 0x18>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>, <4>, <5>, <6>;
};
diff --git a/dts/Bindings/interrupt-controller/renesas,irqc.yaml b/dts/Bindings/interrupt-controller/renesas,irqc.yaml
index 620f01775e..62fd47c882 100644
--- a/dts/Bindings/interrupt-controller/renesas,irqc.yaml
+++ b/dts/Bindings/interrupt-controller/renesas,irqc.yaml
@@ -37,6 +37,7 @@ properties:
- renesas,intc-ex-r8a77990 # R-Car E3
- renesas,intc-ex-r8a77995 # R-Car D3
- renesas,intc-ex-r8a779a0 # R-Car V3U
+ - renesas,intc-ex-r8a779g0 # R-Car V4H
- const: renesas,irqc
'#interrupt-cells':
diff --git a/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 92e0f8c3ef..99e01f4d0a 100644
--- a/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -66,6 +66,11 @@ properties:
- enum:
- allwinner,sun20i-d1-plic
- const: thead,c900-plic
+ - items:
+ - const: sifive,plic-1.0.0
+ - const: riscv,plic0
+ deprecated: true
+ description: For the QEMU virt machine only
reg:
maxItems: 1
diff --git a/dts/Bindings/interrupt-controller/st,stm32-exti.yaml b/dts/Bindings/interrupt-controller/st,stm32-exti.yaml
index e44daa09b1..00c10a8258 100644
--- a/dts/Bindings/interrupt-controller/st,stm32-exti.yaml
+++ b/dts/Bindings/interrupt-controller/st,stm32-exti.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/interrupt-controller/st,stm32-exti.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: STM32 External Interrupt Controller Device Tree Bindings
+title: STM32 External Interrupt Controller
maintainers:
- Alexandre Torgue <alexandre.torgue@foss.st.com>
diff --git a/dts/Bindings/interrupt-controller/ti,sci-inta.yaml b/dts/Bindings/interrupt-controller/ti,sci-inta.yaml
index 88c46e6173..1151518859 100644
--- a/dts/Bindings/interrupt-controller/ti,sci-inta.yaml
+++ b/dts/Bindings/interrupt-controller/ti,sci-inta.yaml
@@ -59,6 +59,9 @@ properties:
interrupt-controller: true
+ '#interrupt-cells':
+ const: 0
+
msi-controller: true
ti,interrupt-ranges:
diff --git a/dts/Bindings/interrupt-controller/ti,sci-intr.yaml b/dts/Bindings/interrupt-controller/ti,sci-intr.yaml
index e12aee42b1..c99cc7323c 100644
--- a/dts/Bindings/interrupt-controller/ti,sci-intr.yaml
+++ b/dts/Bindings/interrupt-controller/ti,sci-intr.yaml
@@ -58,6 +58,9 @@ properties:
1 = If intr supports edge triggered interrupts.
4 = If intr supports level triggered interrupts.
+ reg:
+ maxItems: 1
+
interrupt-controller: true
'#interrupt-cells':