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-rw-r--r--dts/Bindings/interrupt-controller/al,alpine-msix.txt26
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic.txt1
-rw-r--r--dts/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt22
-rw-r--r--dts/Bindings/interrupt-controller/marvell,odmi-controller.txt44
-rw-r--r--dts/Bindings/interrupt-controller/mips-gic.txt7
-rw-r--r--dts/Bindings/interrupt-controller/sigma,smp8642-intc.txt49
6 files changed, 144 insertions, 5 deletions
diff --git a/dts/Bindings/interrupt-controller/al,alpine-msix.txt b/dts/Bindings/interrupt-controller/al,alpine-msix.txt
new file mode 100644
index 0000000..f6f1c14
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/al,alpine-msix.txt
@@ -0,0 +1,26 @@
+Alpine MSIX controller
+
+See arm,gic-v3.txt for SPI and MSI definitions.
+
+Required properties:
+
+- compatible: should be "al,alpine-msix"
+- reg: physical base address and size of the registers
+- interrupt-parent: specifies the parent interrupt controller.
+- interrupt-controller: identifies the node as an interrupt controller
+- msi-controller: identifies the node as an PCI Message Signaled Interrupt
+ controller
+- al,msi-base-spi: SPI base of the MSI frame
+- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
+
+Example:
+
+msix: msix {
+ compatible = "al,alpine-msix";
+ reg = <0x0 0xfbe00000 0x0 0x100000>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ msi-controller;
+ al,msi-base-spi = <160>;
+ al,msi-num-spis = <160>;
+};
diff --git a/dts/Bindings/interrupt-controller/arm,gic.txt b/dts/Bindings/interrupt-controller/arm,gic.txt
index 5a1cb4b..793c20f 100644
--- a/dts/Bindings/interrupt-controller/arm,gic.txt
+++ b/dts/Bindings/interrupt-controller/arm,gic.txt
@@ -16,6 +16,7 @@ Main node required properties:
"arm,cortex-a15-gic"
"arm,cortex-a7-gic"
"arm,cortex-a9-gic"
+ "arm,eb11mp-gic"
"arm,gic-400"
"arm,pl390"
"arm,tc11mp-gic"
diff --git a/dts/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt b/dts/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt
index 720f7c9..3b2f4c4 100644
--- a/dts/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt
+++ b/dts/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt
@@ -21,6 +21,8 @@ Mbigen main node required properties:
- reg: Specifies the base physical address and size of the Mbigen
registers.
+Mbigen sub node required properties:
+------------------------------------------
- interrupt controller: Identifies the node as an interrupt controller
- msi-parent: Specifies the MSI controller this mbigen use.
@@ -45,13 +47,23 @@ Mbigen main node required properties:
Examples:
- mbigen_device_gmac:intc {
+ mbigen_chip_dsa {
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0xc0080000 0x0 0x10000>;
- interrupt-controller;
- msi-parent = <&its_dsa 0x40b1c>;
- num-pins = <9>;
- #interrupt-cells = <2>;
+
+ mbigen_gmac:intc_gmac {
+ interrupt-controller;
+ msi-parent = <&its_dsa 0x40b1c>;
+ num-pins = <9>;
+ #interrupt-cells = <2>;
+ };
+
+ mbigen_i2c:intc_i2c {
+ interrupt-controller;
+ msi-parent = <&its_dsa 0x40b0e>;
+ num-pins = <2>;
+ #interrupt-cells = <2>;
+ };
};
Devices connect to mbigen required properties:
diff --git a/dts/Bindings/interrupt-controller/marvell,odmi-controller.txt b/dts/Bindings/interrupt-controller/marvell,odmi-controller.txt
new file mode 100644
index 0000000..8af0a8e
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/marvell,odmi-controller.txt
@@ -0,0 +1,44 @@
+
+* Marvell ODMI for MSI support
+
+Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
+which can be used by on-board peripheral for MSI interrupts.
+
+Required properties:
+
+- compatible : The value here should contain:
+
+ "marvell,ap806-odmi-controller", "marvell,odmi-controller".
+
+- interrupt,controller : Identifies the node as an interrupt controller.
+
+- msi-controller : Identifies the node as an MSI controller.
+
+- marvell,odmi-frames : Number of ODMI frames available. Each frame
+ provides a number of events.
+
+- reg : List of register definitions, one for each
+ ODMI frame.
+
+- marvell,spi-base : List of GIC base SPI interrupts, one for each
+ ODMI frame. Those SPI interrupts are 0-based,
+ i.e marvell,spi-base = <128> will use SPI #96.
+ See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
+ for details about the GIC Device Tree binding.
+
+- interrupt-parent : Reference to the parent interrupt controller.
+
+Example:
+
+ odmi: odmi@300000 {
+ compatible = "marvell,ap806-odm-controller",
+ "marvell,odmi-controller";
+ interrupt-controller;
+ msi-controller;
+ marvell,odmi-frames = <4>;
+ reg = <0x300000 0x4000>,
+ <0x304000 0x4000>,
+ <0x308000 0x4000>,
+ <0x30C000 0x4000>;
+ marvell,spi-base = <128>, <136>, <144>, <152>;
+ };
diff --git a/dts/Bindings/interrupt-controller/mips-gic.txt b/dts/Bindings/interrupt-controller/mips-gic.txt
index aae4c38..1735953 100644
--- a/dts/Bindings/interrupt-controller/mips-gic.txt
+++ b/dts/Bindings/interrupt-controller/mips-gic.txt
@@ -23,6 +23,12 @@ Optional properties:
- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
to which the GIC may not route interrupts. Valid values are 2 - 7.
This property is ignored if the CPU is started in EIC mode.
+- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
+ reserved for IPIs.
+ It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
+ of the reserved range.
+ If not specified, the driver will allocate the last 2 * number of VPEs in the
+ system.
Required properties for timer sub-node:
- compatible : Should be "mti,gic-timer".
@@ -44,6 +50,7 @@ Example:
#interrupt-cells = <3>;
mti,reserved-cpu-vectors = <7>;
+ mti,reserved-ipi-vectors = <40 8>;
timer {
compatible = "mti,gic-timer";
diff --git a/dts/Bindings/interrupt-controller/sigma,smp8642-intc.txt b/dts/Bindings/interrupt-controller/sigma,smp8642-intc.txt
new file mode 100644
index 0000000..1f441fa
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/sigma,smp8642-intc.txt
@@ -0,0 +1,49 @@
+Sigma Designs SMP86xx/SMP87xx secondary interrupt controller
+
+Required properties:
+- compatible: should be "sigma,smp8642-intc"
+- reg: physical address of MMIO region
+- ranges: address space mapping of child nodes
+- interrupt-parent: phandle of parent interrupt controller
+- interrupt-controller: boolean
+- #address-cells: should be <1>
+- #size-cells: should be <1>
+
+One child node per control block with properties:
+- reg: address of registers for this control block
+- interrupt-controller: boolean
+- #interrupt-cells: should be <2>, interrupt index and flags per interrupts.txt
+- interrupts: interrupt spec of primary interrupt controller
+
+Example:
+
+interrupt-controller@6e000 {
+ compatible = "sigma,smp8642-intc";
+ reg = <0x6e000 0x400>;
+ ranges = <0x0 0x6e000 0x400>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ irq0: interrupt-controller@0 {
+ reg = <0x000 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ irq1: interrupt-controller@100 {
+ reg = <0x100 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ irq2: interrupt-controller@300 {
+ reg = <0x300 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};