diff options
Diffstat (limited to 'dts/Bindings/iommu/arm,smmu-v3.txt')
-rw-r--r-- | dts/Bindings/iommu/arm,smmu-v3.txt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/dts/Bindings/iommu/arm,smmu-v3.txt b/dts/Bindings/iommu/arm,smmu-v3.txt index c03eec1168..947863acc2 100644 --- a/dts/Bindings/iommu/arm,smmu-v3.txt +++ b/dts/Bindings/iommu/arm,smmu-v3.txt @@ -35,3 +35,25 @@ the PCIe specification. NOTE: this only applies to the SMMU itself, not masters connected upstream of the SMMU. + +- msi-parent : See the generic MSI binding described in + devicetree/bindings/interrupt-controller/msi.txt + for a description of the msi-parent property. + +- hisilicon,broken-prefetch-cmd + : Avoid sending CMD_PREFETCH_* commands to the SMMU. + +** Example + + smmu@2b400000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x2b400000 0x0 0x20000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + dma-coherent; + #iommu-cells = <0>; + msi-parent = <&its 0xff0000>; + }; |