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-rw-r--r--dts/Bindings/iommu/arm,smmu.yaml6
-rw-r--r--dts/Bindings/iommu/rockchip,iommu.yaml2
2 files changed, 2 insertions, 6 deletions
diff --git a/dts/Bindings/iommu/arm,smmu.yaml b/dts/Bindings/iommu/arm,smmu.yaml
index 1181b590db..03f2b2d4db 100644
--- a/dts/Bindings/iommu/arm,smmu.yaml
+++ b/dts/Bindings/iommu/arm,smmu.yaml
@@ -52,16 +52,14 @@ properties:
items:
- const: marvell,ap806-smmu-500
- const: arm,mmu-500
- - description: NVIDIA SoCs that program two ARM MMU-500s identically
- items:
- description: NVIDIA SoCs that require memory controller interaction
and may program multiple ARM MMU-500s identically with the memory
controller interleaving translations between multiple instances
for improved performance.
items:
- enum:
- - const: nvidia,tegra194-smmu
- - const: nvidia,tegra186-smmu
+ - nvidia,tegra194-smmu
+ - nvidia,tegra186-smmu
- const: nvidia,smmu-500
- items:
- const: arm,mmu-500
diff --git a/dts/Bindings/iommu/rockchip,iommu.yaml b/dts/Bindings/iommu/rockchip,iommu.yaml
index d2e28a9e35..ba9124f721 100644
--- a/dts/Bindings/iommu/rockchip,iommu.yaml
+++ b/dts/Bindings/iommu/rockchip,iommu.yaml
@@ -28,14 +28,12 @@ properties:
- description: configuration registers for MMU instance 0
- description: configuration registers for MMU instance 1
minItems: 1
- maxItems: 2
interrupts:
items:
- description: interruption for MMU instance 0
- description: interruption for MMU instance 1
minItems: 1
- maxItems: 2
clocks:
items: