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-rw-r--r--dts/Bindings/memory-controllers/fsl/imx8m-ddrc.yaml11
1 files changed, 6 insertions, 5 deletions
diff --git a/dts/Bindings/memory-controllers/fsl/imx8m-ddrc.yaml b/dts/Bindings/memory-controllers/fsl/imx8m-ddrc.yaml
index c9e6c22cb5..519b123116 100644
--- a/dts/Bindings/memory-controllers/fsl/imx8m-ddrc.yaml
+++ b/dts/Bindings/memory-controllers/fsl/imx8m-ddrc.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX8M DDR Controller
maintainers:
- - Leonard Crestez <leonard.crestez@nxp.com>
+ - Peng Fan <peng.fan@nxp.com>
description:
The DDRC block is integrated in i.MX8M for interfacing with DDR based
@@ -25,9 +25,9 @@ properties:
compatible:
items:
- enum:
- - fsl,imx8mn-ddrc
- - fsl,imx8mm-ddrc
- - fsl,imx8mq-ddrc
+ - fsl,imx8mn-ddrc
+ - fsl,imx8mm-ddrc
+ - fsl,imx8mq-ddrc
- const: fsl,imx8m-ddrc
reg:
@@ -47,7 +47,8 @@ properties:
- const: apb
operating-points-v2: true
- opp-table: true
+ opp-table:
+ type: object
required:
- reg